Two broad categories of work are described: algorithmic studies and hardware design. Several algorithms for digitizing and reducing the data rate of speech signals are described. These algorithms include an adaptive residual coder (ARC) designed to produce data at 16 and 9.6 kbps, an adaptive predictive coder (APC) at 8 kbps, a voice-excited linear predictor (VELP) at 8 kbps, and a straight linear predictive coded (LPC) vocoder at 2.4, 3.6, and 4.8 kbps. In addition, some work on pitch or excitation extraction is described. All these studies are evaluated on a realtime facility which is described. In the hardware design area, the digital voice terminal is described in detail, as well as some follow-on next-generation LSI studies. Volume II will contain a digital voice terminal (DVT) manual, program listings, and a cross assembler.