To insure correct operation of digital logic circuits one must ascertain that the circuits perform functionally correct operations, at desired speeds or clock rates. Extensive research has been expended to derive procedures to ascertain the correct functional behavior of logic circuits. For example, procedures to detect line stuck-at faults and other logic faults help identify faulty circuits that do not perform correct functional operations. Relatively much less effort has been expended to derive procedures to ascertain correct operations by digital logic circuit at desired clock rates. Circuit failures causing malfunctions while operating at desired clock rates, but may not at other clock rates, are modeled to test logic circuits to detect and locate delay faults and to develop methods to design logic circuits that are easily testable for delay faults.