We have developed new procedures for etching porous silicon (PSi), which will allow PSi devices to be more easily integrated with other devices used for initiating, controlling, or utilizing the output of the PSi devices. Of the 2 processes developed, the sacrificial electrode process is the simplest, but it produces an inhomogeneous PSi thickness across the wafer and introduces surface topography due to electro-polishing. By using the anchored electrode method, which incorporates a dielectric layer, more controllable etch depths and patterned devices are obtainable. One complication is that a proximity effect is observed where features closer to the electrode etch more rapidly. A simple voltage divider model can be used to predict the relative etch rates, but more work is required before a quantitative model for predicting etch depth will be possible. In order to vary the etch depth by varying the local electrode/silicon (Si) ratio, the electrode will need to be cut up into electrically isolated sections or else the carriers will conduct along the length of the electrode causing more etching at the most easily reached exposed Si.