In this report we have discussed the characterization of the power FETs procured for this program and failure analysis of low noise devices, including wire bonding failures and environmental stress test failures. A method of etching gold while leaving the underlying refractory metals relatively unaffected was explained. An analysis of the Type A-6 low noise FET was given, in which a failure mode was discussed that involved possible channel doping compensation. Results were then presented on...
Topics: DTIC Archive, Bowman,Lawrence S, HUGHES AIRCRAFT CO TORRANCE CALIF, *GALLIUM ARSENIDES, *FIELD...
A set of logically flexible digital building blocks capable of implementing various logic functions with delays of less than one nanosecond was developed and fabricated in microcircuit form. The set consists of two basic types of circuit modules; with these, all conceivable digital system logic functions can be implemented. Tunnel junction diodes and silicon transistors provide gating functions, and a universal amplifier circuit module reshapes signal waveforms, restores amplitudes, and stores...
Topics: DTIC Archive, MASSACHUSETTS INST OF TECH LEXINGTON LINCOLN LAB, *COMPUTER LOGIC, *MICROELECTRONICS,...
Power MOSFET heavy ion-induced Single Event Burnout tests were performed jointly by representatives of the Aerospace Corporation, NASA Goddard, NWSC Crane and Rockwell International. For the most part, presented are the results of the burnout threshold and cross section characterizations performed on n-channel power MOSFETs, however a small amount of p-channel data is also included. In addition, data on the effect of temperature, gate bias, total dose and inductive loading on MOSFET Single...
Topics: DTIC Archive, Waskiewicz, A E, ROCKWELL INTERNATIONAL ANAHEIM CA, *BREAKDOWN(ELECTRONIC THRESHOLD),...
We describe heavy ion test results for two new SEU tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5microprocess.
Topics: NASA Technical Reports Server (NTRS), SINGLE EVENT UPSETS, HEAVY IONS, GATES (CIRCUITS),...
Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and...
Topics: NASA Technical Reports Server (NTRS), LOGIC CIRCUITS, GATES (CIRCUITS), SEMICONDUCTOR DEVICES,...
Sampling output levels of accelerometers using largest output or any combination of outputs provide control of shaker for spacecraft vibration qualification tests.
Topics: NASA Technical Reports Server (NTRS), ACCELEROMETERS, AMPLIFIERS, CAPACITORS, DIODES, GATES...
A two-dimensional numerical model, TABS-2, was used to predict fine sediment deposition in the lock approach channels upstream and downstream from Lock and Dam No. 3 on the Red River Waterway, Louisiana. The numerical model was used to evaluate the effects of various design changes on fine sediment deposition. These included the cross-section shape in the upstream lock approach channel, the distance between the lock wall and the first spillway gate, the number of openings in the ported guard...
Topics: DTIC Archive, Copeland, Ronald R, ARMY ENGINEER WATERWAYS EXPERIMENT STATION VICKSBURG MS...
Two architectural approaches have dominated the field of optical computing. The first approach uses integrated optics to connect logic gates in arbitrary configurations similar to a conventional computer. An optical computer built with this approach competes directly with a conventional computer. The approach is successful when it results in a computer which is more powerful and can be made more cheaply. The second approach makes use of two dimensional arrays of logic devices interconnected in...
Topics: DTIC Archive, Chipman, Russell A, ALABAMA UNIV IN HUNTSVILLE DEPT OF PHYSICS, *OPTICAL EQUIPMENT,...
This thesis investigated the electromagnetic scattering from conducting, lossless dielectric, and lossy dielectric (absorber) pyramids. The backscatter from pyramids was measured and a time gate was applied to isolate the scattering from the tips. The measured results were compared to predictions from an approximate Uniform Theory of Diffraction (UTD) solution for scattering by a dielectric corner. The accuracy of the corner diffraction solution was found to be dependent on the polarization of...
Topics: DTIC Archive, Tyson, Albert D , IV, AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF...
The paper presents, development on GaAs computers and an approach to designing GaAs computers.
Topics: DTIC Archive, Wang, Qiao-yu, FOREIGN AEROSPACE SCIENCE AND TECHNOLOGY CENTER WRIGHT-PATTERSON AFB...
During this reporting period, the effort was primarily directed toward increasing the power output per unit of gate width and exploiting the previously developed direct selective ion implantation technology to design, fabricate and evaluate successive iterations of multistage monolithic power amplifiers. Improvements in GaAs materials and FET device design and processing have resulted in increases in FET output power per unit of gate width. Values of 0.7 watts per mm have been achieved,...
Topics: DTIC Archive, Oakes, J G, WESTINGHOUSE DEFENSE AND ELECTRONICS CENTER BALTIMORE MD SYSTEMS...
Optical devices and circuits can be synthesized from specified transmission characteristics using the methods of inverse scattering. Both analytical and numerical inverse scattering techniques that have been developed to synthesize optical devices and circuits are discussed. Large-scale guided-wave structures such as optical logic gates and optical interconnects can be synthesized using the techniques discussed here. Finite difference based frequency domain analysis technique has been used to...
Topics: DTIC Archive, Tamil, Lakshman S., TEXAS UNIV AT DALLAS RICHARDSON CENTER FOR APPLIED OPTICS,...
While good gate level and register transfer level digital simulators exist, one can not easily integrate the two due to their inherent limitations. A given simulation can not be described partially in gate level and partially in a higher level. A solution is to create a functional level preprocessor and a library of functional device models linked to a gate level simulator's input language. This permits the mixing of behavioral models with gate level models in the same system structure. The...
Topics: DTIC Archive, Raeth,Peter G, AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING,...
The Probabilistic Multi-hypothesis Tracking (PMHT) algorithm has been successfully applied to a simulated multistatic active sonar data set that contains a single constant velocity target in varying amounts of clutter [1]. The simulated data set in that study contained negligible registration error was therefore easily registered to a common frame of reference for use in a centralized tracking architecture. Unknown sensor registration error can degrade the performance of any multi-static...
Topics: DTIC Archive, NAVAL UNDERSEA WARFARE CENTER DIV NEWPORT RI, *PROBABILITY, *TRACKING, *TARGET...
In this report we have discussed the characterization of the power FETs procured for this program and failure analysis of low noise devices, including wire bonding failures and environmental stress test failures. A method of etching gold while leaving the underlying refractory metals relatively unaffected was explained. An analysis of the Type A-6 low noise FET was given, in which a failure mode was discussed that involved possible channel doping compensation. Results were then presented on...
Topics: DTIC Archive, Bowman,Lawrence S, HUGHES AIRCRAFT CO TORRANCE CALIF, *GALLIUM ARSENIDES, *FIELD...
Results of pulsed-power burnout testing the Fairchild 9046 quad dual-input nand gate and the Amelco 6041 three-input nand gate showed the circuits to be vulnerable to junction burnout for pulses of less than 100 V and pulse widths on the order of 100 nsec. Calculations based on Wunsch-Bell junction burnout theory showed good agreement with the experimental results. Sample calculations applying Wunsch-Bell theory to integrated circuits are given.
Topics: DTIC Archive, Vandre, R H, AEROSPACE CORP EL SEGUNDO CA LAB OPERATIONS, *INTEGRATED CIRCUITS,...
For complete abstract, see ADA100583.
Topics: DTIC Archive, Mead, Carver, CALIFORNIA INST OF TECH PASADENA, *INTEGRATED CIRCUITS, *STANDARDS,...
The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication...
Topics: NASA Technical Reports Server (NTRS), SILICON CARBIDES, POLYMORPHISM, TRANSISTORS, INTEGRATED...
We propose a scheme to perform arbitrary unitary operations on a single electron-spin qubit in a quantum dot. The design is solely based on the geometrical phase that the qubit state acquires after a cyclic evolution in the parameter space. The scheme uses ultrafast linearly chirped pulses providing adiabatic excitation of the qubit states and the geometric phase is fully controlled by the relative phase between pulses. The analytic expression of the evolution operator for the electron spin in...
Topics: DTIC Archive, ARMY RESEARCH LAB ADELPHI MD SENSORS AND ELECTRON DEVICES DIRECTORATE, *ELECTRONS,...
This report contains technical details on several popular types of smart pixels including Self Electro-optic Effect Devices (SEEDs), Surface Emitting Laser Logic Devices (CELLs), Double Heterostructure Opto-electronic Switches (DOES), Diode Laser Logic (DLL), Laser-Quenched Laser (LQL) Optical Gates. Of these devices, the SEED is the most developed and considerable detail is included on the R,D,S, and F SEEDs. The CELL devices consist of Heterostructure Bipolar Transistors (HPTs) integrated...
Topics: DTIC Archive, Parker, M. A., ROME LAB GRIFFISS AFB NY, *ELECTROOPTICS, *LOGIC CIRCUITS, *OPTICAL...
Ti/Pt metal layers are an integral part of the gate stack of many III-V field-effect transistors (FETs). These devices are known to be affected by H(sub 2) exposure. In this study, Auger Electron Spectroscopy (AES) measurements of Ti/Pt bilayers are correlated with electrical measurements of InAlAs/InGaAs/InP FETs fabricated with Ti/Pt/Au gates. The PET measurements show that H(sub 2) exposure shifts the device threshold voltage through the piezoelectric effect. AES reveals the formation of...
Topics: DTIC Archive, Blanchard, R. R., MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS,...
Self-aligned polysilicon gate technology was applied to double-diffused MOS (DMOS) construction in a manner that retains processing simplicity and effectively eliminates parasitic overlap capacitance because of the self-aligning feature. Depletion mode load devices with the same dimensions as the DMOS transistors were integrated. The ratioless feature results in smaller dimension load devices, allowing for higher density integration with no increase in the processing complexity of standard MOS...
Topics: NASA Technical Reports Server (NTRS), GATES (CIRCUITS), INTEGRATED CIRCUITS, METAL OXIDE...
This is the first annual technical report of progress toward a crosstie random access memory. This marks a recent change in direction from the previously studied serial access memory. The more pertinent information learned from the serial memory approach which applies to the CRAM is repeated here. However, previous reports contain much additional important information and can be obtained by writing to the authors. It was realized at NSWC that the crosstie memory elements could be reorganized...
Topics: DTIC Archive, Schwee,Leonard J, NAVAL SURFACE WEAPONS CENTER SILVER SPRING MD, *NONVOLATILE...
An illustrative embodiment of the invention includes apparatus which simultaneously produces both direct delta modulation and pulse code modulation. An input signal, after amplification, is supplied to a window comparator which supplies a polarity control signal to gate the output of a clock to the appropriate input of a binary up-down counter. The control signals provide direct delta modulation while the up-down counter output provides pulse code modulation.
Topics: NASA Technical Reports Server (NTRS), DELTA MODULATION, PULSE CODE MODULATION, AMPLIFICATION,...
A field effect transistor with metal gate suspended above the gate insulator has been fabricated. Fluid samples can freely penetrate into the gap formed between the metal and the insulator. If the molecules carry an electrical dipole, they will alter the surface potential on these two materials giving rise to a change in the drain current of the transistor. Our preliminary results confirm this mechanism for dipolar molecules such as methanol and methylene chloride. (Author)
Topics: DTIC Archive, Blackburn,Gary F, UTAH UNIV SALT LAKE CITY DEPT OF BIOENGINEERING, *Field effect...
Process development work for a hardened N+ polysilicon-gate CMOS/SOS process has demonstrated that it is possible to make functional 4K CMOS/SOS static RAMs that are hard to 5 x 10 to the 5th power rads without the implementation of special hardened circuit design techniques. Present circuit probe yields are low, limited by the lack of a hardened low-temperature contoured field oxide. Independent research has shown that a hardened reflow process is possible for such field oxides. Development of...
Topics: DTIC Archive, Hughes,G W, RCA LABS PRINCETON NJ, *GATES(CIRCUITS), *INTEGRATED CIRCUITS, *SILICON,...
The superior properties of InP material, c.g., higher peak electron drift velocity, thermal conductivity, and breakdown field, to GaAs have made it an attractive alternative for high performance applications in microwave and millimeter-wave regimes as well as high-speed digital circuits. Recently, a high-efficiency InP MISFET has demonstrated 4.5 watts output power with 4 dB gain and 46% power-added efficiency at 9.7 GHz by Messick et al. These impressive results clearly confirmed the promising...
Topics: DTIC Archive, Shey, A J, NAVAL OCEAN SYSTEMS CENTER SAN DIEGO CA, *CIRCUITS, *SEMICONDUCTORS,...
This Final Report describes investigations of the capabilities and limitations of several digital ultrasonic NDE techniques for imaging defects in advanced aerospace materials. The goal of these investigations was to determine the feasibility and practicality of transitioning these techniques from the laboratory to field use. Studies of new digital data collection techniques, signal processing, image enhancement and image restoration techniques revealed that their use can significantly improve...
Topics: DTIC Archive, Frock, Brian G, DAYTON UNIV OH RESEARCH INST, *AEROSPACE CRAFT, *NONDESTRUCTIVE...
WELSE S.p.A., Genoa, Italy has developed an Antisubmarine Warfare Area System (ASWAS) as an underwater defense system for naval bases, coastal installations, harbors, offshore platforms, straits, and sea areas. The ASWAS was designed to operate as an underwater gate against possible attacks from submarines and minisubmarines. It uses a barrier of sensors deployed on the sea bottom and linked via cable to an ashore-based control station. The system is able to interdict the access to naval bases...
Topics: DTIC Archive, OFFICE OF NAVAL RESEARCH EUROPEAN OFFICE FPO NEW YORK 09510, *CONTROL, ACTIVATION,...
As detailed in the previous reports, the necessary current density (60 A/sq cm), linear current density (3 mA/mm) and stability ( 2 days) to meet the contract goals (at least theoretically) have been achieved. The next step is to fabricate three terminal devices to demonstrate the remaining contract goal - a one GHz current gain cutoff frequency (f sub t). Unlike the traditional Spindt-type of emitter where, because of the circularly symmetric nature of the gate, the electrons can be emitted to...
Topics: DTIC Archive, VARIAN ASSOCIATES INC PALO ALTO CA, *CURRENT DENSITY, *EMITTERS, FREQUENCY,...
Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of alpha-particle hits or single event upsets (SEUs) in CMOS standard cell based synchronous sequential VLSI circuits. The speed comes from...
Topics: DTIC Archive, Cha, Hungse, ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB, *VERY LARGE SCALE...
The breakdown voltage in GaAs field effect transistors (FET) has been the fundamental limitation of power performance in these devices. Previous studies have identified the high electric field at the drain edge of the gate metal as the cause of breakdown. At the start of this project, we successfully demonstrated that a low-temperature-grown GaAs (LTG-GaAs) surface 'insulator' dramatically improved the breakdown voltage in a GaAs MISFET. Subsequent device studies have concentrated on the use of...
Topics: DTIC Archive, Mishra, Umesh K, CALIFORNIA UNIV SANTA BARBARA DEPT OF ELECTRICAL AND COMPUTER...
Area and delay estimates facilitate effective decision-making ability in high level synthesis. Current estimation techniques focus on modeling the layout result and fail to deliver timely or accurate estimates. This thesis presents a novel approach to deriving these area and delay estimates by modeling the actions and activities of the layout tool, rather than the layout result. This approach uses machine learning techniques to analyze the input-to-output relationships that result from applying...
Topics: DTIC Archive, Gelosh, Donald S., AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH, *COMPUTER AIDED...
The dynamic dissipation of CMOS circuits is becoming a major concern for designers of personal information systems and large computers. Here, we present new CMOS logic families, including Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically, thus having a power consumption that drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The technique in these new families rely on explicitly...
Topics: DTIC Archive, Younis, Saed G., MASSACHUSETTS INST OF TECH CAMBRIDGE ARTIFICIAL INTELLIGENCE LAB,...
Statement of Problem Studied and Results: This is a collaborative project between the University of Oklahoma (OU) and Boston University (BU) studying the possibility of producing an infrared detector which integrates the function of a spectrometer. The successful implementation of these ideas could lead to a smart infrared detector. The system we are studying as a prototype is the two-dimensional electron system (2DES) GaAs-AlGaAs modulation-doped heterostructure system patterned with very...
Topics: DTIC Archive, Furneaux, John E., OKLAHOMA UNIV NORMAN, *SEMICONDUCTORS, *INFRARED DETECTORS, TEST...
Silicon carbide is a wide bandgap semiconductor that is well suited for high power, high temperature electronic devices due to its remarkable electronic and thermal properties. Photosensitive devices in the 6H polytype of SiC have also been demonstrated, showing high sensitivity in ultraviolet wavelengths near 270 nm. Furthermore, the native oxide on SiC is silicon dioxide, meaning that SiC can be thermally oxidized to form a high quality gate dielectric, making metal-oxide-semiconductor (MOS)...
Topics: DTIC Archive, Cooper, James A., Jr., PURDUE UNIV LAFAYETTE IN DEPT OF ELECTRICAL ENGINEERING,...
Field emitter array structures are under consideration as the gated electron source in inductive-output amplifiers currently being designed, due to the potential for spatio-temporal modulation at the cathode surface. Emission gating of electron beams places stringent demands on the cathode structures where modulation occurs. In spite of the intense interest generated by these structures, a simple analytical treatment of their properties has not been forthcoming. In this work, we present a...
Topics: DTIC Archive, Jensen, K. L., NAVAL RESEARCH LAB WASHINGTON DC, *FIELD EMISSION, *MICROELECTRONICS,...
Topics: DTIC Archive, Bishop, Dwight E., BOLT BERANEK AND NEWMAN INC CANOGA PARK CA, *ACOUSTIC MEASUREMENT,...
The programmable logic array is one of the most fascinating and fast developing areas of technology. Field programmable gate arrays are becoming prevalent in design as the density of the gate arrays goes up. In this thesis study, a fast encoding/decoding algorithm, Extended Golay Coding, is implemented in Xilinx XC4000 family programmable gate array (FPGA) architecture. The encoder/decoder is designed using the Xilinx XACT tool with the Mentor Graphics schematic capture Design Architect (DA)...
Topics: DTIC Archive, Sary, Mehmet, NAVAL POSTGRADUATE SCHOOL MONTEREY CA, *SIGNAL PROCESSING, *CODERS,...
In this thesis, the theory behind a separate-winding excitation direct current (DC) motor and profile of the motor's torque versus rotor speed is studied. The torque versus rotor speed profile results are predictably linear at a given armature voltage. Output torque of a separate-winding excitation DC motor is proportional to the armature current. From this theory, a program was written in Simulink with Xilinx embedded software to enable a user to command the DC motor torque through a Graphical...
Topics: DTIC Archive, NAVAL POSTGRADUATE SCHOOL MONTEREY CA, *DYNAMOMETERS, *ELECTRIC MOTORS, *DIRECT...
We present a nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the resonator's operating parameters. The device can access one of two stable steady states, according to a specific logic function this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the...
Topics: DTIC Archive, BOSTON UNIV MA DEPT OF PHYSICS, *LOGIC CIRCUITS, GATES(CIRCUITS), NOISE, RESONATORS,...
Memristive devices have become very popular in recent years due to their potential to dramatically alter logic processing in CMOS circuitry. Memristive devices function as electrical potentiometers, allowing for such diverse applications as memory storage, multi-state logic, and reconfigurable logic gates. This research covered the fabrication, characterization, and modeling of Al/CuxO/Cu memristive devices created by depositing Al top electrodes atop a CuxO film grown using plasma oxidation to...
Topics: DTIC Archive, STATE UNIV OF NEW YORK AT ALBANY, *CIRCUITS, *PLASMAS(PHYSICS),...
During the past 3 years, we have exploited the memristor's enabling potentials for designing intelligent machines with learning and adaptive capabilities. We have conducted an in-depth study of the nonlinear dynamics of several ion-channels which underpins the biological basis of life itself, where voltage-gated ion channels, with their complex biochemical synaptic dynamics, are memristors. We have discovered that the Hodgkin-Huxley axon is made of memristors, in addition to conventional...
Topics: DTIC Archive, CALIFORNIA UNIV BERKELEY, *ARTIFICIAL INTELLIGENCE, *AXONS, *GATES(CIRCUITS), *IONS,...
The purpose of this thesis is to design and test a fault tolerant reduced instruction set computer processor running a subset of the multiprocessor without interlocked pipelined stages instruction set. This processor is implemented on a field programmable gate array (FPGA) and will be used as the foundation for a payload processor on a cube satellite developed at the Naval Postgraduate School. This thesis begins by considering the radiation effects present in the space environment and the...
Topics: DTIC Archive, NAVAL POSTGRADUATE SCHOOL MONTEREY CA, *COMPUTER PROGRAMMING, *FIELD PROGRAMMABLE...
Replacing the mushroom gate profile with a better collimated evaporation has resulted in FETs with equivalent performance. Balanced FETs have been fabricated with equivalent dc performance to their unbalanced counterparts, but with inferior rf performance. (Author)
Topics: DTIC Archive, Bandy,S, VARIAN ASSOCIATES INC PALO ALTO CA SOLID STATE LAB, *Field effect...
The design, fabrication, and device characteristics of a rectangular gate MOSBJT are described. The characteristics are explained in terms of the merged character of the device and the self-biasing effects of the distributed collector current on the collector channel/base bias. For sufficiently high collector currents a portion of the collector channel is self-biased resulting in a decreased beta. The active area of the device is then controlled by the device operating bias. (Author)
Topics: DTIC Archive, Okada,David, HAWAII UNIV AT MANOA HONOLULU DEPT OF ELECTRICAL ENGINEERING, *Junction...
The buildup of interface states in Al-Si02-Si metal oxide semiconductor capacitors following exposure to pulsed electron beam irradiation has been previously shown to be a two-stage process. In the present work, we further examined the buildup by varying the polarity and magnitude of the field across the oxide during the two stages of the buildup. Specifically, both early (.000001 to 1 s) and late (1 to 10000 s) time regimes are explored. An empirical model of radiation-induced interface states...
Topics: DTIC Archive, Winokur,Peter S, HARRY DIAMOND LABS ADELPHI MD, *MODELS, *GATES(CIRCUITS), *BULK...
The Weinberger Array Generator (WAG) is a tool for implementing random logic. Boolean equations are input, and a layout description of gates and wires (the circuit) realizing the equations is output. In the above aspects, WAG is similar to a PLA generator. The main difference is that the Weinberger array structure allows many levels of logic, with complex gates such as NAND-of-ORs; whereas a PLA structure allows only two levels of logic, with no gates more complex than NORS. We shall describe...
Topics: DTIC Archive, Steiglitz,Kenneth, PRINCETON UNIV NJ DEPT OF COMPUTER SCIENCE, *ALGORITHMS, *GRAPHS,...
We have, in this period, developed a microcomputer-based optical linear transformation processing technique. The technique utilizes a systolic array processing method to perform various types of linear transformations, such as discrete Fourier transformation, discrete Hilbert transformation, discrete chirp-Z transformation and many others. By partially parallel addressing two magneto-optic spatial light modulators (MOSLM), this proposed system would offer high speed and parallel processing...
Topics: DTIC Archive, Yu, Francis T, PENNSYLVANIA STATE UNIV UNIVERSITY PARK DEPT OF ELECTRICAL...
N-channel Polysilicon gate FETs have been fabricated in a laser-melted silicon-on-SiO2-on PLZT structure. Channel mobilities in the devices are 50 sq. cm/Vs with threshold and source-to-drain breakdown voltages as expected from the dielectric thickness and channel doping used. PLZT wafers subjected to the same processing temperatures still show an excellent electro-optic effect. Keywords: Polysilicon gate, Field effect transistors, Ferroelectric materials.
Topics: DTIC Archive, Burgener, M L, NAVAL OCEAN SYSTEMS CENTER SAN DIEGO CA, *FERROELECTRIC MATERIALS,...
