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ACSP * Analog Circuits And Signal Processing 



Bupesh Pandita 



Oversampling A/D 
Converters with 
Improved Signal 
Transfer Functions 



^ Springe 



Oversampling A/D Converters with Improved 
Signal Transfer Functions 



ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES 
Consulting Editor: Mohammed Ismail. Ohio State University 



For further volumes: 

http://www. springer, com/series/73 8 1 



Bupesh Pandita 



Oversampling A/D 
Converters with Improved 
Signal Transfer Functions 



4y Spri 



ringer 



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Bupesh Pandita 

AMD 

Markham, ON, Canada 

bupesh.pandita@amd.com 



ISBN 978- 1 -46 14-0274-9 e-ISBN 978-1 -46 14-0275-6 

DOI 10.1007/978-1-4614-0275-6 

Springer New York Dordrecht Heidelberg London 

Library of Congress Control Number: 2011934486 

© Springer Science+Business Media, LLC 2011 

All rights reserved. This work may not be translated or copied in whole or in part without the written 

permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, 

NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in 

connection with any form of information storage and retrieval, electronic adaptation, computer software, 

or by similar or dissimilar methodology now known or hereafter developed is forbidden. 

The use in this publication of trade names, trademarks, service marks, and similar terms, even if they 

are not identified as such, is not to be taken as an expression of opinion as to whether or not they are 

subject to proprietary rights. 

Printed on acid-free paper 

Springer is part of Springer Science+Business Media (www.springer.com) 



Abstract 



This book proposes a low-IF receiver architecture suitable for the realization of 
single-chip receivers. To alleviate the image-rejection requirements of the front- 
end filters an oversampling complex discrete-time AE ADC with a signal-transfer 
function that achieves a significant filtering of interfering signals is proposed. 
A filtering ADC reduces the complexity of the receiver by minimizing the require- 
ments of analog filters in the IF digitization path. Discrete-time AE ADCs have 
precise resonant frequency and clock frequency ratios and, hence, do not require the 
calibration or tuning that is necessary in the case of continuous-time AS modulator 
implementations. This feature makes the proposed discrete-time AE ADC ideal for 
multistandard receiver applications. 

The AE modulator signal-transfer function (STF) and noise-transfer function 
(NTF) have been designed using complex filter routines based on classical filter 
design procedures. With a filtering STF and stop band attenuation greater than 
30 dB, the AS modulator reduces intermodulation of the desired signal and 
the interfering signals at the input of the quantizer, and also avoids feedback of 
the high-frequency interfering signals at the input of the modulator. 

The reported complex AE ADC is intended for DTV receiver applications. 
With a maximum intended sampling frequency of 128 MHz and an OSR of 16, 
the ADC has been designed to support a maximum DTV signal bandwidth of 
8 MHz. Except for a somewhat reduced maximum sampling frequency, the test 
results of the prototype complex AE modulator are very close to the simulated 
results. The IC achieved 70.9 dB SNDR over a 6 MHz band centered around 
3 MHz. The image rejection ratio (IRR) of the AE ADC was measured to be greater 
than 65 dB. The measurement results confirm the filtering characteristics of the ADC. 
The fabricated chip consumes 177 mW and occupies a silicon area of 2.15 mm 2 . 



Contents 



1 Introduction 1 

1 . 1 Motivation and Background 1 

1.2 Digital TV (DTV) Receivers 4 

1.3 Outline 7 

References 8 

2 A Low-IF Complex AX ADC-Based DTV Receiver 11 

2. 1 Background 12 

2.1.1 Bandpass Signals 12 

2.1.2 Complex Signals 12 

2.1.3 Complex Filters 13 

2. 1 .4 Mismatch in Complex Filters 14 

2.1.5 Real Mixing vs. Complex Mixing 15 

2. 1 .6 Complex Transfer Function Design 17 

2.2 A Low-IF DTV Receiver Architecture 18 

2.3 The 'Interfering Signals' Problem in Wireless Receivers 20 

2.4 Approaches to Filtering Interfering Signals in AE ADC 

Based Receivers 22 

2.4.1 Filtering Interfering Signals in the Digital Domain 22 

2.4.2 Filtering Interfering Signals in the Analog Domain 22 

2.4.3 Filtering Interfering Signals with a Filtering STF 23 

2.5 Specifications for a Complex AE ADC Used 

in a DTV Receiver 28 

2.5.1 Mismatch and Image Rejection Requirements 

of the Low-IF Complex AS ADC 30 

References 32 

3 A Complex AS Modulator with an Improved STF 35 

3. 1 AS Modulator Transfer Functions 35 

3.2 NTF-STF Design Trade-Off 37 



Contents 

3.3 Background 42 

3.3.1 The \L \ 1 Norm and its Impact on the NTF Poles 42 

3.3.2 The Loss Function L(Z) 44 

3.4 STF-NTF Co-Design Optimization Algorithm 

for the Design of Real AS Modulators 46 

3.5 Power and Performance Analysis of the Proposed 

Real AS Modulator 49 

3.5.1 Power Comparison 52 

3.5.2 Sensitivity to Intermodulation Due 

to DAC Non-linearity 53 

3.5.3 Stability Comparison 56 

3.6 The STF-NTF Co-Design Optimization Algorithm 

for the Design of Complex AS Modulators 60 

3.7 Power and Performance Analysis of the Proposed 

Complex AS Modulator 68 

3.7.1 AS Modulator with Unity STF 68 

3.7.2 Power Comparison 70 

3.7.3 Sensitivity to Intermodulation Due 

to DAC Non-linearity 72 

3.7.4 Comparison with a Discrete-Time Receiver 73 

3.7.5 Comparison with an SC + FeedForward ADC 

with Unity STF 79 

3.8 Decimation for Complex AS Modulators 83 

3.9 Advantages of the Proposed AS Modulator Architecture 83 

References 85 

Architectural-Level Design of the Experimental AS Modulator 87 

4. 1 Background 87 

4.2 Mismatches in a Complex AS Modulator 89 

4.2. 1 An Improved Complex AS Modulator 97 

4.3 The Switched-Capacitor Architecture 101 

4.3.1 Complex Integrators 101 

4.3.2 Dynamic Range Scaling 101 

4.3.3 Multibit Quantization 101 

4.3.4 Multilevel DAC 104 

4.3.5 Realizing the Feedins 104 

4.3.6 The Complete Fully-Differential SC Architecture 1 05 

4.3.7 The Clocking Scheme 107 

4.4 System-level Behavioral Simulations 107 

4.4.1 Capacitor Sizing 107 

4.4.2 Clock- Jitter 117 

4.4.3 Opamp Nonidealities 119 

4.4.4 Switch On-Resistances 122 

References 122 



Contents ix 

5 Integrated Circuit Implementation 125 

5. 1 The Complete Fourth-Order SC-Modulator 125 

5.2 Clock Generator 127 

5.3 Sampling Switches 129 

5.4 Operational Amplifier 129 

5.4. 1 Main Stage 129 

5.4.2 Bias Stage 130 

5.4.3 Gain-Boosting Amplifiers 132 

5.4.4 Device Sizes 132 

5.4.5 SC CMFB Circuit 133 

5.5 Quantizers 134 

5.5.1 Comparator 137 

5.5.2 Resistor Ladder 139 

5.6 Layout 139 

5.6.1 Capacitor 140 

5.6.2 Switches 141 

5.6.3 Comparators 142 

5.6.4 Amplifiers 142 

5.6.5 The Resistor Ladder 144 

5.7 Substrate and Supply Noise Decoupling 145 

5.8 The Integrated Circuit 146 

5.8. 1 Pins 146 

5.9 The Test Set-Up 148 

5.10 The PCB Design 150 

5.1 1 Test Results 152 

5.12 Performance Summary 156 

5.13 Explaining the Differences Between the Measured 

and the Simulated Results 158 

5.13.1 Instability and SNDR Degradation 

with Higher Frequencies 158 

5.13.2 Difference Between the Measured 

and the Desired STF 161 

5.14 Power Dissipation 164 

References 164 

6 Conclusions 167 

6. 1 Contributions 167 

6.2 Suggestions for Future Work 168 

6.2.1 Continuous-time Modulator Architectures 1 68 

6.2.2 Frequency-Translating Complex AE Modulator 169 

6.2.3 Demodulator Architectures 169 

Appendix A 171 

Modulator Design Example 171 

Index 185 



List of Figures 



Fig. 1 . 1 DT V receiver front-end block diagram 4 

Fig. 1.2 Single-conversion DTV receiver block diagram example 5 

Fig. 1.3 Double-conversion DTV receiver block diagram example 5 

Fig. 1 .4 Double-conversion DTV receiver block diagram 6 

Fig. 1 .5 Single-conversion DTV receiver architecture 7 

Fig. 2. 1 Spectrum of a bandpass signal 12 

Fig. 2.2 Spectrum of real and complex signals 13 

Fig. 2.3 Realizing a complex filter with real filter blocks 13 

Fig. 2.4 (a) Complex filter constructed from non-ideal components, 
and (b) Signal flow diagram of a complex filter A(z), 

showing common-mode and differential error components 14 

Fig. 2.5 Mixing a real signal with a sinusoid: (a) mixer input 

spectra, (b) mixer output spectrum 16 

Fig. 2.6 Mixing a real signal with a complex exponential 16 

Fig. 2.7 Low pass filter methodology used to realize symmetric 
complex filter. Real lowpass filter: (a) Pole-zero 
constellation, (b) Magnitude Response. Complex bandpass 
filter designed by rotation of the lowpass pole-zeros: 

(c) Pole-zero constellation., (d) Magnitude Response 18 

Fig. 2.8 A quadrature-IF system using a complex Low-If 

AS modulator 19 

Fig. 2.9 (a) AS modulators with distributed feedforward 

summation, (b) AE modulator with distributed feedback. 
(c) Modified distributed feedforward AE modulator 

with feed-ins to introduce STF zeros 24 

Fig. 2.10 NTFs and STFs for the AS modulators with distributed 

feedforward and distributed feedback: (a) NTF, (b) STF 25 

Fig. 2. 1 1 (a) Modified feedback AE modulator, (b) STFs 

for the modulator architectures 27 



xii List of Figures 

Fig. 2.12 AE modulator with additional low pass and high pass 
filters in forward and feedback paths to implement 
a filtering STF 27 

Fig. 2.13 AE modulator with a notch in the stopband to implement 

a filtering STF 28 

Fig. 2.14 The interfering signals for DVB-T with a third order complex 

bandpass filter at the input of the AS ADC 29 

Fig. 2.15 A complex AE modulator structure with mismatch 

in gain elements 31 

Fig. 3.1 A complex AE modulator structure 36 

Fig. 3.2 Structure for the proposed fourth-order AE modulator 

with input feed-ins to realize zeros in the STF 37 

Fig. 3.3 Effect of e on the attenuation characteristics of a filter 38 

Fig. 3.4 Plot of the magnitude of the fourth-order Chebyshev filter 

for different values of the stop-band attenuation parameter L . . . 41 

Fig. 3.5 Movement of the poles of H(s) for increasing values 

of the attenuation parameter L 41 

Fig. 3.6 Root-locus of the equation (3.8) as the filter attenuation, 

L, varies 42 

Fig. 3.7 (a) NTF magnitude for different values of the \L\ l norm, 
(b) movement of the NTF poles with an increase 
in the \L\ l norm 44 

Fig. 3.8 A flow chart for filter designing with defined stop-band 

zeros and passband response type 45 

Fig. 3.9 Real Transfer functions for SQNR=88 dB. (a) NTF 

magnitude response, (b) pole-zero constellation for the 
non-optimized NTF, (c) pole-zero constellation for the 
optimized NTF, (d) STF magnitude response, (e) pole-zero 
constellation for the non-optimized STF, (f) pole-zero 
constellation for the optimized STF 47 

Fig. 3.10 Real Transfer functions for SQNR=101 dB. (a) NTF 
magnitude response, (b) pole-zero constellation for the 
non-optimized NTF, (c) pole-zero constellation for the 
optimized NTF, (d) STF magnitude response, (e) pole-zero 
constellation for the non-optimized STF, (f) pole-zero 
constellation for the optimized STF 48 

Fig. 3.1 1 The proposed AE modulator modified to realize 

a fourth-order real AE modulator 50 

Fig. 3.12 The STF and NTF the proposed AE modulator without 

feed-ins: (a) NTF magnitude gain, (b) STF magnitude gain 50 

Fig. 3.13 The proposed AE modulator modified to realize 

a fourth-order real AE modulator with input feed-ins 

to realize zeros in the STF 51 



List of Figures xiii 

Fig. 3.14 The STF and NTF the proposed AS modulator with feed-ins 
to implement STF zeros: (a) NTF magnitude gain, (b) STF 
magnitude gain. Pole-Zero plot of: (c) NTF, (d) STF 52 

Fig. 3.15 Histogram plots of the integrator outputs for the modulator 

with unity STF (FFADC) 53 

Fig. 3.16 Histogram plots of the integrator outputs for the modulator 

with filtering STF (FADC) 54 

Fig. 3.17 Output PSD plot of the real AZ modulators with DAC 

mismatch = ±0.5% for a weak desired signal (f ) at —46 

dBFS and strong interferers (fj and f 2 ) at —6 dBFS 55 

Fig. 3.18 Histogram plots of the SNDR for the FFADC and FADC 

for DAC mismatch = ±0.1% 55 

Fig. 3.19 Histogram plots of the SNDR for the FFADC and FADC 

for DAC mismatch = ±0.5% 56 

Fig. 3.20 PSD plots at the integrator outputs for the feedforward 

ADC with unity STF (FFADC) 57 

Fig. 3.21 PSD plots at the integrator outputs for the ADC 

with filtering STF (FADC) 58 

Fig. 3.22 Response of the feedforward AE modulator ADC with unity 

STF to an in-band signal and out of band interferer 59 

Fig. 3.23 Response of the feedforward AE modulator ADC with filtering 

STF to an in-band signal and out of band interferer 59 

Fig. 3.24 Design of the STF-NTF using the optimization algorithm 
for |L|j= 3.5: (a) NTF magnitude gain, (b) STF magnitude 
gain, (c) NTF pole-zero plot, (d) STF pole-zero plot, 
(e) PSD plot of a complex AE modulator with STF 
and NTF transfer-functions as shown in (a) and (b) 62 

Fig. 3.25 NTF and STF designed for different values of the |L|j norm: 
(a) NTF magnitude plot, (b) in-band zoom-in of the NTF, 
(c) STF magnitude plot 63 

Fig. 3.26 Design of the STF-NTF using the optimization algorithm 
for |L|j= 6.5: (a) NTF magnitude gain, (b) STF magnitude 
gain, (c) NTF pole-zero plot, (d) STF pole-zero plot, (e) PSD 
plot of a complex AE modulator with STF and NTF transfer- 
functions as shown in (a) and (b) 64 

Fig. 3.27 Transfer functions for SQNR=101 dB. (a) NTF 
magnitude response, (b) pole-zero constellation 
for the non-optimized NTF, (c) pole-zero constellation 
for the optimized NTF, (d) STF magnitude response, 

(e) pole-zero constellation for the non-optimized STF, 

(f) pole-zero constellation for the optimized STF 65 



xiv List of Figures 

Fig. 3.28 Transfer functions for SQNR=94 dB. (a) NTF 
magnitude response, (b) pole-zero constellation 
for the non-optimized NTF, (c) pole-zero constellation 
for the optimized NTF, (d) STF magnitude response, 

(e) pole-zero constellation for the non-optimized STF, 

(f) pole-zero constellation for the optimized STF 66 

Fig. 3.29 Transfer functions for SQNR=89 dB. (a) NTF 

magnitude response, (b) pole-zero constellation 

for the non-optimized NTF, (c) pole-zero constellation 

for the optimized NTF, (d) STF magnitude response, 

(e) pole-zero constellation for the non-optimized STF, 

(f) pole-zero constellation for the optimized STF 67 

Fig. 3.30 (a) a AE modulator topology with a unity STF, 

(b) Traditional AE modulator topology 68 

Fig. 3.31 Structure for a fourth-order AE modulator 

with a unity STF 69 

Fig. 3.32 Histogram plots of the integrator outputs 

for the feedforward modulator with unity STF 70 

Fig. 3.33 Histogram plots of the integrator outputs 

for the modulator with filtering STF 71 

Fig. 3.34 DAC output swings for 300 samples for the triple tone test 

inputs: (a) feedforward AE modulator with unity STF, 

(b) proposed FADC 72 

Fig. 3.35 PSD plot of the proposed complex AE modulator 

with a DAC mismatch = ±0.5% for a weak desired signal 

at —42.6 dBFS and a strong interferer at —2.6 dBFS 72 

Fig. 3.36 Histogram plots of the integrator outputs for the modulator 

with filtering STF for the defined test input 74 

Fig. 3.37 Histogram plot of the SNDR for the feedforward 

modulator with unity STF for DAC mismatch = ±0.5% 75 

Fig. 3.38 Histogram plot of the SNDR for the feedforward modulator 

with unity STF with image zero for DAC mismatch = ±0.5% . 75 
Fig. 3.39 Histogram plots of the SNDR for the filtering 

ADC for DAC mismatch = ±0.5% 76 

Fig. 3.40 PSD plots for the test input with a DAC mismatch of ±0.5% 

(a) proposed complex AE modulator, (b) feedforward 

complex AE modulator with unity STF 77 

Fig. 3.41 A quadrature-IF system using a complex Low-IF AE 

modulator and a SC filter for channel filtering and selectivity. . . 78 
Fig. 3.42 (a) A third-order analog elliptic lowpass filter, 

and (b) SC lowpass filter 79 

Fig. 3.43 Frequency-response of the third-order switched capacitor 

filter: (a) the real filter, and (b) the complex filter response 80 



List of Figures xv 

Fig. 3.44 Amplifier output voltages response of the third-order 

switched capacitor filter 81 

Fig. 3.45 Frequency response of the noise transfer functions 

of the third-order switched capacitor filter 82 

Fig. 3.46 (a) A complex mixer for decimation of output 

bit-stream of complex AE modulator, (b) Frequency 

domain illustration of complex decimation 82 

Fig. 3.47 Complex demodulation of the complex AS 

modulator output 84 

Fig. 3.48 Architecture for a DTV receiver demodulator 84 

Fig. 4.1 Realizing a complex pole atp — p r + jp, using 

(a) a complex signal flow graph and (b) a two-input 

two-output real linear signal flow graph 88 

Fig. 4.2 (a) Signal flow diagram of a complex filter with mismatch, 

(b) Magnitude of the signal and image response for a single- 
pole complex filter with mismatch 89 

Realizing a complex pole atp = p r +./p, using two-input 

two-output non-ideal linear signal flow graph 90 

Linear model of a complex AE modulator showing 
the four transfer functions that decide the output 

of the modulator in the presence of mismatches 91 

(a) Transfer Functions -INTF and NTF, (b) Zoom 

of the INTF and the NTF 92 

Output spectrum: (a) Ideal spectrum (b) with 0.5% 
mismatch, (c) Zoom-in image quantization aliasing 
into signal-band 93 

(a) Transfer Functions - ISTF and STF, (b) Zoom-in 

of the ISTF and the STF 94 

Output spectrum with a signal-band tone and an image-band 

tone: (a) Ideal spectrum, (b) with 0.5% mismatch, 

(c) Zoom-in of image-tone aliasing into the signal-band 95 

Fig. 4.9 Transfer functions for the original modulator: (a) NTF 

and INTF variation for ±0.5% random mismatch, (b) STF 
and ISTF variation for ± 0.5% random mismatch. 
Histograms for (c) SNR and (d) IMR for the modulator 
with ± 0.5% random mismatch. Histograms 
for (e) SNR and (f) IMR for the modulator 

with ±0.25% random mismatch 96 

Fig. 4.10 The modified AZ Modulator: (a) NTF pole-zero plot, 

(b) NTF magnitude response, (c) Zoom-in of the signal-band 

and image-band 98 

Fig. 4. 1 1 Output spectrum of the modified modulator: (a) Ideal 

spectrum, (b) with 0.5% mismatch, (c) Zoom-in of image 
quantization aliasing into signal-band 99 



Fig. 


4.3 


Fig. 


4.4 


Fig- 


4.5 


Fig- 


4.6 


Fig. 


4.7 


Fig. 


4.8 



xvi List of Figures 

Fig. 4.12 Transfer functions for the modified modulator: (a) NTF 

and INTF variation for ±0.5% random mismatch, (b) STF 

and ISTF variation for ± 0.5% random mismatch. 

Histograms for (c) SNR and (d) IMR for the modulator 

with ± 0.5% random mismatch. Histograms for (e) SNR 

and (f) IMR for the modulator with ±0.25% 

random mismatch 100 

Fig. 4.13 Realization of a complex pole atp — p r +jpi using 

(a) a complex signal flow graph and (b) a two-input two- 
output real linear signal flow graph, (c) a fully-differential 
SC realization of the nondelaying complex integrator 102 

Fig. 4.14 Realization of a complex pole atp = p r +jpi using 

(a) a complex signal flow graph and (b) A two-input two- 
output real linear signal flow graph, (c) A fully-differential 
SC realization of the delaying complex integrator 103 

Fig. 4. 15 Architecture of the modified AS modulator 104 

Fig. 4.16 Multi level DAC 105 

Fig. 4.17 Single-ended representation of the SC implementation 

of the complex AS modulator 106 

Fig. 4.18 Clocking scheme- real-channel fourth-stage 

and the quantizer 107 

Fig. 4.19 Histograms for (a) SNR and (b) IMR for the proposed 
AS modulator with ±0.5% random coefficient 
mismatch in the DAC elements 108 

Fig. 4.20 Representation of noise sources in a complex 

integrator: (a) SC switch noise sources added to 

the complex signal flow graph, and (b) an equivalent 

noise representation in a signal-flow graph, including 

noise due to opamp devices 110 

Fig. 4.21 Noise sources added to the complex AS modulator Ill 

Fig. 4.22 Frequency responses of the noise transfer functions 112 

Fig. 4.23 Noise sources to model switch thermal noises 

in a complex coefficient 118 

Fig. 4.24 Complex-integrator realized with finitedc gain amplifiers 119 

Fig. 4.25 Simulated SNDRpeak versus maximum dc gain A 0max 

of the opamps in the experimental AS modulator 120 

Fig. 5.1 Single-ended representation of the SC implementation 

of the complex AS modulator 126 

Fig. 5.2 Two-phase nonoverlapping clock generator 127 

Fig. 5.3 Clock signals for the two phases, their early versions, 

and the inverted early phases 128 

Fig. 5.4 Operational amplifier main stage 130 

Fig. 5.5 Opamp loop-gain magnitude and phase response - first stage 

of the modulator 131 



List of Figures xvii 

Fig. 5.6 Master bias circuit for the modulator 132 

Fig. 5.7 Biasing circuit for the opamp 133 

Fig. 5.8 Circuit diagram of the NMOS device gain-boost amplifier 134 

Fig. 5.9 Circuit diagram of the PMOS device gain-boost amplifier 135 

Fig. 5.10 CMFB circuit for the opamp 136 

Fig. 5.11 Comparator block diagram 137 

Fig. 5.12 Comparator circuit diagram 138 

Fig. 5.13 Result of the Monte Carlo transient simulation performed 

to determine the input-referred offset of the comparator 139 

Fig. 5.14 Modulator floor-plan 140 

Fig. 5.15 Layout plan for the first stage of the modulator channel 141 

Fig. 5.16 DAC-switches and the input and feedback capacitor arrays 142 

Fig. 5.17 Comparator layout 143 

Fig. 5.18 Amplifier layout 143 

Fig. 5.19 Resistor ladder for the quantizers 144 

Fig. 5.20 Microphotograph of the fourth-order AS modulator 146 

Fig. 5.21 Pin assignment for the 80-pin CFP packaging of the chip 147 

Fig. 5.22 The test set-up for measuring the SNDR of the chip 148 

Fig. 5.23 Power-splitter-based ADC front-end 149 

Fig. 5.24 RC Polyphase filter designed to attenuate the image at 

the input of the test chip: (a) circuit diagram showing 

the component values, (b) frequency response 

of the three-stage polyphase filter 149 

Fig. 5.25 Master bias current generation for the chip 150 

Fig. 5.26 Component side of the four-layer PCB, which was designed 

for testing of the AS modulator chip 151 

Fig. 5.27 STF measured at a sampling frequency of 96 MHz 153 

Fig. 5.28 Output PSD measured with zero-input at a sampling 

frequency of 96 MHz 153 

Fig. 5.29 SNDR vs. input amplitude 154 

Fig. 5.30 Output PSD measured with —3 dbFS input at a sampling 

frequency of 96 MHz 154 

Fig. 5.3 1 Test set-up for measuring the IMR of the chip 155 

Fig. 5.32 Image rejection measurement with a three-stage polyphase 

filter at the input of the IC 155 

Fig. 5.33 Output spectrum of the chip for a full-scale two-tone test 156 

Fig. 5.34 Output PSD measured with —3 dbFS input at a sampling 

frequency of 100 MHz 158 

Fig. 5.35 Pole-zero plot of the AS modulator NTF 159 

Fig. 5.36 Monte Carlo simulation with a random variation of ± 2.5% 

in the B2 coefficient: (a) variation in the B2 coefficient. 

Output spectrum of the AS modulator for: (b) bin 89, 

(c) bin 45 of the B2 coefficient 160 



xviii List of Figures 

Fig. 5.37 Monte Carlo simulation with a random variation 

of ± 0.5% in the feed-in coefficients. STF magnitude 

with variation in the: (a) Fl coefficient, (b) F2 coefficient, 

(c) F3 coefficient, (d) F4 coefficient 161 

Fig. 5.38 Difference in the STF magnitude due to approximation 

to F 3 coefficient 162 

Fig. 5.39 STF magnitude plotted from the SIMULINK model 163 

Fig. A. 1 Mathematica code for initializing the coefficient 

determination for the STF and the NTF 172 

Fig. A.2 Mathematica code for determining the coefficients 

of the NTF 173 

Plot of the NTF in Mathematica 173 

Mathematica code for determining the coefficients 

of the STF 174 

Plot of the STF in Mathematica 175 

Simulink model of the complex AT, modulator 176 

Simulink model of the complex AE modulator 178 

Code for Monte Carlo simulation of the Simulink Model 179 

(a) Basic delaying SC integrator, (b) model of the delaying 

integrator used in SIMULINK 181 

Model of the delaying integrator used in SIMULINK 181 

An Example code for Noise Analysis of the Model 182 



Fig- 


A.3 


Fig- 


A.4 


Fig- 


A.5 


Fig. 


A.6 


Fig- 


A.7 


Fig. 


A.8 


Fig. 


A.9 


Fig- 


A.10 


Fig. 


A.ll 



List of Tables 



Table 3.1 SQNR vs. stop-band attenuation performance summary 49 

Table 3.2 SNDR Comparison for the FFADC and FADC 

for DAC Mismatch 56 

Table 3.3 NTF-STF performance summary 63 

Table 3.4 SQNR vs. stop-band attenuation performance summary 67 

Table 3.5 Simulated modulator performance with ±0.5% DAC 

mismatch 74 

Table 3.6 Required number of ADC bits 78 

Table 3.7 Flexible SC filter and ADC architecture 78 

Table 3.8 Component values for the switched-capacitor filter 81 

Table 4.1 Simulated modulator performance with ±0.5% mismatch 100 

Table 4.2 Implementation of the feed-ins and the feed-forward 

coefficients 105 

Table 4.3 PSDs for the noise sources referred to the sampling 

capacitor of the first stage of the modulator 116 

Table 4.4 PSDs for the noise sources referred to the sampling 

capacitor of the second stage of the modulator 116 

Table 4.5 Stage capacitor sizes and spreads 1 17 

Table 4.6 Opamp open-loop requirements 121 

Table 5.1 Device sizes in the clock generator 128 

Table 5.2 Master bias device sizes 135 

Table 5.3 Opamp and bias stage device sizes 136 

Table 5.4 NMOS and PMOS gain-booster device sizes 136 

Table 5.5 Sizes of the switches and capacitors in the CMFB circuit 137 

Table 5.6 Comparator device sizes 138 

Table 5.7 Logic-gate device sizes in the comparator 138 

Table 5.8 Summary of the simulated and measured performance 

of the prototype chip 156 



List of Tables 



Table 5.9 Measured performance of the IC 157 

Table 5.10 Comparison of the performance of some of the recently 

reported complex AZ modulators 157 

Table 5.11 Comparison of the filtering characteristics of some 

of the recently published modulators 157 

Table 5.12 Sensitivities of the NTF poles to the coefficient 

variations 159 

Table A.l Coefficient sizes 177 



Chapter 1 
Introduction 



1.1 Motivation and Background 

Many applications require receiver designs that are small and low power, and 
have a small bill-of-material for passive components. These designs should also 
provide inexpensive, reliable, and easily manufactured receiver systems. These 
requirements call for integration of RF front-end and baseband processing in a 
single chip. Though the desirable case of converting directly from analog to digital 
at the antenna input does not seem to be feasible as yet, the trend is to include 
analog RF front-end with digital signal processing on the same chip. 

Heterodyne architectures, due to their high performance and ease of implementa- 
tion, continue to be employed in most modern receivers [1-6]. In these architectures, 
the input RF signal is down converted to an intermediate frequency (IF), amplified, 
and filtered before it is finally demodulated by a low-frequency demodulator. This 
demodulator is typically built to operate at frequencies below 100MHz; therefore, two 
intermediate conversions, with one IF sufficiently different from the RF signal, are 
often needed to facilitate image filtering. The multiple stages of IF filtering and 
amplification add to the complexity and cost of the receiver. Passive bandpass filters 
that offer high selectivity with high linearity and low noise, such as surface acoustic 
wave (SAW) filters, typically are used in the RF and IF stages to attenuate the 
interferers accompanying the desired signal. By attenuating interferer power prior to 
amplification, these filters greatly reduce the linearity and dynamic range requirements 
of the analog-to-digital converter (ADC) block used in the IF digitization. However, 
such filters are not amenable to on-chip implementation using present VLSI technol- 
ogy, and they limit the extent to which a receiver can be miniaturized. 

An alternative is the direct conversion receiver (DCR), which promises superior 
performance in power consumption and size. This architecture has been seen as 
a potential solution for single-chip receiver implementations [7-8]. A power- 
splitter divides the RF input signal into two paths, which are further down 
converted by a quadrature mixer to in-phase (I) and quadrature (Q) baseband 
signals. Analog-to-digital conversion of each channel is performed at baseband 



B. Pandita, Oversampling AID Converters with Improved Signal Transfer Functions, 
Analog Circuits and Signal Processing, DOI 10.1007/978-l-4614-0275-6_l, 
© Springer Science+Business Media, LLC 2011 



2 1 Introduction 

frequency by a dedicated ADC, and the digital bits are processed by a digital signal 
processor (DSP). By down-converting the entire receive band directly to a baseband 
centered at or near dc (zero-IF or low-IF), usually less than 5MHz, the direct- 
conversion receivers allow most of the necessary amplification and interferer 
filtering to be performed by lowpass baseband amplifiers and filters, which are 
amenable to on-chip implementation. However, in contrast to superheterodyne 
receivers, the baseband components in a DCR must be highly linear, since they 
must pass the desired signal and at the same time reject the relatively large 
interfering signals; for example, in the case of a DVB-T (Digital Video Broadcast- 
ing - Terrestrial) receiver the interfering signal can be 45dB more powerful than the 
desired signal. Any interferer subjected to an even-order nonlinearity introduces a 
distortion product, which can potentially corrupt the dc or near-dc down-converted 
desired signal. In zero-IF DCRs, two additional problems are caused by the 
local oscillator having the same frequency as the RF desired signal: one, the local 
oscillator signal can inadvertently be radiated and interfere with other nearby 
receivers, and, second, the signal can couple to the RF mixer input port, and become 
down-converted to dc, and thereby contribute to a large unwanted offset on 
the down-converted desired signal. Circuit mismatches also contribute to dc offset, 
and flicker noise introduced by the baseband components directly corrupts the down 
converted desired signal. 

Low-IF direct conversion receivers avoid the dc offset problems and are less 
sensitive to flicker noise, but are sensitive to gain and phase mismatches in their 
quadrature paths. These mismatches can cause interferers at image frequencies to 
corrupt the down-converted desired signal. 

One of the important and growing trends in VLSI system integration is the 
shift of signal processing from the analog to the digital domain. In communication 
systems, this shift implies that the ADC is moved toward the front-end of 
the system, for example the antenna in the case of terrestrial reception. This 
usually increases the stringency of the ADC performance requirements, such as 
dynamic range and bandwidth. A signal seen at the front-end of a receiver 
typically consists of a desired signal centered at a frequency of interest and 
numerous interfering signals centered at surrounding frequencies. Thus, the 
receiver must have sufficient linearity that intermodulation products and aliased 
harmonics of the interferers do not impact the reference bit-error rate (BER). The 
fact that, at lower frequencies, analog circuits such as operational-amplifiers have 
higher gains and higher linearity justifies reducing the frequency of the IF signal 
and performing analog-to-digital conversion at a lower IF. The main advantage of 
using low-IF or zero-IF is that the required ADC bandwidth is as low as possible; 
however, in addition to downconversion of the desired signal to the IF, the 
frequency conversion is related to the conversion of the image frequency to the 
IF. This conversion of the image frequency to IF is known as the "image-band" 
problem [9]. 

Most existing receivers rely on analog filtering for rejecting interfering signals 
and use analog automatic gain control (AGC) to compensate for the wide dynamic 



1.1 Motivation and Background 3 

range of the desired signal. The result is that a precise analog-to-digital conversion 
is not usually necessary, and the conversion rate can be as low as the symbol rate of 
the transmitted signal. In integrated receivers, because of the reduction in power 
consumption and circuit complexity that can be achieved by trading analog 
processing for digital processing, the trend is to perform as much of the 
signal processing, for example, channel selection, in the digital domain. An advan- 
tage of this architecture is that the I/Q matching accuracy is very good, depending 
basically on the matching of the ADC input stage. The filters, as they are 
implemented digitally, can also have a very accurate frequency response and linear 
phase characteristic, that are important for digital modulation techniques. However, 
this interchange of channel filtering and ADC greatly increases the dynamic range 
and sample-rate required of the ADCs. ADCs with a resolution of more than 13-bits 
are typically required. This high-resolution requirement, together with wide 
Nyquist bandwidth (on the order of MHz), which is necessitated by high data-rate 
and to avoid aliasing of the interferes onto the down converted signal, necessitates 
the use of high performance ADCs. Among the wide variety of high-resolution 
ADC architectures, AZ ADCs, with their high tolerance for component mismatches 
and lower power dissipation, are becoming increasingly popular in wireless 
receiver applications. However, the presence of interferers puts a severe demand 
on the linearity requirements of the analog circuitry and also calls for high-order 
digital filters to attenuate these interfering signals. For example, in Chap. 3 it has 
been demonstrated through behavioral model simulations that DAC nonlinearity in 
a AS modulator ADC cause aliasing of interfering signals into the signal band and 
result into a severe degradation of the ADC performance. Therefore, in such 
applications, it may be more desirable to have a filtering Signal Transfer Function 
(STF) with significant out-of-band attenuation instead of AS ADC with unity STF. 
Depending upon the application, e.g., single sideband (SSB), it may also be 
desirable to have higher attenuation in image band frequencies. 

However, the design of an STF with higher stop-band attenuation has an 
implication for the quality of the Noise Transfer Function (NTF), and there is a 
trade-off involved in STF-NTF design. An independent STF and NTF design 
disregards the inherent STF-NTF trade-off and implements either an STF with 
reduced stopband attenuation or an NTF with degraded signal-to-noise ratio (SNR). 
The primary goal of this book is to develop an STF-NTF design methodology. 
The main challenges facing the design of a high SNR NTF and STF with significant 
out-of-band filtering are identified, and appropriate methodolgy to overcome these 
challenges is proposed. The impact of mismatches on a low-IF complex modulator 
is thoroughly investigated. A low-IF complex AS ADC modulator suitable for 
digital TV (DTV) receivers is developed. The specifications and requirements of 
an ADC suitable for digitization of DTV signals are studied, and both the system- 
level and the circuit-level requirements are derived. The analog circuitry required 
for the proposed complex modulator is implemented on a 0.18 urn CMOS chip. 
Extensive behavioral and circuit simulations and measurements of the test-chip 
result verify the proposed NTF-STF co-design methodology. 



4 1 Introduction 

1.2 Digital TV (DTV) Receivers 

Figure 1.1 [10] shows a functional block diagram of a DTV receiver. The functional 
blocks of a modern DTV receiver are: 

• Tuner, including RF amplifiers, automatic gain control (AGC), filtering, and the 
local oscillator (LO) and mixer (or pair of LOs and mixers in the case of double 
conversion tuners) needed to down-convert the desired RF channel frequency to 
that of the intermediate frequency (IF). 

• IF filter and amplifier, which condition the signal to exploit the full ADC 
dynamic range. This block usually includes major portion of the predecoding 
gain, channel selectivity, and some desired-channel band-shaping. 

• ADC 

• Digital demodulator, which includes in-band interference rejection, multipath 
cancellation, and signal recovery. 

In addition, the digital receiver may include other blocks, e.g., Forward Error 
Correction (FEC) for detecting and correcting errors in the demodulated digital 
stream or synchronization blocks to detect carrier and phase offsets. 

The frequency of the DTV receivers covers the range between 42 and 1000 MHz. 
There are two different architectures of the DTV receiver chip that have been in 
common use in the industry: (1) single-conversion; see Fig. 1.2, and (2) double- 
conversion; see Fig. 1.3. 

The single-conversion architecture directly down-converts the RF signal to an 
IF (about 44 MHz). The single-conversion receivers rely on front-end "tracking 
filters" for image suppression. Often, these filters are divided in to Low VHF, high 
VHF, and UHF bands to cover the whole frequency range. The single-conversion 
architecture, which traditionally is implemented with Bipolar or Bi-CMOS pro- 
cesses, has been widely used in DTV tuner ICs [4,9]. 

The double-conversion DTV receiver architecture up-converts the RF signal to 
an IF, which is higher than the highest frequency in the input frequency range 
(about 1.2 GHz), and then, using a fixed frequency mixer, down-converts the IF to a 
second IF (about 36 - 44 MHz). Though, dual-conversion architecture can realize 
high image-rejection, it suffers from high power consumption. In addition two 



V 



Tuner 



IF Filter 

and 
Amplifier 




ADC 



Demodulator 



Fig. 1.1 DTV receiver front-end block diagram 



1.2 Digital TV (DTV) Receivers 



SAW Filter 
(Centred at 44 MHz) 



V 



Tracking 
Input RF Filter IF 

Filter Amplifier (TV Channel) Mixer Amplifier 



n 



n\ 




r\ 



IF 
Amplifier 



ADC 



Demodulator 



LP 



(44MHz above the TV channel) 
Fig. 1.2 Single-conversion DTV receiver block diagram example 



SAW Filter SAW Filter 

(Centred at 1.2 GHz) (Centred at 44 MHz) 



Input RF 
Filter Amplifier 


1st 
Mixer Amplifier 


-M- 


Mixer 


*r> 


2 nd IF 
Amplifier 






/ \ 


-&- 


L>[^>y^ 




Demodulator 




T 




T 








LP 


LP 





(1.2GHz above the TV channel) (44MHz below the 1 st IF) 
Fig. 1.3 Double-conversion DTV receiver block diagram example 



off-chip SAW filters are usually required for signal selection and image rejection, and 
these external filters limit the integration level and add to the cost of the receiver. 

A direct-conversion receiver architecture for the European digital video broad- 
casting for hand-held (DVB-H) has been proposed in [7]. An off-chip band-limit 
filter at the input is used to suppress the undesired signals, and an external LNA has 
been employed to satisfy the noise requirement. The IC uses on-chip eighth order, 
inverse Chebyshev low-pass filtering for channel selectivity, and RF tunable 
bandpass filter and a polyphase mixer for harmonic rejection. The I/Q mismatch 
errors have been addressed by the digital signal processing (DSP) in the demodula- 
tor, but frequency-dependent errors have been minimized by circuit design and 
layout. The IC has integrated a DC-offset correction system. Image rejection and 
channel filtering have been implemented digitally. The receiver is implemented in a 
0.35 um SiGe BiCMOS technology and consumes 240 mW from a 2.775 V supply. 

A dual-conversion multi-standard analog and digital TV architecture has been 
reported in [5]. The receiver consists of an up-conversion mixer, a digitally gain- 
programmable image reject down-conversion mixer, and relies on two external 
first- and second-IF SAW filters for channel filtering. The receiver is implemented 



1 Introduction 



SAW Filter 
(1.22GHz) 



V 



Balun 



LNA Mixer Amp|ifier 



r n n 



Mixer 



Analog Baseband 



IF 
Amplifier 



H ^cn>l <ai- 




(0-4 MHz) 



Quartz 

(27 MHz) (1-26 -2.08 GHz) (Quad) 



Fig. 1.4 Double-conversion DTV receiver block diagram [2] 



in a 0.35 mm SiGe BiCMOS technology and consumes 1.5 W from a split 5 V and 
3.3 V supply. 

Besides the single- and double-conversion architectures, other architectures 
have been reported in the literature. A double conversion zero second-IF (DZIF) 
DVB-T receiver chip has been reported in [2]; refer Fig. 1 .4. In this architecture, the 
desired RF signal is first up-converted to an intermediate frequency of 1.22 GHz 
and then quadrature down-converted to a zero intermediate frequency. Channel 
filtering is partially performed by an external SAW filter centered at the first 
intermediate frequency. The I and Q outputs of the quadrature mixer are digitized 
by two 14bits 4 MHz bandwidth AZ ADC modulators. The IQ gain mismatch is 
corrected in the analog domain, and the phase mismatch is corrected by digital 
algorithms processing the ADC outputs. The receiver has been implemented in a 
2.5 V, 0.12 um CMOS technology and consumes 1.4 W. 

A double-conversion, low-IF, multi-standard TV receiver chip has been reported 
in [6]. The proposed receiver uses an up-conversion followed by a quadrature 
down-conversion mixer to shift the desired channel to a frequency of 1.75 MHz. 
The complex outputs of the quadrature mixer are filtered with a complex low-pass 
filter and finally digitized by two 1 lbit ADCs. The chip does not use any external 
SAW filters, and channel filtering and in-band image rejection are performed in the 
digital domain. The receiver, which is fabricated in a 0.25 (Am CMOS technology, 
consumes 1W from a 2.5 V supply. 

Over the past few years, there has been a marked shift from high-IF dual- 
conversion to low-IF single-conversion architectures. A single-conversion, low-IF 
receiver architecture for multi-standard TV has been presented in [8] [Fig. 1.5]. 
Quadrature mixing is used to down-convert the desired channel to a low intermedi- 
ate frequency (4.57 MHz). The architecture splits the quadrature mixer into three 



1.3 Outline 



(Harmonic Rejection) 



/ 



(Image Rejection) 



/ 






/ 


Hilbert 
Filter 


\ 


DAC 


ADC 


i 






ADC 


\ 


/ 





/2/4/16/32 
3-Phase LO 



J 



Crystal 
(27 MHz) 



Fig. 1.5 Single-conversion DTV receiver architecture [8] 

individual mixers. A coarse, selectable filter, together with the three-phase mixers, 
is used for harmonic rejection. Two 1 lb pipelined ADCs are used for the digitiza- 
tion of the I and Q signals. The image rejection has been performed digitally. The 
chip which is implemented in a 0.18um CMOS process, consumes 750 mW from a 
single 1.8 V supply. 



1.3 Outline 



This book is organized as follows: In Chap. 2, a low-IF complex AE modulator- 
based DTV receiver is presented. The chapter provides background information on 
real and complex mixing and on how complex-mixing is ideally suited for on-chip 
integration. A low-IF receiver architecture that alleviates some of the problems 
faced by a zero-IF receiver is presented. A major problem faced by receivers 
handling wireless signals is the presence of interfering signals or "interferers", 
which are usually stronger than the desired signal, and accompany the desired 
signal. Often, intermodulation products generated by these interferers and the 
desired signal limit the SNR of the receiver. After a discussion of the "interfering 
signals" problem in DTV receivers, the chapter presents and compares the existing 
approaches used to filter interfering signals in AE modulator ADC-based receivers. 
Finally, the chapter concludes by deriving specifications for a low-IF complex AE 
modulator ADC suitable for a DTV receiver. 

Chapter 3 starts with background information on the norm and how it can be 
used in the design of an NTF. The chapter discusses the trade-off involved in 
the design of an NTF and an STF; further, the need for developing an NTF-STF 
co-design methodology is explained. The chapter presents design methodology 
for deriving NTFs, and STFs (real and complex) with significant stop-band 



8 1 Introduction 

attenuations. Finally, the advantages of the proposed AX ADC modulator with 
filtering STF are presented. 

In Chap. 4, architecture-level design and simulations of the proposed AS 
modulator are presented. The impact of circuit mismatches on a complex AX ADC 
modulator and the need for stage-ordering are presented. The complete fourth order 
AE ADC modulator architecture is presented in this chapter. The transition from the 
Simulink™ [12] model to the switched-capacitor (SC) circuit is presented. There is 
consideration of the impact of SC circuit non-idealities, e.g., the settling errors of the 
integrators, finite gain of the Opamp, finite resistance of the sampling switches, 
random jitter in the sampling clock, capacitor mismatches, and multi-level DAC 
nonlinearity, on the SC circuit specifications. 

Chapter 5 presents the circuit-level design and simulation of the blocks proposed 
in Chap. 4. The circuit of the SC AZ ADC modulator consists mainly of opamp, 
multi-bit quantizer, multi-level DAC, non-overlapping clock generators, switches, 
and biasing. A detailed description of the design of the various blocks in the SC AZ 
ADC modulator is presented. Finally, the layout techniques for capacitors, 
switches, quantizers, Opamp and the complete fourth order modulator are 
presented. Further, the chapter describes the experimental testing of the fabricated 
chip. The test set-up, including the fabricated chip, and the designed printed circuit 
board (PCB), is presented in the chapter. The measured results are also reported. 

Chapter 6 concludes the book and suggests directions for future research. 



References 



1. Mehr, I.: Integrated TV tuner design for multi-standard terrestrial reception. In: IEEE Radio 
Frequency Integrated Circuits Symposium, pp. 75-78, 12-14 June 2005 

2. Saias, D., Montaudon, F., Andre, E., Bailleui, F., Bely, M., Busson, P., Dedieu, S., Dezzani, A., 
Moutard, A., Provins, G., Rouat, E., Roux, J., Wagner, G., Paillardet, F.: A 0.12um CMOS 
DVB-T tuner. IEEE International Digest of Technical Papers. ISSCC, pp. 430—431, 2005 

3. Dawkins, D., Burdett, A.P., Cowley, N.: A single-chip tuner for DCB-T. IEEE J. Solid-State 
Circuits. 38(8), 1307-1317 (2003) 

4. van Rumpt, H., Kasperkovitz, D., van der Tang, J., Nauta, B.: UMTV: a single chip TV 
receiver for PDAs, PCs, and cell phones. In: IEEE International Digest of Technical Papers. 
ISSCC, pp. 428^129, February 2005 

5. Stevenson, J.-M., Hisayasu, P., Deiss, A., Abesingha, B., Beumer, K., Esquivel, J.: A multi- 
standard analog and digital TV tuner for cable and terrestrial applications. In: IEEE Interna- 
tional Digest of Technical Papers. ISSCC, pp. 210-213, February 2007 

6. Heng, C.-H., Gupta, M., Lee, S.-H., Kang, D., Song, B.-S.: A CMOS TV tuner/demodulator IC 
with digital image rejection. In: IEEE International Digest of Technical Papers. ISSCC, 
pp. 432—433, February 2005 

7. Antoine, P., Bauser, P., Beaulaton, H., Buchholz, M., Carey, D., Cassagnes, T., Chan, T.K., 
Colominers, S., Hurley, F., Jobling, D., Kearney, N., Murphy, A., Rock, J., Salle, D., Tu, C.-T.: 
A direct-conversion receiver for DVB-H. In: IEEE International Digest of Technical Paperss. 
ISSCC, pp. 426-427, February 2005 

8. Gupta, M., Lerstaveesin, S., Kang, D., Song, B.-S.: A 48-to-860 MHz direct-conversion TV 
tuner. In: IEEE International Digest of Technical Papers. ISSCC, pp. 206-208, February 2007 



References 9 

9. Mirabbasi, S., Martin, K.: Classical and modern receiver architectures. IEEE Commun. Mag. 
38(11), 132-139(2000) 

10. Henderson, J.G.N. , Bretl, W.E., Deiss, M.S., Goldberg, M.S., Markwalter, B., Muterspaugh, 
M., Touzni, A.: ATSC DTV receiver implementation. Proceedings of the IEEE, vol. 94, No. 1, 
pp. 119-147, January 2006 

11. TUA 9001, RF Silicon Tuner for DVB-H/T and CMMB (Direct Conversion Recever), 
INFINEON Technologies. 

12. The Math Works, Inc., Matlab, Version R2007a, Natick, Massachusetts: The Math Works, 
Inc., 2007 



Chapter 2 

A Low-IF Complex AX ADC-Based 

DTV Receiver 



This chapter provides background information regarding the "image-band problem" 
that is related to frequency conversion, complex filters, mismatch issues 
associated with complex filters, and "interfering-signals problem" in wireless 
receivers. 

As the analog television broadcast system is being phased out and replaced by 
all-digital transmission in recent years, research has been conducted to develop 
digital television (DTV) receivers. However, for the available DTV receiver 
solutions, the issues of low-power and low-cost design still remain there. For 
example, most commercial DTV receivers use a dual-conversion architecture and 
are implemented with expensive technologies like SiGe and BiCMOS, instead of 
with low-cost CMOS technology. These receivers rely on external surface-acoustic 
wave (SAW) filters for image rejection and channel selection. This chapter presents 
a low-IF complex AS modulator-based receiver architecture suitable for realization 
of a highly integrated DTV receiver with CMOS technology. 

Signals seen at the front-end of a wireless receiver typically consist of a desired 
signal accompanied by strong interfering signals. Though AE ADCs with wide 
dynamic range are suitable for digitizing such signals, there is often a need to pre- 
filter these signals due to the linearity and power requirements of the analog 
circuits. This chapter reviews some of the solutions for handling the interfering 
signals in AE modulator-based wireless receivers and presents their advantages and 
disadvantages. The benefits of AE ADC with integral filtering for digitizing signals 
accompanied by high interfering signals are outlined. In the next chapter, a design 
methodology for the realization of a AE modulator with a filtering signal transfer 
function (STF) is presented. 



B. Pandita, Over sampling AID Converters with Improved Signal Transfer Functions, 1 1 

Analog Circuits and Signal Processing, DOI 10.1007/978-l-4614-0275-6_2, 
© Springer Science+Business Media, LLC 2011 



12 2 A Low-IF Complex AE ADC-Based DTV Receiver 

2.1 Background 
2.1.1 Bandpass Signals 

Fig. 2. 1 shows spectrum of a real-valued signal, with spectrum centered at a non- 
zero frequency,/.. The bandpass signal could be represented as: 

x(t) = xi(t) cos(2nf c t) - x Q (t) sin(2nf c t) (2.1) 

The components, Xi(t) and XQ(t), can be viewed as real-valued lowpass signals 
impressed on the carrier frequency, f c . X/(t) and Xq{i) are referred to as in-phase (I) 
and quadrature (Q) component of the bandpass signal. 

Real-valued signals are characterized by spectrum with: 

• amplitude symmetric around zero frequency (DC), and 

• phase antisymmetric around zero frequency (DC). 

X(f)=X*(-f) (2.2) 

where X(f) is the frequency spectrum of x(t). 



2.1.2 Complex Signals 

Complex signals can be thought as a representation of a pair of real signals. For 
example, for a pair of wires at voltages V\ and V2, we may represent the pair of 
wires as carrying a "complex voltage" V = V\ +JV2. Similarly, for a pair of time 
varying signals, f\(t) and fz(t), one can consider it as a complex signal, 
f{t)=f,{t)+jf 2 (f). 

The complex signals differ from real signals in the frequency domain. For real 
signals the frequency spectrum must be symmetric about DC, however, no such 
constraint applies for the complex signals, and complex signals can be asymmetric 
about DC. Fig. 2.2 shows frequency spectrum of real signals V\ = cos (2nf c t), and 
complex signal V — cos(2nf c t) +jsm(2nf c t). Compared to double impulses for 

k(/)l 



-f c DC 

Fig. 2.1 Spectrum of a bandpass signal 



2.1 Background 



13 



amplitude 



amplitude 



-f c DC f c f DC f f 

Vi = cos(27t/;o V- cos(2nf c t) +jsin(2nf c t) 

Fig. 2.2 Spectrum of real and complex signals 



amplitude 



▲ 1 



-f c DC f 

V* = cos(27t/;0 +jsm(2nf c t) 



Fig. 2.3 Realizing a complex 






A(z) 










niter with real niter blocks 


Y M 








| 






A re (z) 


— ®- 

▲ - 








A reW | 
X- M I 
























A im (z) 




































A im (z) 






























A re (z) 


fcffi 










*<L> 



















->Y re (z) 



-► Y im (z) 



V\ at frequencies f c , V has power only at positive frequency/,. A conjugate signal, 
V* ', with power only at negative frequency —f c is defined as image of signal V; for 
example, V* — cos(2nf c f) — j sin(2nf c t) is image of signal V. 



2.1.3 Complex Filters 

A complex filter has a transfer function with complex-valued coefficients [1]. 
Unlike a real filter, a complex filter is not constrained to have conjugate poles 
and zeros, and, as a consequence, is not restricted to a symmetrical magnitude 
response around DC. This can be useful in some situations, for example the use of 
polyphase filters to generate single sideband signals. 

Though the input and output of a complex filter are complex, the filter is 
constructed from several cross-coupled real filters, as shown in Fig. 2.3. 

If there is a complex input signal 



X(z)=X re (z)+jX im (z) 



(2.3) 



14 



2 A Low-IF Complex AZ ADC-Based DTV Receiver 



A(z)=A R (z) + jA,(Z) 



Xr(z) 




X,(z) 



Yr(z) 



A 11(2) 



A l2 (2) 



X(z) = 

Afi*A l2 

Am*A R2 



J> ()* =£> AA diff (z) 



v A nom (Z) 




Y(z) 




{> AA cm (z) 



-Yi(z) 
X(z)=X R (z) + jX l (Z) 

Y(z)=Y R (z)+jY l (Z) 



Fig. 2.4 (a) Complex filter constructed from non-ideal components, and (b) Signal flow diagram 
of a complex filter A(z), showing common-mode and differential error components 



input to a complex transfer function 

A(z)=A re (z)+jA im (z), (2.4) 

then the complex output signal is: 

Y(z) = Y,,(z) +jY lm (z) = A(z)X(z) (2.5) 

Y(z) = [A re (z)X re (z) - X im (z) A im (z)] + j[A re (z)X im (z) + X re [z)A im (z)] (2.6) 



2.1.4 Mismatch in Complex Filters 

In circuit realizations of a complex filter, due to component mismatches, etc., the 
two real-part transfer functions may not be equal, and the same variation may be 
true for the two instances of the imaginary-part transfer functions. In [2] and [3], it 
has been shown that the transfer function of the mismatched complex filter can be 
written as a nominal term, a common-mode error term, and a differential-error 
term; refer to Fig. 2.4. 

The output of the filter can be written as 



Y{z) = A nom X{z) + AA cm X(z) + AA diff X*(z) 



(2.7) 



2.1 Background 15 

where X*(z) denotes complex conjugate ofX(z), and the error transfer functions are 
defined as 

a. r\ (A R i+A R2 . . ,1 , .(A n + A I2 , , A ,_ „, 

AA em (z) = <^ A^„ om (z) ^ + ^ A, nom (z) \ (2.8) 



&A<uff( z ) = — n — r +n — o — r ( 2 - 9 ) 



The term AA fm represents a common-mode variation of Am and A«2, and 
similarly kAdiff lS the differential variation in Am and A«2- 

The effect of differential term, (2.9), is that it causes conjugation of the image- 
band and the desired signal-band. The undesired input signal band, which will be 
superimposed on the desired signal band after conjugation, is called the "image- 
band." This aliasing of image frequency into desired signal can seriously degrade the 
quality of the desired signal at the output. The aliasing or leakage of image frequency 
into signal-band is quantified by image rejection of the complex system. The aliasing 
of signal-band into image-band is usually not an issue. The common-mode variation, 
AA cm , is usually small compared to A nom and can be ignored. 



2.1.5 Real Mixing vs. Complex Mixing 

Continued on-chip integration of receiver front-ends has resulted in the lowering 
of the intermediate frequency (IF). The fact that at lower frequencies analog 
circuits like operational-amplifiers have higher gains, and higher linearity justifies 
frequency down conversion to a lower non-zero IF signal and performing analog- 
to-digital conversion at the lower IF. However, frequency conversion is related to 
"image-band" problem [4] as described in Sect. 2.1.4, which is actually 
downconversion of two frequency bands symmetric to the multiplying frequency 
to the same output band. Frequency down-conversion of a passband signal is 
typically performed by mixing the signal with a sinusoid, e.g., cos,(2nf LO t) . This 
is shown pictorially in Fig. 2.5. 

The spectrum of the mixer output signal is the superposition of the positive and 
negative shifted versions of the spectrum of the input signal. As is shown in Fig. 2.5, 
the two frequency bands that are symmetrical around the multiplying frequency are 
down-converted to the same output band. It is necessary to suppress any signal in 
the image band prior to the mixing operation. This is the task of the image-reject 
(IR) filter, which usually precedes the mixer. The previously discussed image 
problem arises due to the fact that the frequency spectrum of a real sinusoid 
contains impulses at both positive and negative frequencies. As shown in 
Fig. 2.6, one way to avoid this problem is to mix the signal with a complex 
exponential, e.g., e~^ 2n ^ LO ', which has only a single frequency component, in this 



16 



2 A Low-IF Complex AZ ADC-Based DTV Receiver 



x r (t) 



-► y r (t) 



cos(2ji f LO t) 



amplitude 



Desired Image 



Image Desired 



Fig. 2.5 Mixing a real signal with a sinusoid: (a) mixer input spectra, (b) mixer output spectrum 



x r (t) — >&&> yr(t) + jy im (t) 

-j2nf L0 t 
e 

amplitude 



A 



-+-f 



Desired Image 



f IM f LO f o 
Image Desired 



i 



4 *< 



Fig. 2.6 Mixing a real signal with a complex exponential 



2.1 Background 17 

case at a negative frequency, — f L0 . Therefore, mixing a real signal with this 
negative-frequency complex exponential results in a complex signal whose spectrum 
is a shifted version of the real signal spectrum. Theoretically, this process eliminates 
the image problem associated with frequency shifting when mixing is done with a 
real sinusoid. Although a quadrature signal path is needed for suppression of signals 
at the image frequency, this topology is still favorable due to performance and 
efficiency in terms of power consumption. Almost all modern receivers employ 
quadrature demodulation. The quadrature demodulation is performed by an I/Q 
mixer that uses two local oscillators with a same frequency, but a 90° phase 
difference. The I and Q components are independent and orthogonal to each other. 

As discussed in Sect. 2.1.5 mismatches in the complex path cause undesired 
image-frequencies to alias into the desired signals. For a gain error of AG from the 
nominal gain of G and phase error of A<fr between the two paths of a quadrature 
system, "image rejection ratio" IRR is given by 

IRR ^ 2 + (AG/G) 2 ; (A(j) ^ { (ag)/g ^ 1} (2 1Q) 

For an IRR of 60 dB the gain and phase mismatches between the two paths of the 
quadrature system have to be less than 0.1% and 0.1', respectively. Often, the IRR is 
limited to less than 40 dB, and gain-phase calibration or additional filtering is 
required to improve IRR of the system [5]. 



2.1.6 Complex Transfer Function Design 

A complex frequency response symmetric around a center frequency can be 
obtained by frequency shifting of a real response- the frequency shift in z-plane 
means rotation of the real response filter pole-zero constellation. Fig. 2.7a shows a 
pole-zero constellation of a lowpass filter with equiripple stopband response. In 
Fig. 2.7b the pole-zero constellation has been rotated by n/A to realize the shifted 
complex magnitude response shown in Fig. 2.7d. What this example highlights is 
that all the standard methods for designing real filters can be applied in the 
realization of symmetric complex filters. A simple design procedure for obtaining 
the complex filter transfer using MATLAB involves following steps: 

[z,p,k] =cheby2(4, 60, 1/4) 

The complex pole-zero constellation (z, p) shown in Fig. 2.7c has been realized 
from the real pole-zeros (z,p) by: 

£ = z x e'^ 4) 
p=pxe i( ^ 



18 



2 A Low-IF Complex AZ ADC-Based DTV Receiver 




-0.5 0.5 

Normalized Frequency (f s 



= 2) 













-10 






\ 


-20 






\ 


-30 
m 
-o-40 






\ 


-50 






l 


-60 








-70 






I\/ 


-80 






. I u 




1 -0.5 





0.5 1 



Normalized Frequency (f s - 2) 



Fig. 2.7 Low pass filter methodology used to realize symmetric complex filter. Real lowpass 
filter: (a) Pole-zero constellation, (b) Magnitude Response. Complex bandpass filter designed by 
rotation of the lowpass pole -zeros: (c) Pole-zero constellation., (d) Magnitude Response 

A methodology to design complex response bandpass transfer functions without 
the requirements of first designing a real response transfer function has been 
described in Chapter 3. 



2.2 A Low-IF DTV Receiver Architecture 



Fig. 2.8 presents a digital DTV receiver architecture built around a low-IF complex 
AS modulator [6]. In the proposed architecture, a single down-conversion step 
divides the input signal into quadrature branches at a low-IF frequency. The high-Q 
RF image reject filter in the traditional receiver architecture has been replaced by a 



2.2 A Low-IF DTV Receiver Architecture 



19 



Mixer VGA 



V 



n 



Relaxed Amplifier 
BP Filter 



'90 



Mixer 




LO 



IF Polyphase 
Filter 



VGA 




n 



Complex 
Bandpass 
AS- ADC 



Demodulator 



Fig. 2.8 A quadrature-IF system using a complex Low-If AZ modulator 



relaxed low-Q bandpass filter [7]. In the low-IF receiver, the IF has been modified to a 
low but non-zero frequency value; the frequency value falls into the baseband signal- 
processing capabilities of the analog circuits. An architecture based on low-IF 
eliminates some of the detrimental effects, e.g., DC-offset, LO self-mixing, second 
order intermodulation, that are faced by the direct-conversion scheme. The main 
drawback of the low-IF architecture is that the image band interference is close to 
the desired signal, and it is difficult to separate the image frequency from the desired 
signal through the use of relaxed low-Q bandpass filters. The mismatches between the 
in-phase (I) and quadrature (Q) channels cause an aliasing of the image frequency into 
the desired channel. Since the image frequency can be significantly stronger than the 
desired signal, the image rejection requirements of the receiving system may demand a 
higher matching of the in-phase (I) and quadrature (Q) channels. 

The dual ADCs in the traditional low-IF receiver architecture have been 
replaced by a complex low-IF AE ADC. The low-IF has been selected at a value 
of 3 MHz for ATSC and 4 MHz for DVB-T standards. At a maximum sampling 
frequency of 128 MHz, and an over-sampling ratio (OSR) of 16, the architecture is 
suitable for digitization of the maximum DTV signal bandwidth of 8 MHz. The two 
anti-alias filters in the traditional dual ADC architecture have been replaced by a 
single complex bandpass anti-aliasing filter, and the replacement is advantageous 
since the same complex bandpass filter can be designed for alias rejection and also 
for image signals rejection. A low-IF means lower Q bandpass poles, practical 
resistor and capacitor ratios, and a low sensitivity of the bandpass filter center 
frequency to the errors in the RC time constants. 

Among the wide variety of high-resolution ADC architectures, AZ ADCs, with 
their reduced sensitivity to component mismatches and lower power dissipation, 
are becoming increasingly popular in systems that have stringent per- 
formance requirements such as wide dynamic range, wide bandwidth, and low 
power. The presence of interferers puts a severe demand on the linearity requirements 
of the analog circuitry in a wireless receiver, and often the intermodulation products 
generated due to the non-linearities of the receiver limit the system's signal-to-noise 



20 2 A Low-IF Complex AX ADC-Based DTV Receiver 

ratio (SNR). An advantage of AE ADCs over other ADC architectures is that for a 
given dynamic range over a narrow passband and sufficient linearity to accommodate 
interferers over a large frequency band, AZ ADCs tend to consume less power than 
other ADC architectures that have comparable linearity but achieve the full dynamic 
range over a larger frequency band [8]. With a large dynamic range and high 
linearity, AZ ADCs allow for reduced analog baseband components and transfer 
much of the baseband filtering from the analog to the digital domain. 

In a receiver system based on dual "one-input and one-output" AH modulators, 
the same AZ modulator performs analog-to-digital conversion on not only the 
signal component but also on an image component. In contrast, a complex AE 
modulator, with no constraints of poles and zeros to be in conjugate pairs, digitizes 
only the signal component. For a given OSR and sampling rate, the complex AS 
ADC signal bandwidth is effectively halved and this halving translates into 
almost double the power efficiency as compared with a dual AZ ADC approach. 
Further, with a multi-bit complex quantizer and a multi-level digital-to-analog 
converter (DAC), the requirements for performance of the internal operational 
amplifiers are moderate, and a larger SNR can be implemented by a low-order 
loop filter. The main advantages of a complex low-IF architecture are that offset 
and also flicker noise do not interfere with the desired signal; self-EMI is not 
an issue because the local-oscillator frequency is different from the carrier fre- 
quency. As in any bandpass system, only odd-order distortion products have 
an effect. A complex-IF mixer alleviates the image problem, so that the front-end 
filter can have relaxed specifications and thus reduced size. 

DSP algorithms at the digital backend can be employed to compensate for I/Q 
imbalance, complex down-conversion, equalization, etc. Furthermore, signal 
processing, like channel selection, demodulation are performed in the digital 
domain, and this feature gives the architecture the advantages of flexibility with 
respect to multi-standards. 



2.3 The 'Interfering Signals' Problem in Wireless 
Receivers 

A typical RF signal received at the input of a wireless receiver consists of a desired 
signal along with numerous interfering signals, which are usually stronger than the 
desired signal. The ATSC Receiver Performance Guidelines [9] describe the 
minimum desired-to-undesired (D/U) channel ratio, under which the DTV receivers 
should exceed the reference bit-error-rate (BER). 1 For example, according to [9], 
there can be an interferer six channels (36 MHz) away that has 57 dB higher power 
than the desired channel. 



At this BER level, the error protection can correct most of the data errors and deliver a high 
quality picture. 



2.3 The 'Interfering Signals' Problem in Wireless Receivers 21 

Similarly, DVB-T/H receiver standards [10] define signal reception conditions 
in the presence of other interfering digital and analog TV channels. DVB-T [10] 
defines two different interference pattern sets that may be used to test the immunity 
of the DTV receiver to interferences. The first set, which tests the selectivity of the 
receivers, includes two separate interferer patterns, i.e., SI and S2: 

• SI pattern: analog interference signals from PAL/SECAM TV (SI pattern), 
especially PALG interference, defined as 35 dB stronger than the wanted 
64-QAM signal. The carrier of the analog TV signal is located a single channel 
away from the center of the wanted signal; 

• S2 pattern: a digital TV channel two channels away and up to 40 dB stronger 
than the wanted signal. 

For a low-IF receiver architecture, these requirements translate into sharp 
channel select filters and high linearity of the receiver. 

The second set tests the non-linearity of the receiver with three different 
interferer patterns: LI, L2, and L3, each consisting of two interferers: 

• one digital interferer and one analog interferer, two and four channels away from 
the wanted channel. The interfering channels can be 40 dB and 45 dB stronger 
than the wanted signal; 

• two analog interferers, two and four channels away from the wanted channel. 
The interfering channels can be 45 dB stronger than the wanted signal; 

• two digital interferers, two and four channels away from the wanted channel. 
The interfering channels can be 40 dB stronger than the wanted signal. 

The presence of other interfering signals, e.g., GSM interference from cell- 
phone up-link, add to the linearity and filtering requirements of the receiver. 

In addition, the receiver's non-linearity can also generate interferences to DTV 
reception. The inter-modulation among the interfering channels or cross-modula- 
tion between the interfering channels and the desired channel creates distortion or 
noise components that fall in the desired channel. For example, interference from 
undesired signals on channels in the form N+K and N+2K (N is the desired channel) 
can cause two third-order intermodulation products falling in the channels N and 
N+3K [11]. Narrow tracking filters for rejecting these interfering signals are not 
amenable to silicon integration, and, as a result there is a large frequency range of 
signals present at the input of an analog-to-digital converter in a receiver. The 
receiver has to reject these interfering signals and detect the transmitted bit 
sequence. The presence of interfering signals requires that the analog-to-digital 
converters, in addition to handling large signal dynamic range and bandwidth, must 
have sufficient linearity that intermodulation products and aliased harmonics of the 
interferers do not impact the reference BER. 



22 2 A Low-IF Complex AX ADC-Based DTV Receiver 

2.4 Approaches to Filtering Interfering Signals 
in AS ADC Based Receivers 

The interfering signals accompanying a desired signal may be filtered by digital 
filters processing the ADC output, or they may be suppressed by an analog filter 
at the input of the ADC. An alternative topology includes filtering as an integral part 
of the ADC. 



2.4.1 Filtering Interfering Signals in the Digital Domain 

The first solution to handling interferers consists of using an analog-to-digital 
converter, typically a AE ADC, with a relaxed broadband analog filter at the 
front-end. Due to its inherently anti-aliasing nature, in a continuous-time AE 
ADC, an anti-aliasing analog filter of a lower order may be sufficient to meet the 
alias suppression requirements of the ADC. The analog signals at the input of the 
ADC comprise the desired signals and possibly the adjacent channel's interfering 
signals. The presence of interferers demands a high bandwidth and a dynamic range 
for the ADC. Another requirement is for the analog circuits to be linear in order 
to prevent the intermodulation products of large interferers from disturbing the 
reception of a desired weak channel. 

The bulk of signal processing, for example, interference attenuation, channel 
selection, digital demodulation, takes place in the digital domain. An advantage of 
handling channel filtering and demodulation functions in the digital domain is that 
this method leads to flexible multi-standard receiver architectures. Filters with 
sharp stop band roll-off and linear phase characteristics can be easily synthesized 
in the digital domain. However, since, in that case, the task of the digital filters, 
in addition to filtering the quantization noise, includes attenuation of the interfering 
signals, the situation calls for digital filters of higher complexity, which cause 
higher power dissipation. A possible way to reduce power dissipation would be 
to adapt the order of the digital filter to the levels of the interfering signals, for 
example, reduction of the filter order for low interfering signal levels. However, the 
required interferer power detection circuitry adds to the complexity of the receiver, 
and there can also be transition errors when the order of the filter is changed. 



2.4.2 Filtering Interfering Signals in the Analog Domain 

An analog filter at the input of an ADC may be used to attenuate the interferers, and 
the dynamic range and the linearity requirements of the ADC are thus relaxed. 
However, a serious drawback of the analog filters is the change of the filter 
characteristics due to process variations, and there can be differences between 



2.4 Approaches to Filtering Interfering Signals in AX ADC Based Receivers 23 

identical circuits on the same chip- this can lead to mismatches and image issues in 
a receiver. There is a need for tuning or calibration to compensate for these process 
variations. The additional components add noise and distortion, which degrade the 
sensitivity of the receiver. Further, the signal quality at the input of the ADC can 
suffer due to the limited phase and pass band shape characteristics that can be 
implemented with analog filters. Unlike digital circuits, analog circuits do not scale 
well with technology migration and also lack the flexibility required for 
multistandard receivers. 



2.4.3 Filtering Interfering Signals with a Filtering STF 

An alternative solution is designing the signal transfer function (STF) of the AE 
ADC to provide a filtering transfer function. The ADC performs a filtering of 
the input signal before generating the corresponding digital output. The DSP 
performs high order filtering and channel selection at the ADC output. A filtering 
ADC relaxes the requirements of both the filtering in the IF path and the filtering in 
the digital domain. With a filtering STF, the AZ ADC modulator reduces inter- 
modulation of the desired signal and the interfering signals at the input of the 
quantizer, and avoids the feedback of the high-frequency interfering signals at 
the input of the modulator. As will be shown in Chap. 3, AZ modulator ADCs 
with filtering STF have significantly reduced intermodulation products caused 
by the feedback DAC non-linearities. Due to these reduced intermodulation 
products, AE modulator ADCs with filtering STF demonstrate higher SNDR 
for applications where the input signal is accompanied by strong out-of-band 
interfering signals. 

The distributed feedforward and feedback (Fig. 2.9a, b) are two common 
topologies that have been successfully used to realize stable higher order AE 
modulators [12]. In the distributed feedforward topology the error signal fed into 
the loop filter consists primarily of quantization noise. The absence of signal 
component in the error signal results into reduced requirements on the loop filter 
linearity. These reduced linearity requirements enable reduction of the bias currents 
of the consecutive stages, and as a consequence makes feed forward architecture a 
low-power design. In comparison in the distributed feedback topology each inte- 
grator output contains a combination of filtered quantization noise and a large 
signal component to compensate for the average DC value of the quantizer feed- 
back provided to each integrator. Keeping the integrator output swings within limits 
usually results in larger feedback integrator capacitors, and this increase in size 
tends to make the distributed feedback AE ADCs larger and more power hungry 
than circuits that use the feedforward architecture. 

Fig. 2.10 shows NTFs and STFs derived for the fourth-order distributed 
feeedforward and feedback AX modulators shown in Fig. 2.9a and Fig. 2.9b. 
The transfer-function have been derived for a butterworth placement of the 



24 



2 A Low-IF Complex AX ADC-Based DTV Receiver 






i ► -L+ T -A> ~ -i* 

z-1 z-1 z-1 




Quantizer) — •— ► \/ 



b 




z-1 




z-1 




z-1 




z-1 



Quantizer? — » — ► 



DAC 



1/ 




Fig 2.9 (a) AX modulators with distributed feedforward summation, (b) AX modulator with 
distributed feedback, (c) Modified distributed feedforward AX modulator with feed-ins to intro- 
duce STF zeros 

transfer-function poles. The coefficients used in the derivations of these transfer- 
functions are: 

a\ = d 4 = 2.5535 
a 2 = d 3 = 2.7446 
a 3 =d 2 = 1.4212 
a 4 =di= 0.2923 



The NTFs for the two architectures are identical, however, as is evident from 
Fig. 2.10b the STF of the feedforward AE modulator shows an out-of-band peaking. 



2.4 Approaches to Filtering Interfering Signals in AX ADC Based Receivers 



25 




NTF 



71 3 71 

2 4 

Radian Frequency 




STF FF AX ADC 



STF FB AS ADC 



71 3 It 

2 4 

Radian Frequency 



Fig. 2.10 NTFs and STFs for the AS modulators with distributed feedforward and distributed 
feedback: (a) NTF, (b) STF 



The STF for the feedforward AE ADCs is flat within the signal conversion 
bandwidth, shows some overshoot for out-of-band frequencies, and provides first- 
order filtering beyond the unity-gain frequency of the loop. This out-of-band 
overshoot makes feedforward AZ ADCs unsuitable for digitization of signal 
frequencies accompanied by high-frequency interferers. The out-of-band overshoot 
is caused by the STF zeros and implies that the out-of-band frequencies 
are amplified toward the output. This amplification means that the stable input 
range for out-of-band frequencies is smaller than that for the desired channel. 



26 2 A Low-IF Complex AX ADC-Based DTV Receiver 

In comparison the STF of the distributed feedback AE modulator shows a lowpass 
filtering characteristic. The distributed feedback architecture results in an all- 
pole STF that does not contain significant peaking; as can be seen from 
Fig. 2.10b the STF may actually be a low-pass filter, which results in improved 
stability when it is driven by signals with significant out-of-band energy. However, 
the low-pass response of the STF for the distributed feedback architecture 
becomes significant at least one decade above the signal bandwidth, and that 
response makes its filtering ineffective for signals accompanied by adjacent 
channel interferers. 

A possible way to control the out-of-band characteristics of the STF for the 
feedforward AE modulator is to insert zeros in the stopband region of the STF. For 
example, these zeros in the STF can be achieved by introducing feed-ins as shown 
in Fig. 2.9c. However, as will be demonstrated in Chap. 3, this independent 
designing of NTF and STF does not produce STFs with optimum out-of-band 
filtering characteristics. In Chap. 3 an NTF-STF co-design algorithm for designing 
of high SNR AE modulators with filtering STFs is proposed. 

In [13], a combination of distributed feedback and feedforward topologies 
has been used to implement a AE ADC with a filtering STF. In the proposed 
architecture, a feedback coefficient in a fourth order distributed feedback archi- 
tecture has been replaced by a feedforward path: d2 coefficient in Fig. 2.9b has been 
replaced by a feed-in coefficient c2 (refer to Fig. 2.11a). With a feedforward 
coefficient, it is possible to introduce a zero in the STF of the AE ADC, and this 
introduction allows attenuation of the interferers around the frequency band 
corresponding to the zero, refer to Fig. 2.1 lb. However, the value of the coefficient 
is bound to the NTF transfer-function. The zeros introduced also neutralize the STF 
poles, and thus reduce the higher-frequency filtering. 

An alternative AE ADC topology based on feedforward architecture, with 
additional high-pass and low-pass filters in the feedback and forward paths, has 
been presented in [14]. The proposed architecture controls the STF's shape with a 
low-pass filter, H LP , in the forward path. A high-pass filter, H HP , has been 
introduced in the feedback path to compensate for the low-pass filter and thus 
retain the NTF shape; refer to Fig. 2.12. 

However, the order of the low-pass filter implemented by the STF is limited by the 
low-pass filter introduced in the forward path, and the order can not be increased 
without impacting the loop filter noise and stability characteristics. The continuous- 
time AE ADC in [14] has been designed for the bluetooth signal bandwidth of 2 MHz, 
and the STF has been reported as a first-order low-pass filter with 3 dB bandwidth of 3 
MHz. 

A distributed feedback AE ADC with a filtering STF has been proposed in [15] 
(refer to Fig. 2.13). The AE ADC implements a notch in the STF stop-band by 
introducing a complex filter after the first integrator in the loop. However, the 
technique is limited to introducing STF zeros for selected interfering signals, and 
designing an STF mask for greater selectivity increases the complexity of the 
loopfilter and has impact on the stability of the modulator. 



2.4 Approaches to Filtering Interfering Signals in AX ADC Based Receivers 



27 




■D 

OS 




STF FF ,\I ADC 



STF Modified FB M ADC 



STF FB ML ADC 



Frequency 
Fig. 2.11 (a) Modified feedback AX modulator [13], (b) STFs for the modulator architectures 



U—> S£H> 




H LP + H /tp - I 

Fig. 2.12 AX modulator with additional low pass and high pass filters in forward and feedback 
paths to implement a filtering STF [14] 



28 



2 A Low-IF Complex AX ADC-Based DTV Receiver 



s 








Quantizer 




V 



Fig. 2.13 AX modulator with a notch in the stopband to implement a filtering STF [15] 

2.5 Specifications for a Complex AX ADC Used 
in a DTV Receiver 



The proposed AS ADC has been designed for a low-IF receiver for ATSC and 
DVB-T digital TV standards. The digital TV signal bandwidth is approximately 6 
MHz for ATSC and 8 MHz for DVB-T. At an OSR of 16, the sampling frequencies 
are 96 MHz and 128 MHz for ATSC and DVB-T respectively. The OSR value has 
been selected as a trade-off between the anti-alias filtering and the signal-to-noise 
ratio (SNR) requirements of the ADC. A third order complex bandpass filter, 
centered at 8 ±2.4 MHz, and with 3 dB bandwidth of 24 MHz, meets the anti- 
aliasing requirements of the ADC; refer to Fig. 2.14. 

Most of the conventionnal receiver architectures rely on analog filtering for 
rejecting interfering signals and use analog automatic gain control (AGC) to 
compensate for the wide dynamic range of the desired signal. The result is that 
usually a precise analog-to-digital conversion is not necessary, and the conversion 
rate can be as low as the symbol rate of the transmitted signal. For example, the bit 
detector in a DVB-T receiver requires only 27.5 dB of SNR to achieve the required 
2 x 10~ 4 BER. Therefore, a pair of flash ADCs that each perform 5-bit uniform 
quantization sampling at Nyquist frequency would more than suffice in a DVB-T 
receiver that performs quadrature down-conversion, with all filtering and AGC in 
the analog domain. However, in integrated receivers, given the reduction in power 
consumption and circuit complexity that can be achieved by trading analog 
processing for digital processing, the trend is to perform as much of the signal 
processing as possible, e.g., channel selection etc., in the digital domain. 

An advantage of this architecture is that the I/Q matching accuracy is very good, 
depending basically on the matching of the ADC input stage. In addition, as the 
filters are implemented digitally, they can have very accurate frequency response 
and linear phase characteristic, which are important for digital modulation 
techniques. However, this interchange of channel filtering and ADC greatly 
increases the dynamic range and sample-rate required of the ADCs. ADCs with a 
resolution of more than 13-bits are typically required. For example, DVB-T tuner 
sensitivity for a 8 MHz channel is approximately —95 dBm for the QPSK scheme 
and —75 dBm for QAM scheme. In the absence of any interference, the maximum 



2.5 Specifications for a Complex AZ ADC Used in a DTV Receiver 



29 



28 

4 




-10 
-20 
-30 
-40 
dB-50 
-60 
-70 
-80 
-90 
-100 



128 










fff ^%\ 


-10 


III \ 1 \ 


-20 


Third order complex bandpass //v 


\\ 


-30 


- filter centered at x i 1MHz Iff 


^k 


-40 


jf 




^k 


dB-50 


jf 




\^\ 


-60 


ffl 




\is 


-70 


III 




W. 


-80 


- *~Ji\ 




Wi^,^ 


-90 


W if 




IWjf 


-100 


I ,1 , 


! \nv 

■ IN 



-96 



-64 



-32 



32 

frequency (MHz) 



64 



96 



J"_ * 




40 dB 



Image channel 



45 dB 



I 
35 dB | 

I 



-96 



-64 



-32 



32 



M 



96 



128 



Fig. 2.14 The interfering signals for DVB-T with a third order complex bandpass filter at the 
input of the AX ADC 



wanted DVB-T signal for the tuner input is —28 dBm. Therefore, considering —95 
dBm sensitivity, the receiver has to provide at least a dynamic range of 67 dB. 

The proposed low-IF receiver solution follows a variable gain amplifier (VGA) 
with automatic gain control (AGC) and ADC approach. By distributing the receiver 
specifications between VGA and ADC, both the circuits can be designed with 
reduced complexities. With the analog front-end filter implemented as a broadband 



30 2 A Low-IF Complex AX ADC-Based DTV Receiver 

anti-aliasing filter, the SNR requirements of the ADC are decided by the required 
adjacent-channel immunity. The ADC samples signals comprising the desired 
signal, the image signal, and some adjacent signals. 

The target SNR for the ADC has been determined in a way that is consistent with 
the following considerations: 

• For ATSC, the required desired-to-undesired signal ratio (D/U) for the adjacent 
channel NTSC interference into the desired DTV channel is —40 dB [9]. For 
higher channels, the maximum rejection threshold for DTV interference into 
DTV has been set at —48 dB. When a carrier-to-noise ratio (C/N) of 15.5 dB is 
maintained, the required SNR of the ADC works out to be 63.5 dB. 

• According to DVB-T standards, assuming 64-QAM and CR = 3/4, the adjacent 
channels (A' ± 1) can be up to 35 dB stronger, while the channels (N ± 2) can be 
up to 43 dB stronger [10]. With the required carrier-to-noise ratio (C/N) of 
27.5 dB for the reference BER in the Rayleigh channel (Pj), the dynamic range 
of the ADC is 62.5 dB. When an extra headroom of 9 dB [16] is added to avoid 
clipping of the OFDM signal due to peak to average ratio (PAR) variations, the 
SNR of the ADC is 71.5 dB. 

The output of the AE ADC comprises the desired signal centered at the low-IF 
of 3 MHz or 4 MHz, depending on the DTV standard, the mirror signal, the 
interfering signals, and the noise-shaped quantization noise. The final image 
rejection, down-conversion, and baseband filtering are done with the DSP. The 
down-conversion to the baseband can be performed by a double quadrature 
multiplication of the AE ADC output with a quadrature IF signal [17]. This 
quadrature multiplication will down-convert the desired signal to the baseband, 
centered around DC; however, it will also upconvert the mirror signal to the 
baseband. Given the image resulting from the adjacent channel, an image rejec- 
tion of 55.5 dB for ATSC and 62.5 dB for DVB-T is required of the digital down- 
converter. To have an image rejection of higher than 62.5 dB, the AS ADC needs 
at least 1 1 bits of resolution. 



2.5.1 Mismatch and Image Rejection Requirements 
of the Low-IF Complex AX ADC 

A complex AZ modulator, like a complex filter suffers from mismatches in the I and 
the Q paths. Due to mismatches, signal or noise at the image frequency aliases into 
signal band of interest and this leads to the deterioration of the ADC SNR. Figue 
2.15 is a block diagram of a complex AE modulator with a mismatch in gain 
elements between the I and Q paths of the modulator. In Fig. 2.15, the complex AE 
modulator shown includes a complex filter having a transfer function H(z), 
two quantizers, and two mismatched multipliers with multiplication coefficients 



2.5 Specifications for a Complex AX ADC Used in a DTV Receiver 



31 



X,(z) 



X Q (z) 



Real-channel 
Quantizer 



Y,(z) 







1-Ag 




E| 


z) 


/ 


/ 


— 0- 








h) fr. 






1+Ag 


H(z) 
Complex 
Loop-filter 


— 0— 

il 


\ 


- — >~ 










Eq(z) 


• 

\ 



X(z)=X|(z)+yXQ(z) 
Y(z)=Y,(z) + yY Q (z) 



' Yq(z) 



Imaginary-channel 

Quantizer 



Fig. 2.15 A complex AX modulator structure with mismatch in gain elements 



of 1 — Ag and 1 + Ag. In the absence of mismatches (Ag = 0), the following 
equation is satisfied: 

Yj(z) +jY Q (z)= T f^- ) (X l (z) +JXq(z)) +T _L^(E / ( Z ) +jE Q (z)) (2.11) 

In the presence of mismatches between the gain elements (Ag ^ 0), (2.12) is 
satisfied. 

1M+/T.M = JgM^IWW)) 



l+2//(z) + (l-Ag 2 )// 2 (z) 

. Ag//(z) 

l+2//(z) + (l-Ag 2 )// 2 (z) 

1 + H(z) 

+ l+2//(z) + (l-Ag 2 )// 2 (z) 

Ag//(z) 
l+2//(z) + (l-Ag 2 )// 2 (z) 



(X,(z) -jX Q (z)) 
(£/(z) +y£ Q (z)) 
(£/(z) -/B fi (z)) (2.12) 



The last term represents the quantization noise in the image band aliasing 
into the signal band, and this process leads to the deterioration in SNR of the 
complex AS modulator. In [18], two more transfer functions - image signal 
transfer function (ISTF) and image noise transfer function (INTF) have been 
added to the existing two transfer functions - signal transfer function (STF) and 



32 2 A Low-IF Complex AX ADC-Based DTV Receiver 

noise transfer function (NTF)- to describe the impact of mismatches in a complex 
AE modulator. In the presence of mismatches the output of the complex AE 
modulator can be written as [18]: 

Y(z) = G(z)X(z) + AG diJf X*(z) + H(z)E(z) + AH diJf E*{z) (2.13) 

AGdiff is the image signal transfer function, or ISTF, which determines the gain 
from the image-signal input to the output, and AHdiff is the transfer function which 
determines the gain from the quantization-noise input to the modulator output. 
Though the in-band noise is shaped by the deep in-band notches of the NTF, the, 
image-band noise, which is significantly larger than in-band noise, is shaped by the 
INTF. The results is that mismatches cause out-of-band quantization noise in the 
complex AE modulator to alias into the in-band region. The INTF created by 
differential mismatch plays a critical role in determining the SNR of the non- 
ideal modulator. One of the techniques to reduce the differential error term AH dig- 
is to place one of the NTF notches in the quantizer's own image band; this method 
attenuates some of the image band noise, E*(z), before it aliases into the signal band 
[18]. However, the other differential error term, AGdig, does not improve through 
the placement of the NTF notch in the image band, and strong interference at image 
frequency can be aliased into the signal band. 

Given the strength of the adjacent channel interferers and the desired carrier-to- 
noise ratio, the image rejection requirements for the AT, ADC work out to be 55.5 
dB and 62.5 dB for ATSC and DVB-T standards respectively. Providing a safety 
margin to account for other noise sources which will degrade the SNR of the ADC, 
a AE ADC with a dynamic range of 75.0 dB, and image rejection better than 65 dB 
should be adequate for the digitization of the DTV signals in the proposed low-IF 
receiver. 



References 



1. S. Mirabbasi and K. Martin, "Classical and modern receiver architectures," IEEE 
Communications Magazine, Nov 2000, pp. 132-139. 

2. Q. L. Liu, W. M. Snelgrove, and A.S. Sedra, "Switched-capacitor implementation of complex 
filters," Proceedings of the 1986 IEEE ISCAS, vol. 3, pp. 1 121-1 124, May 1986. 

3. A. S. Sedra, W. M. Snelgrove, and R. Allen, "Complex analog bandpass filters designed by 
linearly shifting real low-pass prototypes," Proceedings of the 1985 IEEE ISCAS, vol. 3, 
pp. 1223-1226, June 1985. 

4. R. H. Allen, "Complex analog filters obtained from shifted lowpass prototypes", M.A.Sc. 
thesis, University of Toronto, 1985. 

5. S.A. Jantzi, K. Martin, and A.S. Sedra, "Quadrature bandpass DS modulation for digital radio," 
IEEE J. Solid-State Circuits, vol. 32, pp. 1935-1949, Dec. 1997. 

6. J. Crols, M.S.J. Steyaert, ' 'Low-IF topologies for high-performance analog front ends of fully 
integrated receivers," IEEE Trans. Circuits Syst. -II: Analog and Digital Signal Processing, 
vol. 45, no. 3, pp. 269-282, March 1998. 



References 33 

7. M. Hajirostam, K. Martin, "On-chip broadband tuner design for cable modem and digital 
CATV," 48th Midwest Symposium on Circuits and Systems, vol. 2, pp. 1374-1377, 2005. 

8. I. Galton, "Delta-Sigma data conversion in wireless transceivers," IEEE Transactions on 
Microwave Theory and Techniques, vol. 50. no.l, pp. 302-315 Jan 2002. 

9. ArSC Recommended Practice: Receiver Performance Guidelines, ATSC A/74, June 2004, pp 
13-14. 

10. Mobile and Portable DVB-TIH Radio Access Interface Specification, EICTA MBRAI-02. 

11. G. Sgrignoli, C.W. Rhodes, "Interference mitigation for improved DTV reception," IEEE 
Transactions on Consumer Electronics, vol. 51, no. 2, pp. 463^-70. 

12. S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds., Delta-Sigma Data Converters: Theory, 
Design, and Simulation. New York: IEEE Press. ISBN 0780310454. 

13. F. Munoz, K. Philips, and A. Torralba, "A 4.7mW, 89.5dB DR CT complex A£ ADC with 
built-in LPF," ISSCC Dig. Tech. Papers, pp. 500-501, Feb., 2005. 

14. K. Philips, P.A.C.M. Nuijten, R.L.J. Roovers, A.H.M. van Roermund, F.M. Chavero, M. 
T. Pallares, A. Torralba, "A 2mW, 89dB DR continuous-Time AX ADC with increased 
wide-band interference immunity," ISSCC Dig. Tech. Papers, pp. 86-87, Feb., 2004. 

15. Y. Le Guillou, and H. Fakhoury, "Elliptic filtering in continuous-time sigma-delta 
modulator," Electronics Letters, vol. 41, no. 4, pp. 167-168, 17th Feb., 2005. 

16. Hua Yu, Gang Wei, "Statistical distribution of the signal PAR in the practical OFDM 
systems," International Conference on Communications , Circuits and Systems Proceedings, 
vol 2, 25-28, June. 2006, pp. 1235-1239. 

17. Chun-Huat Heng, Manoj Gupta, Sang-Hoon Lee, David Kang, Bang-Sup Song, "A CMOS TV 
tuner/demodulator IC with digital image rejection," IEEE Journal of Solid-State Circuits, vol 
40, no. 12, Dec. 2005, pp. 2525-2535. 

18. S.A. Jantzi, K. W. Martin, and A. S. Sedra, "The effects of mismatch in complex bandpass AX 
modulators," IEEE International Symposium on Circuits and Systems, vol. 1, 12-15, May 
1996, pp. 227-230. 



Chapter 3 

A Complex AX Modulator 

with an Improved STF 



The presence of interferers puts a severe demand on the linearity requirements of 
the analog circuitry of a AE ADC and, in such applications, instead of unity signal- 
transfer functions (STF), it may be more desirable to have an STF with improved 
out-of-band attenuation. Depending on the application, e.g., single sideband (SSB), 
it may also be desirable to have higher attenuation in image band frequencies. 
Historically, complex transfer functions have been based on frequency 
transformations of real prototype filters. However, because of arithmetical symmetry, 
such complex transfer functions are inefficient in meeting the asymmetric 
requirements of a wireless receiver. 

The design of an STF with higher stop-band attenuation has an implication for 
the quality of the noise-transfer function (NTF). This chapter discusses the trade-off 
involved in STF-NTF design. 

The chapter further presents a methodology for designing arithmetically asym- 
metric complex signal-transfer functions and noise transfer functions that use 
complex filter routines [1] based on classical filter design procedures. A complex 
AS modulator architecture suitable for realizing the transfer functions that have been 
derived using the optimization is presented. The modulator and the design method- 
ology have been used to design a prototype modulator for the DTV (ATSC and 
DVB) specifications. The advantages of the proposed AE modulator are presented. 



3.1 AS Modulator Transfer Functions 

A complex single-loop AZ modulator can be modeled as a complex input linear 
block with arbitrary transfer functions, L and L ; , from its two inputs, U(z) and E(z), 
to the output (refer to Fig. 3.1) [2]: 

E{z) l-Li(z) 



B. Pandita, Oversampling AID Converters with Improved Signal Transfer Functions, 35 

Analog Circuits and Signal Processing, DOl 10.1007/978-l-4614-0275-6_3, 
© Springer Science+Business Media, LLC 2011 



36 



3 A Complex AX Modulator with an Improved STF 



Quantizer 



U=U re +yU 




Fig. 3.1 A complex AX modulator structure 



Y=Y re +/Y ln 



STF(z) = 



U(z) 



Lq(z) 
l-Li(z) 



(3.2) 



The double lines in the figure represent complex signals. 

The design of a AZ modulator typically starts with the selection of the NTF, which 
then defines L^z) and hence the poles of the NTF and the STF. However, L (z), 
which defines the zeros of the STF, can be chosen independently of the NTF, and this 
independence allows the design of modulators with non-flat signal transfer functions 
and stop-band attenuation characteristics controlled by the zeros of L (z). 

Figure 3.2 shows the structure of the proposed fourth-order complex AE 
modulator. The input feed-ins into each integrator stage set the four zeros of the 
fourth-order complex STF. The zeros of the complex NTF are set by the complex 
poles of the integrators, and a modulator with higher SNR over the signal band- 
width can be realized by distributing these zeros over the signal-band. The complex 
quantizer at the end of the channels (I and Q) of the modulator quantizes the 
complex analog-output signal and provide complex multi-bit output. The multi- 
bit outputs are feedback into the first stage of the modulator. 

The loop transfer functions, Li(z) and L (z), of the modulator are given by: 



L l {z) = -C 1 



\ z \ z Bi I z (B 2 +Biz- 1 ) z 



z-p x z-p 2 z-p 3 z-p 4 z-piz-p 3 z-p 4 z-pi z-p 4 

(3.3) 



L (z) = -C 1 L 1 (z)+F 1 



1 z 



F 2 - 



1 z 



z-p 2 z-p 3 z-p 4 z-p 3 z-~p 4 



(F 3 z- l +F 4 ) 



z-p 4 
(3.4) 



3.2 NTF-STF Design Trade-Off 



37 



3 2 T D3Z 




z-P 4 


"Pr 



>Y(z) 



Fig. 3.2 Structure for the proposed fourth-order AX modulator with input feed-ins to realize zeros 
in the STF 



From (3.4) and (3.2), it is evident that the input feedin coefficients (F) can be 
independently selected to define the zeros of the signal transfer function STF(z). 
This property provides a freedom to design signal transfer functions with sharper 
transitions or with higher attenuation in specific stop-band regions. 

A possible AE modulator design methodology could be to start with the design 
of the NTF and then use the feed-ins to control the STF zeros. The modulator 
coefficients can be derived by matching the STF and NTF with the desired transfer 
functions. However, an independent NTF and STF design disregards the inherent 
STF-NTF trade-off and implements either an STF with reduced stop-band attenua- 
tion or an NTF with degraded SNR. The next section discusses the trade-off 
involved in STF-NTF design. 



3.2 NTF-STF Design Trade-Off 

Filter approximation starts with the design of an input-output transfer function 
H(j(o) that approximates an arbitrary shape f(m) over the jco axis. For reasons of 
convenience, instead of H(jco), the filter approximation uses the characteristic 
function K(joj), which is defined this way [3] 



H(jco)H(-j(o) = 1 + K(j(o)K(-jco) 1 



(3.5) 



This equation is known in the literature as Feldtkeller's equation. 



38 



3 A Complex AX Modulator with an Improved STF 




Large s 



Small e 



Zeros of K(s) 



Fig. 3.3 Effect of £ on the attenuation characteristics of a filter 



Attenuation of the filter network is given by 



A(ffl) = 10 1og 10 |//0ffl)| 2 



10 log 



in 



\KU°>)\' 



(3.6) 



By eliminating the unity constant, the filter approximation problem is reduced to 
the determination of the characteristic function K(s). Thus, when K(j(o) is infinite, 
the attenuation is infinite, and, when K(ja>) is zero, the attenuation is zero (Fig. 3.3). 
The characteristic function can further be written as: 



K(ja>)K(—ja>) = e 



2 F(j(o)F(-ja) 
P{jm)P{-ja) 



(3.7) 



The parameter 'e' is referred to as the "passband ripple factor" [4]. From (3.7), 
it follows that, for given zeros and poles for K(s), different values of the parameter 
'g' will result in different zeros for the transfer function H(s). (refer to [4]). 

The constraints imposed on the characteristic function are [1]: 

• The zeros of K(s) lie in the pass-band, and 

• The poles of K(s) lie in the stop-band region. 



3.2 NTF-STF Design Trade-Off 39 

In terms of the zeros and poles of K(s), the magnitude of H(s) for an odd order 
filter can be written as: - 



\H(jco)\ 2 = l+L 2 



(o(w 2 x — an . . . (w 2 n — coj 



(tfi ~ m ) •••(<,- ro ) 



(3.8) 



A similar expression can be written for an even order filter. A bilinear 
transformed variable (Z) is used to map the filter passband to the entire imaginary 
axis and the stopband to the finite positive-real axis. The transformed variable Z is 
related to the frequency variable s by the relation [3]: 

9 S 2 + (Ob 2 

Z 2 = \ (3.9) 

S l + C0 A l 

As a result of this transformation, the pass-band region (s —joj, coa < \co\ < cog) 
of the s-plane is mapped to the entire imaginary Z-axis. The real frequencies (s = a) 
are mapped to the region 1 < Z < ojb/coa of the real Z-axis. Similarly, the stop-band 
(co>co B or co<(o A ) and transition band are transformed to the real Z-axis [4]. Two 
of the advantages of carrying the filter design in terms of the transformed variable Z 
are that: (1) it simplifies the filter design expressions, and also (2) improves the 
numerical accuracy of the poles of H(s) near the passband edge by spreading the filter 
passband. 

The trade-off involved in an STF-NTF design can be explained by considering 
an example of a filter design with poles of K(s), which are placed using an iterative 
procedure as discussed in [1], For an equiripple or maximally flat passband 
response the zeros of the characteristic function, K(s), are defined explicitly by 
the poles of K(s). In terms of the transformed variable Z, the characteristic function 
K(s) is given by: 

K(7\K( 7] _ r 2 KP(Z)+P(-Z))/2] 

K(Z)K(-Z) - £ P{Z)P{ _ Z) ( 3 - 1Q ) 

For a maximally flat passband, the characteristic equation is given by: 

K(Z)K{-Z) = e 2 { , ±p>- (3.11) 

v ' v ; P{Z)P{~Z) 



" The zeros of the transfer function H(s) are referred as natural modes, and, similarly, the zeros and 
the poles of the characteristic function are known as reflection zeros and loss poles in the filter 
design literature. 



40 3 A Complex AX Modulator with an Improved STF 

where 

l/m 



7 2 



^ \2NZ N 

-) IK 



■■NZ + NIN + 2N (3.12) 



Z, is the transformed variable corresponding to the poles of K(s) on the imagi- 
nary axis (s = joj) ; NZ — number of poles of K(s) at the origin; NIN = number of 
poles of K(s) at oo; and N — number of poles of K(s) on the jco axis. The transfer 
function H(s) can be obtained by solving (3.5) and assigning the roots in the left- 
half plane to H(s). 

An insight into STF-NTF trade-off can be gained by considering a discrete 
fourth-order inverse Chebyshev filter with a monotonic passband and equiripple 
stop-band behavior designed for different values of the stopband attenuation 
parameter L(=llz). The Feldtkeller equation for a fourth-order inverse Chebyshev 
filter with unity bandwidth and in terms of the continuous frequency variable s can 
be written as: 

mH(-s) = l + V4{s _ l ^ { _ s _ 1) (3.13) 

where V^s) is the fourth-order Chebyshev polynomial given by: 

V 4 (s) = 8/ - 8.v 2 + 1 (3.14) 

The transformation from the continuous analog filter to a discrete filter with 
bandwidth co c can be done by the low-pass to low-pass transformation, written as 
(3.15), followed by the bilinear transformation, written as (3.16) 



(3.15) 
tan(^) 



2 z- 1 
5--— T (3.16) 

T z+ 1 

Figure 3.4 shows the magnitude plot of the fourth-order inverse Chebyshev filter 
versus co for different values of the stopband parameter L. The case L=0 
corresponds to the degenerate case where the zeros of H(s) and the poles of the 
characteristic function K(s) cancel out each other exactly. Figure 3.5 shows the 
movement of the poles of the filter for increasing values of stopband attenuation. 
The figure makes it is evident that for higher stop-band attenuation of the low-pass 
filter, the filter poles crowd into the passband and stop-band transition region. 
A further insight into the movement of the filter poles can be gained by drawing a 
root locus plot of (3.13), with L(=1/e) as the variable gain parameter. The zeros of 



3.2 NTF-STF Design Trade-Off 



41 



20 

-20 
-40 
-60 
-80 
-100 
-120 
-140 



L=0dB 




20 dB 




~W\ 


\\l^ 


1 40 dB 




I I I I 1 


f 60 dB 


- 





0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 



Fig. 3.4 Plot of the magnitude of the fourth-order Chebyshev filter for different values of the 
stop-band attenuation parameter L 




Re(z) 



60 dB 

40 dB 

L= 20 dB 



For L=0 dB the zeros of H(s) 
coincide with its poles 

Fig. 3.5 Movement of the poles of H(s) for increasing values of the attenuation parameter L 



H(s) are given by the points on the root locus branches for different values of L. 
The root locus branches start from the poles, <o pi , of the characteristic function K(s) 
for L — > and terminate on the zeros, co Z j, for L — > oo (Fig. 3.6). 

What this movement means is that, at increasing values of stopband attenuation, 
the zeros of H(s) move from the stop-band into the passband region. This movement 



42 



3 A Complex AX Modulator with an Improved STF 





Real axis 

Fig. 3.6 Root-locus of the equation (3.8) as the filter attenuation, L, varies 



of zeros of H(s) into the passband can cause partial or full cancellation of the zeros 
of the NTF and result in degradation of the NTF SNR at increasing values of the 
stop-band attenuation. 



3.3 Background 

3.3.1 The \L\ l Norm and its Impact on the NTF Poles 

The |L|j norm of an impulse response of a transfer function H(z) is given by: 



E i^wi 



(3.17) 



B=0 



where h(n) is the impulse response of the transfer function H(z). The \L\ l norm has 
been used as a stability criterion in the design of delta-sigma modulators. Some of 
the other criteria used in the design of stable delta-sigma modulators are: 



\L\ 2 = J2\ h (") 



(3.18) 



n-0 



3.3 Background 43 

and 

\H\ X = max |//(e*»)| (3.19) 

Compared with the |L| 2 and |H| M norms, the \L\ l norm is a stricter norm [5,6]. 
For a stable AS modulator, the upper and lower bounds on the quantization error 
accumulated at the input of the quantizer are given by: 

oc » 

«(n)<j>(n)|- 

= (|Z,| 1 -1)| (3.20) 



and 



e(n) > J2 1%) 



i=\ 



-A 
~2~ 



= -(Wi-l)| (3-21) 

Equations (3.20) and (3.21) assume that the quantization error is bounded 
between — A/2 and A/2, and, for an NTF, /?(0) = 1. For an M-step quantizer to 
avoid overdriving the quantizer, the accumulated quantizer errors plus the peak- 
to-peak amplitude of the input, u(n), should be less than the full-scale range, 
(M + 1)A, of the quantizer. Hence, the worst case upper bound of: 

(M+ 1)A + A- max|w(«)| 
\L\ , = (3.22) 



for the |L| j norm guarantees that the accumulated quantization errors do not exceed 
the stable input range of the quantizer and ensures the stability of the modulator. 

The relation of the \L\ l norm to the NTF gain and the poles of the NTF can be 
seen in Fig. 3.7. Figure 3.7a shows the magnitude response for a fourth-order NTF 
at different values of the \L\ l norm. The NTF poles have been designed using the 
inverse Chebyshev function from the Matlab toolbox [7], and the NTF zeros have 
been independently distributed over the signal bandwidth. Figure 3.7a shows a 
pole-zero plot of the NTF poles and the corresponding values of the \L\ { norm. 
From Fig. 3.7, the conclusion may be drawn that the \L\ l norm increases as the 
NTF poles move away from the signal pass-band. This relation of |L|j norm to 
the NTF poles can be used to constrain the placement of the NTF poles and hence 
indirectly control the STF stop-band attenuation. This relation forms one of the 
constraints in the STF-NTF design optimization algorithm. 



44 



3 A Complex AX Modulator with an Improved STF 




0- 1 0.2 0.3 0.4 

Normalized frequency (!-»/$ ) 



0.5 



lm(z) 



/ 

/ 
/ 

/ 
/ 
/ 
i 
1 
1 
1 
i 


'«.>»"J\: 

..X \ 

\ / 4\ 
* 1 /*3i ■ 


1 
1 
■ \ 
\ 
\ 
\ 
\ 
\ 
\ 
\ 


1 k * «? 

1 \ ^ ; ■ 
s< / ■ 

x 

/ 

/ 
/ 



Re(z) 



Fig. 3.7 (a) NTF magnitude for different values of the \L\ , norm, (b) movement of the NTF poles 
with an increase in the \L\ l norm 



3.3.2 The Loss Function L(Z) 



As discussed in Sect. 3.2, the poles of the characteristic function K(s) are 
constrained to be in the stop-band region, and the zeros are constrained to be in 
the passband region. By defining the poles of K(s) and the type of desired passband, 
it is possible to use simple formulae, as shown in (3.9) and (3.10), to directly 



3.3 Background 



45 



Fig. 3.8 A flow chart for 
filter designing with defined 
stop-band zeros and passband 
response type [4] 



Input 



1 . Passband type 

2. Filter zeros 

3. Passband deviation 



Calculate zeros of K(s) 
using the appropriate 
formulae 



Solve the Fedltkeller 
equation: 



The zeros of H(s) in the 
LHP and the zeros of K(s) 
define the filter transfer-function 



calculate the zeros of the characteristic function K(s). These calculated zeros and 
the pre-defined poles can then be used in solving the Feldtkeller's equation and 
extracting the zeros of the input-output transfer function H(s). 

The approximation problem for filter design when the zeros of the filter and the 
desired passband response are defined can be solved by a computer program 
illustrated in the flowchart of Fig. 3.8. This solution means that, given the filter 
zeros, the passband deviation, and the passband type the filter transfer function can be 
determined. However, in actual filter design, the stopband zeros are not known, and 
the task of the computer program still remains to find them. It is possible to introduce 
a function, L(Z), which, for an equiripple or maximally flat passband type, enables us 
to calculate the stop-band attenuation only in the terms of filter zeros. For a filter with 
an equiripple filter passband <±>a < co < cl>b and with the following zeros: 

• NZ zeros at the origin 

• N finite zeros at co,-(i = 1, 2, . . . iV) 

• NIN zeros at infinity 



the loss function L(Z) is defined as 



L(Z) = 



ffi> j j/m A \ ivz/2 /Z- 
(Ob/(o a J \Z 



NIN /2 N 



n 



Z + Zj 



(3.23) 



where Z? = ( 



(!J- 



co: 



i)/( 



cat — co a 



46 3 A Complex AX Modulator with an Improved STF 

For an equiripple passband filter, the stop-band attenuation is given by 



A(m) = 10 log 



s 2 / 1 x 2 

l + E -(\L\ 



(3.24) 



A similar expression showing the stop-band attenuation only in terms of filter 
zeros can be found for a filter with maximally flat passband. The significance of this 
result lies in the fact that for a filter with an equiripple or maximally flat passband 
response the zeros of the filter uniquely determine the stop-band attenuation. 

The filter approximation algorithm can now be described as: 

• The poles of K(s) are iteratively modified to achieve the stop-band attenuation. 
This process of finding the optimum pole positions is known as pole placement. 
A modified Remez algorithm for pole placement has been described in [1]. 

• After achieving the optimum pole positions, the zeros of the characteristic 
function K(s) are obtained, as shown in (3.10) and (3.11). 

• Finally, the Feldtkeller's equation (3.5) is solved in order to evaluate H(s). 

On the basis of this background information on the |L|j norm and its impact on 
the STF-NTF poles, and the pole placement algorithm that can be used for the 
optimum placement of zeros of the STF, the Sect. 3.6 describes an optimization 
algorithm for the STF-NTF co-design. 



3.4 STF-NTF Co-Design Optimization Algorithm 
for the Design of Real AX Modulators 

The STF-NTF co-design optimization algorithm for the design of lowpass AE 
modulator transfer functions can be described as [8]: 

• The zeros of the STF are derived using the pole-placement algorithm described 
in[l], 

• The Optimization algorithm proceeds with the minimization of the objective 
function, given by: 

u>s 

Ins I! 

I \NTF(a>)\ 2 dm (3.25) 

o 

Note the limits of the integral have been modified to correspond to the in-band 
noise for the lowpass case. 

• The constraints for the minimization of the objective function are 

(a) the |L|j norm of the impulse response of the NTF. 

(b) the maximum radius for the NTF poles. 

(c) the maximum-deviation of the STF over the passband 



3.4 STF-NTF Co-Design Optimization Algorithm for the Design. 



47 



3 20 



-20 

m -40 

-60 

-80 

-100 



E0 




Optimized NTF 



NTF with Butterworth 
Poles 



16 32 

Frequency (MHz) 



64 



X 

X ° 

O 

* ° 

X 





Re(z) 



X 

x « 

o 

° 




Re(z) 



I 



^ - 



STF with 

zeros in stop-band 




16 32 

Frequency (MHz) 



x 
x 

....O' 



-1 




Re(z) 



X 



o 

Re(z) 



Fig. 3.9 Real Transfer functions for SQNR=88 dB. (a) NTF magnitude response, (b) pole-zero 
constellation for the non-optimized NTF, (c) pole-zero constellation for the optimized NTF, 
(d) STF magnitude response, (e) pole-zero constellation for the non-optimized STF, (f) pole- 
zero constellation for the optimized STF 



An additional constraint on the complex poles and zeros of the NTF and STF is 
that they occur in complex conjugates. This limitation restricts the flexibility to 
place the complex poles and zeros in optimal positions: 

NTFs, and STFs were derived for an SQNR of 88 dB and 101 dB. Figures 3.9 
and 3.10 show the NTFs and STFs derived for a lowpass AX modulator for the 
following two cases: 

1 . The NTF and STF are derived independently. The transfer function design starts 
with an NTF that meets the required SQNR specifications, and the lowpass STF 
is obtained by inserting zeros in the stop band. 



4<S 



3 A Complex AX Modulator with an Improved STF 




Optimized NTF 



NTF with Butterworth 
Poles 



32 32 
Frequency (MHz) 




STF with 

zeros in stop-band 



64 




-32 32 

Frequency (MHz) 



J= 



■o . 

.o" 

• -x 

X 

O. _-•" 

...-0'' 




Fig. 3.10 Real Transfer functions for SQNR=101 dB. (a) NTF magnitude response, (b) pole-zero 
constellation for the non-optimized NTF, (c) pole -zero constellation for the optimized NTF, 
(d) STF magnitude response, (e) pole-zero constellation for the non-optimized STF, (f) pole- 
zero constellation for the optimized STF 



2. The NTF and STF are co-derived employing the proposed algorithm. The 
algorithm starts with placement of the NTF and the STF zeros, and proceeds 
to the positioning of the transfer function poles. 

As is seen from the Figs. 3.9 and 3.10 the NTFs derived by the by the proposed 
algorithm achieve the required SQNR, and the STFs have superior out-of-band 
rejection (refer to Table 3.1). 



3.5 Power and Performance Analysis of the Proposed Real AZ Modulator 49 

Table 3.1 SQNR vs. 
stop-band attenuation 
performance summary 



Stop-band attenuation (dB) 




Optimized Non-optimized 


SQNR(dB) 


25 20 
50 40 


101 

88 



3.5 Power and Performance Analysis of the Proposed 
Real A2 Modulator 

Figure 3.11 shows the AZ modulator proposed in Sect. 3.1 modified to realize a 
low-pass AZ modulator. The A£ modulator architecture resembles a distributed 
feedforward architecture without input coupling [9]. The resonator formed by 
the last two delaying integrator stages and G\ coefficient realize a pair of NTF 
zeros located at non-zero frequencies outside the unit circle, at z = 1 +j\/G\ [9]. 
Figure 3.12a shows the shape of the NTF designed for the proposed AE modulator. 
The NTF has been designed to realize an SQNR of 88 dB. A disadvantage of the 
architecture shown in Fig. 3.11 is that once the coefficients B u B 2 , 5 3 , G\, and C 2 
have been decided to realize the optimum loop filter, the shape of the STF is fixed. 
As can be seen from Fig. 3.12b the STF for the selected loop-filter shape shows an 
out-of-band peaking. This out-of-band peaking can cause reduced input signal 
range and instability problem in presence of interfering signals. It is possible to 
control the shape of the STF by introducing zeros in the STF. In Fig. 3.13 the STF 
zeros have been realized by feeding input signal weighted by the feed-in 
coefficients, F u F 2 , F 3 , and F 4 , to each integrator input. 

The NTF for the architecture shown in the Fig. 3.13 is given by: 

^=i3cb^y (3 - 26) 



where 



(z- 1) 
U 0) - -B 3 I(z) + B 2 I(z) , \ 2 ; — + B x I(z) - 



{z-iy+Gx (z-ir+G, 

/(z) = l/(z — 1) is the transfer function of the delaying integrator. 
The STF for the architecture shown in the Fig. 3.13 is given by: 

STF(z) = °7 (3.27) 

1 -C 2 Li{z) 



where 

L (z) = -C l L l (z)+F l I(z)- \- 2 + F 2 - \- 2 + F 3 ^"^ +F 4 

(z-l) 2 +G! (z-l) 2 +G! (z-l) 2 +Gi 



50 



3 A Complex AX Modulator with an Improved STF 



X(z)_*[>*0h> J^ W* ^ 




•Y(z) 



Fig. 3.11 The proposed AX modulator modified to realize a fourth-order real AX modulator 




16 24 32 40 48 56 64 
Frequency (MHz) 



out-of-band peaking 
of the STF 



8 16 24 32 40 48 56 64 
Frequency (MHz) 



Fig. 3.12 The STF and NTF the proposed AX modulator without feed-ins: (a) NTF magnitude 
gain, (b) STF magnitude gain 

An interesting choice for the feed-in coefficients is to make C\ = C2, 
F\ = F2 = Fj = 0, and F4 = 1. By the selection of these values for the feed-in 
coefficients the STF is equal to 1 . Analysis of the input feedforward AE modulator 
architecture with unity STF reveals several advantages of the architecture: 

• The input to the loop filter is given by: 



X - Y = X - STF ■ X - NTF ■ E = NTF ■ E 



(3.28) 



Thus the loop filter has to process quantization noise only. This results into 
reduced swings at the outputs of the integrators, which relaxes the headroom 
requirements of the opamps. 



3.5 Power and Performance Analysis of the Proposed Real AX Modulator 



51 



X(z) 1 +£>_k2 > ->. J- !*©_► 



# 




o 



^^Afrt 



-G, 



£■ 



•Y(z) 



< 

Fig. 3.13 The proposed AX modulator modified to realize a fourth-order real AX modulator with 
input feed-ins to realize zeros in the STF 



• The distortion added becomes independent of the input signal, and this relaxes 
the linearity requirements of the analog blocks in the modulator. 

A disadvantage of the input-feedforward architecture is that the feedforward 
introduces a delay-free loop starting from the input, through the quantizer, and finally 
through the DAC back to the input of the loop filter. This delay-free loop creates a 
speed path that complicates its implementation for high speed multi-bit modulators 
[10]. Also an active summation of the input signal and the loop filter output at the 
input of the quantizer increases the circuit complexity and power dissipation. An 
alternative technique of passive summation results into reduced signal level at the 
quantizer input, and hence demands comparators with higher resolution. 

The proposed STF-NTF co-design optimization algorithm was used to design 
an NTF for an SQNR of 88 dB (OSR = 32), and an STF with low-pass filtering 
characteristics. Figure 3.14 shows the NTF and the low-pass filtering STF designed 
with the STF-NTF co-design optimization algorithm. A real AE modulator with the 
filtering STF (referred to as FADC in further discussion) and the NTF was 
implemented and compared to an input-feedforward AE modulator with the same 
NTF but with unity STF (referred to as FFADC in further discussion). The 
modulators were compared for power, and the impact of DAC and other coefficient 
mismatches on the modulator performance. 

The ADCs were simulated in SIMULINK (Matlab) under the following conditions: 

1. The a(3y representation [11] has been used to model the impact of finite dc gain 
of the opamp on the transfer function of an ideal integrator. The integrator model 
accounts for the finite dc gain and the output saturation voltages of the opamps. 

2. The output saturation voltages of the integrators have been set at ± 1 . 



52 



3 A Complex AX Modulator with an Improved STF 




8 16 24 32 40 48 56 64 
Frequency (MHz) 

lm(z) 



X ■ . 

i-2 - 



16 24 32 40 48 56 64 
Frequency (MHz) 









Im(z) 




I 










.0 


: 








X 


Re(z) 







» 




" 








i « / 






o. 


.-■' 




-1 




. ._,...o' 



Re(z) 



Fig. 3.14 The STF and NTF the proposed AZ modulator with feed-ins to implement STF zeros: 
(a) NTF magnitude gain, (b) STF magnitude gain. Pole-Zero plot of: (c) NTF, (d) STF 

3. Dynamic range scaling was performed to make the swings at the integrator 
outputs for the FFADC, FADC comparable. 

4. A DAC mismatch of ±0.5% and ±0.1% was assumed to simulate for the 
impact of DAC non-linearity on the SNDRs of the ADCs. 



3.5.1 Power Comparison 

Figure 3.15 shows the signal swings at the integrator outputs for the feedforward 
modulator with unity STF (FFADC), which are estimated through the use of a 
histogram plot from the behavioral model simulation in Matlab. Figure 3.16 shows 
the histogram plots of the integrator outputs for the proposed real modulator with 
filtering STF (FADC). A comparison between Figs. 3.15 and 3.16 that the integrator 
swings for the modulator with unity STF are smaller; for example, for the first stage, 



For the selected process the standard-deviation (a) for capacitor mismatch is given by 
<t% = -J— (appx.). Assuming the smallest realizable unit capacitor of dimensions 6[i x 6[i yields 
<r% = 0.16. Hence, for a 3a design assuming a mismatch of 0.5% seems reasonable. 



3.5 Power and Performance Analysis of the Proposed Real AX Modulator 



53 



X10 J 



x10 J 



18 




18 


16 








16 


14 








14 


12 














12 


10 














10 


8 














8 


6 














6 


4 














4 


2 


















2 


n 
















I I i 






-0.2 -0.15 -0.1 -0.05 0.05 0.15 0.2 
First integrator output 
c 

x10 3 
18 

16 
14 
12 
10 

8 

6^ 

4 

2 


-0.04 



-0.02 0.02 

Third integrator output 



-0.2 -0.15 -0.1 -0.05 0.05 0.15 0.2 
Second integrator output 

x10 3 



16 




14 


I — 




■ 


12 










- 


10 










- 


8 












■ 


6 














- 


4 
















- 


2 

n 
















— i - 



0.04 



-0.015-0.01 -0.1 -0.005 0.005 0.01 
Fourth integrator output 



Fig. 3.15 Histogram plots of the integrator outputs for the modulator with unity STF (FFADC) 



the output swings are about one-sixth of the proposed FADC and have higher 
distribution around the output common-mode. This difference in integrator swings 
means that, assuming that the same sampling capacitor sizes are constrained by 
noise considerations, dynamic range scaling [9] can be applied to make the 
integrating capacitors smaller in the £ ADC with unity STF. This application 
results in reduction of the area of the chip. 



3.5.2 Sensitivity to Intermodulation Due to DAC Non-linearity 



AE modulators employ multi-bit quantization to meet the desired SNDR 
specifications. The advantages of the multi-bit quantization include 6 dB increase 
in the SQNR for every quantizer bit, the enhanced linearity of the feedback loop, 
and the relaxed slew rate requirement of the opamps in the loop filter. However, due 
to the device mismatches, the digital-to-analog converter (DAC) in the feedback 
path is inherently nonlinear. Error introduced by the DAC directly feeds to the input 



54 



3 A Complex AX Modulator with an Improved STF 



X10 J 



15 



10 



x10 J 





-0.8 -0. 





12 










10 
















- 


8 










- 


















6 
4 


















! - 












- 


















2 
























- 














































6 -0.4 -0.2 0.2 0.4 0.6 
First integrator output 



10 



x10 J 



-0.8 -0.6-0.4 -0.2 0.2 0.4 0.6 0.8 

Second integrator output 
I 

x10 3 



9 




- 


8 










- 


7 












- 


6 












- 


S 




















. 


4 






3 






















- 


2 






















- 


1 






















- 




-0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 
Third integrator output 



-0.2-0.15-0.1-0.05 0.05 0.1 0.15 0.2 
Fourth integrator output 



Fig. 3.16 Histogram plots of the integrator outputs for the modulator with filtering STF (FADC) 



of the AE modulator. DAC non-linearity causes the high-frequency quantization 
noise to alias into the signal band, and results into the degradation of the SNDR of 
the modulator (refer to Fig. 3.17). 

To determine the SNDR degradation of the modulators due to DAC mismatches, 
Monte Carlo simulations were run with a differential error ±0.5% and ±0.1% added 
to the DAC elements. The input to the modulators is a triple-tone consisting of: (1) 
-46 dBFS input at 4 MHz, (2) two interferers of strength —6 dBFS each at the 
frequencies of 24 MHz and 46 MHz respectively. Results from a set of 100 Monte 
Carlo simulations with DAC mismatches of ±0.5% and ±0.1% show that the 
SNDRs of the FFADC drops significantly and shows an SNDR (95th percentile) of 
14.5 dB and 28.10 dB respectively. The FADC shows comparatively lower degrada- 
tion in the SNDR and shows an SNDR (95th percentile) of 37.24 dB and 24.3 dB for 
the same DAC mismatches (refer to Table 3.5) (Figs. 3.18 and 3.19). 

Table 3.2 summarizes the comparison between the proposed modulator with 
filtering STF and the feedforward modulator with unity STF for the test input (-46 
dBFS desired signal at 4 MHz, two interfering signals of strength -6 dBFS each and 
at the frequencies of 24 MHz and 46 MHz respectively). 



3.5 Power and Performance Analysis of the Proposed Real AX Modulator 



55 



Interferer Interferer 
tl = 24 MHz f 2 = 46 MHz 



VA 




Intermodulation tone - 
generated due to DAC 
non-linearity 



20 30 40 50 
Frequency (MHz) 

FFADC 



Interferer Interferer 
f 1= 24MHz f 2 = 46MHz 




20 30 40 50 
Frequency (MHz) 
FADC 



Fig. 3.17 Output PSD plot of the real AX modulators with DAC mismatch = ±0.5% for a weak 
desired signal (f ) at —46 dBFS and strong interferers (f t and f 2 ) at —6 dBFS 



16 














18 
















14 














16 














- 


12 




















14 


















- 


10 






















12 




















- 


























10 




















- 


a 
























8 
























6 


























6 
























4 


























4 
























- 


2 


























2 
























- 


o 


























o 


























26 


28 30 


32 34 36 38 40 


4 


2 35 


36 


37 


38 39 40 41 


42 4 












F 


FA 


DC 
























FA 


DC 













Fig. 3.18 Histogram plots of the SNDR for the FFADC and FADC for DAC mismatch = ±0. 1 % 



The reason for the large degradation in SNDR for the feedforward AS 
modulator with unity STF can be understood by comparing the output PSDs 
for the two architectures. For the feedforward AE modulator with unity STF, 
the interfering tones at the output of the quantizer remain of the same magnitude 
as at the input (refer to Fig. 3. 20). The large out-of-band quantization noise and 
the interfering tones are aliased back in-band due to the DAC non-linearity 
resulting into a severe SNDR degradation. Figure 3.21 shows the PSD at 
the output of the proposed real AS modulator. Due to the filtering nature of the 
ADC the interfering signals at the output of the quantizer are attenuated, and that 



56 



3 A Complex AX Modulator with an Improved STF 



20 

18 

16 

14 

12 

10 

8 

6 

4 

2 





I — I 


25 


1 


■ 


■ 












20 






■ 


I 


~ 














15 
10 














■ 






















5 














— 1 


n 
















~l ^ 


n 
















. r - 1 



10 15 20 25 30 35 
FFADC 



22 24 26 28 30 32 34 36 38 40 
FADC 



Fig. 3.19 Histogram plots of the SNDR for the FFADC and FADC for DAC mismatch = ±0.5% 



Table 3.2 SNDR Comparison for the FFADC and FADC for DAC Mismatch 



Modulator 


SNDR min 


SNDR max 


SNDR a 


DAC Mismatch 


FFADC 


27.22 


41.03 


28.10 


±0.1% 


FADC 


35.65 


42.62 


37.24 




FFADC 


11.75 


31.80 


14.5 


±0.5% 


FADC 


22.65 


38.54 


24.3 





a 95 th Percentile 



means reduced intermodulation products caused by DAC nonlinearities (refer 
to Figs. 3.22 and 3.23). This results into superior SNDR performance of the 
filtering ADC. 

The two ADCs were compared for the impact of opamp dc gain variation and 
coefficient mismatch on SNDR performance. For an opamp dc gain variation from 
80 dB to 40 dB both the architectures show an SNDR degradation of less than 0.5 
dB. Similarly, for a coefficient mismatch of ±0.5% the two ADCs show an SNDR 
degradation less than 1 dB. 



3.5.3 Stability Comparison 



The proposed filtering AE modulator with optimized NTF poles was investigated 
for stability. Two types of modulators were designed with a peak NTF gain of 12 
dB. One modulator was built with NTF poles arranged in butterworth order, and the 
second modulator was designed with NTF poles optimized by the STF-NTF 
co-design algorithm. The AE modulator with optimized NTF poles behaves well 
for inputs up to full-scale and reaches a peak SNR of 88 dB. The modulator with 
NTF poles arranged in butterworth order does not show any stability advantage 
over the modulator with optimized NTF poles. 



3.5 Power and Performance Analysis of the Proposed Real AX Modulator 



57 




20 30 40 50 
Frequency (MHz) 
First Integrator output 



20 30 40 
Frequency (MHz) 
Second Integrator output 




20 30 40 50 
Frequency (MHz) 
Third Integrator output 



10 20 30 40 50 60 
Frequency (MHz) 
Fourth Integrator output 




30 40 50 
Frequency (MHz) 
Input to the quantizer 



20 30 40 50 60 

Frequency (MHz) 
A£ modulator output 



Fig. 3.20 PSD plots at the integrator outputs for the feedforward ADC with unity STF (FFADC) 



58 



3 A Complex AX Modulator with an Improved STF 




re 



20 30 40 50 
Frequcncj iMtt/i 

First Integrator Output 



20 30 40 50 

frequent} (Mils) 

Second Integrator Output 



20 




-40 








B -60 
i.100 


/*** 


^^^rPP 


l^f^w 


•120 




-140 




-190 





10 » 30 40 50 60 
treqianK) IMlfr) 

Third Integrator Output 




Fourth Integrator Output 




20 30 40 50 
Frvqucnc> lMH/1 

Input to the quantizer 



20 30 40 50 
Ircqumc} (Mllr> 

\L modulator output 



Fig. 3.21 PSD plots at the integrator outputs for the ADC with filtering STF (FADC) 



3.5 Power and Performance Analysis of the Proposed Real AX Modulator 



59 



■> 



> 



O-n 



u -r*{>-^©-^ '(*) **&+ 'ft) -*©-* 'ft) -*©-► i(z) -r>Q-+ /" 




Interferer 
unattenuated 
at the output 



\ 



< 



Quantization noise 



& 



<r 



I 



In-band signal 



out of band signal 



Fig. 3.22 Response of the feedforward AX modulator ADC with unity STF to an in-band signal 
and out of band interferer 



T 

u -r*[>-KD->] l(z) 9*0~*\ l(z) 



-t> 



^> 



o 



£>-i 




i>- 1 



'ft) 



i 



■> 



Interferer 
attenuated 
at the output 



HH i(z> f^H/V 



\ 
h 



<r 



■> 



<J 



In-band signal 



out of band signal 



Fig. 3.23 Response of the feedforward AX modulator ADC with filtering STF to an in-band signal 
and out of band interferer 



60 3 A Complex AX Modulator with an Improved STF 

3.6 The STF-NTF Co-Design Optimization Algorithm 
for the Design of Complex AX Modulators 

It is possible to derive complex transfer functions from the real prototypes by 
performing a simple frequency translation of the filter [25]. The real prototype 
filter symmetric about the dc is transformed into a non-zero IF complex filter 
symmetric about the IF. However, a disadvantage of complex filters derived this 
way is that they are arithmetically symmetric. Sometimes, it maybe desirable, for 
example, SSB modulation or demodulation, to derive complex filters with asym- 
metric specifications. With the background knowledge developed in Sect. 3.3, the 
optimization algorithm for an STF-NTF co-design for a complex AX modulator can 
now be described as [8]: 

• The zeros of the STF are derived using the pole-placement algorithm described 
in[l]; 

• The Optimization algorithm proceeds with the minimization of the objective 
function, given by: 



\NTF(ca)\ 2 dco (3.29) 



• The constraints for the minimization of the objective function are: 

(a) The \L\ l norm of the impulse response of the NTF NTF(z). 

(b) The maximum radius for the NTF poles. 

(c) The maximum-deviation of the STF over the passband 

A fourth-order complex delta-sigma modulator was designed for the DTV 
receiver specifications for the DVB and ATSC [12,13]. To avoid issues such as 
dc-offset that are related to Zero-IF, the IF has been set at BW/2 (where BW 
corresponds to the signal bandwidth for the particular standard). For example, for 
ATSC and DVB DTV standards with signal bandwidths of 6 MHz and 8 MHz 
respectively, the IF has been set at a value of 3 MHz and 4 MHz respectively. For a 
maximum signal bandwidth of 8MHz, the sampling frequency has been set at a 
value of 128 MHz, which corresponds to an over-sampling ratio of 16. 

In the first version of the modulator, the NTF zeros were distributed over the 
signal bandwidth. In a second version, three of the NTF zeros were distributed over 
the signal bandwidth and the fourth zero has been placed at the image frequency in 
order to reduce the aliasing of image-band noise into the in-band region of the 
modulator [14]. Sacrificing one of the NTF zeros degrades the signal-band 
quantization noise shaping of the modulator, but it results in a modulator with 
higher immunity to coefficient mismatches. The topic is further discussed in Chap. 4. 
For the DTV receiver application, it is advantageous to design an asymmetric 
complex STF with greater attenuation in the image band. An advantage of complex 



3.6 The STF-NTF Co-Design Optimization Algorithm. . . 61 

transfer functions not designed by a simple frequency shift of the real lowpass 
prototype filters lies in the fact that they can be designed to meet these asymmetric 
requirements optimally. 

The algorithm starts with an initial STF zero placement derived using [1] and 
then proceeds with the minimization of the objective function (refer to (3.29)). 
Through application of an iterative procedure involving fixed and moveable zeros 
of the transfer function, which is a feature allowed by the complex filter approxi- 
mation routines, it is possible to experiment with different stop-band attenuations 
and the STF-NTF design. Figure 3.24 shows the NTF and the STF, which have 
been designed using the optimization algorithm for |L|]= 3.5. With help of 
Mathematica, the transfer-functions were mapped to the modulator coefficients 
shown in Fig. 3.2. Figure 3.24b shows the asymmetric filtering STF. The STF 
achieves a stop-band rejection of greater than 40 dB and 60 dB for the positive and 
negative frequencies respectively. Figure 3.24e shows a 64k-bin output spectrum 
of the modulator simulated in Matlab. With a 15-level DAC and at a sampling 
frequency of 128 MHz, the complex AE modulator achieves an SNDR of 55 dB for 
a -3 dBFS tone input frequency of 4 MHz. 

Figure 3.25 also shows the NTF and the STF designed using the optimization 
algorithm for different values of the |L|j norm. Some of the things that can be 
observed from the figure are: 

• Increasing the |L|j norm causes the NTF gain and the NTF attenuation to 
increase. 

• Increasing the |L| [ norm degrades the stop-band attenuation of the STF. 

After mapping the transfer-functions to the modulator coefficients, a set of 
simulations were performed in order to observe the SNDR of the modulator. 
Table 3.3 summarizes the modulator performances for different signal and noise 
transfer functions generated using the optimization algorithm. The transfer 
functions derived for the norm value of |L|[ = 6.5 have been selected for the 
implementation of the proposed AE modulator. 

Figure 3.26a, b show the NTF and the STF selected for the proposed complex 
AZ modulator. The modulator achieves an SNDR of 80 dB for a -3 dBFS tone input 
frequency of 4 MHz. 

A set of fourth-order real NTFs was designed to meet a list of SQNR 
specifications of 101 dB, 94 dB, and 89 dB. The real NTFs were designed for a 
signal bandwidth of re/16 radians and an OSR of 16 (In terms of frequency this 
could correspond to a signal bandwidth of 4 MHz and sampling frequency of 128 
MHz). The zeros of the NTF were distributed over the signal band, and the poles are 
placed in the butterworth configuration. It is possible to constrain the NTF pole 
position by specifying the out-of-band NTF gain. The lowpass transfer functions 



By using the modulator stability condition derived in (3.22), the case |L|j= 6.5 corresponds to an 
input signal more than 65% of the quantizer range, whereas the case |L|[= 7.5 corresponds to 
an input signal less than 60% of the quantizer range. 



62 



3 A Complex AX Modulator with an Improved STF 





-64-48 -32-16 16 32 48 64 
Frequency (MHz) 

lm(z) 



-64 -48 -32 -16 16 32 48 64 
Frequency (MHz) 

lm(z) 



/ X \ 

X % 

':.... K I 

X I 



1 



Re(z) 



/ * \ 

/ X I 

;....* 

i x / 



Re(z) 




-64-48 -32 -16 16 32 48 64 
Frequency (MHz) 

Fig. 3.24 Design of the STF-NTF using the optimization algorithm for \L\ { = 3.5: (a) NTF 
magnitude gain, (b) STF magnitude gain, (c) NTF pole-zero plot, (d) STF pole-zero plot, (e) 
PSD plot of a complex AX modulator with STF and NTF transfer-functions as shown in (a) and (b) 



were frequency shifted to an angular frequency of re/ 16 (4 MHz) to realize complex 
transfer functions. The frequency shift was implemented by multiplying all NTF 
poles and zeros by e^ 11 / 16 '. As a result of the frequency shift the poles and zeros of 
the NTF have no complex-conjugates and the magnitude response is not symmetric 
about dc. The STF shares poles with the NTF. To realize a complex filtering STF 
zeros were inserted in the stop band region of the transfer function. To evaluate the 
efficacy of the optimization algorithm, a set of complex NTFs and STFs were 



3.6 The STF-NTF Co-Design Optimization Algorithm. . . 



63 



20 





10 







m 




D 




(!) 


-10 


T> 




1 




r 


-20 


CO 

2 




-30 


LL 




r- 


-40 




-50 




-60 




-70 



: } 

i i i 




t 

If: 
If 

Hi o 

| -20 
S -30 
1 -40 
f -50 
\ -60 
' -70 


^-*~ 




b 


1 




1 = 4 - 5 /> 

If? 


'it- 
'll 

If 


- 


5 -4 


4 


8 
7.5 



-64 -48 -32 -16 16 32 

Frequency (MHz) 



48 64 










-10 




-?0 


m 




n 








m 


-30 


o 




3 








c 


-40 


in 




CO 




:> 


-50 


ii 




r- 




w 


-60 




-70 




-80 



/■^^-■■■. 


■ ■'■' \\v. ■■ 


/# %\ 


:# \&\ ,-.. 


: '// \V'--' 


*' V* ..." . - 


■"'/ H 1/ ** '■ 


vi &«v\ ^ 


I \ _ 


\ 










■ i(i "» i 




1 . 1 . , , 


' ' 



-64 



-48 



-32 



-16 16 
Frequency (MHz) 



32 48 



L h 


= 7.5 


L H 


= 6.5 


L H 


= 5.5 


L H 


= 4.5 


L H 


= 3.5 



64 



Fig. 3.25 NTF and STF designed for different values of the |L|j norm: (a) NTF magnitude plot, 
(b) in-band zoom-in of the NTF, (c) STF magnitude plot 



Table 3.3 NTF-STF 

performance summary 





Stop 


-band attenuation 






|L|jnorm 


-ve frequency 


+ve 


frequency 


SNDR (dB) 


3.5 


60 




40 




55 


4.5 


50 




34 




71 


5.5 


50 




32 




74 


6.5 


46 




26.5 




80 


7.5 


40 




20 




85 



64 



3 A Complex AX Modulator with an Improved STF 







.'"" ""X 


if -20 


/ \ 


m 

1 -40 

§ 

S -60 




pn 


an 




■ 



-64-48 -32 -16 16 32 48 64 

Frequency (MHz) 

lm(z) 



-64 -48 -32 -16 16 32 48 64 
Frequency (MHz) 

lm(z) 



/ * t 

K 1 

V K / 



Re(z) ■ 




Re<zj 



-1 ■ 



u 
-20 




■ 


-40 




■ 


■a -80 


^"^^^H||k 


J^^^^Wrnr^'Pr' 


-100 


l 


f 


-120 


\ 


/ 


-140 


V 



-64 ^18 -32 -16 16 32 48 64 
Frequency (MHz) 

Fig. 3.26 Design of the STF-NTF using the optimization algorithm for |£|j= 6.5: (a) NTF 
magnitude gain, (b) STF magnitude gain, (c) NTF pole-zero plot, (d) STF pole-zero plot, (e) 
PSD plot of a complex AX modulator with STF and NTF transfer-functions as shown in (a) and (b) 



designed for the same specifications using the algorithm proposed in Sect. 3.6. 
Figures 3.27-3.29 show the NTFs and the STFs generated using these two different 
approaches. A comparison of the two sets of STFs generated reveals that for the 
same value of SQNR, the optimization algorithm generates STFs with flatter 
passband, and an out-of-band rejection response which is at least superior by 7 
dB (refer to Table 3.4). 



3.6 The STF-NTF Co-Design Optimization Algorithm 
Optimized NTF 



65 



a 



10 



pro 



-1 



h STF with 

zeros in stop-band 




-32 32 

Frequency (MHz) 



64 -64 

d 



32 32 

Frequency (MHz) 



■ X 

O 

; - °2 

A 

X 

X 



-1 


.•■<* 


■ "O- . . 


lo 




X 




X 






X 


1 


"■*>. 


&■ 




Re(z) 




Re(z) 



x O 

o2 

I .; .« 

X 



-1 



E 



1 ■ 



x 

'"■■■... ..•»■'■'' 




Re(z) 




Re(z) 



Fig. 3.27 Transfer functions for SQNR=101 dB. (a) NTF magnitude response, (b) pole-zero 
constellation for the non-optimized NTF, (c) pole-zero constellation for the optimized NTF, 
(d) STF magnitude response, (e) pole-zero constellation for the non-optimized STF, (f) pole- 
zero constellation for the optimized STF 



66 



3 A Complex AX Modulator with an Improved STF 



Optimized NTF 



Optimized : 5TF 




-32 32 
Frequency (MHz) 



-32 32 

Frequency (MHz) 



64 



b 
x ° 

.6 






-1 




Re(z) 




Re(z) 



-1 




.-•<*' 


■ -o-.. 








* 


"n" 






x 


E 












X 








X 


1 




'q. 


.o--' 



» 6 

o 

.4 



N 

e"o 




Re(z) 



..--■ :••©-. 
.. O 

x 
x 

X 





Re(z) 



Fig. 3.28 Transfer functions for SQNR=94 dB. (a) NTF magnitude response, (b) pole-zero 
constellation for the non-optimized NTF, (c) pole-zero constellation for the optimized NTF, 
(d) STF magnitude response, (e) pole-zero constellation for the non-optimized STF, (f) pole- 
zero constellation for the optimized STF 



3.6 The STF-NTF Co-Design Optimization Algorithm. 



67 



" 

-20 

-40 

cq-60 

-80 

-100 

-120 



Optimized NTF <j 



E 




CD 

-O-30 



H NTF with Butterworth -40 
Poles _ 50 

-60 



£TF with 
-1 :eros in stop-byBhi 
-20 



-64 -32 32 

Frequency (MHz) 




Re(z) 







v A 







£ 



-32 32 

Frequency (MHz) 




Re(z) 



:•-•©■. 
. o 

x "• . 

;' ■; X 



„ 6 

o 2 

• ft 

x 




Reft 



S 



1 



.'•©.. 

.O 

x 

X 

>-... ..»■•■' 




Re(z) 



Fig. 3.29 Transfer functions for SQNR=89 dB. (a) NTF magnitude response, (b) pole-zero 
constellation for the non-optimized NTF, (c) pole-zero constellation for the optimized NTF, 
(d) STF magnitude response, (e) pole-zero constellation for the non-optimized STF, (f) pole- 
zero constellation for the optimized STF 



Table 3.4 SQNR vs. 

stop-band attenuation 
performance summary 



Stop-band attenuation (dB) 




Optimized 


Non-optimized 


SQNR(dB) 


40 

32 
47 


20 

25 
37 


101 

94 
89 



68 



3 A Complex AX Modulator with an Improved STF 



3.7 Power and Performance Analysis of the Proposed 
Complex AS Modulator 

3.7.1 AX Modulator with Unity STF 

Figure 3.30a shows a AE modulator topology where the input signal is fed directly 
to the quantizer [15]. The loop-filter of the modulator has been represented by the 
transfer function H(z). As a result of the input to the quantizer the signal is directly 
fed to the quantizer without passing through the loop-filter of the modulator. As 
shown by (3.30) the magnitude of the STF of the modulator is unity across the 
frequency. The NTF of the modulator is same as that of any traditional AS 
modulator topology, Fig. 3.30b, with loop-filter H(z). 



STF{z) = 



1 



, m 

\+H{z) l + H(z) 



(3.30) 



= 1 



NTF(z) 



1 + H(z) 



(3.31) 




>— 0— [7/r 



DAC 



Y(z) 




7>r 



DAC 



Y(z) 



Fig. 3.30 (a) a AX modulator topology with a unity STF, (b) Traditional AX modulator topology 



3.7 Power and Performance Analysis of the Proposed Complex AX Modulator 



69 



B 2 + B 3 z"' 




v^-E 



•Y(z) 



Fig. 3.31 Structure for a fourth-order AX modulator with a unity STF 

An advantage of the AE modulator architecture shown in the Fig. 3.30a is that as 
the integrators are processing the quantization noise only the output swings of the 
opamps can be reduced with proper scaling of the coefficients. Depending on the 
choice of the coefficients, the linearity requirements of the opamps in the 
integrators maybe reduced and this results into an overall low-power consumption. 

It is possible to transform the proposed modulator (refer to Fig. 3.2) into an unity 
STF modulator, refer to Fig. 3.31, by modifying the coefficients as shown in (3.32): 



Ci=C 2 
Fj = 

F 2 = 
F 3 = -p 4 
F A =\ 



(3.32) 



The proposed modulator with unity STF shown in the Fig. 3.31 avoids signal 
summation at the input of the quantizer by moving the signal feedforward to the 
input of the last integrator. A side-effect of signal feed-in at the last integrator input 
is that the integrator is processing both the signal and the quantization noise. 
However, due to the noise-shaping of the preceding stages of the modulator, the 
nonlinearities of the opamp in the last stage of the modulator have little impact on 
the SNDR of the modulator. 

Despite the advantage of low-per consumption, feedforward AE modulators 
have some limitations that make them unsuitable for digitization of wireless 
signals. As discussed in Chap. 2, feedforward AE modulators require a front-end 
filter to compensate for the out-of-band peaking or slow roll off the STF [16]. 
The high-frequency interferers at the quantizer input can also react with the 



70 



3 A Complex AX Modulator with an Improved STF 



x10 4 



xlO' 3 



2.5 


, , , , 


14 


2 








12 
10 


1.5 


I — 






8 


1 












6 


0.5 




" ^ 








~n 


4 
2 



-0.1 -0.05 0.05 0.1 


First integrator output 




x10 3 


d 


18 




12 


, — , 


16 
14 










10 


12 










8 


10 
8 














6 


6 














4 


4 
2 


















2 





—_i i 










. 




, I r. 






x10 



■0.15 -0.1 -0.05 0.05 0.1 0.15 
Second integrator output 

,3 



-0.06 



Third integrator output 



-0.8-0.6-0.4-0.2 0.2 0.4 0.6 0.8 
Fourth integrator output 



Fig. 3.32 Histogram plots of the integrator outputs for the feedforward modulator with unity STF 



quantizer noise, which is large at these frequencies, and generate in-band intermod- 
ulation products, thus degrading the SNDR of the modulator [17]. 

In the following sub-sections the proposed AS modulator (referred to as FADC 
in further discussion), is compared to the feedforward AZ modulator with unity 
STF. For reasons discussed in Chap. 4, the FADC has been modified by moving one 
of the zeros from the signal band to the image frequency. First, the power consump- 
tion of the two ADCs are compared. The next sub-section compares the impact of 
DAC and other coefficient mismatches on the two architectures. Finally, the FADC 
is compared with a Discrete-Time Receiver [18, 19]. 



3.7.2 Power Comparison 



Figure 3.32 shows the signal swings at the integrator outputs for the feedforward 
modulator with unity STF, which are estimated through the use of a histogram plot 
from the behavioral model simulation in Matlab. Figure 3.33 shows the histogram 
plots of the integrator outputs for the proposed modulator with filtering STF. 



3.7 Power and Performance Analysis of the Proposed Complex AX Modulator 



71 




-0.8 -0.6-0.4 -0.2 0.2 0.4 0.6 
First integrator output 




0.8 -0.6-0.4 -0.2 0.2 0.4 0.6 0.1 
Second integrator output 

x10 3 



-0.8 -0.6-0.4 -0.2 0.2 0.4 0.6 0.8 
Third integrator output 



12 
10 
8 
6 
4 
2 




-0.8-0.6-0.4-0.2 0.2 0.4 0.6 0.8 
Fourth integrator output 



Fig. 3.33 Histogram plots of the integrator outputs for the modulator with filtering STF 



A comparison between Figs. 3.32 and 3.33 reveals that the integrator swings for 
the modulator with unity STF are smaller; for example, for the first stage, the output 
swings are about one-sixth of the proposed FADC and have higher distribution 
around theoutput common-mode. This difference in integrator swings means that, 
assuming that the same sampling capacitor sizes are constrained by noise 
considerations, dynamic range scaling [8] can be applied to make the integrating 
capacitors smaller in the S ADC with unity STF. This application results in 
reduction of the area of the chip. 

For the AEADC with unity STF, the presence of unfiltered interfering signals, 
and hence large voltage steps from sample to sample at DAC input (refer to 
Fig. 3.34) translates into stringent settling requirements for the reference buffers 
driving the feedback DAC capacitors. These requirements mean that some of the 
power advantages of the AE ADC with unity STF may not be realized in actual 
implementation. 



72 



3 A Complex AX Modulator with an Improved STF 






Fig. 3.34 DAC output swings for 300 samples for the triple tone test inputs: (a) feedforward AX 
modulator with unity STF, (b) proposed FADC 



f 2 =16MHz, -2.6dBFS 
(Interferer) 



-140 



-160 L- 1 



SNDR=29.7.6 dB 




Intermodulation tone 
generated due to DAC 
non-linearity 



-60 -40 -20 20 

Frequency (MHz) 



40 



60 



Fig. 3.35 PSD plot of the proposed complex AX modulator with a DAC mismatch = ±0.5% for a 
weak desired signal at —42.6 dBFS and a strong interferer at —2.6 dBFS 



3.7.3 Sensitivity to Intermodulation Due to DAC Non-linearity 



Figure 3.35 shows the output spectrum of the proposed AX modulator for a —42.6 
dBFS input and a —2.6 dBFS interfering signal in the adjacent channel for a ±0.5% 
mismatch in the DAC elements. 



3.7 Power and Performance Analysis of the Proposed Complex AX Modulator 73 

To investigate the robustness of the proposed complex 4th order filtering ADC to 
intermodulation due to DAC mismatches, the proposed filtering ADC (FADC) was 
compared with the following ADCs: 

• Complex 4th order Feedforward ADC with unity STF (referred to as FFADC in 
further discusssion), 

• Complex 4th order Feedforward ADC with unity STF and an image zero 
(referred to as FFADC_IZ in further discusssion). 

The ADCs were simulated in SIMULINK (Matlab) under the following conditions: 

1. The discrete integrators have been modeled using a(3y representation [11]. The 
integrator model accounts for the finite dc gain and the output stauration voltages 
of the opamps. 

2. The output saturation voltages of the integrators have been set at ± 1 . 

3. Dynamic range scaling was performed to make the swings at the integrator 
outputs for the FFADC, FFADCJZ, and FADC comparable. 

4. A mismatch of ±0.5% was assumed for the DAC elements. 

The input to the modulators is a triple-tone consisting of: (1) -46 dBFS input at 
8 MHz, (2) two interfereres of strength -6 dBFS each at the frequencies of 20 MHz 
and 36 MHz respectively. This test pattern corresponds to the selectivity tests 
recommended for DVB-T compliant receivers [13]. For this test input the FFADC 
and FFADCJZ show an SNDR of 43.5 dB and 32.3 dB respectively. The FADC 
achieves an SNDR of 32.5 dB for this test input. Figure 3.36 shows the swings at the 
integrator outputs for the FADC. As is evident from the figure, the integrators of the 
filtering ADC do not saturate for strong out-of-band interfering signals. 

To determine the SNDR degradation of the modulators due to DAC mismatches, 
Monte Carlo simulations were run with a differential error 0.5% added to the DAC 
elements. Results from a set of 100 Monte Carlo simulations with a DAC mismatch of 
0.5% show that the SNDRs of the FFADC and FFADCJZ drop significantly and show 
an SNDR (95 percentile) of 14.6 dB and 15.2 dB respectively. The FADC shows 
comparatively lower degradation in the SNDR and shows an SNDR (95 percentile) 
of 23.5 dB (refer to Table 3.5) (Figs. 3.37-3.40) 

Table 3.5 summarizes the comparison between the proposed modulator and the 
feedforward modulators with unity STF for the test input (^-6 dBFS desired signal 
at 8 MHz, two interfering signals of strength -6 dBFS each and at the frequencies of 
24 MHz and 36 MHz respectively). 

For a reduced DAC mismatch of ±0.1% the SNDR (95th percentile) of the 
FADC degrades to 31.63 dB. For the FFADC and FFADCJZ the SNDR degrades 
to 27.3 dB and 28.5 dB respectively. 



3.7.4 Comparison with a Discrete-Time Receiver [18, 19] 

A DTV receiver includes an IF filter and a demodulator for demodulation and 
error-correction of the IF signals. Currently, analog TV broadcasting and digital 
TV broadcasting are coexisting; hence, these interferences are mainly undesired 



74 



3 A Complex AX Modulator with an Improved STF 




-0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 
First integrator output 



0.8 -0.6-0.4 -0.2 2 0.4 0.6 0.8 
Second integrator output 




-0.6 -0.4 -0.2 0.2 0.4 0.6 
Third integrator output 



0.4-0.3-0.2-0.1 0.1 0.2 0.3 0.4 
Fourth integrator output 



Real Integrator output 

Imaginary Integrator output 

Fig. 3.36 Histogram plots of the integrator outputs for the modulator with filtering STF for the 
defined test input 



Table 3.5 Simulated 
modulator performance with 
±0.5% DAC mismatch 



FFADC 
FFADCJZ 

FADC 



SNDR (dB) 



SNDR (95 percentile) (dB) 



43.5 
32.3 
32.5 



14.6 
15.2 
23.5 



digital TV and/or analog TV channels. The power levels of those adjacent interfering 
channels can be higher than the desired channel, for example, 40 dB for ATSC signals 
[12]. In addition to the linearity requirement, it is necessary that the IF filters attenuate 
the interfering channels enough so that the ADC in the demodulator is not saturated. 
For example, for ATSC the IF filter has to provide over 50 dB attenuation for the 
adjacent channel. 

The possible ways to implement IF filtering in a DTV receiver are: 
Option 1- The IF filter is typically implemented using SAW filters and the 
receiver uses a bank of SAW filters to accomodate multi-standards. An advanatge 



3.7 Power and Performance Analysis of the Proposed Complex AX Modulator 



75 



25 



20 



15 



10 



SNDR=14.6dB 



12 14 16 18 20 22 24 26 

X = 95 th Percentile 



Fig. 3.37 Histogram plot of the SNDR for the feedforward modulator with unity STF for DAC 
mismatch = ±0.5% 



18 




1 


■ 


1 






1 


1 


1 


SNDR=15.2 dB 




16 
























14 




























12 




























10 






8 






6 






4 
2 



1 
























































4 


15 


16 


17 18 


19 


20 


21 


22 23 2 


4 
























X = 


95 ,h 


Percentile 



Fig. 3.38 Histogram plot of the SNDR for the feedforward modulator with unity STF with image 
zero for DAC mismatch = ±0.5% 



of the SAW filters is the attenuation of the adjacent channels which results into a 
reduce dynamic range requiremenst of the ADC. However, to achieve a higher level 
of integration and hence low cost it is necessary to integrate the IF filters on 
the chip. 



76 



3 A Complex AX Modulator with an Improved STF 



25 



20 



15 



10 







SNDR=23.5 dB 



i — r 



20 22 24 26 28 30 



32 



X = 95 Ul Percentile 
Fig. 3.39 Histogram plots of the SNDR for the filtering ADC for DAC mismatch = ±0.5% 



Option 2- Two possible filter technologies for integrating IF filters on chip are: 
the continuous-time filters and the switched-capacitor filter. Though, the continu- 
ous-time filters consume less power, but they need calibration to set the frequency 
characteristics accurately. Also, the requirement to support multi-standards adds to 
the tuning complexity for these filters. 

Unless, a narrow band IF filter is implemented for adjacent channel rejection, 
an ADC with greater than 11 bit resolution is required to digitize the adjacent 
interfering channel (refer to Table 3.6). 

Option 3- A possible solution to reduce the dynamic range requirement of the 
ADC is the inclusion of a switched-capacitor (SC) filter to implement some of the 
channel filtering and selectivity at the input of the modulator (refer to Fig. 3.41). 

Some of the advantages of implementing the filtering in the discrete-time domain, 
as compared with the continuous-time domain, are that SC filters do not require 
tuning to correct process and temperature-related variations, and also, because for SC 
filters frequency response depends only on the capacitor ratios and the clock fre- 
quency, these filters are easily amenable to multistandards. However, with SC filters, 
it is desirable to sample at a higher frequency to prevent the interfering signals 
aliasing into the signal-band. In addition, the quality of interfering signal suppression 
depends on the continuous-time anti-aliasing filter preceding the SC filter. The SC- 
filter can be followed by a decimation block for a sample-rate conversion to the 
analog-to-digital converter clock frequency. This sampling scheme can relax the 
requirements of the analog-to-digital converter, but at the cost of the order and 
complexity of the filters at the front-end. SC filters require opamps with greater 
bandwidth than the signal they are processing, and this requirement translates into 



3.7 Power and Performance Analysis of the Proposed Complex AX Modulator 



77 







-20 


f 1= 20 MHz, -6 dBFS 

(Interferer) \^ 


f 2 = 36 MHz, -6 dBFS 
(Interferer) 




f = 8 MHz, -46 dBFS 


jS 


-40 




- 


-60 


Offset ^^ 








-80 


^!™1L 




JF 


-100 


1 




t 


120 


f HV ^\ 


-140 
-160 


Intermodulation product 
at 4 MHz 

i i i i i i i 



-60 -40 -20 20 

Frequency (MHz) 



40 



60 





■ i i i i i i 
f,= 20 MHz, -6 dBFS f 2 = 36 MHz, -6 dBFS 


-20 


(Interferer) \^ I 


Interferer) 








^ 




f = 8 MHz, -46 dBFS 






-40 






- 


-60 


Offset \ 


^ 








3 -80 


ffrfffl Wk. 




jfl 









'IHk 




mm iiw r i'" t 


00 






in^ft.i 




J^BP |M ' 


Ph 




m 




JBP ' 


3-100 


. 


"M 


iw 


Jr 


& 


'M 


> 


r»' 


3 


'■ i>J IM 


o 


M W\ 


-120 


■ | N 




WKf Intermodulation product 




W ' at 4 MHz 


-140 
-160 


i i i i i i i 



-60 -40 -20 20 

Frequency (MHz) 



40 



60 



Fig. 3.40 PSD plots for the test input with a DAC mismatch of ±0.5% (a) proposed complex AX 
modulator, (b) feedforward complex AX modulator with unity STF 



78 



3 A Complex AX Modulator with an Improved STF 



Table 3.6 Required number of ADC bits 




Standard C/N (dB) Adjacent channel (dB) 


ADC (No. of bits) 


ATSC 15.5 40 
DVB-T 27.5 35 


10 
11 



Mixer VGA 




Relaxed Amplifier 
BP Filter 



^<gH^ 



, , i^i 1 ^ / Complex 

/|~\ _s_ jl II Bandpass 
i-aliasinn fir. Filter V Z ~ ADC 



Anti-aliasing SC Filter 
Filter 



Demodulator 



\ 



AS-ADC with unity-STF 



Mixer 



Fig. 3.41 A quadrature-IF system using a complex Low-IF AX modulator and a SC filter for 
channel filtering and selectivity 



Table 3.7 Flexible SC 
filter and ADC 
architecture 



SC filter 


Adjacent channel 


ADC 


order 


rejection (dB) 


(No. of bits) 


- 


- 


12 


3 


10 


10 


4 


20 


9 


8 


60 


6 



higher power dissipation as compared to the continuous-time filters. Reduction of the 
switch thermal noise problem in SC filters may require large capacitors, and this 
requirement further compounds the power dissipation and bandwidth problems. 

A trade-off exists between the attenuation characteristics of the IF filter and the 
dynamic range of the ADC. It is possible to find an optimum architecture by 
distributing the requirements between the filter and the ADC. Table 3.7 lists the 
possible SC filter order and the required ADC resolution to meet the requirements 
of the ATSC and DVB-T standards. 

The first row in the table corresponds to the case where an ADC without a front- 
end SC filter is used for the digitization of the signal and the interferers. Consider- 
ing the fact that high dynamic range AZ modulators can be designed easily without 
the need for highly linear components, the first option in the table is advantageous 
over the other possible architectures in the table. 



3.7 Power and Performance Analysis of the Proposed Complex AX Modulator 



79 



C 2 =216.2 mF 



Rr=1 



WW 



© 0^1.859 F^= 



L,=864.3 mH 



C 3 =1.859F^= <^Rl=1 



VJz) 




c„ = -c 



<l 



C, = Cz 



< 



>-&~BH>-&- 



C e = Cz 



< 



c, = -c 



c, = -c, 



<K 



D> 



® 



1/C 



1-z 



T -^Vo^z; 



C 3 = -C 2 '(l-z ) 
Fig. 3.42 (a) A third-order analog elliptic lowpass filter, and (b) SC lowpass filter 

3.7.5 Comparison with an SC + FeedForward ADC 
with Unity STF 



Alternatively, it is possible to use a feedforward ADC with unity STF and a relaxed 
SC filter at the front-end. The SC filter at the front-end attenuates the interferers and 
thus lowers the linearity requirements of the feedforward AZ modulator. This 
section compares the power and performance of the proposed AZ modulator with 
the architetcure comprising a feedforward ADC with unity STF and a relaxed SC 
filter at the front-end. 

Figure 3.42a shows a third-order elliptic lowpass filter designed with following 
characteristics: 

• stop-band attenuation = 40 dB, 

• cut-off frequency = 1 radian/s, 

• passband ripple = 0.2 dB. 



80 



3 A Complex AX Modulator with an Improved STF 



s 

s o 

s 








\ 


£-20 

& 

3-40 




/ 


V- : 


O-60 








\ 



-64 -48 -32-16 16 32 48 64 

Frequency (MHz) 




-64 -48 -32-16 16 32 48 64 
Frequency (MHz) 



Fig. 3.43 Frequency-response of the third-order switched capacitor filter: (a) the real filter, and 
(b) the complex filter response 



Following the procedure for the exact design of SC ladder filters described 
in [20] the analog filter was transformed into a switched-capacitor filter with 
following characteristics: 

• stop-band attenuation A= 40 dB, 

• sampling frequency / s = 128 MHz, 

• cut-off frequency f c = 5 MHz. 

Figure 3.42b shows the corresponding switched capacitor filter signal-flow 
graph. Compared to a third-order switched capacitor filter developed by cascading 
a first and second-order filter section, the filter shown has less sensitivity to 
element-value variations. Figure 3.43a shows the frequency response of the real 
switched capacitor filter. The notches at (fJ2) are due to the zeros introduced by the 
bilinear transformation. 

Figure 3.43b shows the response of the complex filter obtained by frequency 
shifting the variable z in the transfer function: 



,-JtOoT 



(3.33) 



where co is the frequency shift, and T (= l/f s ) is the sampling period. 

Table 3.8 list the capacitor sizes for the real switched capacitor filter. The 'scaled 
values' column lists the capacitor sizes scaled for maximum dynamic range for 
each amplifier. 

The frequency responses of the three amplifier outputs of the switched-capacitor 
filter for the scaled capacitor values are shown in Fig. 3.44. 

Interesting information can be obtained by plotting the transfer functions from 
the integrator outputs to the filter output. The transfer function from the last 
integrator output to V out , V ut,c> reveals the poor quality of the NTF for a AE 
modulator designed with this switched-capacitor filter as the loop-transfer function. 
The other two transfer-functions represent the contribution of noise-sources at each 
integrator stage input to the switched-capacitor output voltage V out ; for example, 



3.7 Power and Performance Analysis of the Proposed Complex AX Modulator 



81 



Table 3.8 Component values for the switched-capacitor filter 

Scaled values 
for dynamic range 



Component 



Unsealed values 



Scaled values 
for SNR (pF) 



c, 


0.1233 


0.2467 


0.1 


c 2 


0.2467 


0.4935 


0.2 


c 3 


-0.2338 


-0.2338 


-0.070 


c 4 


1 


3 


0.1 


c 5 


-1 


-0.3333 


0.1 


c 6 


0.2467 


-0.3333 


0.1 


c 7 


-0.2467 


-0.2467 


-0.1 


C 8 


1 


3 


0.1 


c 9 


-1 


-0.3333 


-0.135 


Cio 


-0.2338 


-0.2338 


-0.094 


c A 


1.9695 


1.9695 


0.7965 


C B 


14.2039 


14.2039 


0.473 


C c 


1,9695 


14.2039 


4.2 



20 



-20 



-40 



-60 



-80 



1 


^/ / ' \ \^ 


^^^ / 1 \ X B """"-\ 


-/ ^s^"^^ \ 


\ r c ^\ ^\ 


1 







-64 -48 -32 -16 16 32 48 64 

Fig. 3.44 Amplifier output voltages response of the third-order switched capacitor filter 

K>ut,A' K>m,B represent the noise contributions of the sampling switches connected 
to the capacitors C4 and to C5 respectively to the output of the filter. These transfer- 
functions reveal the absence of noise-shaping found in a AE modulator; this 
absence of noise-shaping is related in a way to the trade-off involved between the 
quality of the STF and the NTF in a AZ modulator. The absence of noise-shaping 
(Fig. 3.45) means that each stage of the filter has to be designed for minimum 
switch and opamp noise and other circuit nonlinearities. 

Table 3.8, which does not take the amplifier noise into account, lists the capacitor 
values required to achieve a signal-to-thermal-noise ratio of 80 dB at an oversamp ling- 
ratio of 16 at the output of the switched-capacitor filter [21] (refer to Chap. 4). 
A comparison of these capacitor values and the values derived for the proposed AE 
modulator shows that each of the filter stages can be expected to have power 
consumption similar to the first-stage of the proposed AZ modulator. 



82 



3 A Complex AX Modulator with an Improved STF 




-64 -48 -32 -16 16 32 48 64 

Frequency (MHz) 

Fig. 3.45 Frequency response of the noise transfer functions of the third-order switched capacitor 
filter 



-jnw IF T 




Complex Low 
Pass Filter 



2 



-f IF o 



2 



2 



Y//A Quantization noise 
|;:;:8:;:| Desired signal 
i 1 Image frequencies 

Fig. 3.46 (a) A complex mixer for decimation of output bit-stream of complex AZ modulator, 
(b) Frequency domain illustration of complex decimation 



It is possible to convert the real switched capacitor filter into a complex switched 
capacitor filter by replacing each element of the real filter with a corresponding 
frequency-shifted complex element. A complex filter derived from a dynamic 
range scaled lowpass filter preserves the optimum dynamic range of the low-pass 
filter [22]. 



3.9 Advantages of the Proposed AE Modulator Architecture 83 

For a real SC filter, component variations change the location of the poles and 
zero, whereas, for a complex filter mismatches can completely alter the complex 
filter transfer function and significantly degrade the SNR of the filter [14]. Study of 
the sensitivity of complex filters to component mismatches has been done in [23] 
and [24]. It has been observed that the component mismatches of the final stage of 
the complex SC filter have a greater effect on the stop-band response, and the final 
stage of the complex SC filter should be designed with large and carefully matched 
devices. This is unlike a AE modulator, in which the first integrator stage amplifier 
is typically dominant in the modulator noise, linearity, and power requirements. 

The conclusion is that, due to the reduced power and linearity requirements of the 
amplifier, feedforward AE modulator with unity STF is an attractive option, however 
this receiver architecture results into an increased complexity of the filter at the front- 
end. The noise and matching requirements of these front-end filters outweigh the 
advantages gained from the feeforward AE modulator architecture. 



3.8 Decimation for Complex AS Modulators 

The output of the complex AE modulator is at the intermediate frequency, fo, 
and a complex decimator is required to reduce the bit rate of the modulator. 
The complex bitstream is modulated to baseband by mixing with e~^ m>irT 
(T = l/F s , where F s is the sampling frequency) and then filtered by a complex low- 
pass filter (Fig. 3.46). Modulating complex bit-stream to DC requires multiplying of 
two complex numbers, however, a suitable choice for fip frequency simplifies 
the architecture for the mixer and the complex filter. For example, for co IF T = 
n/2, e~' nwwT can be decomposed into a sum of 0, ± 1 streams multiplied by constants. 

«-*(*/*> = (1, 0, -1,0, ...)+./(o, -1,0, i,...) 

For this choice of the IF frequency, demodulation can be simplified as shown 
Fig. 3.47: 



3.9 Advantages of the Proposed AX Modulator Architecture 

The proposed AE modulator offers several advantages over the traditional AE 
modulator architectures: 

• Unlike the feedforward architecture, the proposed AE modulator avoids 
having a weighted summation before the quantizer, and, hence, issues like signal 
attenuation and reference scaling for the purpose of passive summation or power 
dissipation in the case of active summation have been eliminated. In the 
proposed AE modulator, the summation of the signals has been distributed at 
various integrator inputs. 



84 



3 A Complex AX Modulator with an Improved STF 



{1,0,-1,0,...} 



{I(0),-Q(1),-I(2),...} 




{Q(0),l(1),-Q(2),...} 



{1,0,-1,0,...} 

Fig. 3.47 Complex demodulation of the complex AZ modulator output 




l(n) 



Quadrature 

Analog 

Input 



Q(n) 



Complex Quadrature Digital Filter and Receiver 
Mixer Decimator Demodulator 

Output 



Fig. 3.48 Architecture for a DTV receiver demodulator 



Due to the low-pass nature of the STF, the modulator avoids stability issues 
related to the peaking of the STF at higher signal frequencies. Compared to the 
traditional feedforward AS modulator, the proposed modulator shows signifi- 
cantly reduced sensitivity to process variations and coefficient mismatches. This 
reduction occurs because of the filtering nature of the STF. 
With a filtering STF and stop band attenuation greater than 30 dB, the AS 
modulator reduces intermodulation of the desired signal and the interfering 
signals at the input of the quantizer, and also avoids feedback of the high- 
frequency interfering signals at the input of the modulator. 
Figure 3.48 shows digital signal processing in a typical AS modulator-based 
DTV receiver. The task of the complex demodulator includes demodulation 
and recovery of the transmitted bit sequence. Prior to lowering the bit-rate, 



References 85 

the decimation filters at the output of the complex bandpass AX ADC attenuate 
the high-frequency quantization noise and out-of-band interferers components 
that may alias into the signal band during decimation. The order of the 
decimating filters is decided by the required attenuation of the quantization 
noise and the interfering signals at the input of the decimating filters. The 
interfering signals are attenuated by the antialias filter at the input of the ADC. 
The filtering STF of the ADC further relaxes the decimation filter design by 
attenuating these interferers. 
• The role of the digital quadrature mixer, the complex NCO in Fig. 3.48, consists 
of correcting any frequency offset errors that may occur between the carrier 
frequency and the symbol rate and converting the complex signal from low-lF to 
zero-IF. The baseband signal at the output of the mixer is subsequently low-pass 
filtered in order to attenuate image frequencies and other sum frequencies 
generated by the mixing operation. The output of the low-pass filters goes to a 
data recovery block where the transmitted data bit sequence is recovered. The 
low-pass filters act as image rejection filters, and the order of these low-pass 
filters depends on the attenuation desired for the image frequencies. An asym- 
metric filtering ADC with significant attenuation for image frequencies reduces 
the complexity of these low-pass filters. 



References 



1. K. Martin,"Approximation of Complex IIR Bandpass Filters Without Arithmetic Symmetry," 
IEEE Trans. Circuits and Systems-I, vol. 52, No. 4, pp. 794-803, April 2005. 

2. S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds., Delta-Sigma Data Converters: Theory, 
Design, and Simulation. New York: IEEE Press, 1997. ISBN 0780310454. 

3. Richard W. Daniels, Approximation Methods for Electronic Filter Design: With Applications 
to Passive, Active, and Digital Networks, McGraw-Hill, 1974. 

4. Peter O. Brackett, A.S.Sedra, Filter Theory and Design: Active and Passive, Matrix Series in 
Circuits and Systems. 

5. Bupesh Pandita, K. W. Martin, "Designing Complex Delta Sigma Modulators with Signal- 
Transfer Functions having Good Stop-Band Attenuation," pp. 3626-3629, ISCAS 2007. 

6. Richard Schreier and Gabor C. Temes, Understanding Delta-Sigma Data Converters. 
Wiley-IEEE Press, 2004. ISBN 0-471-46585-2. 

7. KiYoung Nam, Sang-Min Lee, D. K. Su, and B. A. Wooley, "A low-voltage lowpower sigma- 
delta modulator for broadband analog-to-digital conversion," IEEE J. Solid-State Circuits, vol. 
40, no. 9, pp. 1855-1864, Sep. 2005. 

8. Richard Schreier, "An Empirical Study of High-Order Single-Bit Delta-Sigma Modulators," 
IEEE Transactions on circuits and systems-II: analog and digital signal processing, vol. 40, 
no. 8, August 1993. 

9. John. G. Kenney, and L. Richard Carley, "Design of multibit noiseshapingdata converters," 
Analog Integrated Circuits and Signal Processing, vol. 3, no. 3, May 1993. 

10. The Math Works, Inc., Matlab, Version 6.4, Natick, Massachusets: The Math Works, Inc., 
R14, 2005. 

11. ArSC Recommended Practice: Receiver Performance Guidelines, ATSC A/74, June 2004, 
pp 13-14. 



86 3 A Complex AX Modulator with an Improved STF 

12. Mobile and Portable DVB-TIH Radio Access Interface Specification, EICTA MBRAI-02, 
Jan 2004. 

13. S.A. Jantzi, K. W. Martin, and A. S. Sedra, "The effects of mismatch in complex bandpass 
AZ modulators," IEEE International Symposium on Circuits and Systems, vol. 1, 12-15, 
May 1996, pp. 227-23. 

14. R. B. Staszewski, K. Muhammad, D. Leipold, Chih-Ming Hung, Yo-Chuol Ho, J. L. Wallberg, 
C. Fernando, K. Maggio, R. Staszewski, T. Jung, Jinseok Koh, S. John, Irene Yuanying Deng, 
V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de-Obaldia, 
P. T. Balsara, "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth 
radio in 130-nm CMOS," IEEE Journal of Solid-State Circuits, Volume 39, Issue 12, 
pp 2278-2291, December 2004. 

15. Zhiyu Ru, E. A. M. Klumperink, B. Nauta, "On the Suitability of Discrete-Time Receivers for 
Software-Defined Radio," IEEE International Symposium on Circuits and Systems, 2007, 
27-30 pp. 2522-2525, May 2007. 

16. W.-H. Ki, G. C. Temes, "Low-phase-error offset-compensated switched-capacitor integrator," 
Electronics Letters, Volume 26, Issue 13, 21 June 1990, pp.957-959. 

17. Anas A. Hamoui, Delta-Sigma Data Converters for Broadband Digital Communications, 
Ph.D. Thesis, University of Toronto, 2004. 

18. J. Silva, U. Moon, J. Steensgaard, G. C. Temes, "Wideband low-distortion deltasigma ADC 
topology," Electronics Letters Volume 37, Issue 12, 7 June 2001 pp 737-738. 

19. E. H. Dagher, P. A. Stubberud, W. K. Masenten, M. Conta, T. V. Dinh, "A 2-GHz analog-to- 
digital delta-sigma modulator for CDMA receivers with 79-dB signal-tonoise ratio in 1.23- 
MHz bandwidth," IEEE J. Solid-State Circuits, vol. 39, pp. 1819-1828, November 2004. 

20. K. Philips, P. A. C. M. Nuijten, R. L. J. Roovers, A. H. M. van Roermund, F. M. Chavero, M. T. 
Pallares, A. Torralba, "A continuous-time ZA ADC with increased immunity to interferers," 
IEEE J. Solid-State Circuits, vol. 39, issue. 12, pp. 2170-2178, December 2004. 

21. Roubik Gregorian, Gabor C Temes, Analog Mos Integrated Circuits for Signal Processing, 
Wiley Series On Filters, Wiley-Interscience, 1986. 

22. R. Schreier, J. Silva, J. Steensgaard and G.C. Temes, "Design-oriented estimation of thermal 
noise in switched-capacitor circuits," IEEE Transactions on Circuits and Systems, vol. 15, 
no. 11, pp. 2358-2368, November 2005. 

23. Q. L. Liu, W. M. Snelgrove, and A.S. Sedra, "Switched-capacitor implementation of complex 
filters," Proceedings of the 1986 IEEE ISCAS, vol. 3, pp. 1 121-1 124, May 1986. 

24. A. S. Sedra, W. M. Snelgrove, and R. Allen, "Complex analog bandpass filters designed by 
linearly shifting real low-pass prototypes," Proceedings of the 1985 IEEE ISCAS, vol. 3, 
pp. 1223-1226, June 1985. 

25. R. H. Allen, "Complex analog filters obtained from shifted lowpass prototypes", M.A.Sc. 
thesis, University of Toronto, 1985. 



Chapter 4 

Architectural-Level Design of the Experimental 

AX Modulator 



This chapter provides background information for "image transfer function" related 
to mismatches in complex filters. The impact of mismatches on the modulator 
proposed in Chap. 3 is examined, and on the basis of the results, an improved 
complex AE modulator is proposed. 

The chapter further discusses the architectural-level design of the proposed 
complex AE modulator. The SC circuit configuration for the realization of a 
nondelaying complex integrator, clocking, the number of quantization bits, and 
the dynamic-range scaling are discussed. The SC implementation nonidealities like 
noise, finite resistance of the switches, finite dc gains of the opamp, etc., are 
considered in order to arrive at the SC circuit specifications for a complex AE 
modulator with a SNR of 75 dB over a signal bandwidth of 8 MHz, at a sampling 
frequency of 128 MHz. The chapter also presents behavioral simulation results for 
the experimental AE modulator. 



4.1 Background 

A complex AE modulator is realized with complex poles. Figure 4.1 describes the 
realization of a complex pole with two real integrators. As seen in the figure, the 
complex pole realization can be considered a two-input two-output real system, 
with the additional condition that the inputs and outputs are quadrature signals [1]. 

A mismatched complex filter can be represented with two complex filters. 
In Fig. 4.2a, the first ideal complex filter operates on the input signal, and the 
second, the image transfer function, operates on the input signal after conjugating 
it. The conjugation of the image frequency means the transfer of energy at the 
image frequency into the signalband and vice versa. This transfer of the image 
frequency into the signal-band, which defines image rejection of the complex filter, 
can degrade the quality of the signal at the output of the complex filter. 

Figure 4.2b shows the ideal signal response and the image response of a complex 
filter with a pole of magnitude 0.9 at an angular frequency of n/2. The image 

B. Pandita, Oversampling AID Converters with Improved Signal Transfer Functions, 87 

Analog Circuits and Signal Processing, DOl 10.1007/978-l-4614-0275-6_4, 
© Springer Science+Business Media, LLC 2011 



88 



4 Architectural-Level Design of the Experimental AX Modulator 




t>Y(z) 



(Pr-1) 







1 










z-1 


Pi 
















Pi 






1 








z-1 







Yr(z) 



Y|(z) 



X(z) = X R (z) + J X R (z) 



(P r -1) 



H(z) = ^= -L 
v ; X(z) z-p 



/(z) = Y R (z) + JY R (z) 
p = Pr + jPi 



Fig. 4.1 Realizing a complex pole at p =p r +jpi using (a) a complex signal flow graph and 
(b) a two-input two-output real linear signal flow graph 

response was obtained by introducing a mismatch of ± 0.1% in the complex filter 
coefficients, refer to Fig. 4.3. As can be seen from the image response plot, an input 
at the image frequency m = —n/2 has aliased into the output at n/2. In this 
example given, the signal response and the image response indicate that with a 
mismatch of ±0.1% the complex filter has an image rejection (IMR) of 63.07 dB 
at the signal frequency of n/2. The example underlines the significance of compo- 
nent matching in a complex system. 



4.2 Mismatches in a Complex AZ Modulator 



89 



X(z) 




H(z) 



Image transfer function 



X(z) z -p 



30 

20 r 

10 

-10 
-20 
-30 
-40 
-50 1- 
-60 
-70 



p = 0.9 e 



j(n/ 2) 




Image Frequency aliased 
into signal band 




' nom\Z/ 

Signal Response 



Ydiff(z) 
Image Response 



Radian Frequency 



Fig. 4.2 (a) Signal flow diagram of a complex filter with mismatch, (b) Magnitude of the signal 
and image response for a single-pole complex filter with mismatch 



4.2 Mismatches in a Complex AS Modulator 



The coefficients in the system model of a AZ modulator are mapped to capacitor 
ratios in the switched-capacitor (SC) circuit implementation. Due to process 
variations, the feed-in capacitors and the integrating capacitors may show variation 
from their desired values, and these variations manifest as errors in the realized 
coefficient values. In a AX modulator, these ratio-errors can cause the gains of 
the integrator stages to differ from their nominal values, and this difference may 
result in modification of the NTF zeros. In the worst case, this modification 



90 



4 Architectural-Level Design of the Experimental AX Modulator 



-1 (1 +A) 



Xr(z) 



X,(z) 




Yr(z) 



Y,(z) 



-1(1 -A) 



H(z) 



Y(z) _ 1 



X(z) z-p 
p = 0.9 JWL J0.9 

A = 0.1% 

Fig. 4.3 Realizing a complex pole at p = p, + jpi using two-input two-output non-ideal linear 
signal flow graph 



may cause a AZ modulator to become unstable. Amplifiers implemented with 
opamps also vary in dc gain and settling characteristics from stage to stage or 
channel to channel. 

In a complex AE modulator the circuit mismatches cause the real and the 
quadrature paths to differ, and this difference impacts the image rejection and the 
SNDR of the modulator. As discussed in Chap. 2, in addition to the signal transfer 
function (STF) and noise-transfer function (NTF), two additional transfer functions, 
refer to Fig. 4.4, are needed to describe the behavior of a complex AZ modulator 
with mismatches in its coefficients [2]: (1) Image noise transfer function (INTF) 
that describes the transfer from the quantization noise in the image-band to in-band 
at the output of the modulator, and (2) Image signal transfer function (ISTF) that 
describes the transfer from the image-band signals at the input of the modulator to 
the in-band signals at the output of the modulator. 

The STF determines the gain from the signal input to the output of the modulator 



STF 



G'{e 



Y(e jco ) 
X (ei<°) 



(4.1) 



4.2 Mismatches in a Complex AZ Modulator 



91 



Fig. 4.4 Linear model of a 
complex AX modulator 
showing the four transfer 
functions that decide the 
output of the modulator in the 
presence of mismatches 



N(z) i [) //'(z) 




>^) 



The NTF determines the gain from the quantization-noise to the output of the 
modulator: 



NTF 



' L,J'°\ - 



trie 



Y(e jco ) 

N(eJ° J ) 



(4.2) 



ISTF determines the gain from the image-signal to the output of the non-ideal 
modulator: 



ISTF 



AG m (e*°) = 



Y(e ja ) 

X(e-i a ) 



(4.3) 



INTF determines the gain from the image-quantization noise to the output of the 
non-ideal modulator: 



INTF 



AH diff (e 



.!'•') 



Y(e Jm ) 
N(e-J m ) 



(4.4) 



The impact of mismatches on the proposed complex AZ modulator was simu- 
lated using the developed behavioral Simulink [3] model (refer to Appendix A). 

Figure 4.5 shows the NTF and the INTF created by a mismatch of 0.5% in the 
modulator coefficients. As can be seen from the in-band zoom in Fig. 4.5b, the in- 
band noise has been shaped by deep in-band notches of the NTF. However, the 
quantization noise in the image-band is aliased by the INTF, whose gain in this 
particular case is comparable to that of the NTF. High-gain INTF implies that a very 
large amount of energy from out-of-band quantization noise is transferred into the 
in-band of the AL modulator. 



92 



4 Architectural-Level Design of the Experimental AX Modulator 



a 20 



-20 

3 -40 
u 
| -60 

§> -80 



-100 
-120 



^"l/^ 



NTF 
INTF 



-64 -48 -32 -16 16 32 

Frequency (MHz) 



48 



64 




4 6 

Frequency (MHz) 

Fig. 4.5 (a) Transfer Functions -INTF and NTF, (b) Zoom-of the INTF and the NTF 



Figure 4.6 shows the output spectrum for the same nonideal modulator for an 
input: o.7e /27r ( 4xlo<,/128xl ° 6 ). Fig. 4.6c shows the in-band quantization noise 
(in black) and the aliased image-band quantization (in gray). The aliased image- 
band quantization is clearly larger than the in-band quantization noise, and this 
aliased noise may actually limit the SNR of the modulator. Figure 4.7 shows the 
STF and the ISTF created by a mismatch of 0.5% in the modulator coefficients. 
ISTF plays a critical role in transferring the image-band input signals into in-band 
signals at the output of the modulator. An image tone signal at the input of 
the modulator is shaped by ISTF. For the given modulator with 0.5% mismatch, 
in-band zoom in Fig. 4.7b indicates that the ISTF is about 50 dB below the 
ideal STF. This means that, assuming a linear-model, the image rejection for 
the modulator is 50 dB, in-band. 

Figure 4.8 shows the response of the modulator for inputs in the signal-band 
and image-band. Fig. 4.8a shows the response of the modulator, without 
any mismatches, to a —20 dB two-tone signal at the image-frequency of — 5 MHz 
and signal-band frequency of 6 MHz. In absence of any mismatches, the two 
tones can be seen at the output of the modulator, and there is no aliasing of the 



4.2 Mismatches in a Complex AZ Modulator 



93 




01 


-zu 


■a 








E 


-4U 


1 


-60 


■ i 




a. 


-80 






-100 


- 




o 


-120 




-140 




-160 



-16 16 
Frequency (MHz) 



- 


- 


- 


Image quantization noise 
aliased into signal-band 


- 


i I ! 


f&tSff 



-6-4-202468 
Frequency (MHz) 

Fig. 4.6 Output spectrum: (a) Ideal spectrum (b) with 0.5% mismatch, (c) Zoom-in image 
quantization aliasing into signal-band 



94 



4 Architectural-Level Design of the Experimental AX Modulator 



CD 

-a 

-^ 

'c 
Bb 

03 



10 






u 










20 






ISTF \ 


STF (ideal) 
STF(non-ideal) 


40 


■Y 


yV i 




1 V 


60 


- 


sn 


■ i 


i I . .4 » 


. ! 


1 



-64 -48 -32 -16 16 

Frequency (MHz) 



32 



48 64 



10 







m 
3 

-1— > 

'S 

60 



-10 - 
-20 . 

-30 - 



STF (ideal) 

STF(non-ideal) 



ISTF 



-40 - 

-50 - 

" 60 2 4 6 

Frequency (MHz) 

Fig. 4.7 (a) Transfer Functions - ISTF and STF, (b) Zoom-in of the ISTF and the STF 



signal-band frequency to the image-band or vice versa. However, with ±0.5% 
mismatches added, the -20 dB image-frequency is shaped by the ISTF, and an 
aliased signal at -70 dB, 5 MHz, appears in the output spectrum, Figure 4.8b. 

To determine the SNDR degradation of the modulator due to mismatches, 
Monte Carlo simulations were run with amplifier nonidealities, and a differential 
error of ± 0.5% added to all gain and complex pole parameters. Figure 4.9a,b 
show in-band transfer functions for 200 Monte Carlo simulations. Figure 4.9a 
shows NTF and INTF curves for the modulator. Compared to the NTF curves, 
the INTF shows wider variation and can be responsible for transferring out- 
of-band noise to the in-band region. Figure 4.9b shows the STF and ISTF 
curves for the modulator. The in-band variation of the STF is less than 1 dB. 



4.2 Mismatches in a Complex AZ Modulator 



95 



a 







-20 


r 




T) 


-41) 


^~- 




i 


-60 






-J 


-80 


ft 




Wl 




5 


■100 


& 








3 


-1V0 








- 1 1 r - 



-140 



-160 



§ 


-20 


-o 








£ 


-40 


u 


-60 


u 




ft 


-80 


4— ' 

a 
ft 




-100 



-160 



Image Input at -5 MHz (f 2 ) 




Signal Input at 6 MHz (f-,) 



-48 -32 -16 16 32 48 64 

Frequency (MHz) 




-2 2 

Frequency (MHz) 



Fig. 4.8 Output spectrum with a signal-band tone and an image-band tone: (a) Ideal spectrum, 
(b) with 0.5% mismatch, (c) Zoom-in of image-tone aliasing into the signal-band 



96 



4 Architectural-Level Design of the Experimental AX Modulator 



a 

-40 

| -60 

•8 -80 

|-100 

-120 

-140 





1 


| NTF variation ts^^J 


A 


nsnaraffirasiS 


IF- 





2 4 6 

Frequency (MHz) 




2 4 6 

Frequency (MHz) 



40 












30 














20 


















10 























I 




■" 














I 


( 


57 


69 71 73 75 77 79 81 83 85 




SNR (dB) 


lU 












60 






50 












40 












30 




















20 




10 

















I 


X 











73 75 77 



79 81 
SNR (dB) 



83 85 



35 
30 
25 
20 
15 
10 
5 




& 



19 23 27 31 35 39 43 47 51 55 
IMR (dB) 



30 
25 
20 

15 

10 

5 





r 


* 
















Tm n rn 



27 31 35 39 43 47 51 55 59 63 

IMR (dB) 

X represents 95 percentile 



Fig. 4.9 Transfer functions for the original modulator: (a) NTF and INTF variation for ± 0.5% 
random mismatch, (b) STF and ISTF variation for ± 0.5% random mismatch. Histograms for 
(c) SNR and (d) IMR for the modulator with ± 0.5% random mismatch. Histograms for (e) SNR 
and (f) IMR for the modulator with ± 0.25% random mismatch 



The ISTF starts at approximately 50 dB below the STF; however, closer to the 
signal band-edge the distance progressively decreases to 40 dB. This implies 
greater than 50 dB image-rejection, which however deteriorates to 40 dB for 
signals closer to the band-edge. This conclusion about image-rejection is based on 



4.2 Mismatches in a Complex AZ Modulator 97 

a linear model for the modulator; however, actual image rejection will need to be 
determined through full simulations. Monte Carlo simulations of the modulator 
with ± 0.5% coefficient mismatch and finite dc-gain nonidealities of the amplifier 
modeled were performed to generate the SNR and IMR histograms shown in 
Fig. 4.9c, d. An another set of simulations with the same amplifier nonidealities, 
however the peak mismatch decreased to ± 0.25% were performed to generate 
the histograms shown in Fig. 4.9e, f. For ±0.25% random mismatches, 95% of the 
modulators achieve SNR greater than 71 dB and IMR greater than 21 dB. For 
±0.5% coefficient- mismatches, the minimum SNR drops to 67 dB, which is a loss 
of 14 dB from the ideal case. 



4.2.1 An Improved Complex AX Modulator 

A technique to reduce SNR degradation due to image quantization noise aliasing 
into the signal-band is to move one of the NTF zeros to the image frequencies [2]. 
The advantage of this method is that the image zero suppresses the image band 
quantization noise before it aliases into the signal-band. However, sacrificing one of 
the NTF zeros means reduction in the suppression of the in-band quantization noise; 
effectively, thus reducing the order of the modulator. 

In the modified AE modulator, one of the NTF zeros has been placed in the 
center of the image-band (^1 MHz). For a fourth-order modulator, there is appar- 
ently a flexibility in choosing the stage in which to realize the image zero, but, it 
turns out that technique offers significant improvement over the original modulator 
only when the image-zero is realized in the third or the fourth stage. The signifi- 
cance of stage-ordering for complex filters can be understood from the fact that, 
under mismatches, complex filters are not commutable; for example, a complex 
filter, AB, made of stage A followed by stage B, is not same as a complex filter, BA, 
made of stage B followed by stage A. The order in which the in-band zeros are 
realized has a negligible impact on the INTF variation. 

Figure 4.10a shows the pole-zero plot of the modified AE modulator. An NTF 
zero has been moved to the image-frequency of -4 MHz. Figure 4. 10b, c show the 
NTF magnitude response and the zoom-in view of the image-band and the signal- 
band. Figure 4.1 la shows the 64k-bin output spectrum of the modified complex 
AS modulator. The output PSD plot shows three notches in the signal-band and a 
single notch in the image-band. Figure 4.11c shows the zoom-in of the signal- 
band for a random ±0.5% coefficient mismatch. Compared with Fig. 4.8c, Fig. 
4.11c shows that negligible image-band quantization noise has aliased into the 
signal band. 

Compared to the ideal AE modulator with all the NTF zeros distributed over 
the signal- band (0-8 MHz), the modified AS modulator shows lower SNR. This 
SNR degradation is due to the NTF which is effectively 3rd order now. However, 



4 Architectural-Level Design of the Experimental AX Modulator 



9 



3 

5 
to 

s 

P-, 

H 



20 

-20 
-40 
-60 
-80 



-100 




k 










| -20 I 

a- 40 

|-60 



-80 
-100 



1 Re(z) 



NTF zero in the 
image-band 



"l 


r^ 


ryi 



-64 -48 -32-16 16 32 48 64 
Frequency (MHz) 



-4 4 

Frequency (MHz) 



Fig. 4.10 The modified AX Modulator: (a) NTF pole-zero plot, (b) NTF magnitude response, 
(c) Zoom-in of the signal-band and image-band 



the modified AE modulator shows an increased robustness and relatively small 
SNR degradation due to coefficient mismatch. Compared to the worst SNR degra- 
dation of 11.74 dB and 10.47 dB for ±0.5% and ±0.25% coefficient mismatches 
respectively, for the original modulator, the modified modulator shows an SNR 
degradation of 2.8 dB and 1.9 dB for the same coefficient mismatches. (Refer to 
Fig. 4.12.) 

Introduction of a zero in the image-band has relatively little impact on the shape 
of the ISTF, and the expectation is that the image-rejection of the modulator should 
remain unaffected by this method. Mismatch simulations (Fig. 4.12b) reveals that 
the ISTF variation of the modified modulator is close to the original modulator. 

Table 4. 1 summarizes the comparison between the original modulator and the 
improved modulator. 



4.2 Mismatches in a Complex AZ Modulator 



99 




b 







-20 


j£ 


-40 






E 


-60 


1 


-80 


•> 




a, 




:S: 


-100 






= 




a. 


-120 


O 


-140 



-160 



-64 





-20 


ffl 




*a 


-40 


p 




R 


-60 






-i 






-80 


w 






-100 


ex 








- 
O 


-120 



-140 
-160 



-8 



-48 



-32 -16 16 32 48 64 

Frequency (MHz) 



■ i i ■ i i ■ i ■ ■ ■ ■ i i i 



Image quantization noise 
aliased into signal-band\ 




-2 2 
Frequency (MHz) 



-32 -16 16 32 48 64 
Frequency (MHz) 



Fig. 4.11 Output spectrum of the modified modulator: (a) Ideal spectrum, (b) with 0.5% 
mismatch, (c) Zoom-in of image quantization aliasing into signal-band 



100 



4 Architectural-Level Design of the Experimental AX Modulator 




2 4 6 

Frequency (MHz) 



10 


-20 



£ -40 

BO 



-60 
-80 



STF variation 


■ 


■ 




HlSTF variation £ 




^^<f>5^I> ; N^O^ 





2 4 6 8 



Frequency (MHz) 




76 77 

SNR (dB) 



30 
25 
20 

15 

10 

5 



22 26 



X 



30 34 38 
IMR (dB) 



42 46 50 




77 
SNR (dB) 



35 
30 
25 
20 
15 
10 
5 




fit 



25 29 33 37 41 45 49 53 57 
IMR (dB) 



Fig. 4.12 Transfer functions for the modified modulator: (a) NTF and INTF variation for ± 0.5% 
random mismatch, (b) STF and ISTF variation for ± 0.5% random mismatch. Histograms for 
(c) SNR and (d) IMR for the modulator with ± 0.5% random mismatch. Histograms for (e) SNR 
and (f) IMR for the modulator with ± 0.25% random mismatch 



Table 4.1 Simulated 
modulator performance 
with ±0.5% mismatch 



SNR (ideal) 

SNR (95th-percentile) 

IMR (95th-percentile) 



Original 


Modified 


modulator 


modulator 


81 dB 


77 dB 


71 dB 


76 dB 


23 dB 


25 dB 



4.3 The Switched-Capacitor Architecture 101 

4.3 The Switched-Capacitor Architecture 
4.3.1 Complex Integrators 

A complex integrator is created by two cross-coupled real integrators, as shown in 
Fig. 4.13. The nondelaying complex integrator of the proposed AZ modulator 
has been realized by two non-delaying SC integrators. As the SC implementation 
is fully-differential, the negative valued cross-coupling coefficient is realized 
by reversing the connection to the differential amplifier outputs. The ratio of 
the feedback capacitor, Cj, to the integration capacitor, C„ sets the real part of 
the complex zero, and the ratio of Cj to C, sets the imaginary part of the complex 
zero. Figure 4.14 shows realization of a delaying complex integrator by two 
delaying SC integrators. 



4.3.2 Dynamic Range Scaling 

For an SC modulator, the voltage swing at an integrator output is limited by the 
output saturation voltages of the opamps. The AX modulator Simulink model was 
simulated for different input frequencies and amplitudes in order to obtain the peak 
values at each integrator output. To ensure that each opamp output never exceeded 
the reference levels, dynamic range scaling was performed by multiplying the 
coefficients at an integrator input by a factor and dividing the coefficients at the 
output of the integrator by the same factor [1]. In the Simulink model, for a -6 dB 
input signal, the peak values at the integrator outputs were limited to 70% of the 
reference levels. 

The reference levels to the multibit quantizer and the multilevel DAC are set at 
1.4 V and 0.4 V, and centered around a common-mode of 0.9 V. With Dynamic 
range scaling, each opamp is limited to a maximum differential swing of 1 .4 V p _ p . 



4.3.3 Multibit Quantization 

During the noise assignment of the modulator (see Sec. 4.4.1.2), 25% of the total 
permissible noise was assigned to in-band quantization noise. At an OSR of 16, 
a 4-bit quantizer is required to suppress the in-band quantization-noise to the 
required level that is, below the noises from the analog circuit and other sources. 
Behavioral simulations with a 4-bit quantizer predict a peak signal-to-quantization 
ratio (SQNR peak ) of 81 dB for an overload-ratio (A OL ) [4] of 0.75. 

In the proposed AZ modulator implementation, the 4-bit quantizer will be 
implemented as a 15-level flash ADC. Behavioral Monte Carlo simulations show 
that the modulator is robust to quantizer offsets, and even an offset of value 20 mV 
has a negligible impact on the SNR of the modulator. 



102 



4 Architectural-Level Design of the Experimental AX Modulator 



(p-1)z 



(P r -1)z" 




r^r ^^Y(z) X R (z) 



X(z) 


= X R (z) + J X R (z) 


Y(z) 


= Y R (z) + J Y R (z) 


P 
-l(z) 


= P r + JPi 

X(z) z-p 




c 



X,(z) 



z-1 






/ -1 

-P/Z 

-1 

\' z 


z 
z-1 







Yr(z) 



(P r -1)z" 




Y,(z) 



Fig. 4.13 Realization of a complex pole atp = p,- +jp; using (a) a complex signal flow graph and 
(b) a two-input two-output real linear signal flow graph, (c) a fully-differential SC realization of 
the nondelaying complex integrator 



4.3 The Switched-Capacitor Architecture 

a (p-1) b 



103 




Y(z) x r( z ) 



X(z) = X R (Z) + JXpU! 



Y(z) s 


- Y R (z) + J Y R (z) 


P : 


~- Pr+JPi 
. Y(Z)_ 1 
X(Z) z p 




C 



X,(z) 



(P r D 





(P r -1 ) 



Yr{z) 



Y|(z) 



Fig. 4.14 Realization of a complex pole at p = p, + jpi using (a) a complex signal flow graph and 
(b) A two-input two-output real linear signal flow graph, (c) A fully-differential SC realization of 
the delaying complex integrator 



104 



4 Architectural-Level Design of the Experimental AX Modulator 



B 2 + B 3 z"' 




>Y(z) 



Fig. 4.15 Architecture of the modified AX modulator 

4.3.4 Multilevel DAC 

The proposed complex AZ modulator uses one multilevel DAC in the feedback 
loop. The complex feedback coefficient, C 2 , in Fig. 4.15 is realized by a real and an 
imaginary array of 15 capacitors each (refer to Figure 4.16). The thermometer 
output code of the quantizer is connected to the switched-capacitor feedback DAC. 
To account for the effect of capacitor mismatches in the DAC unit capacitors, the 
behavioral model of the modulator was simulated with mismatch error in the DAC 
elements. Section 4.4.1 reports the worst-case SNDR performance due multilevel 
DAC nonlinearity found over 100 simulations of the modulator. 



4.3.5 Realizing the Feedins 



In Figure 4. 13, the coefficient F 3 realizes an input feed-in term delayed by one clock 
cycle before it is added to other inputs of the last integrator. To implement F 3 , the 
combined feed-in terms Ft, and F 4 were implemented as the summation of a 
nondelayed term and a differentiator term: 



F%z 



F 4 = F 3 + F 4 - F 3 (1 



_-n 



Similarly, to reduce the coefficient spread for the coefficients B 2 and B 3 , the 
feed-forward B 2 + B3 z" 1 was implemented as Table 4.2: 



B 2 



B 3 z- 1 =B 2 



S 3 - B 3 1 



4.3 The Switched-Capacitor Architecture 

d„A2 (n=1...ib) 
Vrefp 



Vrefn O 



105 




£> Vdacp 

(DAC input to 
1 st stage) 



(Array of 1 5 capacitors) 
1 



Fig. 4.16 Multi level DAC 



Table 4.2 Implementation 
of the feed-ins and the 
feed-forward coefficients 



Initial coefficient values 



Modified coefficient Values 



F 3 = -0.32 - 0.67/ 
F A = 0.02 
B 2 = 2.0+3.93/ 
B 3 = -0.93- 1.88/ 



F 3 + F A = -0.3 - 0.67/ 
- F 3 = 0.32 + 0.67/ 
B 2 +B 3 = 1.15 + 2.04/ 
-B 3 = 0.93+ 1.88/ 



4.3.6 The Complete Fully-Differential SC Architecture 



Figure 4.17 shows a single-ended representation of the SC implementation of 
the complex AZ modulator. The actual circuit implemented is fully-differential. 
The NTF zero at dc is realized by the first stage. The second stage with complex 
feedins realizes the complex NTF zero, and the zeros at the image frequency and 
the centre of the signal passband are realized by the real resonator, that is, stage 
three and stage four. Each channel output goes to a 4-bit quantizer. The two 4-bit 
quantizers generate a 15-bit thermometer code, which is connected to a switched- 
capacitor feedback DAC. The feedback DAC implements a complex coefficient 
that uses a real and an imaginary array of 15 capacitors each, with the smallest unit 
capacitor sizes equal to 24 ff (real) and 25.7 ff (imaginary) respectively. 



106 



4 Architectural-Level Design of the Experimental AX Modulator 



ra 



— I : , nw 



^/ 




i > i i i 



^iLioix, 






/ A I! I I 

_i I— Is ,^r-~~~ <d ra <d co 

I 111 * Ti /s -=7 . . 






CM U^> 



J&>+ 



r*rt 



0) TO 

<l> Q 
in < 

r 




1 1 1 1 ' 1 

- Wr W/- W,- 4-2--I 



talS# 



a » 

I I 

cp O 

in < 

•*- Q 
o 




> 

+ 

> 






0> I, 0) 






{ D az''az} 



Par'az} 



"a 
X 



<3 



£ 
"5. 












■a 

u 

I 

u 

To 

e 






4.4 System-level Behavioral Simulations 



107 



lop4 O- 




+1 

§2 



'if , 








1 
1 


1 


; 





















4»i 



He 



=>D| 

(4b data) 



Fig. 4.18 Clocking scheme- real-channel fourth-stage and the quantizer 

4.3.7 The Clocking Scheme 

The AZ ADC uses two non-overlapping clock phases, cf> l and <f> 2 , and their "early" 
versions, § Xe and 2e , to minimize charge-injection [5], A nonoverlapping clock 
generator provides the necessary clock phases. 

The first stage of the modulator samples input during clock phase (/>,, and the 
feedback DAC applies the references during clock phase <p 2 - Figure 4.18 shows 
the fully-differential implementation and clocking for the fourth-stage amplifier 
and the 4-bit quantizer. 



4.4 System-level Behavioral Simulations 



4.4.1 Capacitor Sizing 



4.4.1.1 Capacitor Mismatch 

In an SC AE modulator, the integrator gains are implemented by capacitor 
ratios. Process variations cause the realized capacitors to deviate from their 
nominal values. For example, for a coefficient of value G realized as a ratio 



108 



4 Architectural-Level Design of the Experimental AX Modulator 



40 
35 
30 
25 
20 
15 
10 
5 
























:^^ 



69 70 



71 72 
SNR 



73 



74 



20 










15 












10 














5 


















n 


-X- 
















I 



45 50 55 60 65 70 75 80 85 90 
IMR 



Fig. 4.19 Histograms for (a) SNR and (b) IMR for the proposed AX modulator with ± 0.5% 
random coefficient mismatch in the DAC elements 



of two capacitors, Cg and C„ the actual implemented coefficient value, G , is 
given by: 



C g 1 



■s/m{WL\ 



Ci[\ 



\/"(WL) t 



(4.5) 



where A c is a process-dependent parameter. ' The deviations of the coefficients from 
their nominal values are manifest as a modification of the NTF and STF of the 
modulator. A technique intended to realize capacitor ratios with higher accuracy is 
implementation by capacitors realized as an array of unit capacitors. Behavioral 
simulations of the modulator were used to identify the sensitive coefficients, and the 
capacitors realizing these coefficients were sized larger in order to minimize their 
deviations. 

The multilevel DAC has been implemented as an array of unit capacitors. Errors 
in the values of these unit capacitors can limit the linearity and resolution of the AE 
modulator. To account for the effect of capacitor mismatches in the DAC unit 
capacitors, over 100 behavioral simulations, with random mismatches of ± 0.5% 
peak-value in the DAC unit elements, were performed to examine the worst case 
SNDR and IMR. 

For ± 0.5% mismatch values, the minimum SNDR falls to 69.7 dB with 
95-percentile at 70 dB. The minimum IMR drops to 46.2 dB, with 95-percentile 
of the IMR at 48.6 dB (Fig. 4.19). 

However, when realistic mismatch values based on the process mismatch 
factor and (4.5), and also the capacitor values derived in Sec. 1.4.0.1 are used, 



This assumes that the area effects dominate and the edge effects can be ignored. 



4.4 System-level Behavioral Simulations 109 

(C C 2R = 23.2 x 15 = 348/F,C C2 / = 51.4 x 15 = 771.5/F ,C, = l.9pF), the actual 
mismatch for the DAC coefficients, C2RC21, comes out to less than ±0.1%. 
For ±0.1% mismatch in the feedback coefficient, the minimum SNR comes out 
at 77.5 dB, with 95-percentile at 78 dB. The minimum 1MR for ±0.1% mismatch 
is at 58.2 dB, with 95-percentile at 62.65 dB. 



4.4.1.2 Noise Analysis 

Thermal noise estimation for a complex AE modulator is similar to noise estimation 
for a low-pass AE modulator. The noise estimation in a AE modulator starts with 
the identification of the thermal noise sources, for example, SC switches, opamps in 
the circuit [6], For example, Fig. 4.20a shows a complex integrator with two 
uncorrelated noise sources, V„/i and V„a, but both having the same power added 
to represent the switch noise sources in the cross-coupling SC branches. Similarly, 
V„ji and V„/2 in the Fig. 4.20 represent switch noise sources in the feedback 
branches of the integrator. It can be shown that the noise sources V„a and V n n 
can be combined into a single noise source V„i in a simpler signal-flow graph 
representation of the complex integrator (Fig. 4.20b), where V„j is given by: 



, kT2x+ 1 
tor - 1) a/^TTT (4-6) 



The multiplying factor ^*p (x = 2g m r on ) in the equation represents the reduc- 
tion due to the finite bandwidth of the opamp. Similarly, in Fig. 4.20b, the noise 
sources V„r\ and V„r2 have been combined into a noise source V„r, where V„r is 
given by: 



V„ R = (pi) sj^r^j (4.7) 

Figure 4.20b shows the equivalent noise representation for a complex integrator; 
the SC branch switch noises have been combined with the opamp noises Vo P amp\ 
and Vo P amp2, which represent thermal flicker and other noises generated in the 
opamp devices. 

Figure 4.21 shows the block diagram of the complex AE modulator, with 
thermal noise sources added at the inputs of the feed-ins to the integrators. For an 
integrator stage, the opamp noise after proper scaling can be combined with one of 
the feed-in noise sources. Figure 4.22 shows the frequency responses of the power 
transfer functions for each noise source to the output of the modulator. For a 
complex coefficient, there are two transfer functions corresponding to the real 
and the imaginary parts of the coefficient. Integration of each power transfer 
function from dc to the signal-band edge represents the gain of the noise source 



110 

a 



4 Architectural-Level Design of the Experimental AX Modulator 



v„ 



'nRI 
(Pr-1) | 



(z) = X p (z) + J X p (z) 




Yr(z) 



y(z) = y p (z) + jy p (z) 



Y,(z) 



nR2 



H(z) = g% -L p = Pr +jp, 
X(z) z-p 



V m = V nR + J V nl 




X(Z)[ 



n2 opamp'\ J opamp2 

Fig. 4.20 Representation of noise sources in a complex integrator: (a) SC switch noise sources 
added to the complex signal flow graph, and (b) an equivalent noise representation in a signal-flow 
graph, including noise due to opamp devices 

to the output of the modulator. Since the complex AZ modulator has been designed 
with a unity STF in the signal-band, the input-referred noise power is equal to the 
output-referred noise power. 



4.4 System-level Behavioral Simulations 



111 







X 



< 



o 
Z 

— < 



112 



4 Architectural-Level Design of the Experimental AX Modulator 



10- 

D 

-10 

£-20 



J^ 



I C 2R 



=ED= 



f-30 
O 

O -40 

1-50 






-60 
-70 



12 3 4 5 6 
Frequency (MHz) 




2 3 4 5 6 
Frequency (MHz) 




12 3 4 5 6 
Frequency (MHz) 



2 3 4 5, 
Frequency (MHz) 



10 


-tt) 

oa 
3-20 

1-30 
O 

j " 4 ° 

|-50 

-60 

-70 



Fig. 4.22 







_l(-1+p R )h- 


^ p ' I 



2 3 4 5 6 
Frequency (MHz) 




Frequency responses of the noise transfer functions 



2 3 4 5 
Frequency (MHz) 



4.4 System-level Behavioral Simulations 113 

The noise power spectral densities multiplied by the power transfer functions are 
given by: 

-j— fs/OSR 

— 7 fs/OSR ~^—f,/OSR 

Kc. 



m f \NTF c J df+ V f± J \NTF c J d f ^C 2 

~2 fs/OSR — fJOSR 

-j— f.</OSR 



+m I ^' 2 * 



- 1 —f,/OSR 

+ m I \ NTFA ^ df ^ M 

v\ = — 2 fJOSR — f,/OSR 

-^ fs/OSR ~ r ~ f,/OSR 

+ J/2 J lNTFFj2df+ ^2 J \ NTFF ^ df ^ Fl 

— f s /OSR — f s /OSR 

+ J/2 f \ NTF ^f d f+jfi f \NTF Fvi \ 2 df ^F 34 

-^ fs/OSR _^ fJOSR 

vt 



^| J \NTF B Jdf +j ^ J \NTF Bu \ 2 df ^B, 

~2 fs/OSR — f,/OSR 

j^ f \NTF B3iR \ 2 df + V -0f J \NTF Bl Jdf ^B 13 

~2 fs/OSR -j— f,/OSR 

'"""■ J \NTF B Jdf+^ I \NTF B3l \ 2 df ^B 3 



fs/2 J ' D3SI J fs/2 

~^— fs/OSR 

+ || / \NTF G f d f ^G, 

-j— f s /OSR -^—fs/OSR 

+ m I \ NTFp S df + V jj2 I \ NTF '^ df ^ Zcm " ix 

-^— fs/OSR 

v C 

+ j% \ \NTF\ 2 df ^NTF (4.8) 



114 4 Architectural-Level Design of the Experimental AX Modulator 

After substituting for the sampling frequency, / s , and for the OSR, the power 
transfer functions were integrated in Mathematica [9]. The total output noise power 
is given by Eq. (4.9): 

v^(7.2 x 10- 2 ) <-C, 

+ ^~ (2.1 x io- 2 ) + v^T (l.o x lrr 1 ) «- c 2 

+ ^ (4-0 x 1CT 3 ) + v^ (2.7 x 10- 2 ) <- A, 

+ ^(2-0x 10- 4 )+ ^A 2 

+ ^(4.0x IO" 4 ) + ^A 3 

+ ^T (3.0 x IO" 3 ) + ^7 (2.2 x IO" 2 ) «- F, 



v&, (1-0 X IO" 4 ) +v 2 (3.0x IO- 4 ) ^F 2 



&„ (7.8 x IO- 6 ) + v 2 (4.0 x IO" 5 ) <- F 34 



+ v 2 (3.2 x IO- 4 ) +v 2 (1.3 x 10- 3 ) «-B, 



V 2 nB 23R (LI X IO" 4 ) + V 2 ^ (3.7 X IO" 4 ) ^5 23 



+ vL 3 (LI x IO- 4 ) + vl B (3.7 x IO- 4 ) ^B 3 

+ ^T(3.7x 10- 6 )+ <-G, 

+ ^ (1.7 x IO- 4 ) + ^ (3.7 x 10- 3 ) «- z™^- 

+ vg (2.3 x IO" 6 ) + «- JVTF (4.9) 

In order to simplify the noise analysis, the noise terms with insignificant 

contribution to the total noise in (4.9) can be dropped. The total noise power is 
now approximately given by: 

^7(7.2 x IO- 2 ) 



, 2 (2.1 x 10- 2 )+v 2 (1.0 x 10- 



'»*,. ( 4 -0 x 1(T J ) + v 2 (2.7 x IO- 2 ) 



+ i& u (3.0 x 10- 3 ) + v\ Fu (2.2 x IO- 2 ) (4.10) 

The first three terms in the equation represent the noise contribution of the first 
stage, and the remaining terms represent the noise contribution of the second stage 
of the modulator. 



4.4 System-level Behavioral Simulations 



115 



The next step is to substitute the PSDs for the noise sources. The mean-square 
value of the input-referred noise voltage of an SC integrator is given by: 



1.2 - 



kT\ 2x + 1 



C.J x+l 



(4.11) 



The input-referred noise (4.1 1) does not include any noise contribution from the 
opamp. The opamp thermal noise can be modeled by two noise sources [6], one at 
its input with a mean-square value of: 



4 kT 
3 C, 



1 



(4.12) 



and another at its output with a mean-square value of: 



4 kT 
3CZ 



(4.13) 



where Cl is the effective load capacitance of the opamp, x = TRonSm ■ Ron is the 
switch on-resistance, and g m is the transconductance of the input MOSFET of the 
opamp. For the case x — > oo, the total input-referred noise of an integrator is 
dominated by the noise generated by the SC switches and is equal to 2kT/C s . 

The second noise term in Table 4.3 models the opamp input-referred noise 
power, which is stored at the input capacitor branches at the first stage integrator. 

The effective load capacitance, Cu, f° r the first stage is given by (Table 4.4) 



Cu = C 



si 



Air 



1.413Q 



Cm 

3.60C S 2 



1 



C2R+C21 

Ci 



l + Ci+C 



2R 



C21 



(4.14) 



' For an integrator with several SC input branches, the thermal noise due to switches referred to 
input branch C\ a is given by: 



kT (2x + 1 
CiA-v+1 






However, the opamp input noise referred to the input-branch is given by: 



4\ kT 

3/ C\„ \x- 



Ci„+Ci,,+. 
Cu, 



C\h C\ c 

■ 1 

C\ a C\ a 



The equation for opamp noise has been derived assuming that all the SC branches have identical 
time constants. The modified equation reflects the correlated noise injected at the input branches of 
the integrator. 



116 



4 Architectural-Level Design of the Experimental AE Modulator 



Table 4.3 PSDs for the noise sources referred to the sampling capacitor of the first stage of 
the modulator 
PSD term 



kT flx+\ 
4 kT I 1 



1 + 



C2R + C21 



C, 



3C S1 



Cm+Cn+C\ 
C, 



1 + 



ClR + C21 



Switch noises 



Opamp input noise 



Table 4.4 PSDs for the noise sources referred to the sampling capacitor of the second stage of 
the modulator 
PSD term 



kT (2x + 1 



C S i\x+\ 
4 kT 



1 + 
1 



Au+Fm+Fu 



C, 



3 C Si \ X + Am+A„+F, R +F„ 



1 + 



An 



4 kT 



An 



- Switch noises 

- Opamp input noise, stage two 
Opamp output noise, stage one 



For this design, a value of x = 1 was selected. Substituting for the PSDs and the 
coefficients in (4.9), the resulting noise contribution of the first stage of the 
modulator is: 



kT kT 

v„ w i=— (0.29)+ — (0.19) 

LSI L-si 

= ^(0-49) 

LSI 



(4.15) 



The noise contribution of the second stage of the modulator is: 



kT kT 

V n , stage! = ~ (0-04) + — (0.03) 



kT 



Csi 



C.S2 



1.413 Csi + 3.60C S2 



(0.069) (4.16) 



For a maximum input signal power of -6 dB and a 12-bit performance, the total 
noise power, including quantization noise, thermal noise, external noise sources, 
etc., is 10 ( - 6 - 74)/10 V 2 =(100 uV) 2 . If 65% of the noise power is assigned to thermal 
noise, the total permissible noise power comes out to be (80.6 uV) 2 . Assigning 50% 
of this noise power, (61.5 uV) 2 , to the first stage, and 30%, (44.2 uV) 2 , to the second 
stage of the modulator gives the values for the sampling capacitors in the first stage 
and the second stage of the modulator. 



4.4 System-level Behavioral Simulations 117 

Table 4.5 Stage capacitor sizes and spreads 





Integration capacitors 


Feed-in capacitors 






Capacitor spreads 


Stage 1 


1.878 pF 


C a 


= 642.8 fF, 






5.4 






CciR 


= 348 fF, 


Ccn 


= 771.5/F 




Stage 2 


850 fF 


Cair 


= 240.55 fF, 


Cam 


= 626.11 fF, 


17.25 






Cf\R 


= 207.23 fF, 


Cfu 


= 558.79 fF, 








Ccc 


= 49.72 fF, 


Ccd 


= 286.36 fF, 




Stage 3 


1 pF 


Ca2 


= 277.8 fF, 


Cbxr 


= 242.8 fF, 


39 






Cbu 


= 490.9 fF, 


Cf2R 


= 144 fF, 








Ccc 


= 49.72 fF, 


Ccd 


= 286.36 fF, 




Stage 4 


250 fF 


Ca3 


= 375.0 fF, 


CB2BiR 


= 288.7 /F, 


7 






Cbibv 


= 512.3 fF, 


Cb3R 


= 233.25 fF, 








Cbv 


= 471.55 fF, C F3F4S 


= 73.8 /F, 








Cf3F41 


= 167. 32 fF, 


Cf3R 


= 73.8 /F, 








Cfv 


= 167. 32 fF, 









— (0.496) = (61.5/iV) 2 
Csi = 7 535/F 



/tr kT 



2 



Cj ^ + L413,543fF + 3.60cJ ° M9 ^^ 20 ^ 

C S2 = 172/F 

Due to some process restrictions on the smallest capacitor dimensions that can 
be drawn, the actual capacitor values used in the implementation are slightly bigger 
than the sizes given by the noise requirements. The final capacitor sizes used to 
realize the modulator are listed in Table 4.5. 

The impact of thermal noise on the SNR of the AZ modulator was simulated by 
adding noise sources at the inputs of each coefficient in the behavioral model. 
Figure 4.23 depicts the model used to simulate the effect of switch thermal noises 
on the modulator. 



4.4.2 Clock-Jitter 

Due to the wide bandwidth of DTV signals, about 6-8 MHz, clock jitter will have a 
significant impact on the SNR of the ADC. Assuming the clock jitter-induced error 
can be modeled as white noise, with uniform power spectral density from tof s /2 
and a total power of [8]: 



(Aco IN ) 2 : 



2 



a* (4.17) 



118 



4 Architectural-Level Design of the Experimental AX Modulator 



Fig. 4.23 Noise sources to 
model switch thermal noises 
in a complex coefficient 




The in-band noise power reduced by the oversampling ratio is given by: 



{A(o m ) 2 
-a 



OSR 20SR 



Ai 



(4.18) 



The signal-to-noise ratio due to jitter in the sampling clock can be expressed as: 



SNR 



OSR 1 



jlter 



mj N a\ t 



(4.19) 



From (4.19), for a signal bandwidth of 8 MHz, SNR jiter >80 dB, and OSR of 16, 
the rms value of the clock jitter should be less than 8 psec. This jitter requirement is 
severe and, at the targeted sampling frequency of 128 MHz, clock jitter may 
become the limiting factor for the SNR of the ADC. 



4.4 System-level Behavioral Simulations 



119 



Fig. 4.24 Complex -integrator 
realized with finite dc gain 
amplifiers 



Xr(z 



(P r -1)z~ 



Yr(z) 




(P r -1)z 



H(z) 



= mi. 



X(z) z-p-Ap 



4.4.3 Opamp Nonidealities 

4.4.3.1 Opamp Finite DC Gain 

The behavioral model uses the aPy representation [9] to model the effect of the 
finite dc gain in a practical SC integrator implementation. Using the aPy represen- 
tation, the output of a complex SC integrator (see Fig. 4.24), can be expressed as: 



H(z) = 



m 

X(z) 



ap + (a - P) 



(4.20) 



Assuming a and P can be modeled as: 



a = 1 + Aa 
P = 1 + Ap 



(4.21) 



where a is the gain-error, and /? is the frequency error introduced by the finite dc 
gain of the opamp. These errors modify the transfer function of the complex 
integrator to 



H(z) 



X(z) 



Ap 



(4.22) 



Ap = pAoc — Aa + Ap represents the frequency-error introduced in the complex 
pole by the finite dc gain of the opamp. 



120 



4 Architectural-Level Design of the Experimental AX Modulator 



81.5 




Input Signal: 
-6 dB at 4 MHz 



45 50 55 

DC gain, A 0max (dB) 



60 



Fig. 4.25 Simulated SNDR peak versus maximum dc gain A 0ma x of the opamps in the experimental 
AX modulator 



Behavioral simulations were performed to determine the SNDR degradation 
due to finite dc gains of the opamps. The fourth-order AS modulator was simulated 
for various maximum dc gains, A 0max , with an input signal of amplitude -6 dB 
and a frequency of 8 MHz. Figure 4.25 shows the corresponding SNDR peak versus 
^Omax- The modulator shows an SNR degradation of less than 2 dB for an opamp 
dc gain variation from 30 dB to 60 dB. However, to ensure that there is not a 
significant SNR loss due to opamp gain nonlinearity, a value of 60 dB for the dc 
gain is chosen. 



4.4.3.2 Unity-Gain Frequency and Slew Rate 

Once the capacitor sizes are selected, it is possible to estimate the unity-gain 
frequency and slew current requirements of the opamps used to realize the 
integrators in the modulator. Assuming 25% of the half-clock cycle time period is 
available for slewing, the slew current requirement for an opamp in 'stage i' can be 
estimated as: 



htEWi — SRCu 

__ 100 2 
~ ~Z2 1 



128MHz x 1 VC Li 



1.024 x KfCu 



(4.23) 



Where C Li is the capacitance load for opamp in 'stage V . 



4.4 System-level Behavioral Simulations 121 

Table 4.6 Opamp open-loop requirements 





C L [pF 


1 


P 




AlGBW 


G m [mS] 




IsLEW 


IsETT 


Opamp 


3>! 


<D 2 


*i 


C> 2 


[GHz] 


4>i 


d> 2 


(uA) 


(uA) 


Stage 1" 


2.82 


1.12 


1.0 


0.4 


1.88 


13.36 


13 


573 


650 


Stage 2 b 


0.87 


0.28 


0.3 


1.0 


2.50 


13.65 


1.35 


446 


650 


Stage 3 a 


0.37 


0.58 


1.0 


0.42 


1.79 


1.77 


6.74 


301 


337 


Stage 4 b 


0.19 


3.79 


1.0 


0.24 


3.13 


9.0 


3.6 


985 


450 



a <I>2 is the holding phase, and Oi is the integrating phase 
b <l>i is the holding phase, and ® 2 is the integrating phase 



Assuming that the opamp has a single dominant pole and is not slewing, then the 
response of the integrator to a step input can be described as an exponential with a 
time constant 'x' given by [10]: 

t = -^ (4.24) 

Pgm 

For an integrator to settle to resolution of _/V B -bits in the settling time 'f se tt\ the 
time constant 'x' is given by: 



ln(2 N *) 



(4.25) 



Assuming that for the proposed modulator 65% of the half-period is available for 
integrator settling, and the first integrator has to settle to a resolution of 12-bits, then 
from (4.24) and (4.25) we have: 

g m 7.52 x 10* 

fuGBw =2^c~r — p — ( 6) 

Equation (1.26) was used to calculate the unity-gain frequency (/ugbw) require- 
ments for the four opamps. The calculated values for /ugbw are shown in Table 4.6. 
However, due to the noise-shaping in the AE modulator, it should be possible to 
relax the settling requirements and hence required /ugbw f° r the integrators in the 
subsequent stages. From (4.26) the loop-gain bandwidth (Jlgbw =/ugbw x P) for 
the opamp is 752 MHz. 

The opamp input device current required to realize the transconducatnce (g m ) 
shown in Table 4.6 can be estimated from: 



Isett = ^ (4.27) 



122 4 Architectural-Level Design of the Experimental AX Modulator 

The calculated values for/ SETT for an overdrive voltage (V ov ) of 0.1 V are shown 
in Table 4.6. 



4.4.4 Switch On-Resistances 

In an SC implementation of the modulator, the switches are implemented with 
NMOS and PMOS devices. The finite switch-on resistance and other non-ideal 
behavior of these devices can degrade the performance of the integrators and of the 
modulator as a whole. 

It is possible to decide on the type of the switch, PMOS, NMOS, or CMOS 
transmission gate, on the basis of the node to which the switch is coupled. For 
example, switches coupled to the summing junction of the integrator have one side 
either connected to analog ground or to the summing junction of the opamp. With the 
switch arrangement shown in Fig. 4.17, and with the choice of low-voltage for analog 
ground, it should be possible to use NMOS devices for the summing junction 
switches. The switches coupled to the input signal or the output of the opamp have 
full signal swing across them and, as a result, it may be necessary to use CMOS 
transmission gates for these switches. To minimize parasitics, minimum gate length 
devices will be chosen. The aspect ratio WIL of the devices will also be selected so 
that the time constant Ton = {RonC) of the switch satisfies the equation [11]: 

mT 
Ton < -j- (4.28) 

where mT is the time-period available for the charging of the capacitor C. 



References 



1. Schreier, R., Temes, G.C.: Understanding Delta-Sigma Data Converters. Wiley-IEEE Press, 
New York (2004) ISBN 0-471-46585-2 

2. Jantzi, S.A., Martin, K.W., Sedra, A.S.: The effects of mismatch in complex bandpass 
A£ modulators. IEEE International Symposium on Circuits and Systems, vol. 1, 
pp. 227-230, 12-15 May 1996 

3. The Math Works, Inc., Simulink, Version 6.4, The Math Works, Inc., Natick, Massachusets 

4. Kenney, J.G., Carley, L.R.: CLANS: a high-level synthesis tool for high resolution data 
converters. ICCAD Digest of Technical Papers, pp. 496-499, November 1988 

5. Haigh, D.G., Singh, B.: A switching scheme for switched capacitor filters which reduces the 
effect of parasitic capacitances associated with switch control terminal. Proceedings of the 
IEEE International Symposium on Circuits and Systems, vol. 2, pp. 586-589, lune 1983 

6. Schreier, R., Silva, J., Steensgaard, J., Temes, G.C.: Design-oriented estimation of thermal 
noise in switched-capacitor circuits. IEEE Trans. Circuits Syst. 15(1 1), 2358-2368 (2005) 

7. Research, W.: Inc., Mathematica, Version 6.0, Wolfram Research, Champaign, IL. 

8. Boser, B.E., Wooley, B.A.: The design of sigma-delta modulation analog-to-digital converters. 
IEEE J. Solid-State Circuits 26(12), 1746-1756 (1991) 



References 123 

9. Ki, W.-H., Temes, G.C.: Offset-compensated switched-capacitor integrators. Proceedings of 
the IEEE International Symposium on Circuits and Systems, pp. 2829-2832, May 1990 

10. Temes, G.C.: Finite amplifier gain and bandwidth effects in switched-capacitor filters. IEEE 
J. Solid-State Circuits 15(3), 358-361 (1980) 

11. Gregorian, R., Temes, G.C.: Analog MOS Integrated Circuits for Signal Processing. Wiley- 
Interscience, New York (1986) ISBN 978-0471097976 



Chapter 5 

Integrated Circuit Implementation 



The previous chapter discussed the architecture and system level considerations in 
the design of the proposed fourth-order complex AE modulator. The required 
specifications for each building block were also discussed in that chapter. This 
chapter discusses the implementation of each of these blocks in a 0.18 um CMOS 
technology. Due to a high sampling clock frequency and the mixed-signal nature of 
the ADC, special care has to be taken to minimize the cross-talk of digital noise into 
the sensitive analog nodes. In Chap. 4, the impact of mismatch on the SNDR and 
IMR of the ADC was discussed. In the layout of the ADC, special attention must 
be paid to minimizing the mismatch between the real and the quadrature channels. 
The chapter discusses the layout considerations that were taken into account and the 
techniques that were followed during the layout of the proposed AZ modulator. 



5.1 The Complete Fourth-Order SC-Modulator 

The discrete nature of the proposed AE modulator lends itself easily to realization 
with switched-capacitor (SC) circuits. Due to the advantages of higher power 
supply rejection, reduced clock feed-through and charge injection errors, rejection 
of even-order non-linearities, and increased dynamic range, a fully-differential 
configuration was chosen for the implementation of the SC circuits. The single- 
ended representation of the SC implementation of the AX modulator presented in 
Chap. 4 is shown again in Fig. 5.1. 

The modulator is clocked by nonoverlapping two phases, cf> l and <p 2 , of the clock. 
To a first order, the charge-injection by the MOS switches is canceled by the fully- 
differential implementation of the modulator. The modulator uses bottom-plate 
sampling [1] to suppress signal-dependent charge injection. During (f> l , all of the 
switches labeled 1 are close, while those labeled 2 are open. Similarly, during (f> 2 , all 
of the switches labeled 2 are closed, while switches labeled 1 open. The switches 
labeled l e and 2 e are closed by early versions of <p l and (f> 2 - The output of each 
channel goes to a 4-bit quantizer. In addition to fifteen comparators, two additional 

B. Pandita, Oversampling AID Converters with Improved Signal Transfer Functions, 125 

Analog Circuits and Signal Processing, DOl 10.1007/978-l-4614-0275-6_5, 
© Springer Science+Business Media, LLC 2011 



126 



5 Integrated Circuit Implementation 



O-g 




^fifjwrri lWUff 



fa ^fa-fa^'U 





CM \-£~> 



■::::=£ 






ro 

<p o 

m < 

■■- Q 
o 

+ 
> 



hi 



l — T I — T I — T ^ 
J f~ J J J r~ ^~^~ 



^*T — I — I 1 

1 rfa^-pp- f(- 



1 1 

m o 
10 < 




> 

+ 

> 






O 1 <D 






far'az} 



{°ar'as} 



it 

o 



< 









o 



c 
o 



■a 
■8 

1 



.5 

00 



ir, 

si 

E 



5.2 Clock Generator 



127 



comparators have been added to the quantizers to indicate the stability status 
of the modulator. The comparators are ac-coupled and comprise a two-stage 
preamplifier-latch structure. Thel5-bit thermometer code of the quantizer drives 
the SC DAC during <j> 2 . 



5.2 Clock Generator 

Figure 5.2 shows the logic circuit diagram of the clock generator used to generate the 
two phases of the nonoverlapping clock for the proposed AS modulator. The signal 
CLK shown in the diagram is an external input master-clock fed to the clock 
generator. The clock generator comprises two cross-coupled NOR gates forming 
an R-S flip-flop. One NOR gate receives the master-clock after an inversion, 
whereas, in the case of the second NOR gate, the input clock is delayed through a 
transmission-gate, TG, to compensate for the inverter delay. The NOR gates 
followed by the additional inverters generate the nonoverlapping clock phases, (f) 1 
and </) 2 , respectively. As mentioned in the previous section, the modulator uses early 
versions of cf> l and <p 2 to reduce the effects of signal-dependent charge injection. 



Vhh=3.3V 



6 x |NV 1 



24 x INV.| 



4 x INV-, 16 x INV-, 64 x INV-, 256 x INV-, 




£>o 1e 

0<J>1e 



Dtl 



INV-, NOR 2 INV 2 4 x |NV 2 16 x INV 2 256 x INV 2 

^>J=DTl>H>~-[>^>— *<> »* 



4 x |NV 2 16 x |NV 2 

H>ri>- 



-Qo 2e 



■OO; 



'2e 



Fig. 5.2 Two-phase nonoverlapping clock generator 



128 



5 Integrated Circuit Implementation 



Table 5.1 Device sizes in the 
clock generator" 



Gate 



INVi 

INV 2 

NOR! 

NOR 2 

TG 



" W/L (um/um) 



PMOS 



6.2/0.30 

5.6/0.30 

16/0.30 

10.5/0.30 

3.5/0.30 



NMOS 



1.7/0.35 

1.53/0.35 

4/0.35 

2.25/0.35 

1/0.30 



3.5 

3.0 -- 

2.5 

2.0 

1.5 

1.0 

0.5 



1 











\ 
\ I 


L_ 


*i 


fi \ (T 






-®i. 


11 \l 


*1«->\j 






11 V 


i 
I i 




i 


\\ n( 




\ 




v \ / K... 



6 7 

Time (nsec) 



9 10 11 12 



3.0 










\/T 






~n 


2.5 


A I 


i i 

1 / 






M 1 




/-^ ®2 


H i 


? 2.0 


M 




\\ i 




\ \ 1 


\ i 




1 1 


? 1.5 
> 


^ ^26 


1.0 


| 1 1 


^2e^-i| 




1 1 1 


0.5 

n 


" / Vv 


lv 




1 V v 



12 3 4 5 6 7 8 9 10 11 12 

Time (nsec) 

Fig. 5.3 Clock signals for the two phases, their early versions, and the inverted early phases 

The early clock versions, <p le and <f) 2e , are generated directly from the outputs of 
the NOR gates. The logic gates have been sized in order to make the rise-times and 
fall-times of the phases equal. Device sizes for each gate are given in Table 5.1. 

The switches in the modulator are 3.3 V thick-oxide NMOS transistors, which 
are closed when the controlling clocks are high. Figure 5.3 shows the simulation 
output of the clock generator; the clock phases are loaded with capacitive loads 
equal to the gate-capacitances the phases are driving. 



5.4 Operational Amplifier 129 

5.3 Sampling Switches 

In the SC implementation of the proposed AE modulator, the input common-mode 
of the opamps has been set approximately at 0.5 V and the output common-mode at 
0.9 V. The positive and negative reference voltages for the DAC have been set 
at 0.4 V and 1.4 V respectively. The DAC feedback switches have been realized with 
CMOS switches with regular MOS devices. To avoid the need for transmission-gates 
or clock boosting, the remaining switches in the modulator have been implemented 
with 3.3 V thick-oxide NMOS transistors. Depending upon the value of the capacitor 
load, the switches are sized so that the charging time-constant satisfies an accuracy 
condition of 12-bits. 



5.4 Operational Amplifier 
5.4.1 Main Stage 

The amplifiers used in the integrators are designed to drive the capacitive loads to 
12-bit settling in 3.5 ns. The specifications for the amplifiers were derived in 
Chap. 4. The behavioral simulations in Chap. 4 have demonstrated a negligible 
SNDR degradation for a maximum opamp dc-gain variation from 30-60 dB. 
However, a dc-gain of 60 dB was selected to suppress opamp harmonic distortion 
adequately. 

At a power supply of 1.8 V, 60 dB dc-gain can be easily achieved with a single- 
stage gain-boosted folded-cascode opamp. The folded-cascode opamp shown in 
Fig. 5.4 is designed with a PMOS differential pair, Mj and M 2 . The swing at the 
output of the opamp has been maximized by biasing the NMOS current sinks, M 3 
and M 4 , and M 6 and M 8 , and the PMOS current sources, M 9 and M J0 , and M n and 
M]2, at the edge of the triode region; the drain-source voltage for these transistors 
has been set approximately at their overdrive voltage. For a power supply of 1.8 V, 
the differential output swing of the opamp is 2 V p _ p . The output common-mode 
voltage of the opamp has been set at 0.9 V, which is half the supply voltage. The 
input common-mode of the opamp has been set at approximately 0.5 V, which is a 
value higher than V, in order to guarantee a minimum positive input common 
mode voltage under all conditions [2, 3]. 

Voltages V p j, V p 2, V„j, and V„ 2 are set by a separate bias stage, and the voltage 
Vcmfb is set by the common-mode feedback voltage circuit. The NMOS cascode 
transistors, M 3 and M 6 , and the PMOS cascode transistors, M 10 and M 12 , are gain- 
boosted with additional fully-differential amplifiers. 

The input stage transistors are designed to achieve the desired unity-gain 
frequency. The NMOS transistors, M 3 and M 6 , and the PMOS transistors, M 10 
and M J2 , have been designed with minimal lengths (L = 0.18/ww) in order to place 
the nondominant pole of the opamp at a high frequency. For transistors M 9 , M lh 



130 



5 Integrated Circuit Implementation 



1.8V 



PMOS 




Vd o 

V cmfb |""^ - 
Fig. 5.4 Operational amplifier main stage 



M 4 , M 5 , M 7 , and M 8 longer channel lengths have been chosen in order to achieve 
better matching. 

Figure 5.5 shows the closed loop frequency-response simulations of the overall 
amplifier for the first stage of the modulator. The amplifier achieves a loop-gain of 
56 dB, a loop-gain bandwidth of 750 MHz, and a phase margin greater than 75°. 



5.4.2 Bias Stage 



Each opamp in an integrator has its own local biasing circuit. The input to the 
biasing circuit is a bias current generated by a master bias current distribution 
circuit (refer to Fig. 5.6). The master bias current circuit mirrors a current generated 
off-chip, and the mirrored currents are distributed to local biasing circuits through 



5.4 Operational Amplifier 



131 



CO 

g 
'S 
O 

o 
o 

- 



60 



4(1 



20 



-20 



-40 



10' 



10 



I [■)■' 



10 4 



1 if 



Frequency (MHz) 




10' 



10 



10- 10" 

Frequency (MHz) 



10 3 



10" 



10' 



Fig. 5.5 Opamp loop-gain magnitude and phase response - first stage of the modulator 



NMOS cascode current- mirroring circuits. It is possible to independently adjust the 
bias current to each biasing stage through the use of digital trim bits. 

The opamp uses high-swing cascode mirrors to set the bias levels (see Fig. 5.7). 
Ibias in the figure is an off-chip bias current input. Mj and M 2 together with M 3 -M 5 
form a wide-swing cascode current mirror and set the bias voltages V p j and V p2 , of 
the main opamp. Mj-M 5 form a composite device to bias Mj at a gate voltage 
of V, p + 2V or (V tp is the threshold voltage of the PMOS transistor, and the overdrive 
voltage V ov has been set at approximately 0.15 V). The drain-source voltage forM?, 
and hence forM 9 and M u in Fig. 5.4, is set at the overdrive voltage V ov . Similarly, 
M jg and M 2 o, together with M n -M 13 , form a wide-swing cascode current mirror to 
set the bias voltages V nl and V n2 . The drain-source voltage for M 2 o, and for M 4 and 
M 8 in Fig. 5.4, is set at the overdrive voltage V ov . This wide-swing biasing 
arrangement helps to maximize the voltage swing at the output of the opamp. 
M 16 is a diode-connected transistor that sets the input common-mode, V comi , of 
the opamp. 



132 



5 Integrated Circuit Implementation 



* o 



1.8V 



3ME — <4en 

M 13 | M 1 




v gnd O- 



M 10 



Miel 



I test 



lopamp<1:8>, IquanR, Iquanl 

— o 



Mc 



C 



Mirar^TT 



ivur 



iSE 



|l M 7 "t^e 

Ml, J~Tv1^ .Hill 



\ c \ c \t 



"dd 



- £~~\ Trim<0:17> 



Fig. 5.6 Master bias circuit for the modulator 

5.4.3 Gain-Boosting Amplifiers 

The gain-boosting amplifiers have been designed with reduced current in order to 
minimize power dissipation of the complete opamp. The detailed circuit diagram of 
the NMOS gain-boost amplifier is shown in Fig. 5.8. Since the input to the amplifier 
is closer to the ground rail, a PMOS input amplifier has been used. The circuit uses a 
circuit mirror arrangement, M 17 -M 19 , in order to make the output CM level of the 
amplifier equal to the desired reference voltage, V,,j. The cascode NMOS devices of 
the main opamp, M 3 and M 6 in Fig. 5.4, compensate the amplifier. The PMOS gain- 
boost amplifier, which is shown in Fig. 5.9, is similar to the NMOS gain-boost 
amplifier Table 5.2. 



5.4.4 Device Sizes 



Table 5.3 shows the sizes for the devices in the amplifier used in the first stage of the 
modulator. The opamp used in the second stage of the modulator is identical to the 



5.4 Operational Amplifier 
1.8V 



133 



Hlj 4 [! 4 [* ifj- 




V gnd O 



-O v p 1 



O v p 2 



V "2 



O V C0 

£>Vn1 



Fig. 5.7 Biasing circuit for the opamp 

first-stage amplifier; however, for the third and fourth stages of the modulator, 
circuit simulations in Spectre [4] show that it is possible to scale the opamp currents 
by 30% without any adverse impact on the SNDR of the modulator Table 5.4. 



5.4.5 SC CMFB Circuit 



The opamp output common-mode voltage is controlled by an SC common-mode 
feedback circuit shown Fig. 5.10 [5]. The output common-mode voltage of the 
opamp is set by the current flowing through transistors M 5 and M 7 , which are shown 
in Figure 5.4. Capacitors Cj and C2, which are not switched, form a voltage divider 
to sense the common-mode output voltage of the opamp, and after a level-shift set 
the biasing voltage for the transistors M 5 and M 7 . Capacitors Cj and C 5 provide the 
necessary level-shift voltage to Cj and C2. V como , the desired output common-mode 



134 



5 Integrated Circuit Implementation 



1.8V 




'grid Q. 



Fig. 5.8 Circuit diagram of the NMOS device gain-boost amplifier 

voltage, has been set at 0.9 V, about half the supply voltage. The switches Sj-Ss in 
the circuit, which are shown in the Figure 5.10, are 3.3 V thick-oxide NMOS 
transistors controlled by two nonoverlapping clock phases <p l and <p 2 Table 5.5. 



5.5 Quantizers 



Each channel of the modulator has a quantizer that produces the 4-bit digital output 
and the 15 levels that drive the feedback DAC. In the SC implementation of the 
proposed AZ modulator, the 4-bit quantizers have been realized as 15-level flash 
ADCs. A resistor ladder generates the threshold voltages for the 15 comparators. The 
resistor ladder top and bottom are connected to reference voltages of 1.4 V and 
0.4 V respectively. The output of the flash ADCs is fed to a bubble-correction logic, 
which converts the thermometer code to a " 1 of 16" code (one-hot encoding). A PLA 
converts the one-hot code to binary logic. 



5.5 Quantizers 



135 



1.8V 




Fig. 5.9 Circuit diagram of the PMOS device gain-boost amplifier 



Table 5.2 Master bias device 
sizes 



Component 


Size" 


M,,M 2 


2 x 1.0/0.5 


M 3 


6 x 1.0/0.5 


M 4 ,M 5 


4 x 1.0/0.5 


M 6 


12 x 1.0/0.5 


My, M s 


1 x 1.0/0.18 


M g 


6 x 1/0.50 


M 10 


12 x 1.0/0.18 


M u 


4 x 10/0.50 


M 12 


2 x 1.0/0.50 


M 13 , M 14 , M ls 


8 x 3.0/0.50 


M 16 


2 x 3.0/0.50 



' W/L (urn/urn) 



Table 5.3 Opamp and bias 
stage device sizes 


Opamp 
Component 


Size" 


Bias Stage 
Component 


Size" 




M,,M 2 


104 x 3.0/0.18 M, 


3 x 3.0/0.18 




Mg, Mjj 


120 x 3.0/0.35 M 2 


4 x 3.0/0.35 




M 13 


240 x 3.0/0.35 M 3 , M 4 , M 8 


2 x 3.0/0.35 




M I0 , M 12 


120 x 3.0/0.18 M g 


1 x 3.0/0.35 




M J4 


240 x 3.0/0.18 M 5 ,M l0 


1 x 3.0/0.35 




M 3 , M s 


120 x 1.0/0.18 M M ,M l7 


12 x 3.0/0.35 




M 4 , M 5 , M 6 , M 7 


120 x 1.0/0.50 Mjs,M is 


12 x 3.0/0.18 








M 6 ,M 7 


2 x 1.0/0.70 








M U ,M 12 ,M 13 


1 x 1.0/0.50 








M l6 


32 x 1.0/0.50 








M,g 


12 x 1.0/0.18 








M 20 


12 x 1.0/0.50 




a W/L (um/um) 








Table 5.4 NMOS and PMOS 

gain-booster device sizes 


NBoost 
Component 


Size" 


PBoost 
Component 


Size" 




M,,M 2 


4x3.0/0.18 


M,,M 2 


10 x 1.0/0.18 




M 3 ,M 4 


6 x 3.0/0.18 


M 3 ,M 4 


9 x 1.0/0.18 




M 5 ,M 6 , M 7 , M s 


12 x 3.0/0.50 


M 5 , M 6 , M 7 , M 8 


9 x 1.0/0.50 




Mg, Mjj 


4 x 3.0/0.18 


Mg, Ml, 


3 x 3.0/0.18 




M,o, Mjj 


4 x 3.0/0.35 


M w , M l2 


6 x 3.0/0.35 




M J3 


8 x 3.0/0.18 


M l3 


9 x 1.0/0.18 




M 14 


8 x 3.0/0.35 


M 14 


9 x 1.0/0.50 




Mis 


2 x 3.0/0.18 


Mjs 


1 x 3.0/0.35 




M ]6 


2 x 3.0/0.35 


M 16 


1 x 3.0/0.18 




M,y 


3 x 3.0/0.18 


M l7 


3 x 3.0/0.18 




M ls Mjg 


3 x 3.0/0.50 


M, s , M,g 


3 x 3.0/0.50 




M 20 


1 x 3.0/0.35 


M 20 


1 x 3.0/0.35 




M 21 


1 x 3.0/0.18 


M 2I 


1 x 3.0/0.18 




M 22 , M 23 , M 24 


1 x 3.0/0.50 


M 22 , M 23 , M 24 


1 x 1.0/0.50 




a W/L (nm/nm) 









v outp r^. 



Vcmfb ^J 




Fig. 5.10 CMFB circuit for the opamp 



5.5 Quantizers 



137 



Table 5.5 Sizes of the 
switches and capacitors in the 
CMFB circuit 



Component Size 
C,,C 2 256 fF 

C 3 , C 4 192 fF 



Si-Si 



/i y i m 

0.35 pm 




D 

D 



o[>J 



Fig. 5.11 Comparator block diagram 



5.5.1 Comparator 



For the proposed AE modulator, each comparator must have an accuracy of 125 mV 
to meet the resolution requirements of 4-bits. The comparator has been implemented 
as an ac-coupled preamplifier followed by a regenerative latch. Because of the high- 
speed requirements, the regenerative latch has been designed with small devices. 
A sufficiently high-gain pre-amplifier and an input-offset storage scheme ensure that 
the latch offset does not cause serious quantization errors. An R-S latch holds the 
comparator output during the reset phase, <p 2e (refer to Fig. 5.11 for the comparator 
block diagram). The value of the sampling capacitor has been selected to be 150 fF. 

The quantizer operates as follows: During the clock phase <p 2 , the comparator is 
in the reset phase, and the sampling capacitors, C s , sample the reference voltages 
generated by the resistor ladder. To minimize sampling errors resulting from the 
charge injection of the switches, the pre-amplifier reset switches are controlled 
by the early clock phase <\> le . The result of the previous comparison is held by the 
R-S latch. At the rising edge of the clock phase <p l , the sampling capacitors are 
connected to the modulator channel output, and the pre-amplifier starts amplifying 
the difference between the channel output and the reference voltages. At the rising 
edge of cf> le , the regeneration latch goes into regeneration, and the output after the 
delay through the R-S latch is applied to the feedback DAC, during (f> 2 - 

Since the residue-offset, that is, the offset divided by the dc gain, of the pre- 
amplifier remains uncompensated, it is necessary to properly select the dc-gain and 
device sizes of the pre-amplifier. The pre-amplifier has been designed with a gain of 
ten. The pre-amplifier has been implemented as a NMOS input differential pair with 
diode-connected PMOS loads. M 3 and M 4 in the comparator circuit diagram, refer to 



138 



5 Integrated Circuit Implementation 



1.8V 



iol 1 Mil 




"grid <> 
Fig. 5.12 Comparator circuit diagram 



Thick-oxide NMOS 



Table 5.6 Comparator 
device sizes 


Pre-amplifier 
Component 


Size" 


Regenerative latch 
Component Size a 




M,,M 2 


3 x 1.0/0.18 


M I0 , M n 


3 x 1.0/0.18 




M 3 ,M 4 


3 x 1.0/0.18 


M I2 , M 13 


3 x 1.0/0.18 




M S ,M 6 


3 x 1.0/0.18 


M l4 , M, 5 


3 x 1.0/0.18 




My 


3 x 1.0/0.18 


M lb - M,g 


3 x 1.0/0.18 




M 8 


3 x 1.0/0.18 








M g 


3 x 1.0/0.18 








M 4 , M s , M 7 , M 8 


3 x 1.0/0.18 








M 20 - M 26 b 


4 x 1.0/0.35 








C s 


150fF 







a MOS device sizes are in um 
Thick-oxide NMOS devices 



Table 5.7 Logic-gate device Q ate 

sizes in the comparator 

NOR 

INV b 



PMOS a 



NMOS 11 



1 x 1.6/0.18 
1 x 2.0/0.30 



1 x 0.4/0.18 
1 x 0.9/0.3 



a W/L (um/um) 

b Thick-oxide NMOS and PMOS devices 



Fig. 5.12, have been introduced in order to decrease the load transconductance, and 
hence increase the gain of the pre-amplifier. The regenerative latch is based on [6] . 
The result of Monte Carlo transient simulation of the comparator using circuit 
simulator Spectre [4] shows that the standard-deviation, a, of the input-referred 
offset of the comparator is less than ±10.5 mV (refer Fig. 5.13) (Table 5.6 and 5.7). 



5.6 Layout 



139 

























20 


















c = 10.33 mV 


15 
10 


























5 



























I I 


1 1 



-30 -25 -20 -15 -10 -5 5 10 15 20 25 30 
Offset (mV) 

Fig. 5.13 Result of the Monte Carlo transient simulation performed to determine the input- 
referred offset of the comparator 

5.5.2 Resistor Ladder 

The resistor ladder for the proposed AE modulator comprises 30 unit resistor 
segments with a unit size of R = 24 Q (see Fig. 5.19). The size of the unit resistor 
segment was selected to ensure that the largest time constant, formed by the center 
ladder tap and the capacitor at the input of the comparator, is small enough for the 
ladder tap voltages to settle to their proper value by the end of the reference- 
sampling clock phase [7]. 



5.6 Layout 



The proposed AX modulator was fabricated in a 0.18 urn CMOS process. The 
modulator occupies a total area of 2.5 mm by 1 .8 mm. The micrograph of the chip is 
shown in Chap. 6. The layout of the AS modulator is composed of the opamps, the 
biasing circuitry, switches, capacitors, and quantizers, and other digital logic. 
During the layout of the modulator, special attention has to be paid to the often 
conflicting requirements of the aspect ratio and the matching constraints. A sym- 
metrical layout was chosen for the analog and digital blocks in the modulator in 
a way that was consistent with the fully-differential implementation of the 
modulator. Fig. 5.14 shows the floor plan of the modulator. The placement of the 
real and imaginary channels and the four stages in a channel reflect the horizontal 
and vertical symmetry of the layout. The analog input sampling switches of the 
firststage are at the left of the layout, and are followed by stages one through four 
for each channel. The two quantizers are at the right of the channels. The clock 
input pad and the clock generator have been placed at the right of the layout; 



140 



5 Integrated Circuit Implementation 



Real Channel (I) 



Output 
Buffers 



Stage 1 


Stage 2 


Stage 3 


Stage 4 



Quantizer 



Clock Gen 



Stage 1 


Stage 2 


Stage 3 


Stage 4 



Quantizer 



Imaginary Channel (Q) 



Bias Currents 



Output 
Buffers 



Fig. 5.14 Modulator floor-plan 

the direction of the clock phases is opposite to the flow of the analog signal. Special 
attention has been paid to matching the delays of the different clock phases. 

During the layout of the modulator, care was taken to minimize layout 
mismatches between the nominally-matched analog components and also to reduce 
parasitic capacitances at the sensitive analog nodes. To minimize noise coupling, 
digital circuitry has been placed away from the sensitive analog blocks. The clock 
lines, which are running horizontally along the top and bottom of the layout, have 
been shielded and placed at a greater distance from the two channels. Vertical buses 
connect the switches in a stage to the clock lines. Horizontal and vertical buses 
between the two channels connect the signals between the real and imaginary 
channels, and also connect the input feed-ins to the integrator stages. 

The next important layout aspect after the digital-analog interference consider- 
ation of each stage is the layout of the integrators. Fig. 5.15 shows the layout shape 
for first-stage integrator. The layout shows the opamp, the capacitor arrays, and the 
analog switches. The layout for the remaining stages of the modulator follows a 
similar plan. The placement shown in Fig. 5.15 achieves the objective of isolating 
the switching blocks, e.g., the switches, from the sensitive analog nodes. 



5.6.1 Capacitor 



Metal-insulator-metal (MIM) capacitors available in the technology were used to 
realize the various capacitors in the modulator. The matched capacitors are imple- 
mented as arrays of unit capacitors and a nonunit capacitor per array having an equal 
area-to-periphery ratio. A Mathematica [8] program calculates the width and length 
needed for each nonunit capacitor to maintain the proper perimeter-to-area ratio. 



5.6 Layout 



141 



Clock Phases 





DAC Switches 








^2R 


Input 
Switch 


Ci 




C 2 | 








DAC Switches 








DAC Switches 








C 2 | 


Input 
Switch 


c. 




^2R 








DAC Switches 



Power 



Ground 



Bias 



Opamp 



Bias 



Ground 



Power 



Clock Phases 



Fig. 5.15 Layout plan for the first stage of the modulator channel 

To minimize capacitor mismatches due to etch variations, the capacitor arrays 
are surrounded with dummy capacitors, which are connected to the power supply. 
The capacitor interconnects are properly balanced to minimize mismatches caused 
by the parasitics introduced by the leads. The capacitor bottom plates are connected 
to the amplifier outputs either directly or through sampling switches. 



5.6.2 Switches 



The NMOS switches in the modulator have been realized using multi-finger 
transistors; the switch fingers share the diffusion regions. 

Figure 5.16 shows the layout for the DAC-switch cluster. The switch cluster 
is drawn in a row parallel to the feedback-capacitor array so that the switch- 
to-capacitor routes are of equal length. The (b 2 -gated thermometer-code output 
signals, which are DAC-bits, have been routed as a bus from the quantizers to the 
DAC-switch gates and have been matched in their lengths. The reference voltages 
feed in to the switch-cluster from the left, while the DAC signals feed in from the 
top and bottom, and the sampled outputs leave at the right of the cluster. 



142 



5 Integrated Circuit Implementation 



DAC-bitS 




i : .mmm m mmmmmmmmmmmi 



Opamp 
input 



mm-mm 



:+:'.'* ?:•:■% 



\*i • *V*. £V J -*-'-i-* T-if-* ir-p^i- *■* f+ '^h ¥*-[f-* *-p-^ ^-r-* 1 5*Tt^ '^^v 

.: : * *£* *^* jv* *t* *t* *v* *^* »"£« >W* *^ **=* »v« *v* Sh* ! *^-* fi ■ 




.real 
Imaginary 



DAC-bits 



Fig. 5.16 DAC-switches and the input and feedback capacitor arrays 



5.6.3 Comparators 

The quantizer has been drawn in a 15x1 array, which matches the pitch of the last 
stage integrator. The layout in Fig. 5.17 shows a slice of the quantizer that depicts 
the placement and interconnections of the pre-amplifier, the regenerative latch, the 
R-S latch, the sampling switches, and the sampling capacitors. The sampling 
switches have been surrounded by P+ substrate guard rings. The separation of the 
comparator into analog and digital regions is evident in the layout. 



5.6.4 Amplifiers 



Layout strategies that employ common-centroid, dummies, identical orientations, and 
mirror-symmetrical arrangements [9] have been used in the layout for mismatch- 
sensitive analog circuits, for example, opamp, quantizer, etc. The PMOS differential 
pair has been drawn in a common-centroid layout. Matched devices, for example, 
PMOS current sources, NMOS current sinks, etc., have been drawn with interdigitated 
fingers that have similar orientations. For some of the devices, dummy structures 
have been added to ensure that mismatches due to etching are reduced. 



5.6 Layout 



143 



Power, Ground 
(analog) 



Power Ground 
(digital) 




Sampling Sampling Pre-amplifier Regen. Latch 

switches capacitors 

Fig. 5.17 Comparator layout 



R-S Latch 



CMFB Switches 




^^ww/^ i ^ ^v^jg^ -vi^ ^ 



NMOS Current Sink 



■■ M...,l .. >.Ll >1 ,« LU^W,,,,.^,.^ 




Fig. 5.18 Amplifier layout 



144 



5 Integrated Circuit Implementation 



R 



R 



R 



R 



R 



R 
R 
R 



'REFP 



'R,15 



V 



R,14 



. V R13 280 pm 



V 



R.l 



'REFN 



TT 
J_L 



3 urn 



Fig. 5.19 Resistor ladder for the quantizers 



3 V 



REFP 



3 Vr,is 



3 V R 



14 



3 Vr.13 



3 V R;2 



3 V 



Rl 



3 V 



REFN 



The opamp biasing circuit has been divided into two unit parallel circuits in 
order to meet the layout symmetry. The opamp, including the bias circuits, has a 
horizontal symmetry. The bias circuits have been placed close to the opamp (refer 
to Fig. 5.18). 

During routing, steps were taken to ensure that there is no wiring over the active 
area of the devices. The layout of the modulator was followed by an extraction of 
the route parasitics. The routing parasitics were balanced in order to preserve the 
fully-differential symmetry of the circuits. 



5.6.5 The Resistor Ladder 



P+ silicided polysilicon has been used to realize the resistor ladder. The resistor 
has been implemented with two parallel polysilicon sheets without any bends; 



5.7 Substrate and Supply Noise Decoupling 145 

the parallel sheets effectively double the resistor area and thus improve the 
matching of the unit resistor segments (refer Fig. 5.19 for the layout diagram of 
the resistor ladder). To minimize errors due to contact resistance, arrays of contacts 
have been used to connect the voltage reference taps to the resistor ladder. 



5.7 Substrate and Supply Noise Decoupling 

The chip has been partitioned into analog and digital regions, and separate 
power supplies power the analog and digital circuits. The power supplies have 
been connected through separate bonding pads to off-chip voltage regulators. 
Well and substrate contacts have been used to improve the isolation between the 
analog and the digital circuits. To reduce the threshold-voltage modulation of 
the NMOS analog devices caused by body effect, the NMOS devices have 
been surrounded with a p+ substrate ring, which is connected to the local analog 
ground. 

P+ substrate ties, which are biased to ground, and N-well guard rings, which are 
biased at power supply, have been placed between the sensitive analog circuits, e.g., 
the opamps, and between the analog and digital regions to improve the isolation 
between the circuits. 1 Multiple substrate contacts biased to analog ground have 
been placed close to sensitive analog nodes and in the unused chip area. On-chip 
decoupling capacitors formed of PMOS devices have been placed under the power 
buses and other unused chip area in order to reduce the high-frequency noise on the 
power supplies. 

Metal-layer shielding has been used to protect signal paths and to isolate 
sensitive analog nodes, e.g., opamp inputs, from the noisy signals. A separate pad 
powers the metal-layer shield from an off-chip supply. Clocks have been distributed 
through buses. The clock buses have been shielded by a digital power supply in 
order to reduce clock noise injection through bus parasitics into the substrate, and 
hence into the analog ground. 

The selected CMOS technology offers deep N-well, an optional layer for 
isolating the noise from the P-substrate. To minimize noise injection of the 
switching digital bits into the substrate, the I/O drivers have been realized in an 
isolated P-substrate, which was created by surrounding deep N-well with N-well 
guard ring. The power and ground for the I/O drivers have been routed from 
separate bonding pads. 



Due to the low-ohmic substrate of the selected CMOS technology, guard rings are not expected 
to attenuate substrate coupling significantly. 



146 



5 Integrated Circuit Implementation 



5.8 The Integrated Circuit 

The proposed AE modulator was fabricated in a mixed-signal CMOS 0.18 urn 
six-metal single-poly technology. The chip microphotograph excluding the bonding 
pads is shown in Fig. 5.20. The chip, including the pads and other digital program- 
ming circuits, occupies an area of 2.15 mm . An overlay on the microphotograph 
highlights the two channels, I-channel and Q-channel, and the main blocks of the 
AZ modulator. 



5.8.1 Pins 

Figure 5.21 shows the pin assignment for the modulator. The chip was packaged in 
a 80-pin ceramic flat pack (CFP). 

The differential quadrature inputs, Ip In (Pins 68 and 69) and Qp Qn (Pins 76 
and 75), feed in the chip from the top pins. The DAC references, V REFP (Pin 71) and 
Vrefn (Pin 73), which are shared with the quantizer, also enter the chip from 
the top. Vcmo (Pi n 72) is a "common-mode sense" output, and can be decoupled 




Fig. 5.20 Microphotograph of the fourth-order AX modulator 



The Integrated Circuit 



147 



en 



n £ 



!^?c5oo^5^ 



s 2- 



Vdda1.8 



Vshield 

Gnda 

TestOutQp 

TestOutGn 

SerClkl 

ResDatal 

SerEn 

SerDin 

SerDout 

GndRing3.3 

VddRing3.3 

Vdd3.3 
Ufq 

QdO 
Qd1 
Qd2 
Qd3 
Ofq 

Gnd3.3 




§£ Vshield 

Gnda 

Vdda1.8 

TestOutlp 

TestOutln 

Gnda 

Vdda1.8 

VddaOufl.8 

TestQuan 

GndRing3.3 

VddRing3.3 

Gnd3.3 

Ufi 

IdO 

Idi 
Id2 
Id3 
Ofi 
Vdd3.3 

TestCmpP 



88 



to CJ 

a en 

,E .£ o ■— n ^ 
_ a: rc ri ,5 m u 



CO 



U-d5 
^ "5 2 2 



Z 

Q Q. Q. 

E E E 
"5 2 1 



Fig. 5.21 Pin assignment for the 80-pin CFP packaging of the chip 



off-chip on the PCB. I bias (Pin 79) is the current-input to the master-bias current 
distribution block. Vddal.8 (Pins 3, 56, 60, 66, 78) and Gnda (Pins 5, 57, 61, 67, 77) 
provide the analog power and ground for the amplifiers and the bias circuits. Vdd3.3 
(Pins 15, 31, 42) and Gnd3.3 (Pins 22, 33, 51) are the deep N-well power supplies 
for the clock-buffers and the digital-data output buffers. The chip ESD pad-ring 
upper and lower-voltage values have been set at 3.3 V and V respectively. 
VddRing3.3 (Pins 14, 29, 52) and GndRing3.3 (Pins 13, 30, 53) are the 3.3 V 
power and ground supplies for the pad-ring. 



148 



5 Integrated Circuit Implementation 



Qd0-Qd3 (Pins 17-20) and Id0-Id3 (Pins 46^9) are the 4-bit digital outputs of 
the modulators two channels. Ufq, Ofq, Uft, and Oft (Pins 16, 21, 45, 50) indicate the 
overflow and the undeflow status of the modulator, and, together with integrator 
reset pin, Reslnt (Pin 65), can be used to reset the modulator to a known state. 



5.9 The Test Set-Up 

Different test set-ups were designed to characterize the performance of the proto- 
type AZ modulator. Fig. 5.22 depicts the test set-up used to measure the SNDR 
of the chip. 

The quadrature inputs for the ADC are generated using an RF 0/90 Q power- 
splitter. A pair of 0/180° power-splitters convert the single-ended output from the 
0/90° power-splitter to fully differential signals. The fully differential inputs are 
ac -coupled and rebiased at an input-common mode voltage of 0.7 V. The 33 Q 
series termination resistors, together with the 0.47 nF value capacitor between the 
differential inputs, form a first-order RC anti-alias filter (refer to Fig. 5.23). 

The image-rejection of the test chip was measured with quadrature input from 
the evaluation board CMOS DDS AD9852 [10]. To improve the image rejection of 
the test set-up, the output from the evaluation board was filtered with a three-stage 
RC polyphase filter. The three-stage RC polyphase filter shown in Fig. 5.24(a) has 



Clock Generator 
(DG2030) 



DC 


+5V 


Power 




Supply 




(E3646A) 


Gnd 



0/90° 
(PSCQ-2-8) 



10/180° 
ZFSCJ-2-2 



10/180' 
ZFSCJ-2-2 






CLK 



VDD 



Signal Generator 
(R&S SMT03) 



CLKOUT 

QDrj-3 

ID0-3 
AS Modulator PCB 



GND 



QP 
QN 
IP 
IN 



CLK 

DATA Logic Analyzer 

(TLA 714) 
DATA 




Fig. 5.22 The test set-up for measuring the SNDR of the chip 



5.9 The Test Set-Up 



149 



(PSCQ-2-8) 



Analog « 
Input 



(ZFSCJ-2-2) 0.1 uF 

HI— 



(ZFSCJ-2-2) 



°- 1 mF $1.5 kn 




vwv- 
33n 



.lp 



VICM ==0.47 nF 



T ln 

... ±Qp 

I 
i 



Fig. 5.23 Power-splitter-based ADC front-end 



Chip Boundary 



D <-J\AV f 

\ C 1 



-VW- 

\9i 



k 



r\ 

d — ew^- 



R 2 
-w- 

rV 

-WA- 
^2 



R 3 

-MW t-O 

Rk 

-jwv^-V— o 



RK 

-w- 



Rk 

■Jwrt — d 




R., = 3.9k R 2 = 3.9k R 3 = 3.9 k 

C^OpF C 2 =18.2pF C 3 = 8.1pF 

Fig. 5.24 RC Polyphase filter designed to attenuate the image at the input of the test chip: 
(a) circuit diagram showing the component values, (b) frequency response of the three-stage 
polyphase filter 



been designed with pole frequencies spaced equally on the logarithmic frequency 
range (1-6 MHz) [11]. 

An 8-bit bus transceiver chip, SN74AVCH8T245, buffers the AE ADC bit- 
stream to the logic analyzer. Series termination resistors of value 22 Q have been 
inserted between the ADC output and the transceiver inputs. The logic analyzer is 
edge-triggered by a clock-phase, CLKOUT, that is, pin 32 in Fig. 5.21, which is 
derived on-chip. The data from the logic analyzer is then imported into Matlab, and 
the / and Q data-streams are combined into a complex data-stream / +]Q. After the 
complex data are windowed with Hann window, the data undergoes spectrum 
analysis with complex-FFT. For the SNDR and other measurements of the AE 
modulator, 32k-bin data have been used. 



150 



5 Integrated Circuit Implementation 



Vdda1.8 



. £ 



'bias 



R. 



SET 



Gnda «- 



& 



Chip Boundary 



Fig. 5.25 Master bias current generation for the chip 

The clock input for the ADC, CLK, that is, pin 35 in Fig. 5 .2 1 , is taken from a high- 
performance signal generator, Agilent 8664A, and rebiased using a Bias-Tee (Mini- 
Circuits ZFBT-4R2GW). The SN74AVCH8T245 chip buffers the clock on the PCB. 
During testing, the signal generator, R&S SMT03, was synchronized to an external 
reference generated by the clock generator, 8664A, in order to maintain a precise 
phase and frequency relation between the input signal and the sampling clock. 

All chip voltage references have been generated using multiple voltage 
regulators on the PCB. The master bias current is generated using the arrangement 
shown in Fig. 5.25; the current I hias can be varied by adjusting R set . 



5.10 The PCB Design 



A four-layer PCB was designed for the performance characterization of the 
modulator (refer to Fig. 5.26). A multilayer PCB has the advantage of avoiding 
high-density interconnections and also thin power and ground traces to the ICs. The 
four layers of the PCB have been used as in [12]: 

• Top-layer: The layer has been used for component mounting and signal 
interconnections. 

• Power plane: The power plane has been split into multiple planes associated with 
the analog, digital, and clock-generator supplies. 

• Ground plane: One layer of the PCB has been dedicated to the ground plane. 

• Bottom-layer: The layer has been used for some of the non-critical component 
mounting and some interconnections. 



5.10 The PCB Design 



151 



w 

- *_ 4 ■ •fr i , 

:^£T^1 ■ |Chip Digita 

• Z/^fjsJt 1 L ^ .References 




Fig. 5.26 Component side of the four-layer PCB, which was designed for testing of the AX 
modulator chip 

Two PCBs were designed for the testing of the chip. In the first PCB design, 
the ground plane was split into two sub-planes separating the analog ground from 
the digital ground and the two planes were finally joined at the power supply. In the 
second PCB design, the undivided ground plane was shared between the analog and 
the digital grounds. Compared to the first PCB, the second PCB was less noisy, and 
this fact was confirmed by the SNDR measurements of the chip. The second PCB 
showed an improvement of 3 dB in SNDR, as compared to the first PCB. A possible 
reason for the degraded performance of the first PCB could be that the digital 
ground impedance for the split ground plane was on the higher side, and this higher 



152 5 Integrated Circuit Implementation 

impedance was causing a crossover of the digital noise to the analog ground. In the 
second PCB, instead of splitting the ground plane, an effort was made to partition 
the routes into analog and digital sections. The component placement and layout 
was done in such a way to prevent cross-over of routes from one section to the other 
section. 

Supply decoupling for the chip is achieved through a hierarchical placement of 
on-chip and on-PCB capacitors. The off-chip decoupling is performed using two 
types of surface-mounted capacitors: a bank of large electrolytic capacitors of value 
100 nF and a bank of smaller ceramic capacitors of value 10 nF [13]. The ceramic 
capacitors are placed closer to the power pins in order to minimize the impact of 
parasitic lead-inductance. The decoupling capacitors, local as well as global, are 
connected to the ground and the power plane through interconnects of minimal 
lengths and, hence, of minimal parasitic inductances. Signal crossing, wherever it 
could not be avoided, is provided with a nearby decoupling capacitor between the 
power and the ground plane [14]. 

The chip is directly soldered to the PCB. The differential inputs to the ADC are 
matched in length and placed close together. Special precautions are taken to keep 
the digital signal traces, especially the clock signal, as far away as possible from the 
analog inputs and supply pins. The clock signal is routed on the top-layer, and care 
is taken to avoid crossing clock routes to the bottom-layer of the PCB. 



5.11 Test Results 

The test results of the proposed AZ modulator are very close to the simulated 
results, except for a somewhat reduced maximum sampling frequency. Due to some 
SNR degradation issues between 105 MHz and the maximum sampling frequency 
of 128 MHz, the ADC testing was limited to a sampling frequency of 96 MHz. 
The IC achieved 70.9 dB SNDR over a 6 MHz band centered around 3 MHz. At 
105 MHz, the IC performs with a loss of 3 dB in the SNDR. 

Figure 5.27 shows the STF plot of the proposed AE ADC, which is measured at a 
sampling frequency of 96 MHz. The asymmetric shape of the STF plot is evident 
from this figure. The notch at dc in the STF plot has been caused by ac -coupling. 

Figure 5.28 shows the output PSD of the chip measured for zero-input. The 
output spectrum reveals the complex noise shaping of the modulator and the deep 
notch that has been placed at the image frequency. A plot of the measured SNDR 
versus input amplitude is shown in Fig. 5.29. The modulator shows a dynamic range 
of about 75 dB for an input bandwidth of 6 MHz and a sampling frequency of 
96 MHz. The modulator shows a maximum SNDR of about 71 dB for a 6 MHz 
input frequency at an amplitude of —3 dBFS (refer to Fig. 5.30). 

Using a CMOS DDS evaluation board, AD9852, as a quadrature signal source, 
the image rejection of the IC was measured at a several frequencies within the 
6 MHz signal bandwidth (refer to Fig. 5.31 for the test set-up used to measure the 
IMR of the IC). A three-stage polyphase filter was used at the IC front-end to 



5.11 Test Results 



153 



i 1 1 1 r- 



Measure d 
Simi lated 




-48 -38.4-28.8-19.2 -9.6 9.6 19.2 28.8 38.4 48 
Frequency (MHz) 

Fig. 5.27 STF measured at a sampling frequency of 96 MHz 


-20 

-40 



-I 1 1 1 1 1 1 1 - 



-140 



Simulated 




-40 -30 -20 -10 10 20 30 40 48 
Frequency (MHz) 



Fig. 5.28 Output PSD measured with zero-input at a sampling frequency of 96 MHz 

suppress the phase and gain imbalances due to the DDS (refer to Fig. 5.24 for the 
details of the polyphase filter). Due to the narrow band limitation of the polyphase 
filter, the frequency of the input signal for the image rejection measurement was 
restricted to a range between 2.75 MHz and 4.5 MHz. Figure 5.32 shows the output 



154 



5 Integrated Circuit Implementation 



CO 

01 

Q 

Z 




-60 -50 -40 -30 -20 
Input Amplitude (dBFS) 

Fig. 5.29 SNDR vs. input amplitude 




-20 

£ -40 

Q 

£ -60| 

O "80 
-100 



-120 



Image at -6 MHz 




-3 dBFS input at 6 MHz 



-48-38.4-28.8-19.2-9.6 9.6 19.2 28 8 38.4 48 
Frequency (MHz) 



Fig. 5.30 Output PSD measured with —3 dbFS input at a sampling frequency of 96 MHz 



5.11 Test Results 



155 



Clock Generator 
(DG2030) 



DC 


+5V 


Power 




Supply 




;E3646A) 


Gnd 



CMOS DDS Board 
(AD9852) 



| 300 MHz 



Three-stage 

Polyphase 

Filter 



VDD 



GND 



CLK 



CLKOUT 

QD -3 



IDrj-3 
AS Modulator PCB 

QP 

QN 

IP 

IN 



CLK Logic Analyzer 
DATA (TLA 714) 



DATA 



Clock Generator 
(8664A) 



Fig. 5.31 Test set-up for measuring the IMR of the chip 





-6 5 

Frequency (MHz) 



nn 



Matlab 




15 



Fig. 5.32 Image rejection measurement with a three-stage polyphase filter at the input of the IC 

spectrum of the AE modulator for a -3 MHz input signal. For the input signal 
frequencies between 2.75 MHz and 4.5 MHz, the image rejection of the A£ ADC 
was measured as greater than 65 dB. 

Figure 5.33 shows the in-band spectrum for a two-tone input (-6 dBFS each 
input): the IM3 product is at -69.8 dB, and the IM2 product is at -70.5 dB. 



156 



5 Integrated Circuit Implementation 




-20 



00 

B- -40 

a 
in 
a. 

a -60 
B 

o 

-80 



-100 



-120 



- 1 r - 



70,5 dB 



~I (~ 



69.8 dB 



-6.5 rJBFS tones 



ifimw 




-1 



2 3 4 5 6 
Frequency (MHz) 



Fig. 5.33 Output spectrum of the chip for a full-scale two-tone test 



Table 5.8 Summary of the simulated and measured performance of the prototype chip 



Simulated 



Measured 



Maximum signal bandwidth 

SNDR a 

Dynamic range 

STF characteristics 

IMR 



8 MHz 

76.4 dB 

78.5 dB 

>50 dB (-ve frequency) 
>65 dB 



7 MHz 

71 dB 

75 dB 

30 dB (-ve frequency) 

>65 dB 



"Measured at a Sampling frequency of 96 MHz 

The clock-generator consumes 29.7 mW, and the remaining ADC, including the 
external references, consumes 138.4 mW. The external references dissipate 9 mW. 

Table 5.8 compares the simulated and the measured performance of the proto- 
type chip. 

The main differences between the measured and the simulated results have been 
explained in Sect. 5.13. 



5.12 Performance Summary 



The performance of the chip has been summarized in Table 5.9. 

Table 5.10 compares the performance of the implemented AZ modulator and 
some of the recently published complex AZ modulators: 



5.12 Performance Summary 



157 



Table 5.9 Measured performance of the IC 



Supply voltage 


1.8 V (analog) 
3.3 V (Clock) 


Signal bandwidth 


7 MHz 


Sampling frequency 


105 MHz 




Diff. input range 


1.6 V pp 


OSR 


16 




SNDR" 


71 dB 


Analog power (1.8 V) 


122.4 mW 




Area b 


2.15 mm 2 


Digital power (1.8 V) 


3.6 mW 




DR 


75 dB 


Clock generator" 1 (3.3 V) 


29.7 mW 




IMR e 


>65 dB 


Off-chip references (1.8 V) 


9mW 




SNR a 


71.42 dB 


Technology 


0.18 urn 1- 


■poly 


6-metal mixed-signal CMOS 





"Measured at a sampling frequency of 96 MHz. At 105 MHz the SNDR degrades to 67.8 dB 

Includes pads 
c Includes power consumption of the comparator and PLA 
d Includes power of the digital buffers 
e Measured for frequencies between 2.75 MHz and 4.5 MHz 



Table 5.10 Comparison of the performance of some of the recently reported complex A£ 

modulators 

Modulator type Signal bandwidth OSR IRR (dB) SNDR (dB) Area (mm 2 ) Power (mW) 



CT [15] 


20 MHz 


17 


58 


69 


0.5 


56(1.2 V) 


CT [16] 


10 MHz 


40 


>50 


52 


- 


7(1.2 V) 


CT[17] 


8.5 MHz 


31 


50 


76 


2.5 


375 (3.3 V) 


CT [18] 


200 kHz 


209 


- 


90 


6.0 


210(1.8 V) 


DT [19] a 


4 MHz 


12.5 


- 


70.1 


- 


35 (1.8 V) 


CT [20] 


20 MHz 


16 


47.2 


53.9 


1.30 


32 (2.5 V) 


DT [21] 


200 kHZ 


32 


>75 


57 


0.56 


18.6 


CT [22] 


- 




>65 






4.7 


CT [23] 


23.0 MHz 


12 


>66 


68.8 


0.95 


42.6(1.8 V) 


DT present work 


7 MHz 


16 


>65 


71 


2.15 


164.7 



" The solution uses two low-pass AX modulators for digitizing DTV signals 



Table 5.11 Comparison of the filtering characteristics of some of the recently published 
modulators 

Signal 
Modulator type bandwidth OSR SNDR (dB) STF filtering characteristics 



CT [24] 1 MHz 32 57 

DT Present work 6 MHz 16 71 



Low-pass filter, first order, / 3rfB = 3 MHz 
Complex filter, Stop-band attenuation >30 dB 



There are not many publications regarding the design of AE modulators with a 
filtering STF, and, except for [31], most of the design ideas and results presented are 
either in the form of patents [24-26] or papers with simulation results only [27-30]. 

Table 5.11 shows a comparison of the STF filtering characteristics of the 
implemented modulator with these in [31]. 



158 



5 Integrated Circuit Implementation 



5.13 Explaining the Differences Between the Measured 
and the Simulated Results 

5.13.1 Instability and SNDR Degradation with Higher 
Frequencies 

Two test chips mounted on two separate PCBs were tested and characterized for 
performance. The tests indicate that the modulators performed functionally till 
105 MHz; however, beyond 105 MHz, the modulators became unstable. A PSD 
plot of the modulator at a sampling frequency of 100 MHz is shown in the Fig. 5.34. 
The magnitude plot shows a peaking at a frequency of around 15 MHz, and it was 
found that the peaking worsens for higher sampling frequencies. The modulator 
finally becomes unstable beyond the sampling frequency of 105 MHz. 

A possible reason for the PSD peaking can be understood by looking at the pole- 
zero plot of the modulator NTF (refer to Fig. 5.35 for the pole-zero plot of the AE 
modulator NTF). Two relatively high Q NTF poles at NTFP X = 0.8V (a257t) and 
NTFP 2 = 0.85e' <OO7,I) can be identified in the figure. Fortunately, the NTF pole at 
0.85e ;(0 ' 07,r) is partially cancelled by the NTF zero at the image frequency, and it 
seems that the movement of the second pole towards the unit circle results in the 
out-of-band peaking. 

Table 5.12 lists the sensitivities of the NTF poles NTF] and NTFP2 with respect 
to the coefficient variations, derived with the aid of Mathematica [8]. 

Compared with the pole NTFP 2 , NTFPj shows a higher sensitivity, and particularly 
to the variation in the coefficient B 2 . To determine the SNDR degradation of the 



-20 



-120 



Out-of-band peaking 
al 15 MHz 




-50 -40 -30 -20 -10 10 20 30 40 50 

Frequency (MHz) 



Fig. 5.34 Output PSD measured with —3 dbFS input at a sampling frequency of 100 MHz 



5.13 Explaining the Differences Between the Measured and the Simulated Results 159 



lm ( z ) 1 5. 89 MHz (fs = 1 00 MHz) 




NTFP 1 = (0. 



1 Re(z) 



.2571) 



-/(0.07tc) 



Fig. 5.35 Pole-zero plot of the AX modulator NTF 



Table 5.12 Sensitivities of 








the NTF poles to the 
coefficient variations 


Coefficient 


Sensitivity (s^ FP< 


C, d(NTFPi)\ 
~ NTFPi d(C,-) J 




vNTFP, 


nNTFP^ 




B, 


-0.13+/0.4 


-0.54+;'0.15 




B 2 


- LO-jl.22 


0.33 +70.78 




B s 


-O.I3+7O.4 


- 0.05 -7O.46 




c 2 


-0.09-y0.43 


-O.13+7O.4 




NTFZj 


-0.43+/0.45 


-0.04+yo.io 




NTFZ 2 


0.33 -r-y'0.72 


o-yo.59 




NTFZ 3 


-0.58+/0.57 


-0.02+;'0.12 




NTFZ 4 


-0.33+70.38 


-0.18+y'0.12. 



modulator that occurs due to variation in the coefficient B 2 , Monte Carlo simulations 
were run with no nonidealities except for a differential error of ±2.5% added to the 
B 2 coefficient (refer to Fig. 5.36a). A striking correlation that was observed was that 
the positive peaks of the B 2 coefficient correspond to a well-behaved output PSD plot 
(refer to Fig. 5.36b), whereas the negative peaks of the coefficient correspond to PSD 
plots with out-of-band peaking (refer to Fig. 5.36c). This behavior, taken together with 
the fact that the pole NTFPj has a negative sensitivity with respect to the B 2 coefficient 
indicates that the out-of-band peaking is related with the movement of NTFPj towards 
the unit circle. The coefficient variation could be due to slewing or incomplete settling 
of the modulator at frequencies higher than 105 MHz. 

A possible reason for settling time issues could be that the wiring capacitances 
extracted by the extractor were underestimated. The layout parasitic extraction tool 



160 



5 Integrated Circuit Implementation 



a 4.8 




10 20 30 40 50 60 70 80 90 100 

Bin 
c 




jn 2k k K 2a 
4 4 4 4 4 


4 


Radian Frequency 





4 4 

Radian f-'rcqucncy 



Fig. 5.36 Monte Carlo simulation with a random variation of ± 2.5% in the B2 coefficient: (a) 
variation in the B2 coefficient. Output spectrum of the AZ modulator for: (b) bin 89, (c) bin 45 of 
the B2 coefficient 



used during the layout of the chip was compared with another tool Raphael [32], 
By considering a case of two metal paths on two different layers, it was found out 
that parasitic capacitance between two non-overlapping structures has been ignored 
in the parasitic extractor rule set. For example, for a nonoverlapping pair of metal 
paths on Metal2 and MetaO, the tool extracts the parasitic capacitance between the 
metals and the substrate, but fails to report any parasitic capacitance between the two 
metals. The suspicion that the underestimated extracted parasitic capacitances are 
the cause of the modulator SNR degradation and instability at a higher sampling 
frequency seems to be confirmed by two more observations: 

• Increasing the load capacitance at the output of the second-stage integrator 
lowers the sampling frequency values at which the peaking and instability occur. 



5.13 Explaining the Differences Between the Measured and the Simulated Results 



161 



Increasing the bias current to the second-stage opamp lowers the out-of-band 
peaking and pushes the sampling frequency at which the modulator becomes 
unstable to a higher value. However, after a certain point, increasing the bias 
currents introduces harmonic distortion in the modulator output, raises the 
inband noise floor, and degrades the modulator SNDR. 



5.13.2 Difference Between the Measured and the Desired STF 

Figure 5.38 shows that the measured and the desired STF agree well over the 
frequency band from -9.0 MHz to 19.0 MHz. However, beyond this frequency 
range the measured STF shows reduced attenuation compared to the STF that was 
targeted for this design. The behavior of the STF from -9.0 MHz to 19.0 MHz is 
controlled by the STF poles, and attenuation characteristics beyond this frequency 
range are controlled by the STF zeros. The STF zeros of the modulator have been 
realized by the feed-in coefficients Fj, F 2 , F 3 , and F 4 in the AX modulator 
architecture shown in Fig. 3.2 of Chap. 3. To determine the sensitivity of the 




_3rt _2it 
" A ~ A 



2n 
4 



Radian Frequency 



Radian Frequency 



_ 




23 




3 J 


P \ 


|-20 
u 


w/ y^ 


I" 60 

O -an 


Wi ' 



3x _2jc 
4 "4 



2it |it 
4 4 



Radian Frequency 




3rt In it ^ Zn 
4 4 4 4 4 

Radian Frequency 



4 



Fig. 5.37 Monte Carlo simulation with a random variation of ± 0.5% in the feed-in coefficients. 
STF magnitude with variation in the: (a) Fl coefficient, (b) F2 coefficient, (c) F3 coefficient, (d) 
F4 coefficient 



162 



5 Integrated Circuit Implementation 



CD 
T3 



CO 



i r 



Measured STF 



ed STF 




48 -38.4-28.8-19.2 -9.6 9.6 19.2 28.8 38.4 48 
Frequency (MHz) 



-10 
-20 



STF after changing ' 
the feed-in coefficien 



Measured STF 



ed STF 



CD 
T3 



CO 




48 -38.4-28.8-19.2 -9.6 9.6 19.2 28.8 38.4 48 
Frequency (MHz) 



Fig. 5.38 Difference in the STF magnitude due to approximation to Fj coefficient 



5.13 Explaining the Differences Between the Measured and the Simulated Results 

l r . . , , . 

-5- 

-10- 



163 




-40 -30 -20-10 10 20 30 40 
Frequency (MHz) 

Fig. 5.39 STF magnitude plotted from the SIMULINK model 



modulator STF that occurs due to variation in the coefficient Fj, F 2 , F 3 , and F 4 
Monte Carlo simulations were run with no nonidealities except for a differential 
error of ± 0.5% added to the feed-in coefficients. The STF magnitude shows a 
strong sensitivity to the F 3 coefficient (refer to Fig. 5.37). While inspecting the SC 
implementation of the modulator for the possible causes of the STF variation, it was 
found out that by an oversight while realizing the transfer-function zeros and poles 
with capacitor ratios the feed-in coefficients had been rounded to make them 
multiples of the feedback capacitor unit-sizes. For example, instead of realizing 
the coefficient Ft, = —0.32 — 0.67/, the rounded-down capacitor sizes realized a 
coefficient of value Fj = —0.30 — 0.67/. 

Figure 5.38a shows the impact of the rounded-down value for coefficient F 3 
on the STF magnitude. Considering the sensitivity of the STF magnitude to the 
feed-in coefficient F 3 , it would have been desirable to provide some kind of 
trimming for the capacitor realizing the F 3 coefficient. Figure 5.38b shows the 
STF magnitude for the feed-in coefficients realized in the SC implementation of 
the modulator. Figure 5.39 shows the STF magnitude plot derived from the 
SIMULINK model. The SIMULINK model includes opamp non-idealities and 
opamp and switch noise sources. 

The modulator was simulated for any impact of coefficient approximation on 
the SNDR performance, however, the impact of this approximation on the STF 
characteristics was missed. 



164 5 Integrated Circuit Implementation 

5.14 Power Dissipation 

As can be seen from Table 5.10 the power dissipation of the proposed ADC is 
higher than the other recently published complex AZ modulators. An exercise to 
optimize the opamp used in the modulator design has revealed that it is possible to 
upscale the PMOS devices used in the opamp by 1.5 and reduce the current 
consumed by 30%. By this exercise it should be possible to scale down the analog 
core power dissipation from 120 mW to 84 mW. At this level of power consump- 
tion, though still on the higher side, the proposed ADC is comparable to the 
complex AE modulator presented in [15]. A possible reason for higher power 
consumption could be the larger capacitors used to realize the coefficients of the 
modulator. This was done so that the matching between the two channels (/ and Q) 
remains high. The IMR measurement results of the proposed ADC confirm superior 
matching of the / and Q channels. 



References 



1. D. G. Haigh and B. Singh, "A switching scheme for switched capacitor filters which reduces 
the effect of parasitic capacitances associated with switch control terminal," Proc. IEEE Int. 
Symp. Circuits Syst., June 1983, vol. 2, pp. 586-589. 

2. Mohammed Dessouky, and Andreas Kaiser, "Very low-voltage digital-audio AZ modulator 
with 88-dB dynamic range using local switch bootstrapping," IEEE J. Solid-State Circuits, 
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3. A. Baschirotto, and R. Castello, "A 1-V 1.8-MHz CMOS switched-opamp SC filter with 
rail-to-rail output swing," IEEE J .Solid-State Circuits, vol. 32, no. 12, pp. 1979-1986, 
December 1997. 

4. Cadence Design Systems Inc., Spectre, Version 6.1.1, San Jose, California, 2006. 

5. D. Senderowicz, S. F. Dreyer, J. H. Huggins, and C. A. Laber, "A family of differential NMOS 
analog circuits for a PCM codec filter chip," IEEE J. Solid-State Circuits, vol. 17, no. 6, 
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6. Akira Yukawa, "A CMOS 8-bit high-speed A/D converter IC," IEEE J. Solid-State Circuits, 
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7. M. Rebeschini, and P.F. Ferguson, "Analog circuit design for AX DACs," in Delta- Sigma 
Data Converters: Theory, Design, and Simulation, S. R. Norsworthy, R. Schreier, and G. C. 
Temes, Eds. New York: IEEE Press, 1997, ch. 12. 

8. Wolfram Research, Inc., Mathematica, Version 6.0, Champaign, IL., Wolfram Research, 
2007. 

9. A. Hastings, The Art of Analog Layout (2nd Edition), ISBN 0131464108, Prentice Hall, New 
Jersey, 2005. 

10. Analog Devices Inc., AD9852: CMOS 300 MSPS Complete DDS, 2007. 

11. F. Behbahani, A. Karimi-Sanjaani, Wee-Guan Tan, A. Roithmeier, J.C. Leete, K. Hoshino, 
A. A. Abidi, "CMOS mixers and polyphase filters for large image rejection," IEEE Journal of 
Solid-State Circuits, Vol. 36, Issue. 8, pp. 873-887, June 2001. 

12. Mark I. Montrose, EMC and Printed Circuit Board: Design, Theory, and layout Made Simple 
(1st Edition), ISBN 078034703X, Wiley-IEEE Press, 1998. 



References 165 

13. L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, T. Roy, "Power distribution system 
design methodology and capacitor selection for modern CMOS technology," IEEE 
Transactions on Advanced Packaging, Vol. 22, Issue. 3, pp. 284-291, August 1999. 

14. Ralph Morrison, Grounding and Shielding Circuits and Interference (5th Edition), ISBN 
0470097728, Wiley-IEEE Press, 2007. 

15. L. J, Breems, R. Rutten, R. van Veldhoven, G. van der Weide, H. Termeer, "A 56mW CT 
quadrature cascaded AZ modulator with 77dB DR in a near Zero-IF 20MHz band," ISSCC 
Dig. Tech. Papers, pp. 238-599, Feb. 2007. 

16. S. Ouzounov, R. van Veldhoven, C. Bastiaansen, K. Vongehr, R. van Wegberg, G. Geelen, 
L. Breems, "A 1.2V 121-Mode CT AZ modulator for wireless receivers in 90nm CMOS," 
ISSCC Dig. Tech. Papers, pp. 242-600, Feb. 2007. 

17. R. Schreier, N. Abaskharoun, H. Shibata, D. Paterson, S. Rose, I. Mehr, Q. Luu, "A 375-mW 
Quadrature Bandpass AZ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz," IEEE Journal 
of Solid-State Circuits, Vol. 41, Issue. 12, pp. 2632-2640, December 2006. 

18. Paulo G R. Silva, L. J. Breems, Kofi A.A Makinawa, Raf Roovers, Johan H. Huijsing, 
"An 118dB DR CT IF-to-baseband AZ modulator for AM/FM/IBOC radio receivers," 
ISSCC Dig. Tech. Papers, pp. 66-637, Feb. 2006. 

19. Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lore, Masayuki Miyamoto, "An 80/ lOOMS/s 76.3/ 
70.1dB SNDR AZ ADC for digital TV receivers," ISSCC Dig. Tech. Papers, pp. 76-639, Feb. 
2006. 

20. lesus Arias,Peter Kiss, Vladimir Prodanov, Vito Boccuzzi, Mihai Banu, David Bisbal, Jacinto 
San Pablo, Luis Quintanilla, and Juan Barbolla, "A 32-mW 320-MHz Continuous-Time 
Complex Delta-SigmaADC for Multi-Mode Wireless-LAN Receivers," IEEE Journal of 
Solid-State Circuits, vol. 41, pp. 339-351, Feb 2006. 

21. Kong-Pang Pun, Wang-Tung Cheng, Chiu-Sing Choy, Cheong-Fat Chun, "A 75-dB image 
rejection IF-input quadrature-sampling SC AZ modulator," IEEE Journal of Solid-State 
Circuits, Vol. 41, Issue. 6, pp. 1353-1363, June 2006. 

22. F. Munoz, K. Philips, A. Torralba, "A 4.7mW 89.5dB DR CT complex AZ ADC with built-in 
LPF," ISSCC Dig. Tech. Papers, pp. 500-613, Feb. 2005. 

23. Navid Yaghini, David Johns, "A 43mW CT complex AZ ADC with 23MHz of signal 
bandwidth and 68.8dB SNDR," ISSCC Dig. Tech. Papers, pp. 502-613, Feb. 2005. 

24. John Laurence Melanson, "Delta-sigma modulators with integral digital low-pass filtering," 
United States Patent, US 7,116,721. 

25. Yann Le Guillou, "Feedforward sigma-delta AD converter with an optimized builtin filter 
function," European Patent, WO 2007/066273. 

26. Yann Le Guillou, Hussein Fakhoury, "Continuous-time sigma-delta analog-todigital converter 
with non-invasive filters(s) for immunity preservation against interferers," European Patent, 
WO 2006/054214. 

27. M. Ranjbar, O. Oliaei, "Continuous-time feed-forward ZA- modulators with robust signal 
transfer function," Electronics Letters, vol. 43, no. 24, pp. 1878-1881, 22nd November 2007. 

28. N. Jouida, N. C. Rebai, A. Ghazel, "Built-in Filtering for Out-of-Channel Interferers in 
Continuous-Time Quadrature Bandpass Delta Sigma Modulators," ICECS, pp. 947-950, 
December 2007. 

29. Y. Le Guillou, H. Fakhoury, "Elliptic filtering in continuous-time sigma-delta modulato," 
Electronics Letters, vol. 41, no. 4, pp. 167-168, 17th February 2007 

30. N. Beilleau, H. Abouushady, and M. M. Louerat, "Filtering adjacent channel blockers using 
signal-transfer-function of continuous-time AZ modulators," IEEE Midwest symposium on 
circuits and systems, July 2004. 

31. K Philips, P.A.C.M. Nuijten, R.L.J. Roovers, A.H.M. van Roermund, F.M. Chavero, M.T. 
Pallares, A. Torralba, "A continuous-time ZA ADC with increased immunity to interferers," 
IEEE Journal of Solid-State Circuits, Vol. 39, Issue. 12, pp. 2170-2178, December 2004. 

32. Synopsys, Inc., Raphael- Interconnect Analysis Tool, Mountain View, CA, 2005. 



Chapter 6 
Conclusions 



A digital receiver architecture based on a new low-IF complex AE modulator with 
filtering STF has been proposed in this book. A methodology for designing the 
filtering STF has also been proposed. A thorough examination through simulations 
(Matlab, Spectre, etc.,) was followed by a silicon implementation of a SC prototype 
modulator. 



6.1 Contributions 

This book presents an oversampling complex bandpass AE ADC with a signal 
transfer function that achieves a significant filtering of interfering signals. A filtering 
ADC reduces the complexity of the receiver by minimizing the requirements of 
analog filters in the IF digitization path. Unlike the continuous time AE modulator 
ADCs discussed in the literature, this discrete-time AE modulator ADC with an STF 
that significantly filters interfering signals is the first one of its kind reported. 

The AS modulator signal transfer function (STF) and noise transfer function 
(NTF) have been designed using complex filter routines based on classical filter 
design procedures. With a filtering STF and stop band attenuation greater than 
30 dB, the AE modulator reduces intermodulation of the desired signal and the 
interfering signals at the input of the quantizer, and also avoids feedback of the 
high-frequency interfering signals at the input of the modulator. 

The reported complex AE ADC is intended for DTV receiver applications. 
With a maximum intended sampling frequency of 128 MHz and an OSR of 16, 
the ADC has been designed to support a maximum DTV signal bandwidth 
of 8 MHz. The ADC has been tested up to a maximum sampling frequency of 
105 MHz. The IC achieved 70.9 dB SNDR over a 6 MHz band centered around 
3 MHz. The image rejection ratio (IRR) of the AE ADC was measured as greater 



B. Pandita, Oversampling AID Converters with Improved Signal Transfer Functions, 167 

Analog Circuits and Signal Processing, DOI 10.1007/978-l-4614-0275-6_6, 
© Springer Science+Business Media, LLC 2011 



168 6 Conclusions 

than 65 dB. The out-of-band rejection of the ADC has been measured as greater 
than 30 dB. The key contributions of this book are: 

• A new method for obtaining optimal NTF and STF in the design of AE 
modulators. The approach uses a norm based criterion and allows an STF with 
the desired frequency response specification. The technique has been applied to 
the cases of real and complex AE modulator transfer function designs. 

• The severe SNDR degradation in the traditional input-feedforward AE 
modulators in presence of DAC non-linearities has been identified. For the 
input-feedforward AE modulator, the interfering tones at the output of the 
quantizer remain of the same magnitude as at the input. The large out-of-band 
quantization noise and the interfering tones are aliased back in-band due to the 
DAC non-linearity resulting into a severe SNDR degradation. The proposed AE 
modulator by filtering these out-of-band interfering signals shows an increased 
robustness to DAC non-linearities. 

• A feedforward AE modulator architecture without the limitations of the tradi- 
tional feedforward architectures has been proposed. The architecture avoids 
weighted summation at the quantizer input. The STF of the modulator is well 
controlled and robust in present of mismatches and other non-linearity. The 
well controlled bandpass nature of the STF makes the ADC ideal for wireless 
signals. 

• Chapters 4 and 5 discuss the behavioral and circuit implementation of the 
modulator. The techniques of noise analysis and capacitor sizing have been 
extended from the real AE modulator case and applied to the study of complex 
delta-sigma modulator. Circuit techniques suitable for the realization of the 
modulator have been developed. The modulator avoids issues related to clock- 
boosting by using thick oxide devices for the switches. The feedforward 
coefficients have been realized by a sum of non-delaying and a differencing 
coefficient. 



6.2 Suggestions for Future Work 

6.2.1 Continuous-time Modulator Architectures 

Continuous-time modulators with implicit antialias filtering seem to be better suited 
for digitization of channels that are accompanied by very high adjacent interferers. 
Compared to switched-capacitor implementation, continuous-time modulator also 
have lower power consumption. However, a switched-capacitor modulator is more 
robust to clock jitter and process variations. A continuous-time or preferably 
a hybrid implementation of the low-IF complex AE modulator may be a useful step. 



6.2 Suggestions for Future Work 169 

6.2.2 Frequency-Translating Complex AX Modulator 

A possible IF-to-baseband conversion architecture could incorporate a quadrature 
mixer inside the loop of the baseband modulator. The IF input signal is mixed with 
the LO frequency and translated to the baseband by the mixer in the forward path. 
The feedback signal is upconverted by a second mixer to match the downconverting 
mixer in the forward path. A main advantage of placing the mixer in the forward 
path is that its nonidealities are suppressed by the loopgain. The nonidealities of the 
mixer in the feedback path are not suppressed by the loopgain, but, by a careful 
selection of the LO frequency and the sampling frequency, the frequency 
upconversion in the feedback path can easily be performed in the digital domain 
with perfect linearity. 



6.2.3 Demodulator Architectures 

A next step would be to construct a complete system for demodulation of the digital 
TV signal. The high dynamic range, presence of interferers, and digital modulation 
may reveal further architecture requirements that are not understood yet. It would 
be of interest to include a channel mismatch cancellation strategy and to verify its 
feasibility for the low-IF complex AS modulator. 



Appendix A 

Modulator Design Example 



This appendix introduces the various functions and design procedures written in 
Matlab, Simulink, and Mathematica that were used in the designing of the complex 
AX ADC discussed in this book. 



Modulator Transfer-Function Design 

The AE modulator signal transfer function (STF) and noise transfer function (NTF) 
have been designed using complex filter routines based on classical filter design 
procedures. Once the transfer functions are determined, the modulator coefficients 
are solved by using the symbolic equation solving capabilities of Mathematica. 



B. Pandita, Over sampling AID Converters with Improved Signal Transfer Functions, 171 

Analog Circuits and Signal Processing, DOI 10.1007/978-1-4614-0275-6, 
© Springer Science+Business Media, LLC 2011 



172 Appendix A Modulator Design Example 

Determining Coefficients with Mathematica Figures A.1-A.5 



This section deals with initialization . 

In[221]:= OSR = 16; BW = 8 x 10 6 ; f = 4 . x 10 6 

1.0 

f s = OSR * BW ; a = 2 7r ; 

t. 



pi =E io.oxio'n 

p 2 ,E I (-'xi» 6 °) ; (* 7 MHz *) 
p 3 =E I ^* 10, 



(* 0.0 MHz *) 
(* 7 MHz *) 

(* 4 MHz *) 



{Pi/ P2 , P3 , P4} 

Out[227]= {l.+O.i, 0.941544 + 0.33689 i, 0.980785 + 0. 19509 i, 0.980785- 0.19509 i} 



ln[228]:= ntfpoles = Import ["ntfpoles . txt" , "Table"] 
ntfp! = ntfpoles [ [1, 1] ] +1 ntfpoles [[1, 2] ] 
ntfp 2 = ntfpoles [ [2 , 1] ] +1 ntfpoles [ [2 , 2] ] 
ntfp 3 = ntfpoles [ [3, 1] ] +1 ntfpoles [[3, 2]] 
ntfp 4 = ntfpoles [ [4, 1] ] +1 ntfpoles [[4, 2]] 
(ntfp 1 , ntfp 2 , ntfp 3 , ntfp 4 ) 

Out[233]= {0.830904-0.221809 1, 0.607757 + 0.5 93772 1, 
0.264252- 0.122771 1, 0.197154 + 0.21455 1} 



ln[234]:= stfzeros = Import [ "stf zeros . txt" , "Table"] 
stfZi = stfzeros [ [1, 1] ] +1 stfzeros [[1, 2] ] 
stf z 2 = stfzeros [ [2 , 1] ] +1 stfzeros [ [2 , 2] ] 
stfz 3 = stfzeros [ [3, 1] ] +1 stf zeros [ [3, 2] ] 
stfz 4 = stfzeros [ [4, 1] ] +1 stf zeros [ [4, 2] ] 
stfk = stfzeros [ [5, 1] ] + I stf zeros [ [5, 2] ] ; 
{stfz!, stf z 2 , stfz 3 , stf z 4 , stfk} 



Out[240]= 



{0.2024 + 0.9793 i, 
0.4313 - 0.9022 i, 



■0. 



9433 - 0.2943 i, 
1471 - 0.9891 i. 



.03 + 0. 1} 
Fig. A.l Mathematica code for initializing the coefficient determination for the STF and the NTF 



Appendix A Modulator Design Example 



173 



This section deals with the NTF derivation. 



In[241]:= Li 



Z - P2 Z - P3 Z - p 4 

1 



Z - P3 Z - p 4 



+ (B2+B3Z" 1 ) 



z -Pi) 



■Pi 



1 + C 2 Li 
H g6 „ = Factor [H g6n ] ; 
Hgen = Together [H gen ] ; 
Hden = Denominator [H gen l ; 
tl = CoefficientList[Hden, z] 



ln[247]:= NTF : 



((z-pi) (z-p 2 ) (z-p 3 ) (z-pa)) 



(z-ntfPi) (z-ntfp 2 ) (z-ntfp 3 ) (z-ntfp 4 ) 

Nden = Denominator [NTF] ; 

t2 = CoefficientList[Nden, z] 

Out[249]= {0.0382915 + 0.0488114 i, - . 361626 - . 299796 i, 
1.3448 + 0.694716 i, - 1 . 90007 - . 4 63742 i , 1} 

ln[250]:= sol = Solve [tl == t2 , {Bi, B 2 , B 3 , C 2 }] 

Out[250]= {{Bi -> 2.51467 - 0.66127 i, B 2 -> 8 . 89598 - 10 . 22 i, 

B 3 -> -3. 335 92 + 5. 4 6227i, C 2 ^0.104122 + 0. 1053 6i}} 

Fig. A.2 Mathematica code for determining the coefficients of the NTF 



7 71 37C 571 7C 37C 71 71 



71 71 371 71 571 371 771 




Radian Frequency 

Fig. A.3 Plot of the NTF in Mathematica 



174 Appendix A Modulator Design Example 

This section deals with the STF derivation. 

Ci Li 

ln[253]:= Si 



1 + C 2 L; 

(Fi 



Z-p 2 Z-p 3 Z-p 4 

s 2 = ,- 

1 + C 2 Li 
(P 2 ) — — 

z-Ps Z"P4 

5 3 = ; 

1 + C 2 Li 

(ft-- 1 ***) dpi 

5 4 = ; 

1 + C 2 Li 

Ggen = "1 ■*■ S2 + S3 + 04 ," 
Ggen = Factor [Ggea] -' 

Ggen = Together [G g6 „] ; 

Gnum = Numerator [Gg en l ; 

(z - stfzx) (z - stfz 2 ) (z - stfz 3 ) (z - stfz 4 ) 

STF = stfk ; 

(z-ntfpi) (z-ntfp 2 ) (z-ntfp 3 ) (z - ntfp 4 ) 

Snum = Numerator [STF] ; 

si = CoefficientList[Gnum, z] /. sol2 

s2 = CoefficientList[Snum, z] ; 

sol3 = Solve [si ^ s2, {Fi, F 2 , F 3 , F 4 , Ci)] ; 

sol4 = sol3[ [1] ] ; 

(*{Fi,F 2 ,F 3 ,F4,C 1 } = {F 1 ,F 2 ,F 3 ,F 4/ Ci}/.sol2*) 

coeffs = Union [sol2, sol4] ; 

Out[263]= {(-5.66 94 8 + 2.970141) d - (0. 857729 + 0. 5141031) F 3 , 

(19.6126-13.1427 1) Ci + (0.941544 + 0.336891) F 2 + (2.78006 + 1.046081) F 3 - 
(0. 857729 + 0. 5141031) F«, (-22. 3591 + 19. 71471) Ci- (1. +0. 1) F x - 
(1. 94154 + 0. 336891) F 2 - (2. 92233 + 0. 531981) F 3 + (2. 78006 + 1. 046081) F 4 , 

(8. 89598-10. 221) C, +1. F, +1. F ? + 1 . F 3 - (2. 92233 + 0. 531981) F 4 , 1. F 4 } 

Fig. A.4 Mathematica code for determining the coefficients of the STF 



Appendix A Modulator Design Example 



175 




Radian Frequency 

Fig. A.5 Plot of the STF in Mathematica 

Simulink Model of the Complex AX Modulator 

Figure A.6 presents the behavioral model of the fourth-order complex AS 
modulator developed in Simulink. The only difference between this modulator 
model and any other real AZ modulator model is that the model shown uses 
complex coefficients. The coefficients listed in Table A.l were used in model 
simulation. Simulink is used to implement the modulator architecture and model 
non-idealities like finite dc gain, finite bandwidth, opamp saturation, switched 
capacitor noise and other characteristics. The model presented in Fig. A. 7 differs 



176 



Appendix A Modulator Design Example 



r*Q 




w 



E 








Appendix A Modulator Design Example 177 

Table A.l Coefficient sizes 



Coefficient 


Value 


c, 


0.3426 


c 2 


0.18-/0.41 


A 2 


-0.28 + i0.73 


A 3 


0.27 


A 4 


1.5 


B, 


0.24 + i0.49 


B 2 


2.0 + ;3.93 


B 3 


-0.93-/1.88 


F, 


-0.24 - (0.65 


F 2 


-0.14-/0.24 


F 3 


-0.31-/0.67 


F 4 


0.02 



from the previous presented model by depicting the I and Q paths of the modulators. 
The model closely matches the way the modulator has been implemented in 
schematic. It is possible to introduce mismatches in the I and Q paths and assess 
the impact of mismatches on image rejection and SNDR. The code listing presented 
in Fig. A. 8 presents a possible way to introduce mismatches and perform a Monte 
Carlo simulation of the Simulink model. 



178 



Appendix A Modulator Design Example 




< S A cjy <°A d 



R 



Eo 



m 



< 

ft 





R 



o 



< 



o 



it 



X 









Appendix A Modulator Design Example 

Monte Carlo Simulation of the Simulink Model 



179 



%Code for MonteCarlo Simulation of the IQ Simulink Model 
%Number of coefficents =13 

Num_Coef f s=13 ; 

dev-5; %Ten Percent deviation 
CAPS_I=[]; CAPS_Q=[]; 
for 1-1:100 

sigmai = randn ( 1 , Num_Coef f s ) ; 

sigmai = (dev/100 / s td (sigmai ) ) 

s igmaq = randn ( 1 , Num_Coef f s ) ; 

sigmaq = (dev/100 / s td (s igmaq) ) 

CAPS_I = [CAPS_I (1 + sigmai) ' ] ; 

CAPS_Q = [CAPS_Q (1+sigmaq) ' ] ; 



(sigmai - mean { sigmai ) ) 
(sigmai - mean { sigmaq) ) 



end 

s av 

cl = 

fl = -0 

f3 = -0 

gl = 

a3 = 

bl = 

b3 = -0 

mcruns 

for i=l 

cap 

cap 



CAPSI_100 CAPS_I 
3426; 



.2438 
.3185 
.0256; 
.2778; 
. 2428 
. 9330 
= 10 0; 



. 6 5 7 4 i ; 
. 6 6 9 3 i ; 



. 4 9 9 i ; 
. 8 8 6 2 i ; 



c2 

f2 
f 4 
a2 
a4 

b2 



0.1856 - . 
-0.1440 - 
0.0233 + . 
-0 .2830 + 
1.5; 
2.0877 + 3 



410 
.24 
000 
.73 



935 
%Number of MonteCarl 



51; 

61i; 
0i; 
6 6i; 

£ i ; 

o runs 



: mcruns 

s_i=CAPS_I (1 :Num_Coef f s, i) 

s_q=CAPS_Q (1 :Num_Coef f s, i) 



cl_I = cl *caps_i ( 1 , 1 ) ; cl_Q = cl *caps_q ( 1 , 1 ) 

c2_I = c2 *caps_i ( 1 , 2 ) ; c2_Q = c2 * caps_q ( 1 , 2 ) 

fl_I = fl*caps_i (1,3) ; fl_Q = f l*caps_q ( 1 , 3 ) 

f2_I = f 2*caps_i (1, 4 ) ; f2_Q = f 2 * caps_q ( 1 , 4 ) 

f3_I = f 3*caps_i (1, 5) ; f3_Q = f 3 *caps_q ( 1 , 5 ) 

f4_I = f 4*caps_i (1 , 6) ; f4_Q = f 4 *caps_q ( 1 , 6 ) 

gl_I = gl *caps_i ( 1 , 7 ) ; gl_Q = gl *caps_q ( 1 , 7 ) 

a2_I = a2*caps_i (1, 8) ; a2_Q = a2 *caps_q ( 1 , 8 ) 

a3_I = a3*caps_i ( 1 , 9 } ; a3_Q = a3 *caps_q ( 1 , 9 ) 

a4_I = a4*caps_i (1, 10) ; a4_Q = a4 *caps_q ( 1 , 1 

bl_I = bl*caps_i (1, 11) ; bl_Q = bl *caps_q ( 1 , 1 1 

b2_I = b2*caps_i (1, 12) ; b2_Q = b2 *caps_q ( 1 , 12 

b3_I = b3*caps_i (1, 13) ; b3_Q = b3 *caps_q ( 1 , 13 



sim ( ' adc4th_IQ_' ) ; 

Vpsd = (V) ; 

nfft = Npts/2 ; %Number of FFT points 

window = hanning (nf f t ) ; 

overlap = l/2*nfft; 

signal = fin/fs * nfft + 1; 

cutoff = BW/fs * nfft + 1; 

[PSDw,f] = pwelch (Vpsd, window, over lap , ' twosided ' , nf f t , f s ) 

PSD = PSDw * norm (window) A 2 / sum (window) A 2 * fs/2 ; 

SNR_cal 

SNR_OUTPUT (i) = 10*logl0 (SNR_inband) ; 

IRR(i)= -10*logl0 (PSD (signal) /PSD (nfft-signal + 2)), ■ 
end 

save montecarlo_snr SNR_OUTPUT -append 
save mon tecar lo_i r r IRR -append 

Fig. A.8 Code for Monte Carlo simulation of the Simulink Model 



180 Appendix A Modulator Design Example 

SIMULINK Model for SC Integrators with Finite 
Opamp DC Gains 

The apy representation [1] can be used to model the impact of finite dc gain of the 
opamp on the transfer function of an ideal integrator. For an ideal delaying 
integrator the output vjn) in discrete time domain can be expressed by: 

v («) = -kv in (n - 1 ) + v (n - 1 ) (A. 1 ) 

where k is the gain of the integrator. Due to the finite dc gain of the opamp, the 
modified non-ideal transfer function for a delaying integrator can be expressed as: 

v {n) = -kmn{n - 1) + pv (n - 1) + yV os (A.2) 

The coefficient a modifies the gain of the non-ideal integrator, P shifts the pole 
of the integrator from the dc position, and y is the suppression of the offset voltage 
V os to the output of the integrator. With the help of aPy representation, the transfer 
function of a delaying SC integrator can be written as: 

^\ = ak- i — + y^-Vos (A3) 

v«(z) z-ji z-\i 

The (A.3) has been modelled in SIMULINK as shown in Fig. A.9 b. For the SC 
integrator shown in Fig. A.9 a the aPy parameters are given in Table A.2: 

The effect of the finite dc gain of the Opamp are included in the Simulink model 
of the SC integrators as shown in Fig. A. 10. 



Noise Analysis Using Mathematica 

The noise transfer functions from each noise source to output of the modulator were 
determined in Mathematica. The integration of each power transfer function from 
dc to the signal-band edge represents the gain of the noise source to the output of the 
modulator. Fig. A.l 1 lists part of the code used to determine noise at the output of 
the modulator. 



Appendix A Modulator Design Example 



181 



V in (z> 




Voutfz) 



b 

V in (z) 



"EHHZl — GE 



Pi 



Vout(z) 



Fig. A.9 (a) Basic delaying SC integrator, (b) model of the delaying integrator used in 
SIMULINK 



Table A.2 Expressions for the a(3y parameters for the 
delaying SC integrator shown in Fig. A.9 (a) for the integrator 
\k\ = Cs/Cf, and /i = l/A B , where A„ is the opamp dc gain 
a 

P 
Y 



i+(i+|*|)/. 
i+/. 

1*1/- 
i+(i+l*|)/. 




Fig. A.10 Model of the delaying integrator used in SIMULINK 



182 



Appendix A Modulator Design Example 



Noise due to Cx and C2 



ln[1960]:= 



ln[1961]: 



NTFn 



Ci Li 
1 + C 2 Li 



plot5 = LogLinearPlot[lO*Log[lO, Abs [NTF ±1 ] 2 1 , (f, 100, — ]• , 

L L J L 10SR J 

PlotStyle -» {Black, Thick}, Frame-* True, GridLines Hi Automatic, 
FrameLabel -» {"frequency (Hz)", "Integrated Noise Power (dBV)"} 



Out[1961]= ° 



-2.34 

3 2.36 
I 

Oh 

S - 2 ' 38 

s 

Z 

-o 

I -2.40 
5b 

-2.42 





















































































































































































































100 1000 io 4 10 5 10 6 10 7 

frequency (Hz) 

ln[1962]:= NIntegrate [2 / f s (Abs [NTFn] ) 2 , {f, 0.0, f s /OSR}] 
Out[1962]= 0.07211 

Re[C 2 ] I* 

In[1963]:= RE-NTF i2 = ; 

1 + C 2 Li 

NIntegrate[2/f s (Abs [RNTF i2 ] ) 2 , {f, 0.0, f s /OSR}] 

Out[1964]= 0.021163 



ln[1965]:= IM~NTF i2 



Im[C 2 ] Li 
1 + C 2 Li 



NIntegrate[2/f s (Abs [INTF i2 ] ) 2 , {f, 0.0, f s /OSR}] 
Out[1966]= 0.103525 
Fig. A.ll An example code for noise analysis of the model 



Appendix A Modulator Design Example 183 

Reference 



1. W.-H. Ki, G.C. Temes, "Low-phase-error offset-compensated switched-capacitor integrator," 
Electronics Letters, Volume 26, Issue 13,21 June 1990, pp. 957-959 



Index 



B 

Bandpass signals, 12 
Bias stage, 129-132, 136 
Bilinear transform, 39, 40, 80 



C 

Capacitor 

mismatch, 8, 52, 104, 107-109, 141 
sizing, 53, 71, 80, 105, 107-117, 120, 
163, 168 
Chebyshev polynomial, 40 
Clock 

generator, 8, 107, 127-128, 139-140, 

150, 156, 157 
jitter, 117-119, 168 
Comparator, 51, 125-127, 134, 137-139, 

142, 143, 157 
Complex 

AX ADC, 3, 8, 11-32, 167 

filters, 11, 13-15, 17, 18, 26, 30, 35, 60-62, 

80, 82-83, 87-89, 97, 157, 167 
integrators, 87, 101-103, 109, 119 
pole realization, 87 
signals, 12-13, 17, 35, 36, 85, 88, 102, 

103, 110 
transfer function, 14, 17-18, 35, 60, 62 



Discrete-time receiver, 70, 73-79 
Distributed feedback AX modulator, 24—26 
Distributed feedforward AX modulator, 

23-25, 49 
Double-conversion receiver, 4—6 
Double conversion zero second-IF (DZIF) 

receivers, 6 
Dual-conversion receivers, 1 1 
Dynamic range scaling, 52, 53, 71, 73, 82, 87, 101 



E 

Equiripple 

passband filter, 45^16 
response, 17, 39, 46 



Feldtkeller's 

equation, 37, 40, 45, 46 
Filtering interfering signals, 21-28 
Frequency-translating complex AX 
modulator, 169 



G 

Gain-boosting amplifier, 132 



D 

DCR. See Direct conversion receiver 

Decimation, 76, 82-85 

Determining coefficients with Mathematica, 

158 
Digital TV (DTV) receiver, 3-7, 1 1-32, 60, 73, 

74, 84, 167 
Direct conversion receiver (DCR), 1, 2, 5 



H 

Heterodyne architectures, 1 



I 

Image 

frequencies, 2, 15, 17, 19, 30, 32, 60, 70, 85, 
87, 88, 92, 94, 97, 105, 152, 158 



185 



186 



Index 



Image (cont.) 

rejection, 4-7, 11, 15, 17-19, 30-32, 85, 

87, 88, 90, 92, 96-99, 148, 152-155, 

167-168 
transfer function, 87 
"Image-band" problem, 2, 11, 15 
Image noise transfer function (INTF), 31-32, 

90-92, 94, 96, 97, 100 
Image signal transfer function (ISTF), 31-32, 

90-92, 94, 96, 98, 100 
Input-feedforward architecture, 51 
Interfering-signals problem, 7, 11, 20-21 
Intermodulation due to DAC non-linearity, 

53-56, 72-73 
INTF. See Image noise transfer function 
ISTF. See Image signal transfer function 



ILIi Norm and its impact on the NTF poles, 

42^14 
NTF. See Noise transfer function 
NTF-STF 

co-design, 3, 7, 26, 46^19, 51, 56, 60-67 

design trade-off, 37^12 



O 

Opamp nonidealities, 119-122, 163 
Operational amplifier, 2, 15, 20, 129-134 



Passband ripple factor, 38 

Polyphase filter, 13, 148-149, 152-153, 155 



Loss function L(Z), AA-A6 
Loss poles, 39 
Low-IF 

complex AX modulator, 3, 7, 11-32, 78, 
167-169 

direct conversion receivers (DCR), 2 
Low-pass to low-pass transformation, 40 



M 

Maximally flat passband, 39, 45, 46 
Mismatches in a complex AX modulator, 

31-32, 87, 89-100 
Mismatch in complex filters, 14—15 
AX Modulator 

transfer functions, 35-37, 46, 168 
with unity STF, 55, 68-70, 72, 77, 83 
Multibit quantization, 8, 53, 101-104 
Multilevel DAC, 8, 101, 104, 105, 108 



N 

Natural modes, 39 

Noise analysis, 109-117, 168 

Noise transfer function (NTF), 3, 7-8, 23-26, 
31-32, 35^4, 46-52, 56, 60-68, 80-82, 
89-92, 94, 96-98, 100, 105, 108, 
112-114, 158, 159, 167, 168 

Nondelaying complex integrator, 87, 101-103, 
109,110,119 

I/YI8 Norm, 43 

ILI 2 Norm, 43 



Q 

Quadrature mixing, 1, 6-7, 85, 169 
Quantizer, 8, 20, 23, 30-32, 36, 43, 51, 53, 
55-57, 61, 68-70, 83, 84, 101, 104, 
105, 107, 125-127, 134-139, 141, 
142, 144, 146, 167, 168 



R 

Real mixing vs. complex mixing, 15-17 

Real-valued signals, 12 

Reflection zeros, 39 

ot(3y Representation, 51, 73, 119 

Resistor ladder, 134, 137, 139, 140, 144-145 



SC CMFB circuit, 133-134 

Sensitivity to intermodulation due to DAC 

non-linearity, 53-56, 72-73 
Signal transfer function (STF), 3, 7, 8, 11, 

23-28, 31-32, 35-85, 90, 92, 94-96, 

100, 108, 110, 152, 153, 156, 157, 

161-164, 167, 168 
Single-conversion receiver, 4, 5, 7 
Single sideband (SSB), 3, 13, 35, 60 
Superheterodyne receiver, 2 
Switched-capacitor filter, 76, 80-82 
Switch on-resistances, 122 



Zero-IF DCR, 2