AD 69 4638 DIGITAL COMPUTER - NEWSLETTER Mlt mm letter' “ ' aMlaa Hr \m £r taUristtf MOWMIIm m*- I Imrt r.. lee It 'in*.' teotrlwtera. ' Off ICS OF NAVAL RSSCAZ CH Vol. 14, No. 3 THathsmatical SCISHCSS DIVlJIW Gordon D. Goldstein, Editor D D Oil y 1962 CONTENTS fT^rpnn nrpr EDITORIAL NOTICES I ni OCT 1 6 196-9 - H Editorial Policy I I D 5: SS^:„ c pSrcr ion * ; UUlblifiLLjOUTb COMPUTERS A ND DATA PROCESSORS, NORTH AMERICA O 1. Advanced Scientific Instruments, Inc T,“ADVANCE II, AS1-420 and ASI-210, ^ Minneapolis 22, Minnesota 2. Bend be Computer Division, Multiple-Processor G-21, Los Angeles, California 3. Control Data Corporation, Control Data 3600, Minneapolis 20, Minnesota 4. Control Data Corporation, Control Data 6600, Minneapolis 20, Minnesota 5. Electronic Associates, Inc. HYDAC SERIES 2000-Hybrid Digital/Analog Computer, Long Branch, New Jersey 6. International Business Machines Corporation, IBM 7094, White Plains, New York 7. Scientific Data Systems, 900 Series Computers, Santa Monica, California 6. U.S. Army Ballistic Research Laboratories, Computing Laboratory, BRLESC, Aberdeen Proving Ground, Maryland ?. National Bureau of Standards, Recording Physiological Measurements for Data Processing, Washington 25, D. C. 2. Ordnance Tank Automotive Command, New Computing Systems, Detroit 9, Michigan 3. U.S. Naval Ordnance Laboratory, Mathematics Department, White Oak, Silver Spring, Maryland 4 . U.S. Naval Underwater Ordnance Station, Analysis Branch, Newport, Rhode Island 5. U.S. Naval Weapons Laboratory, Computation Center, Dahlgren, Virginia 6. U.S. Navy David Taylor Model Basin, Flame Program, Washington 25, D. C. 7. U.S. Navy David Taylor Model Basin, Performance Data for LARC System, Washington 25, D. C. COMPUTERS AND CENTERS. OVERSEAS H Inatitut Fflir Angewandte Mathematik, Johannes Gutenberg-Uuiversitat, Siemens 2002, Mains, Germany 2. Leo Computers, Ltd., LEO HI Time-Sharing, London, England 3. Leo Computers, Ltd., LEO HI/F, London, England 4. Leo Computers, Ltd., LEO Document Reader, London, England 5. National Physical Laboratory, Autonomies Division, An Artificial Language for Information Retrieval, Teddington, Middlesex, England MISCELLANEOUS 1. Cornell Aeronautical Laboratory, Inc., Multi-Font Character Recognition, Buffalo, New York 2. A.B. Dick Company, High*Speed Videograph Printer-Plotter, Chicago 48, Illinois 3. Honeywell EDP Division, Auto-Corrective Optical Scanner, Wellesley Hille, 81, Massachusetts 4. Memistor Corporation, The M-2CR Memistor, Mountain View, California 5. The National Cash Register Co,, Photochromic Dynamic Display, Hawthorne, California 6. Penn State and IBM, Home-Study Course in Computer Programming, University Park, Pennsylvania 7. Symposium on Optical Character Recognition, 15-17 January 1962, Washington, D« C. 8. University of Illinois, PLATO 11, Urbana, Illinois 9. U.S. Army Ballistic Research Laboratories, Computing Laboratory, The Computer Tree, Aberdeen Proving Ground, Maryland Approved by The Under Secretary of the Navy 25 September 1961 Kuproduccd bv llio CLEARINGHOUSE lor Eodur.il Scionlilic & Tuchmc.il Informotion Springfield Vn. 22151 NAVEXOS P-645 ' o&cujtfiiat ikai approved" ktr pu.b4te roWtre und sale; it» d«’*rj*v,,fr> u in nniiinitod EDITORIAL NOTICtS EDITORIAL POLICY The Digital Computer Newsletter, although a Department of the Navy publication, is not restricted to the publication ol Navy-originated material. The Office of Naval Research wel¬ comes contributions to the Newsletter from any source. The Newsletter Is subjected to certain limitations in size which prevent pub¬ lishing all the material received. However, Items which are not printed are kept on file and are made available to Interested personnel within the Government. DON is published quarterly (January, April, July, and October). Material for specific Issues must be received by the editor at least one month in advance. It Is to be noted that the publication of in¬ formation pertaining to commercial products does not, In any way, Imply Navy approval of those products, nor does It mean that Navy vouches for the accuracy of the statements made by the various contributors. The Infor¬ mation contained herein is to he considered only as being representative of the state-of- the-art and not as the sole product or technique available. POLICY FOR CONTRIBUTIONS The Office of Naval Research welcomes contributions to the Newsletter from any source. Your contributions will provide assistance in Improving the contents of the publication, there¬ by making It an even better medium for the ex¬ change of Information between government laboratories, academic Institutions, and In¬ dustry. It Is hoped that the readers will partic¬ ipate to an even greater extent than In the past In transmitting technical material and suggestions to the editor for future Issues. Ma¬ terial for specific Issues must be received by the editor at least one month In advance. It la often impossible lor the editor, because of limited time and personnel, to acknowledge individually all material received. CIRCULATION POLICY The Newsletter iB distributed, without charge, to Interested military and government agencies, to contractors lor the Federal Gov¬ ernment, and to contributors of material for publication. For many years, in addition to the ONR Initial distribution, the Newsletter was re¬ printed by the Association for Computing Ma¬ chinery as a supplement to their Journal and, more recently, as a supplement to their Commup itlons. The Association decided that their Communications could better serve its members by concentrating on ACM editorial material. Accordingly, effective with the combined January-April 1961 Issue, the Newsletter became available only by direct distribution from the Office of Naval Research, Requests to receive the Newsletter regu¬ larly should be submitted to the editor. Con¬ tractors of the Federal Government should ref¬ erence applicable contracts in their requests. All communications pertaining to the News¬ letter should be addressed to: GORDON D. GOLDSTEIN, Editor Digital Computer Newsletter Informations Systems Branch Office of Naval Research Washington 25, D. C. COMPUTERS AND DATA PROCESSORS, NORTH AMERICA ADVANCE II, ASI-420 AND ASI-210- ADVANCED SCIENTIFIC INSTRUMENTS, INC., MINNEAPOLIS 22, MINNESOTA Advanced Scientific Instruments, Inc., has designed three computers which cover the field in computing and data processing capability. They are, in order of decreasing size, the ADVANCE II, the ASI-420, and the ASI-210 All three machines are high speed, paral¬ lel, Internally programmed, solid-state 1 computers with random access core memnria* having a tuiai cycle time of 2 microseconds, Including addressing of the next word. All of the computers have extensive input-output buffer- ins facilities which make them adaptable to real¬ time applications, and which permit the integra¬ tion of large quantities of peripheral equipment. To date ASI has delivered one 210 to God¬ dard Space Flight Center, one 210W (a modified 210) to Argonno National Laboratory, and haa announced the sale of another to Chance Vought Corporation. The 210 system sold to Chance Vought car¬ ries a price tag of $113,000. The medium scale ASI-420 sells for $324,000, and the larger scale ADVANCE n for $860,000. Programming The instructions used in all ASI computers are divided into two classes, termed cIosb A and class B. Class A Instructions are used universally in all three machines, and programs prepared with class A instructions can be exe¬ cuted on any ASI machine. Claes B instructions are used only with the larger ASI-420 and ADVANCE II computers; programs prepared with the class B instructions can be executed without modification only on the larger machines. Input-Output The input-output system of the ADVANCE II computer consists of several input-output assembly registers and an independent control system. Information can be exchanged between the computer and external devices completely Independently of arithmetic operations, and the input-output system can provide off-line com¬ munications between items of peripheral equip¬ ment. The total information transfer rate of the ADVANCE n input-output system is 250,000 words per second. Additionally, the ADVANCE n has a direct, high speed Input-output channel •capable of 500,000 42-bit word transfers per second. The ASI-420 and ASI-210 computers also use input-output assembly registers for external communication, but these are controlled by the central control system. The transfer of a block of Information is initiated with a single instruc¬ tion. Thereafter, each assembly register is serviced by the memory during specific times set aside for this purpose in all instructions, and the program is not further affected by the transfer. In other words, the memory is time shared by the arunmetic and input-output sections of the computer. Either fixed or variable block transfers are made possible by two memory address registers associated with each assembly regis¬ ter. One ot these registers contain! the addreee of the first word of the block, and the other con¬ tains the address of the last word of the block. With the transfer of each word, the first regis¬ ter is incremented. When the contents of the registers Are Identical, the block has been transferred and input-output operation ceases. The size block can be varied simply by the addresses entered originally into the address registers. Advance n The ADVANCE II computer Is a 42-blt machine with a memory expandable to 32,768 words. The computer has an optional maximum of eight buffered input-output channels with a combined transfer rate of 250,000 words per second. Arithmetic speeds of the computer are: Operation Speed (psec) add 6 multiply 33 divide 33 The speed of the machine is enhanced by an instruction look-ahead feature in which the next Instruction of a program is extracted from the memory, and Indexing of the operand Is per¬ formed while the current instruction is being executed. This operation is performed simul¬ taneously with arithmetic operations because the memory address register is not used In arithmetic functions, and the indexing addition is performed in an independent 15-blt adder. When the current instruction is completed, the next instruction is Immediately ready. An 84-blt, 512-word magnetic core memory stores micro-program commands from which the instructions of the computer are constructed. The operation code of an instruction is trans¬ lated to the address of the first command In the micro-program memory. Thereafter, the memory is stepped through successive memory locations, and the resultant commands complete the Instruction. Any command or sequence of commands can be repeated under control of a repeat counter. The micro-program memory can be filled or replaced from either the main memory or liie paper laps rentier ox iiiu computer, instruc¬ tion substitutions can be made easily, and unique Instructions for specific applications can be formulated from the available micro-commands. This feature provides the ADVANCE II with exceptional flexibility. One of the most powerful features of the ADVANCE n Is its ability to communicate with other ASI computers In multi-computer com¬ plexes. Such communication can be effected both through the real-time, high-speed, Input- output channels and through the buffered chan¬ nels. Each computer regards the other merely as external devices, and through the facilities of the trapped Interrupt, can be alternately Iso¬ lated from the other computers or enabled to participate, all under program control. In this way, “executive privilege" for one computer is not necessary, and independent computer pro¬ grams can be “merged" effectively. Inter¬ computer communication Is made possible sim¬ ply by wiring, and no auxiliary electronics Is required. ASI-420 The ASI-420 Is a 42-bit machine with a memory expandable to 18,384 words. The com¬ puter has an optional maximum of six Input- output buffer channels with a combined transfer rate of 125,000 words per second. Arithmetic speeds of the machine are: Operation Speed (psec) add 10 multiply 64 divide 96 The speed of the ASI-420 is less than that of the ADVANCE II because of the time allowed in each instruction to service the Input-output buf¬ fer registers. This time is allowed whether or not Input-output data Is transferred, and remains the same regardless of the number of channels used. Therefore, the transfer rate of 125,000 words per second is constant for machines with any number of buffer channels. ASI-210 the Asi-aiO is a general purpose, nign speed, solid-state digital computer of small size. It is well suited to applications In scien¬ tific and engineering computations, data reduc¬ tion, and real-time process control. The ASI-210 has the following outstanding features: 1. Stored program, parallel operation, solid-state circuits, 21-bit word length, and magnetic core memory expandable to 8192 words. 2. Buffered Input-output channels with total transfer rate of 62,500 21-bit words per second. Number of buffered channels is one, with one additional channel optional. Buffers can be uBed in an effective manner off-line for conversion operations. 3. Multiple indexing using Index words stored In the computer memory. 4. Indirect addressing. Successive Indirect addressing is possible with Indexing at each step, 5. Trapped interrupt. Logic circuits, which sense Interrupt eventB, can be armed or disarmed under program control to Jump the program into corresponding sub-routines upon occurrence of the event. The trapped interrupt feature saves a great deal of time and memory In programs because the Interrupt conditions do not have to be tested repeatedly. It Is also useful in cases where two or more computers are used together In the same system, or where a computer converses with several Items of peripheral equipment. 6. One-megacycle phase rate operation. Add time 10 microseconds; multiply time 54 microseconds, Including Indexing and memory access time. 7. Six sense switches. Program branch¬ ing may be controlled by sense switches on the operators console, 8. No air conditioning Is required. High reliability operation in extreme temperature and humidity conditions. Equipment is designed to operate in ambient 32* to 125"F at B5 percent relative humidity. 3 Number Format BBBBBBBBBBBBBBBBBBBBB sign bit 21 Magnitude bits 20-1 B represents 1 binary digit. INSTRUCTION FORMAT Instruction Word BBBBBBBBBBBBBBDBBBBBB ^ ^ y I f_I__ r\ ___1_IJ_ Operation code bits 21-17 Index address Operand address bits 15-14 bits 13-1 Indirect address bit 16 Index Word ^bbbbbbb^^bbbbbbbbbbb^ fottnro hit u Inrtov ha no' Ignore bits 21-14 Index base' bits 13-1 B represents 1 binary digit. Instruction List Notation A Register A is the accumulator E Register E is a second major arithmetic register () Contents of, for example, (A) signi¬ fies the contents of the A register + Add Subtract . Multiply =• Divide - » “Is placed in* I | Absolute value, for example. (A) i signifies the absolute value of the ! ! contents of the A register - Complement of, for example, (K) signifies the complement of the contents of the A register @ Logical OR, for example, (E) @ (m) signifies the logical OR of the complement of the contents of the E register and the operand 0 Logical AND, for example, (E) Q (m) signifies the logical AND of the contents of the E register and Uv; operand a Register A designator in the operand address e Register E designator in the operand address s Shift right designator c Shift circular designator g Gray to binary shift Indicator k Shift count l h Index base p Effective operand address m The memory location specified by p 1 Address of present Instruction . (m) Operand Unless otherwise Indicated, the operand address Is subject to indexing and indirect address. Arithmetic The adder used In the ASI-210 Is a closed loop binary adder using left end-around carry operation in the one’s complement addition. The sign bit (21) is a zero (0) for positive num¬ bers and a one (1) for negative numbers. This is useful In most operations using the entire register A. However, In certain instances such as indexing, only a small portion of the adder Is used and provisions to prevent end-around carry are made. Operation is then carried out 4 In the two's complement addition which gives the correct answer without carry. A comparison of the two systems is shown: Decimal Binary i’s Comp. 2’s Comp. r>3 on 4-3 +3 2 010 4-2 4-2 1 001 +1 + 1 0 000 +0 +0 7 111 -o* -1 6 110 -1 -2 5 101 -2 -3 _4 100 -3 -4 -0 is meaningless. All carries arc forcibly entered in adder so that the number becomes 000 or 4-0, ASI-210 Instruction Chart Octal Code Instruction Including Index & I/O Time (nsec) Not Including Index & I/O Time (paec) HALT 8 JUMP 8 4 sKISii RETURN 12 8 06 END INTERRUPT 8 4 10 ADD 10 6 12 SUBTRACT 10 6 14 LOAD A 10 6 16 LOAD E 12 8 20 ABSOLUTE VALUE 8 4 22 NEGATE 8 4 24 CLEAR 12 8 28 STORE A 8 6 30 MULTIPLY 54 50 32 DIVIDE 56 52 34 ROUND 14 10 36 STORE A ADDRESS 10 6 40 COMPARE<A 14 10 42 COMPARE * A 14 10 44 TEST A < 0 10 6 48 STORE E 10 6 50 AUGMENT INDEX 12 12 52 TEST INDEX 10 10 54 STORE ADDRESS 12 12 66 LOGICAL OR 12 10 60 SHIFT 104-2K 6+2K 62 NORMALIZE A 14+2K 10+ 2K 64 NORMALIZE A,E 14+2K 10+2K 66 LOGICAL AND 12 10 70 TRAP 8 4 72 SENSE SWITCH 10 6 74 EXTERNAL DEVICE 16 12 76 ASSEMBLY REGISTER 20 16 Explanation of Instructions 111 A DU (A) + (m) —* A Add the operand to (A). The sum will appear in Register A. This instruction can result in an add overflow. 12 SUBTRACT (A)-(m)-»A Subtract the operand from the contents ol A. The difference will appear in Register A. This instruc¬ tion can result in an add overflow. 30 MULTIPLY (A) • (ro>—*AE Multiply the contents of A by the operand. The most significant bits of the product will appear in Register A and the least significant bits in Register E. 32 DIVIDE (AE) t (m)—* E rem-*A Divide the contents of A and E by the operand. The quotient will appear in Register E and the remainder in Register A. A fault interrupt may occur if the contents of A is greater than or equal to the operand. 24 CLEAR 0—>A, or 0—>E, or 0—*AE Clear A If the a designator bit 12 of the operand address is a 1. Clear E if the e designator bit 11 of the operand address is a 1. Clear A and E If the a and e designator bits 12, 11 of the operand address are l's. 22 NEGATE (A) —>A, or (E)—>E, or (AE)—> AE Complement the contents of Register A if the a designator bit 12 of the operand address is a 1. Complement the contents of Register E If the e designator bit 11 of the operand address is a 1. Complement the contents of Register A and E if the a and e designator bits 12, 11 of the operand address are l’s. 20 ABSOLUTE VALUE |(A)|-*A, or |(E)|—>E, or |(AE)| —»AE Make the contents of A positive If the a designator bit 12 of the operand address is a 1. Make the contents of E positive if the e designator bit 11 of the operand address is a 1. Make the contents of A and E positive if the a and e designator bits 12, 11 of the operand address are l’s. 34 ROUND (E20) + (A)—*A Add the most significant bit of Register E to the contents of A In the least significant bit. The result will appear In Register A. Register E will be unchanged, 36 STORE A ADDRESS (Ajg.j)—? Stores operand address portion of (A) in the operand address portion of the operand (m). Transfer 14 LOAD A (m)—*A Bring the operand to Register A. 16 LOAD E (m)—»E 6 Bring the operand to Register E, 28 STORE A (A)—»m Store the contents of A in the memory location specified by the operand address. 48 STORE E (E)—>m Store the contents of E in the memory location specified by the operand address. 60 SHIFT Bit Designator SHIFT (A) RIGHT SHIFT (A) LEFT SHIFT (A) LEFT CIRCULAR SHIFT (E) RIGHT SHIFT (E) LEFT SHIFT (E) LEFT CIRCULAR SHIFT (AE) RIGHT SHIFT (AE) LEFT SHIFT (AE, LEFT CIRCULAR CONVERT (E) FROM GRAY CODE TO BINARY LEAVING THE RESULT IN A See “INSTRUCTION LIST, Notation’ for definition of designators a through k. Right shifts arc open-ended shifts. Left shift may be either open-ended or circular shlftB. In open- ended shifts, the bits introduced into the register are identical to the sign bit 21 which remains unchanged. In circular shifts, the sign bit 21 is shifted along with the number. The number of shifts, specified by the shift count (k), cannot exceed 63 decimal (2 s -1). 62 NORMALIZE A (A) • 2 k until A20 t A2I, and, k + (m)—am Shift the contents of A left, leaving the sign bit 21 unchanged, Until the sign bit 21 and the most sig¬ nificant bit 20 are different. With each shift, the sign bit will be entered in the least significant bit 1 of A and the most significant bit 20 of A will be lost. Add the number of shifts required to the operand address portion of the operand specified by the operand address. 64 NORMALIZE A AND E (AE) • 2 k unlll A20 * A21, and, k + (m)— Shift the contents ol A and E left, leaving the sign bit 21 unchanged, until the sign bit 21 and the most significant bit 20 of A are different. With each shift, the sign bit 21 ol' E will be entered In the least significant bit 1 of E, and the most significant bit 20 of E will be entered into the least significant bit 1 of A. The most significant bit 20 of A will be lost. Add the number of shifts required to the operand address portion of the operand specified by the operand address. 66 LOGICAL AND (E)©(m)—»A Form the logical “and" of the operand and the contents of E in Register A. An example of the blt- for-btt result is as follows: i2 11 10 9 8 7-1 Contents of E 1100 Operand 1010 Logical and 1000 7 58 LOGICAL OR (E) © (m) —*A. Form the logical “or* of the operand and the contents of E In Register A. An example of the blt-for- blt result Is as follows: Contents of E 1100 Operand 1010 Logical or ITl5 50 AUGMENT INDEX p + lfc,—»lb Add the specified operand address to the Index base, and replace the Index base with the sum. This Instruction can result In an Index overflow. The addition will be In the two’s complement system. This Instruction permits decrementing as well as Incrementing. 52 SKIP IF INDEX HIGH The specified operand address of this Instruction is the complement of the index limit addresB. This limit address is in one’s complement If the limit 1 b positive, and in two’s complement if the limit is negative. When the Index base (contents of the index register in two’s complement format) exceeds the limit address, the next Instruction in sequence will be skipped. . .otherwise the instructions will continue In sequence. The skip will occur when the addition of the 13-hlt limit address with the 13-bit Index base causes a carry into the 14th bit position. Examples If the lndox base exceeds four and It is desired to skip, the index limit address will be: 1111111111011 (Binary - one’s complement) 14th 14th BU Bit Index Base X0000000000100 X0000000000101 Index Limit X 1 1 1 1 1 1 1 1 1 1 0 1 1 X 1 1 1 1 1 1 1 1 1 1 O 1 1 Sum X 1 1 1 1 1 1 1 1 1 1 1 1 1 10000000000000 No akip occurs when Skip occurs when index base = 4 index base = 5 If the Index base exceeds -4 and It is desired to skip, the index limit address will be: 000000000001 1 (Binary - two’s complement) 14th 14th Bit Bit Index Dase X"i 1 1 1 1 1 1 1 1 1 1 0 0 X 1 1 1 1 1 1 1 1 1 1 1 0 1 Index Limit X0 000000000011 X000000000001 1 Sum X 1 1 1 1 1 1 1 1 1 1 1 1 1 10000000000000 No skip occurs Skip occurs when when lndox base = -4 index base = -3 (in two’s complement) (in two’s complement) (l.e., If the limit desired is a nogativo number, the rule is tho following: lllmltl -1 = index limit address) 8 04 BFTflOM I j. S-*.-< --- " ' 1 thru 13 Store the address of the instructturi following the next sequential Instruction In the operand address of the operand. By letting the operand be a jump Instruction at the end of a sub-routine, the program can jump into the subroutine on the next instruction and return to its program se¬ quence at the end of the sub-routino. 02 JUMP Talte (m) as the next Instruction, 00 HALT Halt, and take (m) as the next Instruction when operation Is resumed, 40 COMPARE<A (m) < (A), skip and take 1 + 2 (m) > (A), take 1 + 1 If the operand Is less than the contents of A, skip the next Instruction of the sequence. 42 COMPARE » A (m) « (A), skip and take 1 + 2 (m) / (A), take 1 + 1 If the operand equals the contents of A, skip the next Instruction of the sequence. 44 TEST A < 0 If (A) are less than 0, take next Instruction from operand. 54 STORE ADDRESS IN INDEX p—!»I b Store the operand address In the base address portion ol the memory location specified by the Index address. The operand address will not be Indexed. 00 ENDINTERRRUPT Take (m) us the next Instruction, then discon¬ tinue the Interrupt. This instruction must be used at the end of an Interrupt routine. 70 TRAP if bit 12 of the operand address Is a “l," the contents of the trap flip-flops will bo stored In operand address portion ol register A In the bit positions specified helow. If bit 11 Is a “1,* the specified traps will be armed. If bit 10 Is a “1,” the specified traps will be disarmed. If bit 13 Is a “1," the contents of the Add ovorflow and Index overflew fllp-fiu|/i, may be aiurati in ine bits of A corresponding to their trap designators. These two flip-flops will be reset by recogni¬ tion of interrupt or by storage In A sc described. Bit specification of the operand address of the Set Trap instruction: 13 Store flip-flop designator 12 Store trap designator 11 Arm trap designator 10 Disarm trap designator 1 External device Interrupt trap 2 Busy Interrupt trap 3 Operator Interrupt trap 4 Fault interrupt trap 5 Add overflow Interrupt trap 7 Index overflow Interrupt trap 3 Operator control light 1 0 Operator control light 2 74 EXTERNAL DEVICE Interpret the operand as an external dovloo con¬ trol word (EDCW). A buoy Interrupt could re¬ sult from this instruction. The external device control word (s described In detail under external device Instruction. 72 SENSE SWITCH If any of the sonso switches 1-0 specified In the operand address bits 1-6 is set, skip the next Instruction In the normal sequence, if the next Instruction is a Jump Instruction, this Is in effect a programmed Jump that Is conditional upon the sense switches. These swltchus may be changed at any time by the oporator. If more than one sense switch Is speckled, the skip will occur If any of tho specified switches Is set. 78 ASSEMBLY REGISTER Interpret the operand as an assembly register control word (ARCW). A busy interrupt can result from this Instruction, The assembly register control 'vord Is described In detail under assembly register Instruction. Trapped Interrupt A number of events can cause the program of the computer to be Interrupted. Some of these are: Busy Oporator Add Overffow Extornal device Fault Index overflow An Interrupt trap associated with each event may be set under program control to either respond when the event occurs or to ignore it. The traps are controlled by the “trap" Instruction. Bits 11 and 10 in the operand address designate whether the specified traps will be armed or disarmed, and bits 9 through 1 oi the operand address specify which traps (or indicator flip- flops) are to be armed (set) or disarmed (cleared). If bit 12 of the operand address is present the condition of each of the traps will be stored in the operand address portion of regis¬ ter A In the bit position that corresponds to the designating bit for that particular trap in the “trap* Instruction. This will occur before any changes are made In these conditions as a result of bit 11 or 10 occurring in the same “trap* In¬ struction. This is very useful in sub-routines that require the use of these traps, but that also must return these traps to their previous condition at the end of the sub-routine. By specifying bit 13 In the trap instruction, ti:c contents of the Add overflow and Index overflow flip-flops may be stored in the bits of A corresponding to their trap designators. These three flip-flops will be reset by recognition of interrupt or by storage in A as described. If a particular trap is set to respond to the occurrence of an event, an interrupt is initiated when the event occurs (and the interrupt routine flip-flop is set). As a result of this interrupt, the current instruction will be completed and the address of the following Instruction will be stored in the Interrupt fixed address (00110). Then control is transferred to a unique fixed address (identified below) associated vth the particular event or condition which c- sed the Interrupt. The contents of the unique fixed address will usually be a jump instruction lead¬ ing to a sub-routine. Thus, the programmer may have a different sub-routine for each event that may cause an interrupt, l'he sub-routines will be entered without the necessity of the programmer writing a decoding program to find which sub-routine to enter since the occur¬ rence of a particular interrupt causes a jump to a particular sub-routine. At the end of each sub- routine is a jump to the interrupt fixed address (00110). In the interrupt fixed address is an “end interrupt* instruction which is identi¬ cal to a jump instruction except that it clears the interrupt routine flip-flop. The “end Interrupt* instruction will cause a return to the main program at the point where it was inter¬ rupted. Only a priority external device may interrupt an “interrupt sub-routine." When automatic interrupts are not available, the pro - grammer must write a scanning program that repeatedly checks certain conditions to see whether the mam program should be interrupted. The ability to uBe the trapped interrupt feature to handle such conditions as arithmetic overflow gives the programmer the opportunity to make any necessary corrections and reenter the main program to continue the calculations. By being able to selectively arm and disarm traps, the programmer has complete program control over either initiating an interrupt when a particular condition occurs or ignoring its occurrence. The following is a description of the inter¬ rupt conditions: BUSY interrupt will occur if an external device Is instructed to do something which it cannot do because either the device or its assembly register is busy. This Interrupt may also occur if an “assembly register* Instruction addresses a busy channel. External Device Interrupt External device interrupt will occur when an ED sends a signal to the central computer that it desires to transmit information. External device interrupt addresses are assigned octal numbers from 00000-00077. These numbers are scanned through periodically to see if an ED requests Interrupt. The normal ED r s are assigned Interrupt addresses at the low end of the memory (i.e., 00,02,04,06, ...) correspond¬ ing to the ED addresses. When an ED requests interrupt, the ED Interrupt flip-flop is set, the current instruction is completed and the address of the next instruction.is stored in a fixed loca¬ tion 00110. Tht n contiol is transferred (jumped) to the interrupt address corresponding to the ED address which requested the inter¬ rupt. An “end interrupt* instruction, which is identical to a jump instruction except that It clears the interrupt sub-routine flip-flop, may be inserted in the interrupt fixed address. Cer¬ tain ED are assigned priority interrupt addresses in a block at the higher end of the memory (i.e., .,66,68,70,72,74,76). The lowest num¬ ber in the block has the highest priority. Only these priority Interrupt devices can interrupt a “normal interrupt sub-routine.* If a priority ED requests ii.errupt, the scanner jumps to toe priority block and scans through for the highest priority ED requesting interrupt. A second flip-flop is set, the next instruction is stored in fixed location 00114 and control is transferred to priority ED. When the priority interrupt sub-routine is completed and an “end interrupt” jump is executed, the priority interrupt flip- flop alone is reset. The normal interrupt 10 flip-flop is maintained In Its set condition. After the interrupt is recognized, the scanner will look for any other priority interrupt. If none is requested, control may be transferred to the original interrupt sub-routine. After this sub-routine is completed and an “end inter¬ rupt” Jump is executed, the first flip-flop is reset and control may be transferred to the main program. External devices in which a failure is ol critical interest to the running program are assigned a second number (normally the odd address following the proper ED address; i.e., 01,03,05,..,), This address Is not employed in any ED instruction, but is the address of the fixed memory location associated with a failure inter¬ rupt by the particular ED. Thus, there is the possibility of two Interrupt routines associated with a particular ED: one for normal interrupt and one for failure. Fault Interrupt Fault interrupt will occur for the following reason: Dividend > divisor in “divide” Add Overflow Interrupt Add overflow interrupt will occur when the result of addition or subtraction exceeds the length ol the arithmetic register and changes the sign bit 21. Index Overflow Interrupt Index overflow Interrupt will occur when the result of the augment index instruction exceeds the length of a memory address. Memory Fixed Addresses Octal 00000-00077 External device interrupts 00100 Operator interrupt 00101 Unspecified 00102 Fault Interrupt 00103 Add overflow Interrupt 00104 Exponent overflow interrupt 00105 Index cverflow interrupt 00106 Busy interrupt 00107 Unspecified 00110 Interrupt fixed address 00114 Priority ED Interrupt fixed address 00115-00117 Index registers Input-Output System—General Features All transfer of data to or from the computer Is conducted via input-output channels which communicate directly with the magnetic core memory of the ASI-210. The access to the memory is time-shared between the operating program and input-output data transfer; in a typical situation, approximately 15 percent of the memory time is available for Input-output data transfer. Since the arithmetic and control functions of the operating program do not re¬ quire access to the memory every computer cycle, they may proceed simultaneously with input-output data transfer with little or no Iobb in Bpeed. The standard ASI-210 is provided with one input-output channel. An additional channel may be optionally, supplied. Each piece of on-line peripheral equipment is known as an ‘External Device* (abbreviated, E.D.). Each external device has an unique address. The ASI-210 can accommodate up to 64 external devices with two-channel operation. The ASI-210 input-output system is pro¬ vided with program interrupt features so that testing of the condition of the external devices by the running program Is not necessary. MULTIPLE-PROCESSOR G-21- BENDIX COMPUTER DIVISION, LOS ANGELES, CALIFORNIA Bendix Computer Division is developing a large-scale special purpose computer system with a vast memory and true parallel process¬ ing capabilities. The super-system, designated the G-21, will be a multiple-processor com¬ puter using proven off-the-shelf components of the G-20 computer system. It will be capable of handling massive amounts of data fed to it from a variety of sources on an on-line, real¬ time basis. The system is designed for special military control applications which require the collect¬ ing and processing of large amounts of intelli¬ gence and operational data for immediate presentation to military commanders. Large Memory The key to the new G-21 system is the multiple processor design which affords one of the largest memory reservoirs. Up to three 11 centrsi processor ur.lis (CPU's), witn ay,344 words ol random access common core memory, can be linked In a single system. An additional 8102 words of exclusive memory Is reserved for each processor, thereby giving a total high¬ speed memory capacity of 81,920 words. Three segments of the same problem or three separate problems may be handled simul¬ taneously with this configuration. If necessary, several 0-21 systems may be Interconnected without modification of exist¬ ing equipment. Transfer of data between sys¬ tems at extremely high speeds will be possible through completely buffered communication lines under the control of independent input-output processors. Input to the C-21 in a complex military control center, could come from any number ol BourceB, such as, radar, teletype, microwave, telephone, A/D converters, and analog and digital computers, as well as from conventional computer input units. 24-Hour Problems Unusual flexibility of the G-21 would allow it to handle so-called “24-hour problems* - continuously receiving data from a number of sources, processing the data, and finally deliver¬ ing outputs in a variety of forms ranging from luminescent screen display to teletype signal, or even to the firing of a weapon. Design of the system also allows individual problems to be handled without interrupting the 24-hour operation. A unique self-adapting feature is built into the machine's programming. An executive con¬ trol program, designed to meet specific user requirements, would recognize the demands being placed on the system, and assign appro¬ priate processors io the same sequence of operations stored in one portion of the common memory, or It can assign one processor to a sequence of operations without affecting the activities of the other processors. It also will switch the role of a processo.;, at will, among many functions. True Parallel Processing This flexibility affords true parallel proc easing, eliminating the need for parts of a programming system to operate sequentially. Information can now be traded instantly through use of data tables common to the multiple processors. Through program modules, operat¬ ing simultaneously, reaction time of one module to conditions as they are identified by another is reduced significantly. A “fail-safe* feature of the executive pro¬ gram will insure system reliability. If one oi the processors should fall, the remaining processors will automatically adjust and hold lower-priority problems until time Is available. The most Important problems assigned to the machine would be unaffected. Field tests of G-21 components already in use at G-20 Installations indicate assured high- reliability standards lor the new machine. As an example, figures gathered from the early months of customer use of the central proc¬ essors units show an availability record of better than 99 percent. G-21 Programs Programming packages for the G-21 will Include many of the compilers, assemblers, routines, and sub-routines developed over the past 3 years for the G-20. The G-21 is the second phase in the devel¬ opment of a universal computer design aimed at eliminating the obsolescence problem for computer users. Future Bendlx computer developments will be keyed to G-20 and G-21 concepts, to provide compatibility with exist¬ ing systems. Standard hardware elements, in addition to the central processors, include high-speed magnetic tape units, high-speed printers, disc memory units, auxiliary core memory units, control buffers, data communicators, and punched-card and punebed-paper tape units. Price of the system will vary according to application needs, but a minimum G-31 system (two CPU’s, one data communicator, three memory units, one high-speed line printer, three magnetic tape units) will cost upwards of $1,250,000. Approximate delivery date will be 18 months from receipt of order. 12 CONTROL DATA 3600- CONTROL DATA CORPORATION, MINNEAPOLIS 20, MINNESOTA Cuntrol Data Corporation recently released details on their new, powerful, large-scale digital computer - Control Data 3600. This computer features modular expandability of Its high-speed magnetic core memory, high-speed data communication channels, ard computing power. Control Data Corporation takes pride In making this announcement less than 2-1/2 years after delivery of their first large-scale computer - the highly successful 1604. The first 3600, with a complete programming system Included, is scheduled to be ready for delivery in approximately 1 year. The system 1 b exceptionally suited for handling large-volume data processing and solv¬ ing large-scale scientific problems at very high speeds. The advanced level of speed and flexi¬ bility In the 3600 are especially Important In real-time applications where computed results must be available nearly aB fast as the problem is presented to the computer. The special fea¬ tures In the 3600 offer superior inherent machine capabilities at a price substantially lesB than other computers approaching the capabilities of the 3600. One of these advanced capabilities Is the modular design of the 3600 which permits smooth expansion of a basic 3600 system in step with the user’s Increased requirements as they arise. This is achieved without the necessity of inter-connecting the modules with control units, or “black boxes.” The magnetic core memory of the 3600, expandable in modules from 1-1/2 million bits of information to more than 12-1/2 million bits, has an information access time of less than 1 microsecond. The 3600 utilizes special circuits, which make use of tunnel diodes, to speed up basic arithmetic processes in the nanosecond (or billionths of a second) range. In transmitting data to and from peripheral equipment, the data communication module operates independently and asynchronously of the main computer program. Each data com¬ munication module haa four bi-directional data channels, expandable to eight at the customer's option. These high-speed channels permit data to be transmitted to and accepted from peripheral equipment In large-volume and at tremendously high speeds while the computer continues to perform highly complex computations. As many as 32 bi-directional data channels can be Incor¬ porated in the fully expanded 3600, each able to handle up to eight control and/or peripheral devices. A complete programming system will be delivered with the first 3600 computer system. Oriented around the Control Data Master Con¬ trol System (MCS), the computer programming will be totally Independent of the hardware- size and type of a given 3600 system, whether the customer has a basic or an expanded ver¬ sion. Therefore, the programming will be as tailor-made to the customer’s requirements as Is the hardware used. The MCS provides for a common library to incorporate systems pro¬ gramming such as FORTRAN and COBOL, an open-ended feature to Incorporate new com¬ pilers and programming systems as they are developed, and a “linking-loader* feature to incorporate several independently compiled or assembled sub-programs into one main com¬ puter program. A basic 3600 computer system, including necessary peripheral equipment, is in a pur¬ chase price range of $2 to 32-1/2 million. Lease of the same equipment will be approxi¬ mately $55,000 to $60,000 per month. This price includes, as standard 3600 computer hardware, many features that are generally held as optional in other systems approaching the capabilities of the 3600. For example, both fixed- and floating-point arithmetic. In both single and double precision, Is standard in all 3600 systems. 13 Characteristics Modular Design and Expandability Basic System 3604 Compute Module 3603 Storage Module 32,768 48-bit words in each module, each word with 3 parity bits 3602 Communication Module Equipped with four (4) high-speed 3606 Data Channels 3601 Console Includes input-output electric typewriter 250-card-per-mlnute punched card reader Expandable to As many as five compute modules can be linked together. Expandable in 32,768-word modules to a total of eight for more than 12-1/2 million bits of information. Expandable up to eight data channels per module, up to eight moduleB per 3600 com¬ puter. Total expansion to 32 bi-directional channels. (As many as eight control and/or peripheral devices can be handled by each bi-directional data channel.) i Operating Speede Magnetic Core Memory Memory cycle time-l.S microseconds Effective cycle time (access)-—— 0.7 microseconds Internal Computing Speeds Typical average execution times are given in microseconds. Instructions Fixed Point Single Precision Floating Point Double Precision Floating Point Multiply 1-6 2-26 Divide 1-14 2-26 Fetch/Store 1.5-2.2 3 Add/Subtract 4 5 Special High-Speed Circuits These special circuits employ tunnel diodes to speed up baste arithmetic operations into the nanosecond range. These operate at 4 nanoseconds per stage. The basic cycle time ol the adder network, for example, is 250 nanoseconds. The shift time is a constant 250 nanoseconds regardless of the number of places shifted. Examples of Arithmetic Function Speeds The 3600 Computer can perform the following functions in 1 second: • 670,000 fixed-point additions or subtractions 250,000 floating-point additions or subtractions in single precision 200,000 floating-point additions or subtractions in double precision 14 167,000 floating-point multiplications (single precision) 71.500 floating-point divisions (double precision) 38.500 floating-point multiplications and/or divisions in double precision Input-Output Communications Input an i output operations occur independently and asynchronously with operations in the com¬ pute module. The standard four bi-directional data channels in each communication module (or expanded modules with eight channels) permit data to be transmitted to and accepted from peripheral equipment In large volume and at tremendously high speeds while the computer continues to perform highly complex computations. The computer only directs the selection of a specific external device and the channel In which the I/O activity is to take place. Once operating conditions have been Initiated, the communication module supervises all I/O functions. Data being transmitted or received goes to or from the magnetic core memory directly, and does not pass through the compute module. Computation Capabilities The 3604 compute module performs all computing and logical operations in the 3600 system. Included as standard hardware in the compute module are provisions for fixed- and floating-point arithmetic in both single and double precision. The 3604 operates In a parallel binary mode. Several new categories of instructions have been included In the 3600 instruction repertoire: 1. Commands for manipulating portions, or “bytes,” of a data word. For example, bytes of 48 bits or less may be transmitted to any portion of a computer register or memory storage word in a single operation. Indexing through bytes in a word (horizontally) or through a list of such words (vertically) In the same operation is also provided. 2. Double-precision, floating-point commands include add, subtract, multiply, divide, fetch, and store. (A 10-bit plus sign exponent is used with an 84-blt plus sign fraction.) 3. A special instruction for list processing, as well as several new indexing operations. 4. A universal bit-sensing instruction that permits any bit to be tested and branched upon. 5. A powerful, extremely fast, interrupt facility is provided, as well as Instructions for process¬ ing interrupts. 6. Six sense switches are Included on the console and can be programmed sensed. These are in addition to three selective jump and three selective stop switches. 7. A 48-bit sense-light register able to set or clear each position in a register under program or manual control. 8. Two hounds registers of 18 bits each, used for memory lockout. Information is not written into the region of the memory specified by the addresses within the bounds registers. Other important features in the 3600 are: 1. Two-way search instructions 2. Auto-load buttons for card and magnetic tape equipment 3. Direct card reader entry into arithmetic register 15 FORTRAN immIV 4. Parity check on all I/O data transmission 6. Special computing (unctions can be added easily via special channel in the compute module (i.e., trigonometric and exponential (unctions, etc.). Programming In parallel with the development o( the 3600, Control Data Is developing a complete and inte¬ grated software system to be delivered with the first computer. This software system will be oriented around a Master Control System (MCS), The MCS will act as a common communi¬ cation link among all programming systems and I/O devices, interrupt, and memory allo¬ cation (unctions. Thus, the MCS will allow programming systems to be independent o( particular machine condgurationa, as well as of types and numbers of I/O media. In addition, the MCS will provide: 1. A library common to all systems, such as FORTRAN and COBOL, which will operate within the MCS. 2. An open-ended ability to Incorporate new compilers and operating systems as they are developed. 3. A linking loader that will permit Joining together, in one program, several sub-programs that may have been separately and independently compiled or assembled. 4. A system easy to modify and adapt, when necessary, to the needs peculiar to a given installation. Some of the Important programming sys¬ tems operating under control of the MCS will be: MONITOR SYSTEM . A complete operations supervisory system for automatic control of all Jobs. It will allow stacking of Jobs with arbitrary intermixing of different Job types, such as assembly, compilation, and execution. COM PASS . A comprehensive assembly system with versatile language features for representing the extensive instruction reper¬ toire in a simple symbolic notation, employing advanced assembly techniques. extensions to, and generalizations of, the basic FORTRAN language using advanced compiler techniques lor producing optimum object programs. COBOL , A complete compiling system for business-oriented applications. 1604 Compatibility Package . A software package which will execute interpretively all trapped I/O Instructions of a 1604 program running in the 1604 compatibility mode. Optional Peripheral Items A variety of optional on/off-llne peripheral items may be used with t.'e 3600 computer. These include 12-, 24-, an/ 48-bit bi-directional data channels; a 48-bit inter-computer data channel; special function generators; magnetic tape handlers and tape synchronizers; medium - and high-speed card readers, card punches; low- and high-Bpeed line printers; paper tape I/O equipment; keyboard entry devices and typewriters; and disc files. CONTROL DATA 6600- CONTROL DATA CORPORATION, MINNEAPOLIS 20, MINNESOTA Control Data Corporation has announced that the Company has received from the U.S. Atomic Energy Commission a $5,574,000 order to furnish and install a super, high-speed com¬ puter Bystem at the Lawrence Radiation Laboratory, The Bystem, called the Control Data 6600, is to be installed and ready for acceptance testing at the Livermore (California) laboratory not later than February 29, 1964. The Lawrence Radiation Laboratory ts operated for AEC by the University of California. Control Data Corporation was selected to furnish the new system on the basis of its pro¬ posal made In response to a solicitation to the computer industry by AEC In 1961, with the delivery of the system requested in mid-1963. Under the terms of the negotiated contract, the Company will furnish interim computer capacity on the Control Data 3800 Computer System (see 3600 description, this issue of DCN) until the new system is accepted. The request for proposals stipulated that the sys¬ tem required, although faster than any existing machine, was not to be a specially designed 16 computer, It was to be capable of high speed operation for employment in the solution of broad complex scientific problems. The Control Data 6600 Computer System Includes a single central processor with a high¬ speed arithmetic and logical unit, a central memory of 61,440 words, peripheral processors, associated consoles, and input-output equipment. The system central processor Is a high-speed, logical and arithmetic unit, especially designed for rapid floating-point operations, The high speed in computing Is obtained through the use of semi-micro instructions and multiple transistor registers for temporary storage. Simple instructions can be combined optimally to execute complicated sequences without loss of time in referencing core storage temporary locations. The new computer system will enable scientists to cope with the increasingly complex problems that scientific advances pose and to obtain solutions to present problems in finer overall detail. The new system, which was designed to be faster than any now existing, will make it possible to solve in shorter time comprehensive technical problems that now require many hours of machine operation. Thus, the addition of CONTROL DATA 6600 will sig¬ nificantly increase the overall work capacity of the Lawrence Radiation Laboratory. HYDAC SERIES 2000-HYBRID DIGITAL/ ANALOG COMPUTER, ELECTRONIC ASSOCIATES, INC., LONG BRANCH, NEW JERSEY The EAI HYDAC Series 2000 Hybrid Digital/Analog Computer introduces a new con¬ cept to engineering and scientific computation by providing the engineer with a single computer that he can easily operate alone and apply either analog or digital techniques as desired to the solution of the problem. The costly process previously practiced in attempts at hybrid computation - that of combining a complete digital data processing computer with an analog computer - has been refined considerably and made economically practical. Analog and digital operations are now combined in one centralized system to achieve a computational efficiency that is well beyond the limits of either analog or digital computers used alone. The tradi¬ tional advantages of both analog and digital computers - the analog computer’s speed, lower coot, and ease of programming and the digital computer’s unique capacity for data storage and time sharing of components - have been combined to expand problem solving capabilities at lower cost. Since many of the digital operations re¬ quired for hybrid computation schemes involve mainly those of timing, selection, sequencing, memory look-up, and calculation of simple functions, such schemes can be accomplished without the expense of large data processing digital machines. Digital operations can become an integral part of the expanded general purpose analog computer making them available to com¬ puter laboratories that have no digital computers, or during those periods when time is not avail¬ able on the latter. With HYDAC Series 2000, analog and digital computation can be centra¬ lized in a single laboratory thereby eliminating scheduling and training difficulties. Programming of the entire system paral¬ lels closely the relatively simple operation of the analog computer. The transition from the use of relays and switches in the general pur¬ pose analog computer to logic devices is made very easy. Extensive retraining of analog pro¬ grammers is unnecessary. Analog operations of summation, Inversion, continuous integration, multiplication, division, and function generation are performed by a proven computing system. All electronic, wide bandwidth computing components Insure high dynamic accuracy for real-time or repetitive mode of operation. Multiplication and other nonlinear operations are performed with signal frequencies in the kilocycle range, so as to realize full advantage of the high-speed digital circuits. Digital Computing Components Digital computing components are general purpose In concept and design. Five major groups of components are available to provide programmed digital logic, digital memory, analog memory, analog digital conversion, and advanced digital arithmetic. Each of these groups of components could be the complete Justification for HYDAC Series 2000, however, a more powerful and useful system is one that combines several of the major classes of digital components. Modular designed digital building blocks permit fullest advantage of the economy and flexibility of the pre-patch panel concept to be realized. Digital switching circuits employing one basic type of universal gating circuit for maximum flexibility and added economy are 17 used to perform basic digital operations. Com¬ pletely solid state with 20-megacycle switching capabilities these basic modules are combined on printed circuit cards to foi m more complex operations. The 2000 is the result of a comprehensive design Btudy by experienced computer users, programmers, and designers who are concerned with the basic requirements of hybrid computation. Major components of the 2000 are a general purpose analog computer and a digital console. This console is designed to take fullest advantage of the economy and flexibility of the pre-patch panel concept; modularized digital building blocks capable of performing basic digital opera¬ tions plug into standard connectors behind the patch panel, and each is terminated in a four-by- ten hole area of the patch panel. The digital building blocks are interchangeable. HYDAC Series 2000 may be made to have many different capabilities by employing different combinations of building blocks. This flexibility is obtainable without prejudice to design or wiring of the digital console. Reliability, economy, and ease of maintenance result from all solid-state design. Digital operations in the 2000 are assembled from the following console units and groups of digital computing components. Digital Console With provisions for mounting the digital computing components, the basic console unit provides power supplies with necessary wiring, facilities for control and slaving of the unit to the analog computer, selector switches, flip- flop Indicator lights, and control buttons, etc., and the 3450-hole pre-patch panel system. A clock unit with timing signals terminated on the patch panel provides control timing and synchro¬ nization for the entire system. Console expan¬ sion unitB available include a punched-paper- tape Input-output system, a decimal-binary conversion system and special control units. Logic Building Blocks Logic components are very high speed (50 nanoseconds switching time), solid-state switch¬ ing circuits, each designed to provide specific logic functions. A wide choice of functions is available, as well as a choice of the level of logical organization, such as; logic gates, RST flip-flops, 4-bit shift registers, monostable multivibrators, up-down counters, preset counters, ring counters, BCD counters, dif¬ ferentiators, buffer registers, adders, multi¬ pliers, special control units, and timing units. Digital Memory Building Blocks High-speed digital memory unite, known ae serial memory units, are available in four different sizes with circuits to make it possible to provide control directly from the patch panel and to connect the units together for special functions. Analog/Dtgital Converters These building blocks convert control sig¬ nals and analog voltage signals from analog to digital, and back to analog. High-speed elec¬ tronic switches and incremental converters, as well as conventional whole number converters, are also available to satisfy additional conver¬ sion requirements. Analog Switching and Memory These building blocks consist of MICRO¬ STORE memory and switching modules which are operated in combination with analog opera¬ tional amplifiers to provide high-speed point storage of analog voltages plus electronic switching capabilities. Advanced Digital Arithmetic Units These digital building blocks consist of accumulators, adders, summers, input units, constant storage units, and comparators. These units provide the analog computer with expan¬ sion units capable of high precision computations. Applications The combination of analog and digital operations not only allows more economic analysis of certain classes of engineering and scientilic problems, but in some instances is a far superior method of analysis. Although the range of applications of the analog computer is indeed wide, the additional ability to store, to process data, and to use the results of this processing as input data for further calcula¬ tions extends the scope of application of the analog machine. HYDAC Series 2000 provides these capabilities and thus increases the rangp of problems that the analog computer can 18 solve economically, it gives new meaning to high-speed computation. Among the move important applications of this new computer are: Iteration and Optimization Studies Problems of this nature arising in model building, process simulation, parameter studies, and end-point boundary value systems can be optimized by trial and error methods. Compu¬ tation time is significantly reduced by the Incorporation of suitable logic and switching functions to allow the analog computer to pro ceed automatically through a complete Iteration procedure until an optimum is found. The same logic functions facilitate the automatic program¬ ming of parameter searches, performance curve fitting, and matching of boundary values. Partial Differential Equations The solution of many scientific problems is represented by the solution of linear or non¬ linear partial differential equations. Solutions based on difference techniques utilizing function storage and playback permit equipment savings through the time sharing of analog circuits. Such techniques allow the time-domain simula¬ tion of field problems where space variables are replaced by high-speed time sweeping, while the physical analogy of time is preserved. Hybrid operations also facilitate the solution of boundary value partial differential equation problems by the method of characteristics or by Integral equation methods through the use of serial solution techniques and time multiplexing. Simulation of Logic Functions Often a problem being studied is partially represented in its physical description by decision functions. Such problems occur with increasing frequency in the study of space vehicle characteristics and the control of com¬ plex processing. A prime example is the simu¬ lation of an adaptive control system, Here the dynamic behavior of the system being controlled is represented by normal analog elements while the logic of the control system Is represented by the available digital logic elements. integral Equations This important class of equations, whether arising directly or Indirectly as in the solution of partial differential equations, can be solved efficiently by a combination of analog and digital elements. Simpler investigations, such as those Involving the solution of the Volterra and Fred¬ holm integral equations, can be programmed easily using general purpose elements. More complex solutions now become economically al ractive. Auxiliary Mathematical Functions Special operations such as multiplications, transport delay simulation, function generation, slow integration, etc., may be custom designed, with suitable programming, for combined opera¬ tions with analog elements. Problems which have been programmed for solution with the 2000 at EAI’s Princeton Com¬ putation Center include: 1. A generalized optimization control program to optimize any non-linear function of n variables that is programmed for an analog computer. 2. An eigenvalue problem for determining the normal modes of a vibrating beam. 3. A reaction-jet space capsule control problem. 4. Iteration solution of tubular reactor and control system design problem. 5. Solution of partial differential equations by the method of characteristics. 6. Integral equatlun solution of a boundary value problem. IBM 7094-INTERNATIONAL BUSINESS MACHINES CORPORATION, WHITE PLAINS, NEW YORK The IBM 7094 data processing system is the most powerful in the company’s line of Intermediate- and large-scale solid-state r.ctentlflc computers. This line also includes 19 the 7040, 7044, and 7090. Increased soeed and processing power of the 7094 are provided by (aster adding circuitry, additional index regis¬ ters and instructions, and the facility for per¬ forming double-precision floating-point arithmetic. The new system is offered in a wide variety of input-output configurations and has storage capacity of 32,768 words. It can be linked to various IBM Tele-processing devices for full data transmission ability. A library of 7094 programs covering a wide range of computer functions is provided at no cost by IBM. Sys¬ tem compatibility enables a customer with a 7090 to use his new 7094 with virtually no reprogramming, The memory reference cycle is 2,00 micro¬ seconds for the 7094, compared to 2.10 micro¬ seconds for the 7090. When processing is per¬ formed in the floating-point mode (generally used when the numbers involved vary greatly in magnitude), the 7094 can perform mathe¬ matical computations 1.4 to 2.4 times faster than the 7090, depending upon the technique used to solve problems. Memory reference speeds for IBM’s Intermediate- and large-scale scientific systems are as follows: System Memory Reference Speed (psec) 7094 2 7090 2.18 7044 2.5 7040 8 709 and 704 12 Modular design provides upward compati¬ bility of these systems. A user can enlarge his system or advance to a more powerful com puter with a minimum of reprogramming. A team of IBM customer engineers can expand a 7090 which is already on rental to a 7094 in the user’s office within 72 working hours, including installation and system test¬ ing. The changeover involves installation of a higher-speed processing unit containing faster solid-state adding circuitry, additional instruc¬ tion circuitry to accommodate new commands, and four additional index registers. Faster circuitry is installed in other elements of the system and a display panel for the additional index registers is mounted on the operator’s console. IBM 1301 disk storage units and Hypertape magnetic tape drives can be linked to the sys¬ tem for high-speed input and output of data. Up to five 1301’s with a combined capacity of 279 million characters can provide additional storage on magnetic disk files. Up to 20 Hypertape units, capable of read¬ ing data from and writing data on tape at the rate of 170,000 characters a second, or up to 80 IBM 729 tape units, ranging in read-write speed from 41,700 to 90,000 characters a second, can be linked to the Bystem. Various combinations of Hypertape and 729 tape units can be used with a single 7094. An IBM 1011 paper-tape reader, capable of reading data into the computer at the rate of 500 paper-tape characters a second, enables the system to accept data transmitted directly by teletype, Common carrier telegraph equip¬ ment can also serve as remote input-output devices for the system. Ability to transmit and receive data over long distances in computer language is provided by the IBM 1009 data transmission unit. This IBM Tele-processing device enables the 7094 to communicate over leased telephone or tele¬ graph lines with another computer (7094, 7090, 7040, 7044, 1401, 1410), a magnetic tape trans¬ mission unit or a card transmission unit at speeds up to 300 characters per second. The 1014 remote inquiry unit, another IBM Tele-processing device, is equipped with and input-output typewriter and can be used for direct interrogation of the computer from a point up lu 8 miles away. Programming Support A number of 7090/94 programming sys¬ tems and languages will be provided by IBM to 7094 users without charge. The 7094 is so designed that programs written for the 704, 709, 7040, 7044, and 7090 can be run with a minimum of modification and at higher speed, 7090/94 programs provided by IBM are: FORTRAN The widely accepted IBM FOR mula TRAN slation system enables the user to write his programs in a language closely resembling that of mathematics. Thus scientists and mathematicians can code problems with a 20 minimum of computer knowledge. The FORTRAN Assembly Program converts these coded tnstr etions Into machine language. COBOL This COmmon Business Oriented Language permits the user to "write programs using familiar business terms. COBOL is the result of work by the Conference on Data Systems Languages (CODASYL), a voluntary effort of various computer manufacturers and users under sponsorship of the Department of Defense. The COBOL processor converts English-like instructions In COBOL language Into a machine- language program. Input-Output Control System IOCS relieves the user of having to write repetitive Input-output instructions for every program. It provides a complete set of instruc¬ tions for effective use of all input-output devices, including the 1301 and Hypertape. Sort This program facilitates automatic reorgani¬ zation of data stored on magnetic tape. 0PAC Designed for business applications, this programming system provides for the establish¬ ment and maintenance of data files and the pro¬ duction of reports with a minimum of program¬ ming effort. Basic Monitor (IBSYS) This system permits uninterrupted proc¬ essing of any of the above programs written for either the 7d90 or the 7094. It calls pro¬ grams into use from a tape library and enables them to take full advantage of whichever input- output devices are linked to the system. Commercial Translator Designed for commercial data processing applications, it enables the user to write his programs in a language based on English. A typical IBM 7004 sells for $3,134,500 and rents for $70,000 a month. Installation of tile 7094 will begin in the fourth quarter of lttOH. The new system li manufactured at the company’s Poughkeepsie, New York, plant. 900 SERIES COMPUTERS- SCIENTIFIC DATA SYSTEMS, SANTA MONICA, CALIFORNIA Th9 Scientific Data Systems 900 Series of computers consists of three general-purpose digital computers - the 610, 620. and 930. This article primarily describes the flrBt two, the 930 is only briefly treated. All the computers in the aeries are Intended both for special- purpose system integration and for general- purpose scientific use. All sell for under $ 100 , 000 . The computers operate with a 24-bit binary word; a twenty-fifth bit provides a parity oheck on all memory operations. Fourteen bits of the instruction serve to address up to 16,364 words of random access core storage; 6 bits are used for the operation code. One bit is used to signify that the address Is Indirect; that Is, that the effective address is to be found in the location specified by the address portion of the given Instruction. The location thus specified may, in turn, contain an indirect address bit. The number of Iterations of this process is not limited. Another bit adds the contents of an index register to the address prior to execution of the Instruction. If an indirect address bit is present, the effective address is found in the location that results after indexing. A relative address bit is also provided in order to simplify the loading of sub-routines, etc. The final bit in the Instruction is used to signify that the operation code is to be interpreted as a Pro¬ grammed Operator. This requires some explanation. There are many practical advantages to be gained from designing a series of computers such that programs for any given computer, within the limitation of memory size, can be run by any other computer in the series. For example, within a given facility a number of different computers can be employed, each of an appropriate size. If any one of these is unavailable, another can be directly employed without extensive reprogramming, This pro¬ gram compatibility is relatively simple to mechanize If the programs from a smaller computer are run on a computer with an 21 instruction renertnire thot_ ;pcsl:tr.g, contains the smaller computer’s instructions as a subset. It is the inverse problem that the programmed operator is intended to solve. The presence of the programmed operator bit causes the operation code to be Interpreted as a sub* routine entry address. Thus larger computer instructions that do not exist in the smaller computers are interpreted directly by sub¬ routines in the smaller computers. As a result, all programs for the 900 Series are inter¬ changeable, that is, the computers are ’‘sym¬ bolically homogeneous." An example will clarify this term. All three 900 Series com¬ puters use different multiply commands. The 910 has only MULTIPLY STEP, the 920 has MULTIPLY, while the 930 has FLOATING POINT MULTIPLY as well as MULTIPLY. In running a 930 program on the 910, for example, the FLOATING POINT MULTIPLY command is identified by the loader as a programmed operator and, upon execution of this command, the operation code is interpreted as the address to which the program transfers in order to pick up the appropriate floating-point multiply sub-routine. In addition to providing symbolic homo¬ geneity, the programmed operator serves to extend the command list of any of the 900 Series computers for a given application. For example, in some classes of programs, complex arith¬ metic instructions are useful. The symbol, ADJ (Add Complex), can be assigned an instruc¬ tion code and the address portion used to specify the location of the real part of the operand. The Imaginary part is stored in the adjacent memory cell. This instruction code will cause a pro¬ gram transfer to the sub-routine while storing the return address. Although all programs are Interchangeable, the time and memory requirements for a given problem vary among the three computers. The baste execution time for addition Is 16 micro¬ seconds for all computers, including indexing and all memory accesses. The 920 requires 128 microseconds to produce a 47-bit product from two 24-bit factors including memory accessing and indexing; the 910 requires 246 microseconds. The floating-point (39-bit man¬ tissa, 9-bit exponent) sub-routine set requires 90 words and approximately 800 microseconds per floating-point operation in the 920, while the 910 requires 180 words and approximately 3000 microseconds per instruction. Input-output is probably one of the most critical design problems in low-cost computers that are to be used for both systems and general scientific computing. Ail 900 Series computers have identical input-output logic which incorpo¬ rates five separate methods of operation: Single Bit Control Up to 16,000 different control signals can be generated or tested by the 900 Series com¬ puters. For example, a single Instruction starts a specific magnetic tape unit, indicates the number of characters per word, and the buffer that ts involved. A single instruction can also test the state of the breakpoint switches, the parity error detector, or any other signal, and Bkip as a function of the result. Input-Output Buffer A full word plus one character buffer is provided which accepts and transmits words between the memory and external devices. The extra character minimizes timing problems and bo increases programming efficiency. The buffer operates upon characters of up to seven bits, generates and checks parity, and operates simultaneously with computation. A program interrupt is provided to facilitate this simul¬ taneity. The program control automatically transfers to an Input-output processing routine when the buffer either is empty during output or contains a word during input. Using this scheme, 15 kc character rate magnetic tape information can be processed while permitting the computer to operate 64 percent of the time on other programs. The maximum transfer rate Is 41.6 kc. Because the buffering hard¬ ware is integral to the computers, the cost of magnetic tape units is minimal. The 15 kc tape units for the 900 Series are under $20,000. As an optional feature, a second and Identi¬ cal buffer is available for applications that require simultaneous input and output. Using this buffer, for example, a gapless magnetic tape can be read and an IBM-format tape written, simultaneously, at a rate of up to 5 kc. Parallel Input-Output In operating with certain devices such as printers, anaiog-to -digital converters, and display systems, it is more convenient to proc¬ ess words than characters. For these cases, the computer can transmit or accept 24 bits in parallel along with an interlock signal to synchronize the transfer. A 25th bit is pro¬ vided for parity information. Using this 22 parallel transfer method, several 900 series computers can be interconnected to perform complex tasks that are beyond the capabilities of any single computer. The maximum transfer rate is 62,800 words per second. External Memory Interlace The memories of the BOO Series computers can be time-shared between the computer proper and external devices. Prior to accessing memory for each instruction, the computer automatically tests to see if an external device, such as a magnetic tape unit, requires access to the memory for either Input or output. If access is required, the computer is halted for the 8 microseconds necessary to transfer a word and computation is then resumed. Character trans¬ fer rates of up to 124 kc are possible with the computer operating and 500 kc with the computer in HALT. An unlimited number of buffered input-output devices may be connected to a 900 Series computer using this technique. A 30 kc magnetic tape unit with automatic search is one such device that is available. Priority Interrupt An optional feature of the 900 Series is a priority Interrupt system with up to 1024 chan¬ nels in blocks of 16. Each channel causes the computer to Interrupt to a unique memory loca¬ tion. Each channel has an assigned priority status such that, when it is activated, it causes the interruption of previous Interrupts of a lower status and, In turn, it Is Interrupted by channels of higher status. The number of input-output devices that can operate with any of the 900 Series com¬ puters is essentially unlimited. Any number and combination can be employed. In addition to the magnetic tape units already discussed and the high-speed, paper-tape punch and reader and typewriter provided as standard equipment, card readers, printers, disc files, analog-to-dlgital converters, and dlgital-to- analog converters are available. Special power failure protection Is provided on all computers. Special sensing devices sense the status of the ac -Input line before each memory operation and halt the computer if the line is low or if power has failed. With priority Interrupt, this sensing system can be used to store all registers before the dc-power fails. The computer can then simply be restarted when power is again available, A typical system that illustrates the speed, memory efficiency, and input-output flexibility of the 900 Series 1 b the general data acquisition and evaluation problem. Analog data Is multi¬ plexed and converted to digital form under the control of the computer. The resultant data is entered Into the computer and compared with high and low limits. A linear transformation is then performed in order to eliminate zero and full-scale errors and, at the same time, to translate the raw data into engineering units. The program to perform these operations requires 29 instructions in the 910 and approxi¬ mately 600 microseconds per point. In the 920, 17 wordB and 300 microseconds per point are required. In construction, the 900 Series i:. unique for nonmllitary computers in that only silicon semiconductors are employed. The 910 uses approximately BOO transistors and 600 watts of power, while the 920 has 1100 transistors and requires 1000 watts. No air conditioning is needed in either case since the computers will operate in ambients of from 0° to 55° C. A complete software system for the 900 Series includes a utility package, a symbolic assembler, and a FORTRAN-compatible com¬ piler. The latter Is similar to the IBM 1620 FORTRAN n compiler with the addition of magnetic tape statements. Again, because of the symbolic homogeneity of the 900 Series computers, any of the computers can be em¬ ployed for compiling and the resultant object program run on any other of the computers. 23 SDS 900 SERIES CHARACTERISTICS SDS fllO Computer 24 -bit word plus parity bit Binary arithmetic Single address instructions with: Index register Indirect addressing Programmed operators Basic core memory 2048 words expandable to 16,384 words Typical execution times (including memory access and indexing): Add - 16 psec Multiply-248 peer Floating-Point Operations: (39-bit Mantissa + 9-bit Exponent) Add -1984 pser Multiply ------ — - — — 2600 psec Program Interchangeability with other SDS 900 Series computers Parity checking of all memory and input-output operations 1024 channels of priority Interrupt (opt’l) Memory nonvolatile 'ith power failure Input-Output: Standard: 300 character/second paper tape reader Program Interrupt Display and manual control of Internal registers Optional: 60 character/second paper tape punch Automatic typewriter Magnetic tape units (IBM compatible) Line printer Punched card equipment Direct communication with IBM 7090 A/D converters, etc. Buffered input-output at rates in excess of 80,000 characters/second FORTRAN Ii and Symbolic Assembler as part of complete software package All silicon semiconductors 0° to b5°C operating temperature range Dimensions: 75 x 24 x 27 in. Power: llOv, 60 cps, 8 amps PRICE: $41,000 SDS 920 Computer 24-bit word plus parity bit Binary arithmetic Single address instructions with: Index register Indirect addressing Programmed operators Basic core memory 4096 words expandable to 18,384 words Buill-ln Floating-Point Instructions Multi-precision Instructions Typical execution times (including memory access and indexing): Add - 16 psec Multiply- 128 psec Floating-Point Operations: (39-bit Mantissa + 9-bit Exponent) Add- 368 psec Multiply--- 560 psec P, ogram interchangeability with other SDS 900 Series computers Parity checking of all nemory and input-output operations 1021 channels of priority Interrupt (opt’l) Memory nonvolatile with power failure Input-Output: Standard: J00 character/second paper tape reader 60 character/second paper tape punch Automatic typewriter Program Interrupt Display and manual control of Internal register} Optional: Magnetic U. ;• « J r s M.HM compatible) Line printe . ■ Punched ca. ju "'.ii Direct com;nun .nth IBM 7090 A/D converter , t Buffered input-output rates In excess of 80,000 characters/:^.!, ond FORTRAN n and Symbolic Assembler as part of complete software package All silicon semiconductors 0° to 55°C operating temperature range Dimensions: 66 x 48 x 27 In. Power; llOv, 60 cps, 10 amps PRICE: $89,000 24 BRLESC—U.S. ARMY BALLISTIC RESEARCH LAuOkaIUKIES, COMPUTING LABORA¬ TORY, ABERDEEN PROVING GROUND, MARYLAND Introduction The complement of large-scale, digital, electronic, general-purpose computers now consists of the EDVAC, ORDVAC, and the new Ballistic Research Laboratories’ Electronic Scientific Computer (BRLESC), which Just recently haB been placed In full service. BRLESC was designed, developed, and assembled by BRL’s Computing Laboratory Engineers, Mathematicians, and Technicians, from con tractor-provided com¬ ponents. The scientific computational workload of BRL Is gradually being shifted to the BRLESC. Many important old problems can now be solved in a small fraction of ,te tJme formerly re¬ quired. Some problems which were previously unsolvable on EDVAC and ORDVAC because of limited speed and storage capacities, are being readily solved by the BRLESC. The BRLESC has 4096 words of magnetic core storage with a 0.6 microsecond access and 1.2 microsecond cycle-time, 63 index registers, a 68-bit word length, fixed- and floating-point logical and arithmetic operations, and an extremely rapid compiler. A three-address instruction requires about 5 microseconds. A fast-carry logic 1 -microsecond parallel digital adder is used. A selection of off-line conversion from and to various media Including cards, tapes, and printer is available. A BRLESC high-speed digital computer compiler (FORAST) has been coded and checked. This compiler is a machine-language set of instructions that accepts programs which are written in any of three languages or any com¬ bination of the three. The languages are: 1. Mathematical formula and English statement language, 2. BRLESC symbolic language, and 3. BRLESC absolute language. This BRLESC compiler language is compatible with the ORDVAC. The preparation of aiming data for fre6 rockets, one of the missions of the Computing Laboratory of the Ballistic Research Labora¬ tories, is based on the reduction of data from flight tests; that is, the mathematical simulation of each such test. The advent of BRLESC with its great computational speed has permitted the introduction of vastly more precise and sophisticated techniques in these reductions, resulting m a more complete mathematical model of the rocket being considered with con¬ sequent Increase In accuracy of the aiming data provided for It in the form of a firing table. Origin of BRLESC . In 1956, BRL transferred $100,000 to the National Bureau of Standards (NBS) to assist in the development of universal logical packages which could be used In the construction of a new, fast, reliable, scientific computing machine. A logical package Is a group of decision mak¬ ing circuits which are capable of developing a certain result in accordance with conditional input statements. For example, one type of element ‘‘agrees’’ that an entire statement Is true If all of a group of conditions are fulfilled; another type yields a "true" signal If only one or more of the conditions are met. With these, coupled with the ability to reverse a decision, all the arithmetic, logical operation, and number manipulations may be performed with reason¬ able economy of electronic parts. At the time the funds were transferred, NBS was committed to the design of their new PILOT Multi-Computer System. The funds assisted the Bureau in arriving at a tentative design of arithmetic, logical, and control units. After tests by BRL, certain changes in the design of the logical package were requested. Modifications of the logical packages were approved by NBS. In February 1958, the sum of $175,000 was transferred to the Bureau to cover the cost of 6000 packages for BRL, to be procured along with the NBS’s own requirement for PILOT. At this time BRL’s programming staff prepared a description of the instructions to be automatically executed by'BRLESC. Due to various considerations - the different types of application, desire for easy programming, and overall economy - BRL and NBS parted ways In development. All that there Is In com¬ mon today between BRLESC and the NBS com¬ puter is the logical package and aspects of the high-speed arithmetic unit. BRLESC is UBlng high NBS-proposed high-speed carry logic. BRLESC’s instruction code, physical construction, Internal nrrangement, control logic, peripheral equip¬ ment, and many other aspects are different. High-speed carry logic is an improved method of licking a problem that confronts 25 ftnymt* who a/Ma a rntmnn of flmtraa It la a third-grader or BRLESC, the matter of "one to carry* can be a poaer, both from the •tandpolnt of setting the right result, and of the time required to get It. In the human cane, a peraon doing the aum 99B9 plus I recogniaea the "one to carry” aapect aa universal, and jumpa forward to the anawar 10,000 Inatantly. In a rough way thla type of thing la also Involved in the BRLESC high-speed carry logic design. Thus, the computer recognizes whether there will be a carry or not In all columns at once, for after all, either there la a carry or there la not. If there la, it can only be a one. A carry cannot propagate past a sum digit which la ZERO; therefore, signals can be generated to indicate at which digit positions a carry should be'generated. In far leas time than It would take to wait and aee If there la a carry propagated from all previous digit positions during a summation,. BRLESC’s High-Speed Storage Unit The high-speed storage unit developed for uae In BRLESC represents a new step forward In the development of computer components. The development contractor - Ampex Computer Products Co - has delivered this unit, not only to BRL for use In BRLESC, but has furnished similar units to a number of computer manu¬ facturers for Integration Into their own sys¬ tems to meet other defense requirements. It furnishes a current example of how Ordnance requirements have been met, with correspond¬ ing benefits to other defense activities. Construction cost accounts of most large- scale, electronic, digital computing systems reveal that the high-speed storage element Is the most expensive single Item. This Is the section of the computer which "receives, stores, and Issues* Information and Instructions In the form of computer numbers or "words.” BRLESC uses a high-speed magnetic core storage unit having a capacity of 4096 words, of up to 72 "bits* each (64-bit numbers are used). The translation of these bits into decimal terms Is equivalent to approximately 19 decimal digits. Such long word length Is necessary to provide the extreme precision required of calculations made In connection with scientific research. For many other types of application, such as ordinary commercial calculations, such a high degree of precision Is not required and Is not Incorporated in many of today's computers. The capability to handle long words carrteB with it a requirement that the computer be able mssWa its* a# iiswy wn w liflti Tl»« saw - plete read-wrlte cycle time of the BRLESC memory Is l.B microseconds, which is the fastest large-scale memory in operation today. BRLESC Is approximately one-half as fast as' the two fastest high performance computers yet constructed 1 anywhere, and twice as fast as the most rapid computer currently available com¬ mercially. 2 The faster machines use overlapping memory cycles from separate banks of memory to achieve high effective memory speed. This cycle time Is Important, since three to four cycles may be required when the computer adds two numbers. Even though the elapsed time for one cycle is only 1.5 millionths of a second, thiB value becomes critical when a long series of computations are undertaken. The computer executes Instructions In the form of a huge number of small steps, each requiring a specific time Interval to perform. These many small steps run Into the billions for typical problems. In view of the time required for delivery of the proposed high-speed storage element, the Chief of Ordnance gave early approval to the contract with Ampex Computer Products Company. After certain delays due to technical difficulties, the operational unit was delivered to BRL on May 15, 1961, at a total cost of $680,000, Including supplements, under Ordnance Contract No. DA-04-495-ORD 1500. The result¬ ing storage element represented a major step forward in computer components. As stated above, the advance was immediately incorporated Into other computer designs. Approval has been obtained to Increase the storage capacity to 12,288 words. Other BRLESC Features BRLESC was designed primarily for the solution of scientific problems In which high computational speed and high precision are required. It may be programmed to perform any task amenable to numerical methods of solution. The binary system Is used exclusively In the arithmetic unit of the machine. ThlB Is the system mentioned previously, in which decimal numbers (to the base 10) are converted Into binary numbers (to the base 2) which yields a long string of ONES and ZEROS. A BRLESC program will convert decimal Input information ^BRLESC is roughly 1/2 the speed of LARC and roughly 1/3 the ipeed of STRETCH 2 IBM 7090, which is 1/4 the speed of LARC and 1/6 the speed of STRETCH 26 Into binary form for rnmrutatlnnal nurnnaaa and that convert the results to decimal form for output, lor the convenience of the user. To supplement the high-speed storage ele¬ ment, magnetic drum storage units will be installed as back-up memory. It Is expected that the capacity of the drums will be about 35,000 words. BRLESC has facilities for reading cards, punching cards, reading magnetic tape, and recording on magnetic tape. A maximum of 16 magnetic tape handlers are directly accessi¬ ble to the programmer. Any two magnetic tape handlers, one drum, the cardreader, and the cardpunch may be operated concurrently under separate automatic controls. Access to Information by the computer is an Important aspect of Its value. Time Is re¬ quired to put Information Into the computer, and to print or otherwise record the results of its calculations. In fact, computers make the actual calculations so rapidly that the Input and output aspects can be troublesome, that Is, slow, tedious, mechanical motions of masses of stored data and Instructions. In the caBe of BRLESC, information may be transferred to the machine via punched cards or magnetic tape. The actual information read into BRLESC may be a straight binary number, a binary coded decimal number, a binary coded group of alpha¬ betic characters, or, broadly speaking, any type of binary coded Information that the pro¬ grammer desires. Another valuable feature of BRLESC Is Its ability to change addresses In Instructions by fixed amounts, automatically. A simple analogy Is the case of the village postmaBter who askB his assistant to put a certain circular In every pigeonhole postbox In the office. The assistant will not need to be told specifically to first fill box one, then box two, then three, and so on. One direction will be sufficient. A more com¬ plicated analogy Is the bank clerk making up a table of monthly payments on loans of various sizes. Interest rates, and repayment periods. If he Is capable, he will progress from one to another without requiring new instructions. After computing the payments for a 5% loan of $10,000 payable in 10 years, he will repeat the calculations for 5-1/2%, then 6% and for terms of 15, 20 and 25 years and so on. This feature of BRLESC, which Is called Indexing, permits the programmer to use the same set of instructions to process as many sets of data as he desires, simply by changing fha in/lav upln« Initaarl nl mortifying IK; WaaU overall Instructions. Hie details of modifying index registers, counting, or Jumping to a dif¬ ferent aet of Instructions, to cite a few examples, are sometimes referred to as "housekeeping.* BRLESC has been designed ao that most of this housekeeping work can be done concurrently with arithmetic operations. For example, while BRLESC is performing a single multiplication operation, as many as four "housekeeping* Instructions may be processed independently of the arithmetic unit, at a great saving of time in the overall computations. As Indicated, BRLESC operates In response to an internally-stored program of detailed Instructions. Arithmetic and logical operations can be performed on these Instructions, per¬ mitting Instructions to be altered In accordance with the results thus far obtained during the course of the program. For example, the com¬ puter might work on evaluating a complex elec¬ trical circuit, expressed In mathematical ternis, to determine what the value of current would be at a certain point X In the circuit. Let us assume that 5 amperes Is the maximum current value tolerable, In the actual physical case. The computer can be relied upon to examine the current value it computes, and do one thing if this value Is less than 5 amperes, or another thing If the value is greater than 5 amperes. In one actual case it was desired to determine whether a certain machine gun previously used on a tank could be adapted to mounting on a helicopter. A machine gun must have a sufficient recoil velocity so that between shots there Is enough time for the firing mechanism to be cocked and a new cartridge properly chambered. Recoil involves action and reaction between gun and its mount. Thus a gun mounted on a tank, on a heavy mass, will have a faster recoil than when mounted airborne fashion on a relatively light helicopter. The computer doing calcula¬ tions of recoil velocity waB able to appraise the various results obtained, and then make new calculations with new or modified Instruc¬ tions, automatically, based upon these initial results. The ability of the computer to modify Its own instructions, along with the Indexing feature, saves writing countless thousands of additional Instructions In complicated problems. BRLESC Potential What actually will BRLESC do for the Ordnance Corps and the scientific community ? It will permit the solution of problems which could never be solved before, due to the exces¬ sive amount of time or space required; and It i i i 3 27 will nrovide a precision not usually possible without the great pain of multi-precision arithmetic. BRLESC will be used in the compu¬ tation ot tiring tables and guidance control data lor Ordnance weapons, including missiles. II will handle interior ballistics problems, tor example, the behavior ot projectile, propellant, and launcher; stability and thermodynamic properties ot rocket propellants; reflected shock waves; vibration ot gun barrels; and flow of fluids through porous media. Terminal ballistics studies to be performed Include nuclear, fragmentation, and penetration effects, in such areas as explosion kinetics, shaped charge, ignition, and heat transfer. Ballistic measurement studies to be per¬ formed will include photogrammetry, ionospheric measurements, damping of satellite Bpln calcu¬ lations, reduction of satellite doppler tracking data, and computation of satellite orbital ele¬ ments. Other studies will comprise anti-aircraft and anti-missile evaluation, war-gaming prob¬ lems, linear programming for solution of Army logistical problems, probabilities of mine deto¬ nations, lethal and kill probabilities of mine detonations, and lethal area and kill probability studies of rocketB and guided missiles. History of BRL Computers At the beginning World War II, the Ordnance Department had the sole responsibility for pro¬ viding the principal scientific and logistic sup¬ port for the Army. The only scientific facility available to them for carrying out these experiments with weapons was the Ballistic Research Laboratory at Aberdeen Proving Ground, Md. Its computing group was staffed by a handful of well trained and highly skilled civilian employees of the Ordnance Department. The laboratory was re¬ sponsible for the preparation of artillery firing and aircraft bombing tables for the Army and the Army Air Corps. They also obtained experimental data of high accuracy and preci¬ sion, necessary to the computation of the firing and bombing tables. This group of scientists at the Proving Ground had available to them at the time an Important calculating device, the Bush differen¬ tial analyzer. This continuous variable calcu¬ lator had been Installed at the Proving Ground about 5 years earlier. This analyzer, consisting of ten Integrating units and two output tables, was an important mechanical aid to computation. Despite Its capability and value, the analyzer had several severe limitations. Probably the most severe ot these was the mechanical torque amplifier, which frequently failed toward the end of a long trajectory run with the loss of the preceding' computations. ENIAC (Electronic Numerical Integrator and Computer) In 1042 the United States was locked In bitter combat with the Axis Powers. It was Imperative that a faster calculation method be devised to provide the troops with firing tables for the many new weapons being developed. The Moore School of Electrical Engineer¬ ing believed that they could utilize electronics and develop a computing machine. The Ordnance Corps awarded them a contract for the design and construction of an electronic computer. In 1947 the completed computed was installed at BRL. The latest thing In computers at that time, the ENIAC, was a decimal machine utilizing 10,000 vacuum tubes, 1500 relays and hundreds of thousands of resistors, capacitors, and inductors. It had 30 separate units weigh¬ ing more than 30 tons. In calculating a 60- second trajectory, ENIAC completed the job in 30 seconds, half the time of the actual flight of the projectile from the gun to the target. EDVAC (Electronic Discrete Variable Automatic Calculator) The urgent need for an operational com¬ puter had made It necessary to freeze the engineering design of the ENIAC early in the game. It was agreed upon between BRL and the Moore School of Electrical Engineering at the University of Pennsylvania that, as work on ENIAC permitted, the design and construction of an Improved computer should be pushed forward. The EDVAC, with greater flexibility and better mathematical performance, was installed at BRL in 1949 and placed in opera¬ tion in 1950. The major features of this computer were: use of the binary system (rather than the 28 decimal system ot numeration that had been used in ENIAC), serial arithmetic mode (Im¬ proved meanB of transferring numbers from one part o! the computer to another), a four-address Instruction (permitting a total of 16 different commands to the computer), and duplicate cir¬ cuitry for check purposes. EDVAC was the first Internally-stored program computer to be built. With an internally-stored program device, the "pattern of Interconnections” Is set up by the computer itself, on command. The program at any given time can be recorded on magnetic tape, a form of “memory* for the computer. Reversing the process, the tape can be fed back Into the computer at any time and all of the previous programs or “Interconnections* will be reestablished. This is of obvious advantage when work on one problem must be momentarily suspended in favor of another, not to mention the simplicity with whlchprograms maybe modi¬ fied during the course of a computation, based on results obtained thus far. Thus the com¬ puter makes Its own decisions, according to what It has discovered. This represents a great breakthrough In computer design concept. Work on the EDVAC stimulated design and construction, by other groupB of a large family of similar computers. Including SEAC, DYSAC, MIDAC, FLAC, and the later UNIVAC's. Next In line of development was the ORDVAC, a parallel binary computer which In turn spawned a new group of computers - ORAC, ORACLE, JOHNNIAC, ILLIAC, SILLIAC, MANIAC, CYCLONE, ERA 1103 (UNIVAC Scientific), and IDM 701, that were constructed by many organi¬ zations In government, Industry, and education. These designs constituted little, if any¬ thing, new In computation design, but carried out existing design principles using the ever advancing technology of electronics. During the early 1950’s a major part of the scientific computational workload of the Western world was accomplished on these machines. ORDVAC (Ordnance Variable Automatic Computer) ORDVAC was constructed by the University of Illinois for the Ballistic Research Labora¬ tories at the Proving Ground, under a contract from the Ordnance Department. The machine was originally designed to solve the following types of problems: 1. Exterior ballistics problems such as high altitudes, solar and lunar trajectories, computation for the preparation of tiring tables, and guidance control data for Ordnance weapons, Including free flight and guided missiles. 2. Interior ballistics problems, Including projectile, propellant, and launcher behavior. 3. Terminal ballistics problems, Including nuclear, fragmentation, and penetration effects In such areas as explosion kinetics, shaped charge behavior, Ignition, and heat transfer. 4. Ballistic measurement problems such as photogrammetrlc, Ionospheric, and damping of satellite spin calculations, reduction of satellite doppler tracking data, and computation of satellite orbital elements. 5. Weapon systems evaluation problems, such as antiaircraft and antimissile evaluation, war game problems, linear programming for solution of army logistical problems, probabili¬ ties of mine detonations, lethal area and kill probabilities of mine detonations, and lethal area and kill probability studies of missiles. ORDVAC is a general purpose computer capable ot carrying out individual arithmetic operations at high speed using a parallel binary number system, in an asynchronous manner. Originally, the ORDVAC operated with an electrostatic storage unit. This has since been converted to a magnetic core storage unit, with Increased speed and capacity, Bibliography BRL Memorandum Report No. 1378, “A Brief Description of the Engineering Character¬ istics of the BRL Electronic Scientific Computer* BRL Memorandum Report No, 1379, “The Instruction Code for the BRL Electronic Scientific Computer (BHLESC)’ Ordnance, January-February 1961, “ENIAC Story” ■ 29 COMPUTING CENTERS RECORDING PHYSIOLOGICAL MEASURE¬ MENTS TOR DATA PROCESSING- NATIONAL BUREAU OF STANDARDS, WASHINGTON 85, D, C. A method for using computers to study the reactions of the human body to psychological stimuli has been developed at the National Bu¬ reau of Standards. The method employs equip¬ ment that accepts simultaneous, rapidly occur¬ ring psychophyeiological measurements in analog form, converts them to digital form, and records them on magnetic tape for later com¬ puter processing. The electronic circuits to drive and Interconnect a standard analog-to- dlgltal converter and recorder were designed for the Air Force Office of Scientific Research by a team which included E. S. Sherrard, of the NBS data processing systems division and Herbert Zimmer, psychologist at the University of Georgia. Although Intended to record the responses of subjects in a continuing psycho¬ logical investigation, this equipment can be use¬ ful for multichannel recording in many biologi¬ cal applications which yield rapidly changing analog data. Such applications include studies of psychological conditioning, reactions to drugs, and autonomic responses to emotions and situations. Studies in experimental psychology often require measurements of subjects' reactions to psychological stimuli. Where autonomic re¬ sponses are being studied, (ha subject may be unable to describe or time the stimuli or to appraise objectively hie responera, sums of which he may nut even be aware of. Ftr jrdlng several slmultanvouely occur ring end some¬ times rapidly changing reactions has been isie of the technical problems In the etudy ui auto nomtr reectluns. Medlrsl Instrumentation has provided transducers to measure autonomii conditions ot thi human lusty, but s weans recording the dels tm Ictei study end (shuts tloii lies been uended Use id a poivgtapli, sui li us s "In ityiui tm has filled Ills IS ul dill* need In sunn- i »«••• This Instrument records Itodv ies|sin«ea t- hmi I. of S Bel les id ellwcull (qm nlli.io. |ini i- iln m l JecO as me Saul entente Into-,I dlt i"Mi hi moving lull Id g< itpii papii |d« el I speclloli id tlw isapotisne >d oeln id> t- Tlte lattulstlnn id these detu In nn ' I. in reqult emeiils i null! Ih iii ■ i'Hi|il' ' .. latter, Itul the lew dels kntiplo-.' . n limit llUl't'IS WtlUUI ilSln It: ill (lilt III >il*lllil I I 1,1 11: t compute i ose The converter-recorder method was de¬ veloped to record, for later statistical treat¬ ment, paychological data (abbJect reaction! to visual stimuli gt - nat 30-sscond Intervals) acquired on a proodctlon-line basis. It scans the continuously meaeurlng transducers r* a 0.1-second repetition rate; since auccees' re converted readings for any analog channr i show little change they are, in effect, contlmr usly presented meaeurementa. The record for each stimulus consists of measurements during the 20-second irast-stimulus period, which are compared against the baseline supplied by measurements of the same conditions during the 10-second pre-stimulus period. Analog Data Handling The converter-recorder will handle eight channels of analog measurements and two channels of nulse-coded session and time Iden¬ tification .U. The following physiological condition* are measured by the transducers used: Skin resistance, respiratory movements of the chest, respiratory movements of the dia¬ phragm, Integrated muscle action potential, time Interval between R-spikes of an electro¬ cardiogram, pulse amplitude, skin temperature, and integrated ahifts of body weight. The analog signal in each channel la am¬ plified by a preamplifier selected or designed for signals having the characteristics of that analog measurement, Six of the analog signals are also presented continuoualy on a strip- chart recorder for on-the-apot observations and Initial equipment adjustments. Conversion and Digital Recording Ruth analog data end the digital session end time dais ere scanned by the converter at a IU milileerond-per-channel rale to convert <-«i h main* channel to an li-bit binary-coded digital atgnsl The II bits of digital Informa- i inn tm x b analog channel can accommodate biiogial numbers from -1024 to * 1024 for a •ci" «entered rang*, for example. The digital signals nMalhml are buffered and again con¬ 'd ted, <iiia time lo a maximum of five words •d IS binary digtla each, thi a Information is supplied 1,1 a diode aelector matrix via 160 leads, I ln diode eeieclor matrix functions to con- iih 1 sui eeasive groups of six digital lines to Hie »u parallel heads which record the digital in r aienals on mairnatir tape ThP motrlv ho« a format of five words, each with six characters of six bits each; It is scanned at a character rate of 300 cps to attain a word rate of 10 per second. The six channels of information plus one channel for parity check are recorded on halt- inch tape driven continuously at 1.5 inches per second. The tape transport used accommodates 10-inch reels for recording 12, 1/2 hour experi¬ ment sessions - a full word day. The seven-channel recorded tape is the end- product of the data converter-recorder; the In¬ formation recorded on it is ready for use by a digital computer. In Its preparation, the pres¬ ence of an operator Is required only for initial checkout of the equipment, selection of the film strip which serves as the stimulus, and attach¬ ment of the transducers to successive subjects. The treatment of these data by a digital com- pu'er can eliminate all repetitive manual com¬ putation and minimize steps needed for statisti¬ cal analysis. Analog-to-digital converters and digital recorders are used for a variety of projects, especially where statistical treatment of the data is to follow. The present converter- recorder will be useful for recording several simultaneous channels of continuously read analog data, or mixed continuous and discretely quantized information (analog and digital), pro¬ vided only that the reading repetition rate is compatible with the greatest rate of variable change. The 6-hour duration of a single reel of magnetic tape makes It particularly convenient to record and store a day’s measurements. NEW COMPUTING SYSTEMS—ORDNANCE TANK AUTOMOTIVE COMMAND, DETROIT 9, MICHIGAN The Ordnance Tank Automotive Command (OTAC) has pressed the start button on OTAC’s second generation electronic computer system. This action put computers to work for two new agencies using a Department of Defense-wide system and on eight new OTAC jobs, The new equipment, RCA 501 and 301 systems, will be capable of doing twice the work of the old com¬ puter at two-thirds the cost. The new computer system will: —v*. »*• tiav uvivimw <*utouiuurc Supply Center's (DASC) annual program of about $200 million. 3. Prepare the procurement package to be eent to bidders and make preliminary bid evaluation. 4. Keep industrial readiness records and data necessary to buy approximately 1200 iank- automotlve items monthly. 5. Analyze vehicle performance on the 1 million OTAC vehicles in the field. 6. Analyze Internal cost and keep track of cost and deliveries on contracts. 7. Expand OTAC’s computer system to provide support to DASC to supply manage 184,000 supply items, such as engines, tires, tubes, etc. - an inventory valued In the neigh¬ borhood of $800 million. 8. Fill approximately 3500 supply requisi¬ tions daily from Army, Air Force, Navy, Marines, and MAP countries. 9. Reduce processing time on high priority requisitions from 3 days to within 2 hours of receipt. 10. Print Supply Catalogs for the 266,000 Automotive Supply Center items. 11. Prepare $46,000,000 annual payroll for 6500 people, 12. Keep personnel records on 6500 people, including operation of the promotion program. The new Mobility Command (MOCOM) will be composed of eight major field installations, including OTAC/Detrolt Arsenal, operated by a total of over 12,000 military and civilian per¬ sonnel. MOCOM will manage the whole spec¬ trum of mobility equipment from research and development through production of over 238,000 separate Items - well over half of all the items of the Army Materiel Command as a whole. The Automatic Data Processing System (ADPS) in OTAC Headquarters will tie together the MOCOM program to be carried out in the following field installations; i 1 1 < ! 1 t . 1 I j 1 [ 1. Control the Mobility Command’s pro¬ jected annual program of about $2.5 billion. 31 1. OTAC/Detrolt Arsenal , with 5226 per¬ sonnel, and its responsibility for development, production, and procurement of tank-automotive ii fidsfe&u rsfc- aqulpmont. Including tanka a«1(>nrnna1lad artll. lery, personnel carriers, trucks, trailers, and commercial vehicles (or the Department o( Defense. 2. General Supplies and Supply Control Offices. In Columbus. Ohio, with 328 personnel. Is the National Inventory Control Point and Na¬ tional Maintenance Point (or general supplies- type equipment, including materials handling equipment repair parts. 3. General Supplies Procurement Office , Columbus,Ohio, staffed with 194 personnel, procures general supplies-type equipment, 4. Engineer Maintenance Center , Colum¬ bus, Ohio, with ITT7 personnel, is the National Maintenance Point for engineering equipment- construction machinery and electric power generating equipment. The Center Is alBO the National Inventory Control Point and Stock Con¬ trol Center for repair parts support for assigned Items. 8. Engineer Supply Control Office , St. Louis, Missouri, with 798 personnel, Is the National In¬ ventory Control Point and Stock Control Center for engineering equipment, including construc¬ tion machinery and electrical power generating equipment. 6... Engineer Procurement Office , Chicago, Illinois, with 280 personnel, procures engineer¬ ing equipment, administers contracts, and io responsible for technical surveillance of con¬ tract specifications. 7. Aeronautica l Agenc y and the Surface Transportation Agency , SI. Lauis/Missouri, are staffed by a total of 2218 personnel, with small elements In the Transportation Research and Development Office at Fort Eustls, Virginia, and the Aero Test Laboratory at Fort Rucker, Alabama. The Aeronautical Agency is respon¬ sible for procurement, Inventory control, and maintenance for all aeronautical equipment, Including observation, utility, and transport air¬ craft. The Surface Transportation Agency manages the procurement, Inventory, and main¬ tenance of amphibian, rail, marine craft, and overland trains, 8. Engineer Research and Development Laboratory , Fort Belvoir, Virginia. with 1775 personnel nas the responsibility for research, design, development, and product engineering for construction machinery, electrical power generating equipment, and related items. Th« artalvAiH nf vphirl* nprfnrmnnnp will provide feedback data to research and engineer¬ ing elements to Isolate design problem; indus¬ trial elements to Improve production and pro¬ curement through isolation of production, inspection, and/or testing problems; Bupply elements to isolate maintenance problems, determine feasibility of maintenance versus replacement, and analyze economies of main¬ tenance. The data will be used to project prob¬ ability studies to create new shapes and char¬ acteristics for vehicles. For example, based on these data, a determination might be made to change design and production characteristics to allow a 20,000-mile experience before major maintenance 1 b required. An example would be the analysis of cer¬ tain type of springs on certain types of terrain. For example, desert terrain might result in such poor performance that a decision to use a different type of material might be made. This historical data can be used to establish new ground rules. OTAC might decide to build a spring for this terrain with the probability of going 15,000 miles before requiring any kind of maintenance. Computer simulation of perform¬ ance before production will permit the design to get into production much more rapidly than possible with design models and tests. This technique will save time from design to use and will permit more accurate initial design. The now computer system performs the following Supply Actions: Determines customer priority Checks availability Checks location Reduces balances Records Inventory Flags danger levels Redistributes stocks to depots (leveling) Triggers procurement action Controls procurement deliveries and dollars Produces shipping instructions Publishes changes to Armed Forces users Establishes supply needs Prices all actions. The first generation, the RCA BIZMAC 1, used since 1956 to manage OTAC’s 80,000 item inventory, saved the government millions of dslliia by eliminating duplicate requisitions and speeding supplies to the troops. It enabled Ordnance Tank-Automotive Command, never before able to fill Army Requisitions in the re¬ quired three days, to process S3 percent of the requisition on time. The new system will save even more be¬ cause it will extend the area of use. In addition, prorating the Initial cost of BIZMAC over the years of operation at OTAC and the annual maintenance figure, the cost to the government averaged more than $1.5 million a year. The new equipment will do twice the work of the old system at two-thirds the cost. MATHEMATICS DEPARTMENT-U.S. NAVAL ORDNANCE LABORATORY, WHITE OAK, SILVER SPRING, MARYLAND On the last working day of December 1961, an IBM 7690 was turned over to the Mathematics Department at NOL. This machine replaces an IBM 704 which had been In use at NOL for over 3 years. The computer configuration Includes eight magnottc tape units (one switched over from the 1401 system) and the cathode-ray tube output unit which had previously been installed on the 704. The transition was smooth since most of the workload hud been converted to the new system before Its installation. Since the installation, two changes in the computer configuration are contemplated, First, three additional tape units will be Installed on the 7090 and one additional unit will be Installed on the 1401 system, The reason for this Is that many of the larger problems are being penal¬ ized by the small number of mugnetlc tape units, Compile and run has nut been possible mid full advantage of the simultaneous Input-output could not be appreciated. Those units are expected to be Installed In June 1902. Second, the cathode- ray tube will be removed due to the high cost und low utilization of this unit. It is planned to linndlo the plotting load on other plotters In the Laboratory and by renting small amounts of time from other Installations. The ert unit is due to bo discontinued In June 1962. ANALYSIS BRANCH—U.S. NAVAL UNDER¬ WATER ORDNANCE STATION, NEWPORT, R. I. The IBM 660, until recently the workhorse ol' the computing section, has been replaced by an IBM The zystiui presently in use IS composed of the central processor with floating point, card input-output, and 60K positions ol core storage. The computer is used primarily tor scientific computing in support of the BAD groups, and for processing data relating to weapons testing, Magnetic tape units will be added (September 1962) primarily to aerve aa Information storage tor propulsion test data. The present computer is being operated on u full one-shift basis. Off line peripheral equip¬ ment includes a full assortment of keypunches, sorters, 407, etc,, as well as an oscillograph reader, film reader, and an electro-plotter. Assistance to other naval activities lr, the Narragansett Bay area ts provided, aB required, on an overtime basis, COMPUTATION CENTER-U.S. NAVAL WEAPONS LABORATORY, DAHLOREN, VIRGINIA Stretch A site Is now being prepared for Installa¬ tion of an IBM STRETCH computer In late summer 1962. The system will Include 48K core memory, u disc file, and 10 tape units. The STRETCH replaces an IBM 7090 which hus been moved to another building for use, along with an additional 7090, in the Naval Space Surveillance system. Operation of the NORC will be continued. It 1 b expected that STRETCH time will be available for use by other government agencies mid government contractors. Inquiries for such use should be dii ected to Head, Computation Division, Naval Weapons Laboratory. High-Spood CRT Printer The high-speed printer mentioned as under construction In a previous Issue of this News¬ letter, Is now in regular operation. Connected to an IBM 1401, this printer records on 35-mm film the data from output tapes of a 7090, STRETCH, etc. Output may consist of alpha¬ numeric characters or plotted point graphs; format ts controlled completely by the tape and/or the 1401 program. Printing speeds up to 16,000 characters per second are attained. Hard copy Is reproduced from the film by moans of a Zcrox Copyflow machine. 33 r f vi.iur SBrRBjiu-t_i e W*tiy DAVID " TAYLOR MODEL BASIN, WASHINGTON 25, D. C. FLAME, a flexible, three-spatial- dimensional, few-energy group (up to 4), nuclear reactor depletion code has been programmed for LARC at the Applied Mathematics Labora¬ tory of the David Taylor Model Basin. The need for such a code to assist in the prediction of the life-time behavior of water-moderated reactors has been outlined by E. M. Gelbard, G. J. Habetler, and R, Ehrlich In the Proc. 2nd U. N. International Conference on the Peaceful Uses of Atomic Energy Mi (1958). FLAME solves a finite-difference approximation to the few- group neutron diffusion equations, taking ac¬ count of interface and boundary conditions. As many as 100,000 network points can be treated. rLAmu la the fiiat pi ailliAi j/iugiam fur treat¬ ing problems of this magnitude. PERFORMANCE DATA FOR LARC SYSTEM- U.S. NAVY DAVID TAYLOR MODEL BASIN, WASHINGTON 25, D. C. The LARC System waB turned over to the Applied Mathematics Laboratory, David Taylor Model Basin, for operation in February 1961. Reliability testing was completed successfully In September 1961. Table I lists performance data for the year June 1961 to May 1962. When the system was turned over, the poorest reliability was experienced in the core memory and drum file sections. Performance totals for the drums tabulated In Table n show significant im¬ provement over the first 15 months of operation. Table I. LARC II Monthly Performance Figures Month Total ON Time Productive Time Down Time Total No. of Inter¬ ruptions Mean Error Free Time Down Time Per Error Performance Percentage Jun 61 203:24 32:16 85 2:43 ■ 87.8% Jul 61 471:00 336:16 69:04 151 2:13 ■ 83.0% Aug 61 556:00 383:05 112:02 186 2:05 36 77.4% Sep 61 368:47 27:54 86 4:18 19 93.0% Oct 61 309:02 217:05 15:08 37 5:51 24 93.5% Nov 61 332:20 243:42 15:09 37 6:35 24 94.2% Dec 61 330:23 223:47 35:41 50 4:28 43 86.2% Jan 62 352:53 249:32 43:06 79 3:30 33 85.3% Feb 62 414:05 357:31 23:49 64 5:35 22 93.7% Mar 62 514:50 429:04 37:18 61 7:02 37 92.0% Apr 62 454:29 383:07 21:44 73 5:15 18 94.6% May 62 411:06 311:18 29:14 86 3:37 20 91.9% Yearly 89.0% Totals 5069:18 3736:36 462:18 995 3:45 : 28 Table TI 3-Month Period Drum Down Time Repair Time per Failure March to May 1961 June to August 1961 Sept, to Nov. 1961 53:45 Dec. 1961 to Feb. 1962 30:10 1:15 March to May 1962 15:10 :45 34 A comparison of the last two columns of Table □ implies that the number of drum fail¬ ures has remained fairly constant. Most of the improvement has been due to the less catastro¬ phic nature of the failures and Increasing skill of maintenance personnel in returning the drums to operation quickly. Tables I and II cannot be compared directly, that is, the effect of drum failures on the over¬ all system operation cannot be obtained from Table □, because of differences in measurement, For example: /PerformanceN _ ''Total time LARC was avatlable\ ^ Percentage / " \ to run scheduled programs j x loo* , Productive Tim e V SSfiml / 100% Productive+Down Time In this calculation, Down Time refers to time when the scheduled program cannot run. Table II lists all Drum Down Time, that Is, all time charged against any drum In the system regard¬ less of whether a scheduled program can run without it, Since most programs make use of only a few drums during the check-out phase, the total drum down time does not necessarily appear In system totals. With large scale full- capacity production runs such as FLAME, the entire system is used and all Down Time is significant. COMPUTERS AND CENTERS, OVERSEAS SIEMENS 2002-INSTITUT FtlH ANGEWANDTE MATHEMATIK, JOHANNES GUTENBERG- UNIVERSITAT, MAINZ, GERMANY Three IBM 727 magnetic tape units and a 10,000-word magnetic core storage were added to the Siemens 2002 (see DCN, April 1959) transistorized digital computer at this institute. The Siemens 2002 in the form which is installed here now includes a 12,000-word magnetic core storage and a 10,000-word magnetic drum. LEO HI TIME-SHARING-LEO COMPUTERS LTD., LONDON, ENGLAND LEO III serial number 1 (see DCN, October 1960) has been Installed at the Company Head¬ quarters and number 2 has just been sent to South Africa to undertake work in association with Rand Mines. Fourteen of these medium size computers in the 150,000-350,000 area have been sold before the first one came on stream. This represents quite a success in England. A problem that often faces the computer user in organising commerical jobs Is that the data and results are large in volume, but that, the Arithmetic Unit is not fully occupied by the Input-output processes themselves. At other times the reverse may be the case, and the amouut of calculating time required to do a Job may far exceed the input-output requirements. LEO IH enables jobs of these two types to be run on the machine simultaneously so that a far better balance is achieved between the reading of data, printing of results, and the carrying out of various calculations. The advantages of the LEO HI system lies in the fact that the jobs are loaded and unloaded by the operators quite independently of one another and the program¬ mer need only concern himself with the Indi¬ vidual Job that he is writing. Any s»t of jobB can be run together provided that there Is suf¬ ficient peripheral equipment and storage avail¬ able. The grouping is thus at the discretion of the operator on the spot. Automatic Interruption and the Master Routine The key to the LEO IH system is the method of automatic interruption used to cause a switch between the various programmes operating at the same time. This efficiently provides a means of time-sharing. However, time-sharing is a system concept, not just a matter of hard¬ ware, and LEO has supplemented its machine interruption feature with an extensive operating and programming method which actually simpli¬ fies the work of the programmer and allows both operator and programmer to treat each programme as a completely self-contained entity. LEO deliberately allotted a separate development group to the project of preparing this software, because it was seen that without it the full advantages of the computer facilities offered would not be achieved by the user, The main elements of the software are the translator which interprets the programmers coding (Intercode) into machine language coding and the Master Routine. 35 The Master Routine lists the programmes running In an order oC priority. Whenever a high priority programme eennot continue be¬ cause an Item of equipment is engaged, the priority control section of the Master Routine causes control to be passed to the next pro¬ gramme in the priority list. When an item of equipment which caused a delay becomes free it signals the fact, automatic interruption occurs, and priority control tahes over and locates the top priority programme now free to continue. Special Checks and Precautions Various precautions have been taken to en¬ sure that the parallel operation of programmes does not result in any errors which would not otherwise occur. On the programming side, all the necessary features, such as tests or equip¬ ment readiness, are automatically Incorporated by the autocode translation routine; loading of the programme and allocation of store space is checked and executed under the control of the appropriate sections of the Master Routine. This ensures tiiat a programme is not loaded unless the necessary equipment and storage is free and so guarantees that there is no conflict between programmes. The Tag Reservation System As a further precaution against one pro¬ gramme altering the data or instructions apper¬ taining to another programme, the LEO Tag Reservation System enables each word in the computer store to be marked with a tag identi¬ fying its allotted programme. If a programme attempts to refer to a location outside its own store area, a special interruption takes place and the programme is suspended. The same feature is used to prevent input-output equip¬ ment from overrunning the buffer areas of storage to which they are required to work. The Demonstration The object of the demonstration is to show three programmes running together on a time¬ sharing basis, as follows: Programme A. Magnetic Tape to Printer Programme B. Paper Tape to Magnetic Tape including a sequenc¬ ing routine Programme C. Counting Programme. These programmes will run in the above order of priority with A taking precedence. The volume of data for each programme haa been so adjusted that each will run for approximately the same length of time when run together. Each programme will be firstly run by itself, then followed by a simultaneous operation. A comparison of the times tor programmes running separately and all three run together follows. The left-hand column, “% ACT* refers to the degree of activity of calculating unit of the computer, expressed as a percentage of the total running time for the programme, Table I Time Shared Theoretical Recorded A 12 6 min 41 sec 6 min 45 Bee 6 min 41 sec B 75 7 min 19 sec 7 min 37 sec 7 min 28 sec C 100 2 min 30 sec 9 min 6 sec 8 min 38 sec The theoretical running time has been cal¬ culated by taking into consideration delays caused by other programmes sharing input and output channels or the calculating unit. These calculations are approximate and the actual figures quoted above depend on the skill with which individual operators carried out the various runs. When all three programmes are running together, the running efficiencies of Pro¬ grammes A, B, and C are calculated to be 99, 96, and 12 percent, respectively. On completion of Programme A, Pro¬ grammes B and C continue and their theoretical running efficiencies are calculated to be 99* and 24 percent, respectively. From these figures, when time is shared the theoretical running times are calculated to be those shown in Table I. The top priority programme does not neces¬ sarily operate at 100-percent efficiency be¬ cause there is a very small overhead of time spent by the Master Routine in carrying out its supervision functions, 36 ht .u wr- LEO COMPUTERS, LTD., LONDON, ENGLAND LEO m (see LEO Ill Time-Sharing, this issue DON) has been designed as a general pur¬ pose computer lor application to a wide range of business problems. It has been built on the modular principle with the main frame, individ¬ ual blocks of storage, and input and output chan¬ nels all physically separate, so that a wide range of different assemblages can be formed to suit different needs incorporating standard parts. Experience has already demonstrated that LEO in is admirably suited to the needs of a wide range of organisations. However, for users who have very large volumes of work in¬ volving lengthly calculations or calling for simultaneous execution of several jobs, a LEO HI/F can be provided with faster arithmetic circuits and a store with quicker access ele¬ ments. The latter can have a store cycle time of 2.5 or 6 microseconds according to need. The resulting overall speed of arithmetic opera¬ tions is respectively 3 or 5 times that for the standard model. To ease the engineering problems of work¬ ing at the higher speeds, the design of the equip¬ ment is more compact and has resulted in a re¬ duction of two cabinets for housing the main frame. As is to be expected however, the cost of the faster circuitry is greater than for the standard computer; for example, for a store of 4006 long words with cycle time of 6 micro¬ seconds the main frame will cost about 25 percent more. The logical design of LEO IU/F is fully consistent with that of the now standard system, Inasmuch as completely standard assemblers are used. Any new assemblers which may be announced later for the standard model will be suitable for the faster one and vice versa. The instruction code is the same as that of the standard LEO in. Full programme compati¬ bility is thus assured. As in the standard model, both mixed radix and binary arithmetic are provided. Floating¬ point arithmetic in binary is fitted to all LEO HI/F models. The equipment Is planned to be available early in 1964. LEO DOCUMENT READER-LEO COM¬ PUTERS, LTD., LONDON ENGLAND The LEO Document Reader to a relatively simple and cheap machine for the automatic reading of handmarked documents. Many suggestions have beer made for the automatic reading of data recorded by cash r> <lsters, adding machines, and the like, as recognisable printed characters or as holes punched in paper tape or cards. Such recording equipment is relatively expensive, and so are reading machines tor printed or typed characters. So far there are no machines available (or read¬ ing handwritten characters. We feel that in many cases it is desirable to be able to produce an automatically readable document simply by means of a pen or a pencil, without any expensive or cumbersome equip¬ ment. This would enable, for instance, a sales¬ man in the field to take orders without having to carry around with him a portable typewriter or punch. Generally, it Is more convenient end also cheaper to use a pencil or a ball-pen In¬ stead of a typewriter or an adding machine. S-ch a handmarked document subsequently can be read directly Into a computer. Investigation of various data preparation jobs leads us to believe that documents properly designed for handmarking can be most effective, and that in many cases handmarking can be just as easy and convenient as handwriting, some¬ times even more so. Suitably designed hand- marked documents are easier to read auto¬ matically than typed characters, and a machine for reading marks can be produced more cheaply than a character reader. The LEO Document Reader has been de¬ signed for a specific application, namely the ordering and dispatching of bakery products ior a considerable number of retail shops. However, It can read a great variety of different forms, provided they are of a suitable size and have the specified arrangement of columns and rows. A typical form is shown In Fig. 1; the marking is done simply by drawing a line con¬ necting ihe two dots of the required square. Ball pen or pencil (preferably grade HB or B) may be used. A form may have up to 16 verti¬ cal columns and up to. 99 horizontal rows of squares, the significance of each column and row being clearly designated. 37 c/21 BAKERY RAILS ORDER FORM J. LYONS a COMPANY LTD. Figure 1 Columns are spaced four to an inch; mini- it is sufficient to smudge it so that it fills the mum row spacing is six to an inch. Forms may fop half of the square, or at least extends be- be from S to 10 inches wide and from 4 to 18 yond the upper location line. This method is inches long. effective because the signal results from the boundary between light and dark rather than Pairs of horizontal lines at the right-hand from the centre of the dark area, end of each row are location marks which define the scanning period for each row. The mark Handmarked documents tend to become drawn between two dots in a square must be dirty. While a proper mark produces an am- sufficiently straight to remain within the two plified output of the reading photocell of more location lines. If it is desired to erase a mark, than 20v, a smudge or fingerprint may produce 38 up to ISv, Similarly, a week mark may produce something like ISv. To cope with such border cases we Introduced the concept of a doubtful mark. When a doubtful mark occurs, that is when the output of any reading cell is about ISv, the machine stops, and an alarm light on the control panel indicates the respective column. The operator then examines the line of marks being scanned through a veiwing window, decides whether the doubtful mark is valid or merely a smudge, and restarts the machine by pressing one of two buttons either to accept the mark or to Ignore the smudge. However, in order to speed up the procedure we are going to change this arrangement. In future the row in which a doubtful mark occurs will be automatically marked and the form ejected into a reject box without stopping the machine. At present our Document Reader is coupled to a tape punch, so that the information scanned from the document is punched into tape. How¬ ever, it is possible to provide a facility to punch the information into cards, or to feed it directly into the computer. At present the documents are fed through the Reader at a speed of 20 Inches per second. Each time a mark has been sensed the paper stops and punching commences. Using a 110 characters a second Teletype punch, the punch¬ ing of each line takes about 60 msecs. Actually for each marked line on the form we punch on the tape three rows of Information, two rows for the line number, and the NUMBER END indica¬ tion. For a foolscap form with IS lines marked, the total time taken for reading and punching is about 2-1/2 seconds, or approximately 1440 forms per hour. This is approximately 32 times faster than handpunchtng and verifying. The end of the form is sensed by the ma¬ chine as a wider gap between the last two loca¬ tion marks. The Document Reader then punches a BLOCK END character followed by five blank rows. This blank space helps the visual identi¬ fication of forms on the paper tape. When the end of form signal is detected, the number of lines counted is compared with a preset number. In case of disagreement the form is'ejected, and the machine punches five rows of all holes, five rows of blank tape and a BLOCK END character. The proper functioning of all reading photo¬ cells is automatically checked after the passage of each form. The experimental Document Reader was used for a 8-month trial run on orders actually taken by travellers. Following this, It read documents continuously tor 2 days. Out of many thousands of marks on the documents0.3percent gave doubtful mark alarm. Not a single mark was missed. On the basis of this experimental machine an improved version has been designed and made as a pre-prototype machine. Production ma¬ chines are expected to be available towardB the end of 1062. The LEO Document Reader is merely an optical mark-sensing machine; It is not a character reader. We make no apologies, be¬ cause we are sure that our machine does help in many cases to solve the problem of data preparation. Further developments of our Document Reader are directed towards speeding-up, direct use on-line, recognition of printed marks produced on a high-speed printer, improvement of marking accuracy, and the use of continuous stationery. AN ARTIFICIAL LANGUAGE FOR INFORMA¬ TION RETRIEVAL-NATIONAL PHYSICAL LABORATORY, AUTONOMICS DIVISION, T EDDINGTON, MIDDLESEX, ENGLAND The ACE computer is being programmed in an experiment to construct an artificial language to be used for the Indexing and re¬ trieval of information. This artificial language will consist of overlapping groups of statistically related key words. A many-one transformation will map statements in natural language on to corresponding statements in the artificial lan¬ guage. It is hoped that, In this way, sets of state¬ ments in natural language that would normally be regarded as being equivalent (e.g., differently worded requests for information on a given topic) will be mapped on to the same statement in the artificial language. The ACE program will analyse a large quantity of scientific text and obtain the fre¬ quencies of occurrence of keywords and of pairs of words occurring within the same context. By applying a tesi of statistical significance (e.g., chi-squared test) the statistically related pairs of words will be found. The keywords will then be grouped In various ways on the basis of this information. The word groupings thus obtained will then be evaluated and compared by using them in an experimental indexing and retrieval system. 3S High-Speed Computing The work of the High-Speed Computing Group of the Autonomica Division hits been con¬ centrated on a atudy of the potentialltiea of the thin film cryotrons formed by vacuum deposition. Studies of thin films of tin have shown that both the superconductive properties and the crys¬ talline structure are strongly dependent upon the conditions of formation of the film. It is of par¬ ticular Importance to reduce the partial pres¬ sures of oxygen, water vapour, and carbon dioxide during deposition. Close control of the substrate temperature and the rates of vapour deposition are also essential. Simple cryotron circuits of tin, lead, and silicon monoxide Insulator have been tested and their time constants have been found to agree with those predicted from a knowledge of cryotron normal resistance and circuit induct¬ ance. It should be possible to reduce the cir¬ cuit time-constants by a factor of 10 when a really reliable thin film Insulator Is found which will stand repeated thermal cycling. The next stage in the work Is the making and testing of more complicated circuits such as shift registers. The liquid helium cryostat already in use will hold at least 20 substrates each 4 inches square. Impedance matched inter¬ plane connections will also be studied. Character Recognition Work is being carried out on a multi-font reading system based upon a feature description of a character. An auto-corrslation process la used to detect the orientation, length and posi¬ tion within the character, of straight lines and curves. The use of auto-correlation permits detection of theae properties independent of the poeitlon and orientation of the character. The range of application of the approach ie being Investigated with an oi/tical system using photo¬ graphed copy in transparency form. The prin¬ cipal problem here Involves the choice of a small number of auto-correlation functions which adequately deacribed the characters to be recognised. The need to evaluate any specified auto¬ correlation function for an opaque pattern, has led to the construction of a prototype reading device. This consists of a flying spot scanner feeding analogue networks which compute a restricted class of auto-correlation function. It la expected to read any single Btyle of numeral at a high speed. References M. B. Clowes and J. R. Parks, *A New Tech¬ nique in Automatic Character Recognition,” The Computer Journal, 4, 2, 121 (1961) M. B. CloweB, “The Use of Multiple Auto¬ correlation in Character Recognition,” Pro¬ ceedings of the Symposium on Optical Character Recognition, January 1962, Washington, D. C. (in press, Spartan Books, 6411 Chillum Place, Washington 12, D. C.) MISCELLANEOUS MULTI-FONT CHARACTER RECOGNITION— CORNELL AERONAUTICAL LABORATORY, INC., BUFFALO, NEW YORK During the past 6 years Cornell Aeronau¬ tical Laboratory (CAL) has been engaged in a continuing program of pattern recognition re¬ search. Recently a portion of this work, sup¬ ported by the Office of Naval Research, has turned toward the application of the perceptron class of pattern recognition devices to such useful tasks as the recognition of printed characters in machine scanning of business re¬ ports or tax forms. The overall program is based on numerous pattern recognition systems and concepts, including those derived from the early perceptron work. Objective: Recognition of Imperfect, Mixed-Font Characters The objective of CAL’s current program is to investigate computer concepts for recogniz¬ ing imperfect printed characters of varying type faces, i.e., mixed fonts. Supplementing analytical studies, a highly flexible general- purpose computer Implementation of a recogni¬ tion system is employed. This research was stimulated by earlier experiments with the Mark I perceptron, which demonstrated the ability of such a unit to recognize a complete alphabet with a limited amount of distortion. The same machine was used to establish the fact that recognition of limited sets of the alphabet could be accomplished, with proper 40 training, using a large amount of distortion, translation, and noise To illustrate multi-font characters, Fig, 1 shows the first seven letters of the alphabet in both lower and upper case In three of the fonts used In recent studies. Upper-case letters are recognized as distinct from lower-case letters, since there may be significant Information con¬ tent in the fact that a letter is upper or lower case, Figure 1 illustrates the marked geo¬ metric differences in the three fonts selected, The first font, taken from a Buffalo newspaper, la a bold type using a minimum of serifs or detail. The second font, which was taken from a second local newspaper, Is an italicized type with serifs and more detail Incorporated. The third font contains the well-known addresso graph characteristics. To get these undistorted letter samples, considerable retouching had to be done to eliminate a large amount of noise and distortion^Inherent in the available samples. The formation of the lower case “a” in the three fonts is markedly different, with the second font Incorporating no upper loop in the formation of tho italic “a.* Throughout the alphabet, simllar variations from one font to another can be observed. The types of noise and distortion incorpo¬ rated in the samples as part of this program are illustrated in Fig. 2, which shows typical imperfect characters in the three fonts. In some cases the distortion is that of background noise produced by the paper; in other cases the noise is that of geometric distortions of the character produced by the method of making the impression. a b c d e f g a b c d e f 8 a b c d e f g A B C D E F G ABC DEF G A B C D E F G Fig. 1 I i 4 I * 5 b t 5 mb b t 4 5 i»t w a 6 7 8 9 c | e f g is l w n 6 7 8 9 e d * f s js l in S 7*9 Fig. 2 Experimental Facilities Since it was intended to implement pattern recognition devices in a general-purpose com¬ puter (IBM 704), a means of Inserting pictorial material Into that computer was necessary. For this purpose, the system shown in Fig. 3 was constructed. The output of a commercially available facsimile machine was converted to digital form for insertion into the real-time package of the 704, The facsimile machine was modified to provide special synchronizing sig¬ nals used by the control system to coordinate reception of the 704 successive binary words representing image density. The result of processing an undistorted lower case “a* from one of the type fonts into the 704 is shown in Fig. 4. The figure is the result of making a printed readout from the tape memory of the stimulus in the machine. Although the Input sys¬ tem produces 16 gray scale levels in the 704 from photographic material, the output in this case has been thresholded to produce a binary output. 41 outputs are statistically independent. Since the second assumption is not completely valid, the initial weight selection is not expected to be perfect. However, these assumptions do pro¬ vide a means of shortening the training cycle, and expeditiously deriving the weights neces¬ sary to the design of a practical machine to recognize printed characters. Fig. J CCWHfCTIOHt CONNICTIOM THROUGH «IIC«U THROUGH VARIAILt Fig. 4 Procedure for Establishing Initial Weights Normally it Is not known at the outset what the variable weights should be. Several train¬ ing routines were proposed and used in the original perception research. They have been shown theoretically to converge to a solution (correct classification) if a solution exists. As the number of different patterns in the 0 and 1 classes and the number of dichotomies which must be achieved Increase, the training time can become rather long. For example, to recognize uniquely all the upper case and lower case letters together with the numerals and a reasonable set of punctua¬ tion marks, it would be necessary to expose the machine in training to over 70 symbols, re¬ quiring many exposures per letter during the training. To reduce training time a method for initially setting the weights, based on the use of Bayes’ theorem,* was hypothesized. It was necessary to employ some assumptions to make these Initial weight selections: (1) use Bayes’ rule, and (2) assume that the A-unlt ijc Classification based on probability densities and prior probabilities. First Results A 100-A-untt perception haa been trained to recognize six undistorted letters of the alphabet in both upper and lower case versions and In three fonts. In doing so, It was distinguishing each of the 12 distinct symbols from all fonts, upper and lower caBe, as well as all numerals. The significance of accomplishing this in a 100-A-unit machine can be appreciated by the following observation: although very few ex¬ perts doubt the ability of perceptrons to perform difficult recognition tasks, many have feared that a perceptron, designed to recognize many fonts in many complete alphabets, and upper/ lower cases, would be prohibitively large. The actual implementation of a 100-A-unit percep¬ tron would be very moderate. In fact, the Mark I, which was built using elementary con¬ cepts without any prior experimental model on which to base the design, had 500-A-units. The most exciting result of the initial ex¬ periments, however, was the finding that in every case (except one in which the threshold for the A-unit linear discriminator was placed too high) the initial weight selection produced a machine which required no further training. In other words, having gone through the Bayes’ rule computation of weights for the 100-A-unlt perceptron, the device properly classified all the undistorted examples presented to it. Thus, without any further training the machine gave a positive output for the desired positive class symbol, whereas exposure to every other letter of three font alphabets in both upper and lower cases and the 10 numerals, produced a negative output. This result was achieved with all 12 of the symbols to which the machine was trained. When the threshold for the A-unlts was made as high as three, however, four training cycles were required before completely correct classi¬ fication was achieved. For thresholds of two and one, the machine accurately classified its input Immedlatelyafter initial weight computation. In subsequent tests an R-unit was trained to recognize undistorted lower case n’s in several different positions In the input field. After this training, the machine was tested by having It 42 classify all of the letters and numerals in the distorted or noisy alphabets of the three type fonts. The results were quite encouraging, In that only 28 mistakes occurred in the classification of 186 characters - a 15-percent error ratio. Of these, one was an incorrect classification of a noisy n, and 27 were cases in which other letters or numerals were classified as an n. This percentage is also higher because the sys¬ tem is not complete. In a complete Bystem there would be an R-unlt for each letter or numeral. Relative outputs of all R-unltB prop¬ erly scaled, would be compared, with the highest positive output identifying each letter. There¬ fore, in a complete system, some of the 28 errors of mistaken letter identity would not have occurred because other R-unlts would have higher outputs than the output of lower case n’s. Future Experimentation As mentioned earlier, this is a continuing program and the results reported are prelimi¬ nary in nature. CAL plans to continue experi¬ ments exploring character noiBe and translation. In the course of this research, an increase Is. anticipated in the density of S- to A-unit con¬ nections from the 10 excitatory and 10 inhibitory connections employed in the Initial experiments. The results of subsequent experiments should suggest variations on the main line of research. CAL expects to explore these variations. HIGH-SPEED VIDEOGRAPH PRINTER- PLOTTER - A. B. DICK COMPANY, CHICAGO 48, ILLINOIS A high-speed electrostatic printer which simultaneously prints a permanent paper record of both alphanumeric data and analog curves at speeds up to 10 inches per second has been in¬ troduced by A, B. Dick Company. It is believed to be the first printer-plotter with these capabilities. The Model 9041 Videograph Printer-Plotter performs as an analog recorder, a digital page printer, or combines both forms of output. It operates on information received from a data acquisition system or from playback of magnetic tapes. Data is printed out directly on an 8-1/2- inch-wlde paper web. The Company also announced that the first production model of the printer-plotter has been purchased by the Rocketdyne Division of North American Aviation, Inc., along with an A. B. Dick Input Control System. The equipment will be used to record results of rocket engine testing. In addition to its high speed capability, the major advantages of the printer-plotter are high reliability, flexibility, and low operating cost. With it, film processing and printed forms are eliminated. Prints Through Cathode-Ray Tube The printing function of the printer-plotter is performed through a special cathode-ray tube having a matrix of fine metal wires permanently sealed through its faceplate. The electron beam of the tube is deflected and modulated by means of video-type electrical signals across the inner ends of the wires, while the outer ends of the wires are in contact with a moving web of paper. The paper is coated with a simple dielectric material which received latent electrostatic images directly on the surface of the paper. These charge patterns are made visible and permanent through a developing process. For alphanumeric printing, a special Video¬ graph Character Generator is employed to convert digital input signals into waveforms that are di¬ rected to the matrix of the tube to form character¬ shaped Images on the paper at high speeds. Through suitable control circuitry, the electron beam of the tube can be directed in a linear sweep by video input signals or driven in response to digitally coded input signals for • accurate point plotting. 3600 'Lines Per Minute As a page printer the unit prints out a for¬ mat of 72 columns with ten characters per inch, five to seven lines per vertical inch, at a rate of 3600 lines per minute. A manually operable cutting attachment permits selective cutting of the web into any output length. Output also may be rewound into roll form. Only manual functions required for opt.ra¬ tion of the printer-plotter are replacement of the paper supply roll and charging and replen¬ ishment of the developer. Controls are push¬ button type, with indicator lights. The unit is' approximately 54 inches long, 24 inches wide, 42 inches high, and weighs 750 pounds. 43 Input System Design Design of the input control system used with the VIdeograph Printer-Plotter depends on the specific application Involved. The complete system designed by A. B. Dick Company for Rocketdyne has the function of producing con¬ tinuous multiple curves or traces of test data obtained from a data acquisition system. In the data acquisition system, sensory instru¬ ments located at a test position will provide as many as 150 Inputs of analog information to a data control center. At the data control center, each of the analog inputs will be converted into a four¬ digit decimal number which will be transmitted in digital form to the printer-plotter output sys¬ tem for recording. AUTO-CORRECTIVE OPTICAL SCANNER- HONEYWELL EDP DIVISION, WELLESLEY HILLS 81, MASSACHUSETTS Honeywell Electronic Data Processing (EDP) has announced the development of an ex¬ clusive auto-corrective technique for use with its optical character readers that should re¬ duce to 0.2 percent the document rejection rate because of mls-scanning or defaced information. Document rejection rates generally accepted by the EDP industry In scanning operations range from 5 to 10 percent. Auto-correction la achieved in the Honey¬ well system through addition of two or more ortho-correction (checking) digits to the infor¬ mation on the document to be scanned. By means of these digits the scanner, linked to a Honeywell computer, automatically regenerates lost or damaged data. Documents remain readable to the scanner even though portions of the document containing the data have been de¬ faced. The correction process is accomplished without interruption and without rejection of the document. The technique represents a new, two-way approach to reliable optical scanning. The reading device has the ability to scan and re¬ scan any document any number of times, at high speed and without machine interruption. This compensates for temporary scanning failures - such failures as might be caused by a speck of dust on the document. The document acceptance rate, however. i« even more sub¬ stantially increased through the orthotronic regeneration of Incorrect or permanently de¬ faced data. The combination of orthotronic control and automatic re-scanning accelerates the input of data to the computer and effects a major improvement in (he percentage of docu¬ ment batches automatically processed by the scanner without manual Intervention. Test runs of orthotronic scanning at Honeywell’s EDP engineering laboratories were performed as follows: Batches of some 250 documents were pro¬ duced on a high-speed printer connected on¬ line to a Honeywell 800 Computer which calcu¬ lated and appended the ortho-digits to the data to be scanned. (The printing of these ortho¬ digits requires no additional time.) The scanner, connected on-line to the trunk system of the Honeywell 800, processed the batches with the orthotronic control capability Inopera¬ tive. The reject rate, after hundreds of runs, averaged about 8-15 percent, or 23 documents in each batch of 250 documents. In a conven¬ tional scanning system, each of these rejected documents would have had to be examined manually to determine the reason for the scanning failure. Re-scanning the same batches, with orthotronic correction, resulted in the doc¬ ument rejection rate dropping to 0.2 percent, which is less than one reject per batch. Returnable Media In the case of returnable media documents, such as invoices and subscription forms, the ability of the Honeywell computer to calculate and append the orthotronic digits to the data printed for scanning, provides “turn-around" documents to which no further information need be added for corrective purposes prior to opti¬ cal reading. However, a “mark-scan" option is available with the Honeywell computers for use in instances where additional information is to be added to “turn-around" documents prior to scanning. The Honeywell system is a breakthrough in optical scanning and is certain to have a marked impact on the future development and applica¬ tions feasibility of document reading. In other scanning systems any document that cannot be road correctly, regardless of reason, is auto¬ matically rejected by the scanner. These re¬ jects then require special handling. '''rthotronic-correction will be standard procedure with all Honeywell optical scanning systems, several of which are on order for delivery within the next few months. 44 THE M-2CR MBMXSTOR—MKMJBTOH CORPORATION, MOUNTAIN VIEW, CALIFORNIA A new electronic circuit element called the memlstor (a resistor with memory) is being manufactured in several forms by Memlstor Corporation for use In adaptive systems, thresh¬ old logic systems, analog systems, and hybrid analog-digital systems. The Memlstor consists of a conductive substrate with Insulated con¬ nection leads, and a metallic anode, all in an electrolytic plating bath. The conductance of the element Is reversibly controlled by elec¬ troplating. Like the transistor, the memlstor is a three-terminal element. The conductance between two of the terminals Is controlled by the time integral of the current In the third, rather than by its instantaneous value, as in the transistor. The memlstor is functionally equivalent to a transistor with a "built-in* integrator. The memlstor was invented at Stanford Uni¬ versity by B. Widrow and M. E. Hoff. Their origi¬ nal work was done under Tri-Service support, administered by the Office of Naval Research. Adaptive “Neuron* Circuits The memlstor was developed to provide simple, cheap, and reliable variable-gain elements with memory for adaptive threshold logic circuits. The ADALINE “neuron” con¬ sists of an adjustable threshold function and the adaptation machinery for automatically adjust¬ ing its weights. (This is described in Stanford University Electronic Laboratories Technical Report 1553-1 of June 1960, by B. Widrow and M, E, Hoff.) The structure of ADALINE changes Bomewhat with each training experience. A steepest descent method requires that each of its weights be changed by the same magnitude with each training cycle, some weights increas¬ ing, and some decreasing, depending on the state of the input signals and the desired output state. The memlstor allows a very natural implementation of such an adaptive process. A memlstor cell stores a single weight in the value of its conductance. Current sources of fixed magnitude are turned on simultaneously to plate the memistors, and they are sensed by ac-voltage sources. Their current outputs arc summed by a Kirchhoff adder. Information is stored in the memistorized ADALINE in terms of the thickness of plated metallic films. Very complex logic functions can be trained into threshold elements and networks of threshold elements, These will provide adaptive logic, “neuron* memory eystema with aaeociatlve information atorage and retrieval, pattern claeslflcatlon aystema with generalising capabilities, and reliable digital syatems that can adapt around their own internal flawa. All of these characteristlca and capabilities have been demonetrated, at Stanford with a machine called MADALINE which contains 300 memis- tors. MADALINE la currently being tested in a connection to an IBM 1020 computer. Analog ClrcultB Memlstor* have been used aa integrators, multipliers, modulators, pulae counters, time base generators, and In sample and hold cir¬ cuits. The Inherent characteristics of the de¬ vice, such ae long-term stability, relative in¬ sensitivity to temperature, linear relation between conductance and integral of plating current, ability to integrate long' pulses and extremely short pulses, low power require¬ ments, and compact size and weight, make it attractive for analog applications. M-2CJR Memlstor Characteristics Memlstor M-2CR can be plated over a resistance range from SOX? to 2fl, and covers this range in 10 seconds with a plating current of 0.2 ma. The plating potential is 0.2 volt, so the required plating power, is 0.04 milliwatt. Sensing the conductance without destroying the stored Information is accomplished with ac- voltage that could range in frequency from 60 cycles to several megacycles. The Integration of the plating current is accurate to within 5 percent, regardless of the frequency content of its waveforms. Pulses as short as 0.5 micro¬ second have been integrated. The M-2CR cells are ma'de in single units for analog applications, and in sheets of 10 or 20 for adaptive neuron applications. Those that are printed on sheets have had, at the same time, some of the resistors and interconnec¬ tions of the ADALINE element also printed. This is a first step towards completely inte¬ grated neuron circuitry, Each memlstor cell contains about two drops of plating fluid, and is encapsulated. The M-2CR is insensitive to shock and vibration, is non-microphonic, in¬ sensitive to temperature (taken from 100* to -196°C with no permanent change in character¬ istics), and exhibits less drift than 1 percent per week. As an electronic integrator, the time constant is of the order of several years. 45 At the present time, work is piogressing toward making these cells more accurate as analog Integrators (goal Is 1 percent), making them faster with less power, making them more stable, and reducing costs in volume pro' ductlon to make large networks of adaptive neurons economically feasible, At the present time, a rough figure for a completed neuron system, almost regardless of configuration, is about SO dollars per weight. Electrical Specifications The unit is an electronically adjustable resistor with the rate of change of resistance controlled by dc-current in a third electrode. Over the active range of the memistor, the rate of change of conductance is proportional to the control electrode current, and is essentially independent of the resistance value. The re¬ sistance range of the memistor covers from 30 ohms to about 2 ohms (0.033 mho to 1/2 mho). Three leads, brown, white, and red are provided (see Fig. 1), The resistance (of the substrate) is measured, using an ac-current, between the brown and white leads. The ac- voltage drop between these leads should not exceed Q.l-v rms. To decrease the substrate resistance, the red lead is made positive with respect to the brown and white leads. The average dc-current Into the red lead should not exceed 0.25 ma. The dc-voltage drop across the cell will be about 0.2 v. For a plating current of 0.2 ma, the rate of change of conductance is about 0.03 mho/sec (the resistance changes from 3012 to 2fl in 10 seconds). The resistance of the substrate may be raised by making the red lead negative with respect to the brown and white leads. Again currents should not exceed 0.25 ma, and the rate of change of conductance is the same. When the resistance of the substrate is set to its maximum value (completely stripped), a negative vollage connected to the red lead will produce relatively little plating current. The voltage drop across the cell should not be per¬ mitted to rise in excess of 1.5 v, or gas will be produced in the cell. When this voltage is removed and the red lead again made positive, the resistance will begin to fall immediately. However, when cur¬ rent tending to reduce the resistance below its OC 1 ohm minimum Is applied to the cell for a length of time, the current must be reversed and maintained for approximately the same length of time before the resistance will begin increasing. PHOTOCHROMIC DYNAMIC DISPLAY— THE NATIONAL CASH REGISTER COMPANY, HAWTHORNE, CALIFORNIA A contract for a photochromic dynamic display has been awarded to the Hawthorne, California electronics division of the National Cash Register Company by the Naval Ordnance Test Station at Pasadena, California. The display will be used to analyze com¬ puter data display requirements In real-time applications for advanced Navy weapons systems. The display provides real-time tracking through the use of slides coated with a molecular dispersion of light-sensitive, reversible photo¬ chromic dyes. Tracks appear on the slide when individual molecules of the normally transparent dye are switched to an opaque state by beams of ultra¬ violet light moving in response to input signals. These tracks, as well as background reference information, are projected onto the display screen. A unique feature of the display is that per¬ sistence of the opaque tracks can be varied by controlling illumination intensity, since high* intensity light returns the dyes to their trans¬ parent state. This property also allows the tracks to be easily erased. The $65,00" contract covers the fabrica¬ tion and installation of the display unit. 46 HOME-STUDY COURSE Df COMPUTER PROGRAMMING-PENN STATE AND IBM, UNIVERSITY PARK, PENNSYLVANIA The Pennsylvania State Univetsity and International Business Machines Corporation announced what is believed to be the Nation’s first university-sponsored home-study course in programming. The need for a course of this type is based on the extension of electronic data processing into almost every area of business, government, and science. Many computer users, facing a shortage of programmers, have set up their own training programs; but it often is difficult for them to find qualified people to enter the training programs. Students who complete this programming course with high grades will have indicated that they have the interest and aptitude required for this work. What kind of aptitudes are required for programming? A background in college mathematics is helpful; but a college background is considered less important than a keen analytical mind, capable of reducing complex problems to their component parts and perceiving the easiest, most direct solution. IBM has prepared a 12-part textbook for the course. A home-study guide, which helps fill the role of the instructor, has been pre¬ pared by Penn State. It advises the student how to get the most out of the course. The course covers the entire range of programming principles as they apply to all computers, from the smallest business com¬ puter to the most powerful scientific system. It introduces the student to the basic elements of data processing; explains the equip¬ ment, and takes him into the coding of a pro¬ gram. In more advanced sections, it covers technical subiects such as symbolic program¬ ming, address modification, branching, and other operations. The entire course is administered by mail. The teaching staff of the university supervises lessons and grades test papers. Final exami¬ nations are given by a proctor selected by the student in his home city. Students receive a final grade an a comple¬ tion certificate when they finish the course. Tuition, including all costs of handling the course, testing, and administration, is $24. Cost of the texi and mailing is approximately $ 10 . The programming course Is the newest in a series of correspondence courses offered by Penn State in cooperation with IBM. Among these are courses in punched card data processing principles and punched card applications. There are also courses in elec¬ tricity and electronics with emphasis on com¬ puter applications. Penn State has been giving correspondence courses, many for college credit, since 1012. Each year more than 10,000 home-study courses are given to an estimated 8000 students all over the world. A staff of 16 directs this complex operation. SYMPOSIUM ON OPTICAL CHARACTER RECOGNITION-15-17 JANUARY 1962, WASHINGTON, D. C. A Symposium on Optical Character Recogni¬ tion, held 15-17 January 1062 at Washington, D. C. under the joint sponsorship of the Office of Naval Research (ONR) and the National Bureau of Standards (NBS), was attended by more than 800 computer scientists and users from the United States and abroad. Plans for the symposium were made by a conference committee consist¬ ing of Donald K. Pollock (ONR), Bernard Radak (BUSANDA), and Mary E. Stevens (NES). Twenty- two papers covering both the operative and re¬ search phases of optical character recognition Bystems were presented in two sessions. This was followed by panel discussions of (1) user requirements for new systems, and (2) the ho¬ rizons of optical character recognition work. Many experts believe that the next great step forward in automatic data processing will come through the development of techniques for automatic character recognition. Data process¬ ing systems in use today require, as inputB, Information that has been carefully translated into the machine’s language and encoded! in a suitable medium. Only a few systems will accept information not already coded on cards or tape. One such system, F06DIC, develop? by NBS for the Bureau of the Census uses 47 optical sensing ot raaponaa placement in a for¬ mat designed to be self-coding. Another type of machine Identifies documents by magnetically scanning areas of numerals printed In a spe¬ cially dealgned typeface and with magnetic Ink. Present-day devices, a few in operation and others under development, can read one or a few fonts ot typed or printed material. How¬ ever, no reading machines with true multifont recognition capabilities are as yet In productive operation, and no devices are as yet available which can read handwritten material with the degree of success that would be accepted In many tasks as a reasonable substitute for the human reader. Today's data processing systems would be much more useful if they could accept a variety of printed, written, or graphic data as Inputs. The symposium was arranged bo that inves¬ tigators working toward this end might benefit from knowledge of developments and findings in other laboratories. In addition, potential users were invited to attend to permit an interchange of information with respect both to require¬ ments and to present-day capabilities. The Information thus shared should facilitate de¬ velopment of new methods of optical character recognition and speed the day when more flex¬ ible input systems will become available for data processing. The symposium was divided into two one- day and two half-day sessions. The first ses¬ sion featured talks on the characteristics of operative character recognition systems, given by people involved in developing them. The second session explored the trends In present character recognition research, while the third and fourth presented panel discussions on user requirements and the prospects for the future. The symposium opened with a welcoming address by M. C. Yovlts of ONR. The first session consisted of talks, under the chairman¬ ship of D. K. Pollock of ONR, describing char¬ acter recognition systems now in operation or being prepared for delivery in the near future. The first paper was by W. T. Hannan of Applied Research, Defense Electronics Products, RCA. He described the RCA multifont reading machine which uses interchangeable photographic matrix masks as reference patterns, accomplishes the recognition-decisions by means of optical cor¬ relation techniques, and Incorporates automatic line and character location features In the elec¬ tronic scanning system. A reading rate of 500 characters per second at accuracies of 1 to 5 errors per million characters was reported for this machine. Potential applications to the reading of printed pages, including Cyrillic texts, were discussed. O. L. Fischer and C. C. Heasly, Jr. of Farrington Electronics were the co-authors of a paper which discussed optical scanning re¬ quirements with special reference to automatic Input systems for a variety of application. A new model Farrington reader, the Selected Data Page Scanner, was announced in a press release coinciding with the opening of the sym¬ posium. The new reader Incorporates inter¬ changeable plugboard-programming format- control features to facilitate line location and field location within a line and to accommodate various word length and storage mode conditions. Following this paper, J. Rablnow described the several approaches to automatic character recognition that have been Investigated by the Rablnow Engineering Company, Inc. Readers using varied techniques, including optical-mask coincidence correlation, weighted area matrix correlation, and multiple non-re-entrant curve tracing, were discussed. It was concluded that anything now typed or printed can be read by machine and that within 5 to 10 years, cursive handwriting should be machine readable. J. B. Chatten and C. F. Teacher of the Phllco Research Center next described the use of high resolution flying spot scan techniques in a variable-font address reader being developed for the Post Office Department. Features in¬ clude automatic character location, means to normalize the size of unknown characters, fol¬ lowing of lines regardless of tilt, and provisions for re-scanning to resolve ambiguity on a character-by-character basis. Recognition decisions in the Philco reader are based on shift-register correlations where the unknown pattern is compared with a number of weighted area reference patterns stored in the form of resistor arrays. The principles of operation of a page-reader for Cyrillic text, under development by Baird- Atomic, Inc., were presented by J. A, Fitz- maurice. This reader uses an optical correla¬ tion technique for character recognition at rates up to 1000 characters per second. Input is in the form of microfilm copies of pages of printed Russian language material. Problems of han¬ dling special symbols, equations, and other interspersed graphic material were discussed. The advantages of vidicon scanning tech¬ niques in character recognition systems using 48 an area analyala principle were discussed by P. Barth of the National Data Processing Cor¬ poration, a Division of Remington Hand UNIVAC, He deacribed reaulta of thla technique aa giving recognition rates of up to 1000 characters per second for 20-microsecond exposures of the source documents. Leon Mlntz deacribed the typed page reader developed for the Army Signal Corps by the Control Instrument Division of Burroughs Cor¬ poration. This equipment was designed to read upper- and lower-case alphanumeric characters In standard elite type font. The device reads types pages stacked in Its input hopper and con¬ verts the characters into teletype code at a rate of 75 characters per second. Line tilt of as much as 10 degrees can be accommodated with¬ out loss of reading accuracy. A numeric character reader that will accept wide tolerances in quality of printing was described by R. K. Gerlach of the Elec¬ tronics Division of the National Cash Register Company. The NCR equipment was designed for use with a special font; source documents consist of paper strips imprinted by various accounting and cash register machines. Reject rates of the order of 10" 4 and error rates of 10“ 6 were reported for this equipment. A paper by W. T. Booth, G, M. Miller, and O. A. Schlelch described character recognition developments at the General Electric Company. A recently developed machine has been designed to read the numeric font under consideration by the X3.1 Subcommittee of the American Stand¬ ards Association. Several recognition logics for reading at rates up to 2500 characters per second were deacribed. Problems in reading mlsregistered and degraded characters were discussed. The first day's session was concluded by E. C. Greanias of the Advanced Systems De¬ velopment Division, IBM, who discussed vari¬ ous factors which affect the realization of practical character recognition devices. The nature of the documents to be read, the admin¬ istrative control that can be exercised in docu¬ ment preparation, the costs of handling rejects, were discussed in terms of determination of economic feasibility. The progress .made in the development of methods of pattern analysis was noted. The recognition logic, testing pro¬ cedures, and printer evaluation studies used in the development of the IBM 1418 reader were described. The second day’s session was dsvoted to trends in character recognition research. The flrat speaker was A. B. Novikoff of the Mathe¬ matical Sciences Department, Stanford Research Institute. He discussed the need for a usable mathematical model tor "geometric 00100 ” which results from random disturbances of a pattern from its Ideal representation, General requirement* which such a model should satisfy and the example of a particular proposed model were described. A system for reading cursive handwriting was described by L. D, Harmon of the Bell Telephone Laboratories. Two distinct problems are Involved: The segmentation of the hand¬ written word into its component characters and the recognition of the script letters themselves. A system involving the use of local, crlterlal features has been developed and tested on sentences written with a special stylus under the constraints of observing base and guide lines. An accuracy of 90 percent was achieved with a number of samples from different writers. The use of confusion matrix BtatlstlcB and diagram probabilities to Improve performance was described. A comparison of computed moments of input character patterns with the corresponding moments of prototype patterns was described by F. L, Ait of the National Bureau of Standards. He pointed out that certain combinations of mo¬ ments are relatively invariant for pattern trans¬ formations such as size, translation, and some slanting. Experiments on a computer Indicate that a process using a modest number of sam¬ ple points and computing moments only up to the sixth order Is adequate to discriminate be¬ tween the characters of a given alphabet. The general problem of classifying Items char¬ acterized by a set of numbers was discussed. The next paper, by R. F. Meyers, V. E. Giuliano, and P. E. Jones of Arthur D. Little, Inc., similarly postulated sets of mathematical derivatives of certain Integral measurements of character patterne. It was noted that methods based on measurements of a number of moments or a number of Fourier coefficients offer means to normalize by computing a set of invariants with respect to frequently encountered pattern transformations, such as translation or scaling. A procedure was described for obtain¬ ing a set of measurement functions which mini¬ mize the error rate for a given alphabet and a given degree of noise. 49 D. M. Baumann of the Massachusetts Insti¬ tute of Technology described preliminary re¬ sults of a study of the use of area weighting techniques for automatic character recognition. Input character patterns were categoriced into subsete on the basis of optical sensing through a sequence of photographic masks. Mask de¬ sign was based upon statistical parameters of a set of characters and weighting functions chosen to provide optimal separation. A paper by L. O. Roberts reviewed char¬ acter and pattern recognition developments at the Massachusetts Institute of Technology dur¬ ing the past S years. It was noted that earlier research on handprinted characters was followed by studies on cursive handwriting and that prog ¬ ress has been made in characterizing hand¬ written strokes. Continuing pattern recognition research in the general Perceptron research program was reported in a paper by W. S. Holmes, H. R. Leland, and J. L. Muerle of the Cornell Aero¬ nautical Laboratory. In particular, a multi¬ layered Perceptron system has been simulated by computer to investigate the feasibility of training the system to recognize mixed torn alphanumeric characters. The input pattern is prefiltered to provide a transformed image space, combinations of intensities at selected points in the transformed image space are used as properties, and a linear discriminant func¬ tion is applied to classify the pattern. A scheme for recognizing patterns from an unspecified class was described by C. Barns of Swarthmore College. Small subsets of speci¬ mens of each of the patterns to be recognized are stored in the machine. The information contents of these subsets change during a learn¬ ing phase to become more typical of the pattern represented. Possibilities for Implementation by optical comparisons were discussed, In a paper by W. H. Highleyman of the Bell Telephone Laboratories, a distinction was made between the ‘receptor* and the ‘categorizer* operations of a pattern recognition system. The categorizer typically determines, from measurements made by the receptor on an unknown pattern, the particular pattern class to which the unknown belongs. The paper con¬ sidered in detail that class of categorizers involving the linear decision functions. In con¬ nection with the problem of recognizing hand¬ printed numeric characters, procedures were illustrated based upon sampling from pattern classes to be identified for choice of linear decision function. Techniques for multtfont print recognition were described by M. C. Andrews of the Thoms* J. Watson Research Laboratory of IBM. Problems encountered and experimental techniques which offer apparently promising solutions were discussed. The speaker also described automatic error detection and cor¬ rection methods applicable to systems which are required to accept and proceas natural language text. M, B. Clowes of the National Physical Laboratory, Teddington, England, described a method for character recognition involving one or more autocorrelation functions of an unknown pattern. The form of the autocorrelation func¬ tion specifies a character feature, such as a straight line or a “hook.* Such functions are Invariant with respect to transformations of size, rotation, and translation and are relatively Insensitive to minor changes in style or printing quality. L.Uhr of the University of Michigan pre¬ sented a paper, prepared by himself and C. Vossler of the Systems Development Corpora¬ tion, reviewing current trends In the ‘search to reconglze.* He noted the specific problems to be solved - the array differing with selec¬ tions of font and vocabulary size, method of presentation, and method of recognition. It was also noted that, on the other hand, general methods for pattern recognition would allow for common solutions to families of problems. He then described a specific experimental tech¬ nique which enables an adaptive categorization ol information-carrying features of unknown inputs, Results were given for subsequent rec¬ ognition both of hand-drawn alphanumeric char¬ acters and of certain outline drawings, including comic-strip faces. The third session of the symposium con¬ sisted of a description and panel discussion of representative user requirements In various government agencies. The panel was under the chairmanship of B. Radack, Bureau of Supplies and Accounts, Navy, and was composed of G. Shiner, Rome Air Development Center; C. Sparks, U.S. Civil Service Commission; P. Howerton, Central Intelligence Agency; Major L. Sears, Army Finance Office; R. Hes- slnger, Post Office Department; and W. Velander, Navy Management Office. The fourth and final session was held Wednesday afternoon, 17 January, under the chairmanship ot M. C. Yovits of the Office of Naval Research. This session was opened by a SO keynote address by O. 0. Selfridge of the Mas¬ sachusetts Institute of Technology. The follow¬ ing panel discussion brought forth remarks on the horizons for optical character recognition research by J. D. Noe, Stanford Research In¬ stitute; J. C. R. Llcklider, Bolt, Baranek, and Newman; H. A. Affel, Jr., Auerbach Corpora¬ tion; D. H. Shepard, Cognitronlcs; D. Brick, Sylvanla; and J. J. Eachus, Minneapolls- Honeywell. A Proceedings will be available, in Sep¬ tember 1962, at an approximate price of $10.00. The publisher is Spartan BookB, 6411 Chlllum Place, Washington 12, D. C,, and orders shquld be directed to Spartan Books or to a bookstore. PLATO II—UNIVE RSITY OF ILLINOIS, URBANA, ILLINOIS Introduction The purpose of the PLATO (Programmed Logic for Automatic Operations) project is to develop an automatic teaching system capable of tutoring simultaneously a large number of students In a variety of subjects. The central control element of the teaching system is a general purpose digital computer. The PLATO system differs from most teaching systems in that a single high-speed digital computer is used to control all student stations. Thus, it has available the power of a large digital com¬ puter to teach each student. A complete de¬ scription of the equipment and systems organ¬ ization was described in the April 1962 issue of DCN. Teaching Studies with College Undergraduates A study was completed in which PLATO II was used to teach the first week of the Uni¬ versity’s course “Introduction to Automatic Digital Computing (Math 196).” This course uses the IBM-660 as a vehicle for Introducing the student to the basic notions of automatic computing. On the first day of class, some 20 students wore chosen at random and asked to attend a demonstration of the machine. Alter the dem¬ onstration, nine volunteers were found whose schedules were compatible with our schedule for use of the computer. These nine students formed the subjects of our study. Each student was first given a practice session (with specially prepared material) to familiarize him with the operation of the ma¬ chine. These practice sessions reconfirmed our previous experiences that students could master the operation of the machine in a few minutes. No student reported any difficulty in this respect, either during the practice session or the lessons proper. Each student was then scheduled for three lessons on the machine. Since these lessons paralleled, almost exactly, the subject-matter discussed by the instructor in class, the stu¬ dents were encouraged not to attend class for the week of the study. None did. Topics covered by the three lessons were: Lessoh 1; The Word as a Number (fixed and floating point representation) Lesson 2: The Biquinary Code and the Storage Unit Lesson 3: The Arithmetic Unit, Instruc¬ tion Format, the Control Unit, and Execution of Single Instructions. Since the PLATO R system can teach two stu¬ dents simultaneously, the students were, when possible, scheduled in pairs so that the nine students each taking the three lessons represent roughly 15 hours of scheduled computer time. The records kept by the computer during each run of each student’s progress through the material are currently being studied. The results and conclusions will be available shortly for publication. The data collected provides information about: 1. The learning ability of each student. 2. The effectiveness of each lesson. 3. The data rate requirement placed on the system. More specifically, under each item the follow¬ ing kinds of information are available. 1. Student a. length of time the student spent on each lesson b. number of times the student re¬ quested help 51 c. imuiucr ui wrung answers submitted by the student. 2. Lesson a. average length of time spent on each slide, b. problems of the main sequence for which heop was requested c. problems for which the computer was requested to supply the correct answer by the student. 3. System a. average rate of inputs to central com¬ puter (per unit time per student) b. number of times each type of request was entered into the computer (e.g,, continue. Judge, etc.). Some data may be of significance in more than one of the above categories, nor is the above list intended to be exhaustive. It does give a fair sample of the type of data available from a study with PLATO D. At the end of the third week of the course, the instructor gave the class an examination covering both material taught with the machine and later material taught only In class. The average grade on this examination of the stu¬ dents who had participated in the study was almost precisely equal to the class average as a whole. Finally, we should like to report that all students, at leaBt for the week of the study, seemed entnusiastic about the machine. None Indicated any desire to drop out, although they were reminded several times that they could do so. THE COMPUTER TREE—U.S, ARMY BALLISTIC RESEARCH LABORATORIES COMPUTING LABORATORY, ABERDEEN PROVING GROUND, MARYLAND The automatic data processing industry is a direct outgrowth of Army sponsored research, which produced ENIAC, the first modern elec¬ tronic computer, in 1945, The computer indus¬ try has grown to a multi-billion dollar activity, and has penetrated every profession and trade in Government, business, industry, and educa¬ tion. The Computer Tree shows the evolution of computers, The serial computers, repre¬ sented by the EDVAC, and the parallel com¬ puters, represented by the ORDVAC, are shown as separate trunks. This has also tended to separate the Blower business computers from the taster scientific computers. Military re¬ quirements have fostered a central composite shoot and have stimulated other growths. Manufacturers have entered the computer field at different times, producing various branches along the main bough. The radial distance from the ENIAC is an approximate indication of the year each computer was either developed, con¬ structed, or placed In operation. The ENIAC, EDVAC, ORDVAC, and BRLESC were sponsored or developed by the Ballistic Resoarch Laboratories, Aberdeen Proving Ground, Maryland (see other BRL article, this issue of DCN).