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APPENDIX 35 

TEST PROCEDURE FOR SYSTEM CONTROLLER 
FINAL SOFTWARE REPORT 
DATA ITEM NO. A005 


INTEGRATED ELECTRONIC WARFARE SYSTEM 
ADVANCED DEVELOPMENT MODEL (ADM) 



1 OCTOBER 1977 


UNCLASSIFIED 


ELECTROMAGNETIC 
SYSTEMS DIVISION 







APPENDIX 35 . . T. 

TEST PROCEDURE FOR SYSTEM CONTROLLER 

FINAL SOFTWARE REPORT 
DATA ITEM A005 

INTEGRATED ELECTRONIC WARFARE SYSTEM (LEWS) 
ADVANCED DEVELOPMENT MODEL (ADM) 


Contract No. N62269-75-C-0070 


Prepared for: 

Naval Air Development Center 
Warm ini st er, Penn sy 1 vania 


Prepared by: 

RAYTHEON COMPANY 
Electromagnetic Systems Division >' 
6380 Hollister Avenue 
Go!eta, California 93017 


1 OCTOBER 1977 














21 September 1976 


PREPRODUCTION TEST PROCEDURE 
PART I 

PERFORMANCE TEST UNDER LABORATORY CONDITIONS 

FOR 

SYSTEM CONTROLLER, IEWS 
CONTRACT-N62269-74-C-0070 
MANUFACTURER-RAYTHEON COMPANY 


Total Pages in the Procedure: 27 


1-1 



SPECIFICATION REQU IRE 
53959-GT-0301, Rev. 3 


TEST 

2.1 

2 . 1.1 

2 . 1.2 

2.2 

2 . 2.1 

2 . 2.2 

2.2.3 

2.2.4 

2.2.5 

2 . 2.6 
2.3 

2.3.1 

2.3.2 

2.3.3 

2.3.4 

2.4 

2.4.1 

2.4.2 

2.5 

2.5.1 

2.5.2 

2.5.3 

2.6 


TABL E OF TESTS 


MMO B PAGE 

Operator Control Test 1-5 

Front Panel Reset 1-5 

Local Control Panel 1-5 

Master Bus Module Tests 1-8 

Master Processor Self-Test 1-8 

Master Bus Memory Test 1-9 

Mxaster Bus PIN/RTC Module Test . I-10 

Master Bus DSI0 Module Test 1-11 

Master Bus SCM Test 1-12 

Master Bus LD/LR Module Test 1-13 

Slave Bus 1 Module Test 1-14 

Slave Processor 1 Self-Test 1-14 

Slave Bus 1 Memory Test 1-15 

Slave Bus 1 PIN/RTC Module Test 1-16 

Slave Bus 1 DS10 Module Test 1-16 

Slave Bus 2 Module Tests 1-18 

Slave Processor 2 Self-Test 1-18 

Slave Bus 2 Memory Test 1-19 

Bus Tests 1-20 

Master Bus Test 1-20 

Slave Bus 1 Test 1-20 

Slave Bus 2 Test 1-21 

System Test 1-22 


1-2 



LIST OF TE ST EQUIPMENT 


1 Local Control Panel (854952-1) and Control Panel Interface 

1 . nocar u Module (894629-4) 

2. 4K PROM/RAM Module (950026-4) 

3. Signal Sorter (893651) 

4. Auxiliary Bus Monitor 

5. Simulated System Controller or Software Development Center 

6. Test Function Unit (see Appendix A) 


Cables (see Appendix A) 

a. Signal Sorter Bus Cable 

b. Auxiliary Bus Cable 

c. Daisy Chain Bus Cables (2) 

d. Serial 10 Bus Cable 

e. Power Cable 


See Appendix A for basic test equipment configuration. 


A number of programs are required to facilitate system testing. 
Some are contained as firmware in the 4K PROM/RAM module. Others 
are software programs which must be loaded into a two—port 4K RAM 
memory in the Simulated System Controller or Software Development 
Center as called out in the test procedure. A list of test programs 
and associated document control numbers are contained in Appendix B. 

Tests in some sections require the use of a MOVE utility program 
located on the 4K PROM/RAM, to relocate programs from 4K memory 
sectors on the Master Bus to 4K sectors on the Slave Buses. A de¬ 
scription of the use of this program is contained in Appendix C. 

Some tests require the operator to use the SSC or SDC to load 
external software into the 4K SSC or SDC memory accessible to the 
SC. A description of this load procedure is contained in Appendix 
D. Use of the MOVE utility program contained in the 4K PROM/RAM 
is also required. 



LIST OF ABBREVIATIONS 


AUX BUS AUXILIARY BUS 

CPI CONTROL PANEL INTERFACE MODULE 

DSI0 DUAL CHANNEL SERIAL 10 MODULE 

LCP LOCAL CONTROL PANEL 

LD/LR LINE DRIVER/LINE RECEIVER MODULE 

PIN/RTC PRIORITY INTERRUPT KETWORK/REAL TIME 

CLOCK MODULE 

SC SYSTEM CONTROLLER, 

SCM SYSTEM CONTROL MODULE 

SDC SOFTWARE DEVELOPMENT CENTER 

SI0 SERIAL 10 CHANNEL 

SS SIGNAL SORTER 

SSC SIMULATED SYSTEM CONTROLLER 

TFU TEST FUNCTION UNIT 


I~4 







TEST PROCEDURES 


1. GENERAL - Unless specified otherwise, all tests shall be 
performed under the following conditions: 

(a) Atmospheric Conditions i - The tests shall be performed 
at prevailing open environment atmospheric•conditions. 

(b) In p ut Po w er -- The Input power shall be 115 volt, 400 
Hertz, three phase. 

(c) Configuration - Unless otherwise specified, all tests 
shall be performed using the basic test configuration 
of Appendix A, with power applied to all units. 

(d) Equipment Operation - The test operator shall have 
familiarity with the operation of both the test equip¬ 
ment and the unit under test. 

2. UNIT TEST - Apply power to the basic configuration and momen¬ 
tarily depress the RESET pushbutton on the SC front panel 

2.1 OPERATOR CONTROL 


2.1.1 Front Panel Reset 

(a) Requirement - Front Panel Reset shall initialize SC, 

SS and externally cabled SI$ and Daisy 
Chain devices. 

(b) Conditions - Basic test configuration. 

(c) Measurement - Depress Front Panel RESET pushbutton. 

Test Function Unit lights SI0CLR and 
DCMCL should be on. RUN light on LCP 
should be off. 

Initial 

2.1.2 Local Control Panel 

(a) Requirement - LCP functions shall be fully operational 

(b) Conditions - Basic test configuration. 

(c) Measurement - 

i. Exercise LCLR function. Test Function 
unit lights SI.0CLR and DCMCL should be 
on when LCP EXECUTE pushbutton is de¬ 
pressed. 

Witnessed by: Initial 

Customer Representative _ • 

Raytheon QA Representative _ 

Date 


1-5 




ii. Exercise PCLR function as in (i). 
Lights should remain off. 

Initial 

iii. Exercise REGSEL function. Load the 
following hexadecimal patterns into 
the data registers and verify upon 
load completion that the contents of 

• each register is unchanged. 


SR 5555 
PR 3333 
BR OFOF 
XR OOFF 
ACR AAAA 
ER CCCC 


WR FOFO 


AR FFOO 


YnitiaT 


Load the following patterns into each 
data register(SR,PR,BR,XR,ACR,ER,WR,AR) . 


0000 

FFFF 

5555 

AAAA 


Initial 

iv. Exercise the Memory function. Store and 
Fetch the following data patterns to 
memory location 0000: 

0000 

FFFF 

5555 

AAAA 

Verify the data returned is the“same as 
data entered. 

Witnessed by: 

Customer Representative _ Initial 

Raytheon QA Representative _ 

Date 


1-6 





Store i the following set of data patterns 
to memory, starting at memory location 0000: 

0000 

0001 

0002 

0003 

0004 

0005 

0006 

0007 

Fetch i the entered data' stax*ting from 
memory location 0000. Verify that data 
returned from memory is the same as data 
entered to memory. 

Initial 

Exercise the STEP/HALT and HUN functions. 
Use the LCP to enter the following simple 
Load programs into memory, starting at 
location 0000. 

Address Contents Program 

0000 
0001 
0002 

Initialize register PR to 0000 and register 
ACR to AAAA, using the LCP, and depress the 
RESET button. Perform the STEP/HALT func¬ 
tion such that one instruction execution is 
performed (two pushbutton depressions). 
Verify that the PR register contains 0002, 
the ACR register contains 5555, and that 
the AR register contains FFFD. Perform the 
RUN function. Perform the HALT function. 
Observe that the LCP Run light if off. 
Verify that the PR and AR registers contain 
one of the following two sets of data: 

PR AR 

0000 FF4C 

or 

0002 FFFD 

TnitiaT" 


Witnessed by: 

Customer Representative _ 

Raytheon QA Representative 
Date 


108C 

5555 

86FD 


LDS A P* 
DC '5555 
JMP-2 


1-7 





Enter the following simple Store program 
into memory, starting at location 0000. 


Address 

0000 

0001 

0002 


Con t ent s. 

008C 
5555 
8 6 PD 


Progr am 

STS A P* 
DC '5555 
JMP-2 


Initialize register PR to 0000 and register 
ACR to AAAA, and depress the RESET button. 
Perform the STEP/HALT function such that 
one instruction execution is performed 
(two pushbutton depressions). Verify 
that the PR register contains 0002 and 
that memory location 0001 contains AAAA. 


2.2 MASTER BUS MODULE TESTS 


Initial 


2.2.1 . Master Processor Self-Test 

(a) Requirements- Test all Master Processor microinstructions 

and microprogram branches that implement 
the processor instruction set and depend 
only on program execution from a zero-origined 
4K memory. Additionally list instruction 
functions using a pseudo-random sample of 
data word values. 

(b) Conditions - Basic test configuration. 

(c) Measurement - Enter 00 80 into memory locations 00 80 and 

0081. Initialize register PR to 0100 and 
depress the RESET button. Perform the RUN 
function. The LCP RUN light shall come on 
for a period of approximately 15 seconds. 
After the RUN light has gone off, examine 
memory locations 0080 and 0081 and verify 
that they contain the following information. 
Memory Location Contents Meaning 

0080 0000 Halt Code 

0081 0000 Success Code 


Witnessed by: Initial 

Customer Representative _ 

Raytheon QA Representative _ 

Date 


1-8 




(a) Requirements - Test Master Bus memory via pattern and 

~ address tests. 

(b) C ondi tions - Basic test configuration 

(c) Measurement - Enter the starting address of the memory 

sector to be tested into memory location 
0080 and the.ending address of the sec¬ 
tor into location 0031. Initialize re¬ 
gister PR to *0600 and depress the RESET button 
Perform the RUN function. The LCP RUN light 
will come on for a period proportional to the 
size of the tested memory sector (—7 sec. for 
each 4K block). After the RUN light has gone 
off, examine memory locations 0080 and 0081 
and verify that they contain the following 
information. ... 


Memory Loc ation Contents Meaning 


0080 

0081 


0000 Halt Code 

0000 Success Code 


Initial 


Execute the Master Bus memory test for 
the following memory sectors: 

From Starting Address to Ending Address 

2000 6FFF 

8000 9FFF 

C000 CFFF 


Initial 

Witnessed by: 

Customer Representative------ 

Raytheon QA Representative ____— 


Date 




2.2.3 


^ X- ... 


r Bus PIN/RTC Module Test 


(a) Req u irements - Test the Master Bus Processor's ability 

with respect to the PIN/RTC to: 

(i) Read and write various data patterns 
• to the Mask Register. 


(ii) Read R9?C counter a.nd verify that it 
is cleared. 

(iii) Read Interrupt Status Register and 
verify that it is cleared. 

(b) Condition s - Basic test configuration 

(c) Measuremen t - Load the PIN/RTC test program into the 

SSC or SDC. Transfer the contents of the 
4K memory, origin C000, to the 4K memory, 
origin 2000 using the MOVE routine. Enter 
0080 into memory locations 0080 and 0081. 
Initialize register FR to 2000 and depress the 
RESET button. Place the DC/INRUPTS switch on 
the TFU into the DC position. Perform the 
RUN function, which will cause the processor 
to run for a fraction of a second. Examine 
memory locations 0080 and 0081 and verify that 
they contain the following inform ation : 

Memory Locate ion Conuents Meaning 

0080 0000 Halt Code 

0081 0000 Success Code 


initial 

Witnessed by: 

Customer Representative ___ 

Raytheon QA Representative___ ' __ 

Date 


I -10 





2,2.4 


D S10 Module Me si 


the Master Bus Processor's ability 
respect to the DSIj? to: 

(i) Read the Status Word and verify 
that it is cleared. 


(a) Requirements - Test 

with 


(ii) Read Mask bits and verify that they 
■ are cleared. 

(iii) Write and Read Mask bits. 


(iv) Transmit and receive serial data 
and check status information for 
various control word patterns. 


(b) Conditions 


Basic test configuration, except that the 
procedure is to be repeated four times, 
with the SI0 bus cable (SC plug end) 
connected to a different SC connector 
jack for each test pass. These are: 


Test Pass 


SC Jack Connection 


1 

2 

3 

4 


Jl 

J2 

J3 

J4 


(c) Measurement - Load the DSI0 test program into the SSC or 

SDC. Transfer the contents of the 4K memory, 
origin C000, to the 4K memory, origin 2000, 
using the MOVE routine. For each pass, enter 
the address of the SI0 channel to be tested 
in memory locations 0080 and 0081. Initialize 
register PR to 2002 and depress the RESET button, 
Perform the RUN function, which will cause the 
processor to run for 5 seconds. Examine memory 
locations 0080 and 0081 and verify that they 
contain the following information: 

Memory Location Contents Meaning 

0080 0000 Halt Code 

0081 0000 Success Code 


Witnessed by: 

Customer Representative _ 

Raytheon QA Representative 
Date 


1-11 



f 


2.2.4 Master Bus DS10 Module Test (Continued) 


(c) Measurem ent (Continued) 

Also verify at the completion of each pass 
that the RCV BUFFER FULL light on the Test 
Function Unit is on. Depress the front panel 
RESET pushbutton and verify that the SI0 CLR 
light comes on and the RCV BUFFER FULL light 
goes off at the Test Function Unit. 


SIJ? channel addresses for each pass are 
as follows: 

Test Pass Channel Address 


1 

2 

3 

4 


FCOO 
FC04 
FCO 8 
FCOC 


2.2.5 Master Bus SCM Test 


Initial 


(a) Requirements - 

(i) Read Breakpoint Status and verify 
that it is cleared. 

(ii) Read Watchdog Timer Status and 
verify that it is cleared. 

(iii) Test Breakpoint Register for Break¬ 
point Halt operation. 

(iv) Test ROM and auto-start features. 

(v) Test Watchdog Timer. 

(vi) 


Witnessed by: 

Customer Representative 
Raytheon QA Representative 
Date 


Test Master Bus Clear distribution. 



t 


.2.5 Mas 

ter Bus SCM Test 

(Continued) 

(b) 

Conditions •- 

Basic test configuration, (but w. 
bootstrap PROMS) 

(c) 

Measurement - 

Load the SCM test into the SSC < 
Transfer the contents of the 4K 
origin C000, to the 4K memory, < 
using the MOVE routine. Enter 1 
memory locations 0080 and 0081. 
Register PR to 2004 and depress 
ton. Perform the RUN function 
cause the processor to run for : 


seconds. 

Depress the RELOAD button on the TFU. 
Examine memory locations 0030 and 0081 and 
verify that they contain the following 
information: 


Memory Location 

0080 

0081 


Contents 

0000 

0000 


Meaning 

Halt Code 
Success Code 


Initial 


2.2.6 Master Bus LD/LR Test 
(a) Requirements - 


(b) Condition - 

(c) Measurement 


(i) Verify the POWER?AIL function. 

(ii) Verify the SKIP function. 

Basic test configuration. 

Remove power from the SCt Verify that 
the POWERFAIL light on the TFU is on. 
Applv power to the SC. Verify that the 
SCPWR FAIL light is off. Depress and 
release the front panel RESET pushbutton, 

Using the LCP, enter the following 
simple program into memory. 

Location Contents Code 


COOO 

104C 

LDS A (P*) 

C001 

0000 

0000 

CO 0 2 

B6FD 

JMP-2 

C003 

B800 

HALT 


*CAUT 


Witnessed by: - - 

Customer Representative_______ 

Raytheon QA Representative______ 

Date __ 

TON: This test may alter the contents of the 4K RAM located in the SSC 

or SDC due to power down/up transients. 



Initializes register PR to C000 and depress the 
ru^Sr/P button. Perform the RUN function, putting 
t-ne processor in the program loop. Depress the 
DC SKIP pushbutton on the TFU. Verify that the 
processor halts with the PR register eauaJ to 
COO4 . 


2.3 SLAVE BUS 1 MODULE TESTS 


initial 


2.3.1 Slave Processor 1 Self Test 

(a) Requirements - Test all Slave 1 Processor microinstruc- 

tions and microprogram branches that im¬ 
plement the processor instruction set 
and depend only on program execution from 
a zero origined 4K memory. Additionally, 
test instruction functions using a pseudo¬ 
random sample of data word values. 

(b) Conditions - Basic test configuration. 

(c) Measurement - Transfer the contents of the 4K PROM/RAM, 

origin 0000, to the 4K memory, origin 2000, 
via the MOVE utility program. 

• Enter 2080 into memory locations 2080 and 

2081, and 0100 into memory location 
2000. Depress the RESET button. Store to memory 
locations FFC1 and FCCB in sequence with the LCP 
to start the Slave 1 processor. After approxi¬ 
mately 15 seconds, examine memory location 2080 
and 2081 with the LCP and verify that they con¬ 
tain the following information. 


Memory Location Contents Meaning 

2080 0000 Halt Code 

2081 0000 Success Code 

Witnessed bv: 

Customaoc- Representative_ 

Raytheon QA Representative 
Date 


Initial 




2.3.2 Slave Bu s 1 Memory Test 

(a) Requi rements - Test all Slave 1 Bus Memory via pattern 

and address tests. 

(b) Condition s - Basic test configuration 

(c) Measurement - Transfer the contents of the 4K PROM/ 

RAM, origin 0000, to the 4K memory, 
origin 2000, via the MOVE utility pro¬ 
gram. 

Enter the starting address of the Slave 1 
memory sector to be tested into memory 
location 2080 and the ending address of the 
sector into location 20 81. Enter 06'00 
^ into memory location 2000. Depress the 

RESET button. Store to memory locations 
FFCl and FFCB in sequence with the LCP 
to start the Slave 1 processor. Allowing 
for 7 seconds of execution for each 4K 
of memory, examine memory locations 2080 
and 2081 and verify that they contain 
the following information: 

Memory Location Contents Meaning 

2080 0000 Halt Code 

2081 0000 Success Code 

Execute the Slave 1 Bus memory test for 
the following memory sectors. 

From Starting Address to Ending Address 

1000 4FFF 

6000 7FFF 

C000 C3FF 


initial 

Witnessed by: 

Customer Representative _ _ 

Raytheon QA Representative______ 

Date 


1-15 





( a ) Requlrements 


- Test the Master Bus Processor's ability 
with respect to the PIN/RTC to: 



(i) 

Read and writ© various data, patterns 
to the Mask Register. 


(ii) 

Read RTC counter and verify that it 
is cleared. 


(iii) 

Read Interrupt Status Register and 
verify that it is cleared. 

(b) 

Conditions - Basic test configuration. 

(c) 

Measurement - Load 

SSC 

the PIN/RTC test program into the 
or SDC. Transfer the contents of the 


4K RAM, origin COOO, to the 4K memory sector 
origin 4000, via the MOVE utility program. 

Enter 2080 into memory locations 2080 and 
2081, and 2000 into location 2000. Depress 
the RESET button. Store to memory loca¬ 
tions FFCl and FFCB in sequence with the 
LCP to start the Slave 1 processor. Examine 
memory locations 2080 and 2081 with the LCP 
and verify that they contain the following 
information: 

2080 0000 Halt Code 

2081 0000 Success Code 


2.3.4 Slave Bus 1 DSlff Module Test 


Initial 


(a) Requirements - Test the Master Bus Processor's ability 

with respect to the DSIjl to: 

(i) Read the Status Word and verify 
that it is cleared. 

(ii) Read Mask bits and verify that they 
are cleared. 

(iii) Write and Read Mask bits. 


Witnessed by: 


(iv) Transmit and receive serial data and 
check status information for various 
control word patterns. 


Customer* Representative 
Raytheon QA Representative 
Date 


: cr 







? 


2.3.4 Slave Bus 1 DSI# Module Test (Continued) 


(b) . Con ditions - Basic test configuration, except that the 

procedure is to be repeated twice, with 
the SI# bus cable (SC plug end) connected 
to a different SC connector jack for each 
test pass. These are: 

Te st P ass ' SC Jack Conn ect ions 

• 1 J5 

2 J6 ' 

.(c) Measurement - Load the DSIO Test Program into the SSC or 

SDC. Transfer the contents of the 4K RAM, 
origin C000, to the 4K memory sector 
origin 4000, via the MOVE utility program. 
For each pass, enter the SI# channel 
address into memory locations 2080 
and 2081, and 2002 into location 2000. 
Depress the RESET button. Store to memory 
locations FFC1 and FFCB in sequence with the 
LCP to start the Slave 1 processor. After 
5 seconds, examine memory locations 2080 
and 2081 and verify that they contain the 
following information: 

Memory‘Location Contents " Meaning 

2080 0000 Halt Code 

2081 0000 Success Code 


Also verify, after completion of each 
pass, that the RCV BUFFER FULL light on 
the TEU is on. Depress the front panel 
RESET pushbutton and verify that the 
SI#CLR light comes on and the RCV BUFFER 
FULL light goes off at the TFU. 

SI# channel addresses for each pass are 
as follows: 

Test Pass 

1 
2 

Witnessed by: 

Customer Representative __ 

Raytheon QA Representative __ 

Date 


Channel A.ddress 

FC00 

FC04 


initial 


1-17 




2.4 -SLAVE BUS 2 MODULE TESTS 


2.4.1 Sla ve Processor 2 Self Tes t 

(a) Requirements - Test all Slave 2 processor microinstruc¬ 
tions and microprogram branches that im¬ 
plement the processor instruction set and 
depend only on program execution from a 
zero origined 4K memory. Additionally, 
test instruction functions using a pseudo¬ 
random sample of data word values. 

.(b)' Conditions - Basic test configuration 

(c) Measurement - Transfer the contents of the 4K PROM/RAM, 

origin 0000, to the 4K memory, origin 8000, 

via the MOVE utility program. Peeress the 
RESET button. 

Enter 8080 into memory locations 8080 
and 8081, and 0100 into memory location 
8000. Store to memory location 
FFD1 and FFDB in sequence with the LCP 
to start the Slave 2 processor. After 
approximately 15 seconds, examine memory 
location 8080 and 8081 with the LCP and 
verify that they contain the following 
information. 

Memory Location Contents Meaning 

0000 Halt Code 

0000 Success Code 


initial 

Witnessed by: 

Customer Representative___ 

Raytheon QA Representative_____ 

Date 


8080 

8081 


1-18 




2.4,2 Slave Bus 2 Memory Test 


(a) Requirements 


- Test all Slave 2 Bus Memory via pattern 
and address tests. 


(b) Conditions - Basic test configuration 

(c) Measurement - Transfer the contents of the 4K PROM/ EhM 

origin 0000, to the 4K memory, 
origin 8000 , via the MOVE utility 
program. 

Enter the starting address of the Slave 2 
memory sector to be tested into memory 
location 8080 and the ending address of 
the sector into location 8081 . Enter 
0600 into memory location 8000. Depress 
the RESET button. Store to memory loca¬ 
tions FFDl and FFDB in sequence with the 
LCP to start the Slave 2 processor. 

lowing for 7 seconds of execution ror 
each 4K of memory, examine memory loca¬ 
tions 8080 and 8081 and verify that 
they contain the following information: 
Memory~'Loca t i on Contents Meaning 

8080 0000 Halt Code 

8081 0000 Success Code 


Execute the Slave 2 bus memory test for 
the following memory sectors. 

From Starting Address to Ending Address 

1000 1FFF 

6000 7FFF 

C000 C3FF 


Initial 

Witnessed by: 

Customer Representative ____ _ __ 

Raytheon QA Representative _ 


Date 





2 .5 BUS TESTS 


2.5.1 Master Bus Test 


( a ) Requirements - Test the following low level interrupts: 


Hung Bus Detector (1) 

Internal Interrupt Generator (1) 
SI0 (4) 

LD/LR (7) 


(b) C o nd.it i on 


- Basic test configuration 


(c) Measu rement 


2.5.2 Slave Bus 1 Test 


- Load the Master Bus Test program into the 
SSC or SDC. Transfer the contents of the 
4K memory, origin C000, to the 4K memory, 
origin 2000, using the MOVE routine. Using 
the LCP, enter 0080 into memory locations 
0030 and 0081. Initialize register PR to 
2006 and depress the RESET button. Place 
the DC/INRUPTS switch of the TFU in the 
INRUPTS position. Perform the RUN func¬ 
tion. Verify that the RUN light on the 
LCP goes off and that memory contains 
the following information: 

Memory Location Contents Meaning 

0080 0000 Halt Code 

0081 0000 Success Code 

Place the DC/INRUPTS switch back into the DC 

position. _ 

Initial 


(a) Requirements - 

(i) Test the SS connector port by controlling 
the SS Supervisor' Processor, and by re¬ 
sponding to MSG and POWERFAIL interrupts 
from the SS. 

(ii) Test the following low level interrupts: 

Hung Bus Detector (1) 

S10 (2) 

(iii) Test Master Clear distribution. 

Witnessed by: 


Customer Representative 
Raytheon QA Representative 
Date 


1-20 




2.5.2 Slave Bus 1 Test (Continued) 


(b) Con d it ions - Basic test configuration 

(c) Measurement — Load the Sla.ve 1 Bus Test pi'og x«.m inco ^Le 

‘ SSC or SDC. Transfer the contents of the 

4K memory, origin C000, to the 4K memory, 
origin 4000, via the MOVE utility program. 
Enter 2080 into memory location 2080 and 
2081. Enter 200A into memory location 2000. 
Depress the RESET button. Store 0 r s to FCFl 
before running slave proces53or 1. Score i_o 
> memory location FFCl and FFCB in sequence 

with the LCP to start the Slave 1 processor. 
Turn the SS power supply of r, then on. icxa. - 
mine memory locations 2080 and verify that 
they contain the following information: 

~ " meiTicjry ~ Loc a t i on "Content s Meaning 

2080 0000 Halt Code 

2081 0000 Success Code 


2.5.3 Slave Bus 2 Test 

(a) Requirements - 


initial 


(i) Write and read data patterns in each 

of the 16 CAM/RAM control memory loca¬ 
tions. Verify operation of the Aux. 
Buffer Full Interrupt. 


(ii) Verify operation of the Aux. Hung Bus 
Detector interrupt function. 


(iii) Test Master Clear distribution. 


(b) Condition - Basic test configuration 

(c) Measurements - Load the Slave 2 Bus Test program into the 

SCC or SDC. Transfer the contents of the 

4K memory, origin C000, to the 4K memory, 

origin A000, via the MOVE utility program. 

Enter 8080 into memory location 8080 and 

8081. Depress the RESET button. Enter 1008 

into memory location 8000. Store to memory 

location FFDl and FFDB in sequence with the 

• LCP to start the Slave 1 Processor. After 

5 seconds, examine memory locations 8080 

Witnessed by: and 80 81 and verify that they contain the 

_ _ , . followina information: . - - 

Customer Representative_ — - - - 

Raytheon QA Representative ___ 





S_ r L_s\rs__3vi L s_2 Test (continued) 


Memory Location Cont ents Meaning 


8080 

8081 


0000 

0000 


2.6 Sy stem Test 

(a) Requirement: 


Halt Code 
Success Code 


Initial 


(b) Condition 


(c) Measurement - 


(i) Verify contro 1 of the Slave px-ocessors 
by tne Master processor, including 
Com.rol Interface, hrgh level inter™ 
rupts from Master to Slaves, and low 
level interrupts from Slaves to Masters. 

(ii) Verify generation of synchronized Real 
i-'-me Cloc.< of Master and Slave 1 proc¬ 
essors, including Master contx~ol of 
Slave RTC and Internal Interrupt Genera¬ 
tion for Slave 1 processor. 

(iii) Verify communication of Slave 1 and 

Slave 2 processors through the common 
two port memories. 

(iv) Test the Aux. Bus connector port in 
conjunction with SS connector port 
stimulation. 

(v) Verify the auto-start feature. 

Basic test configuration (with SCM bootstrap 
test PROMs. 

Load the SC system test program into the SSC or 
SDC. Load the tape containing the SS operational 
software on the device assigned to BIN2". Start 
the SSC at location 8100. Using the LCP store 
0080 into locations 0080 and 0081. Depress the 
RESET button. Start the SC at location C102. 

When the RUN light goes out, examine memory 
locations 0080 and 0081 for the following data: 

Memory Location Contents Meaning 


Witnessed by: 

Customer Representative: 


:ytheon QA Representative: 


0080 

0081 


0000 Halt Code 

0000 Success Code 


Turn power off for (5) seconds, then turn power 
on and, when the RUN light goes out after about 
(j— j) oecOiics, coiiiiiiti mat rhe Master Processor 
P register contains FF04. « 


1-22 






APPENDIX A 

BASIC TEST EQUIPMENT CONFIGURATION 











APPENDIX B 
TEST PROGRAMS 


5413:IEWS:76:69 RP--16 CP Test - PROM Version 

5413:IEWS:76:70 Memory Test - PROM Version 
5413:IEWS:76:71 IEWS SC Test 

PIN/RTC Test 
SI0 Test 
SCM Test 
Master Bus Test 
SP1 Bus Test 
SP2 Bus Test 
IEWS SC System Test 


5413:IEWS:76:72 


APPENDIX C 


OPERATING PROCEDURE FOR MOVE ROUTINE 


1. Enter the origin of the 4K memory module, which the program is 
to be moved PROM , into the XR Register. 

2. Enter the origin of the 4K memory module, which the program is 
to be moved TO, into the Register. 

3. Enter 05EO into the PR Register, and depress the RESET button. 

4. Put the RP--16 into RUN mode. 


C-l 



APPENDIX D 


operating procedure for the ssc 


1. Load the operating system into the SSC and start it. 

2. Mount the tape containing the program to be loaded onto 
Magnetic Tape Drive 0. 

3. Type the following commands on the INFOTON keyboard: 

AS BIN1, MTO 
AS BIN2, MTl 
RW BIN1 
BI 8000 
LO 

To start a program in the SSC, type the command: 

GO address 


D-l