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ED 061 977 



52 



LI 003 647 



AUTHOR 

TITLE 



INSTITUTION 

SP0N8 AGENCY 

BUREAU NO 
PUB DATE 
GRANT 
NOTE 



Silver, Steven 3, 

INTX: Interactive Assembler Language Interpreter 
Users* Manual; Preliminary Programming Manual and 
Version II Extensions, Final Report, 

California Univ, , Berkeley. Inst, of Library 
Research. 

Office of Education (DHEW) , Washington, D. C. Bureau 
of Research. 

BR-7-1083 
Sep 71 

OEG- 1-7—07 1083-5068 
34p. ; (8 References) 



EDR3 PRICE 
DESCRIPTORS 

IDENTIFIERS 



MF-$0. 65 HG— $ 3. 29 

♦Computers ; ♦Electronic Data processing; *Information 
Processing; Manuals; ♦On Line Systems; ♦Programing 
Languages 

Berkeley; ♦University of California 



ABSTRACT 

INTX is an interactive programing and debugging 
system operating under UCLA’s URSA interactive console system. 
Although originally designed as a debugging aid for Interactive 
processor development, the addition of an on-line Assembler makes it 
a programing system in its own right. INTX operates only on the 
computer Communications 301 graphics display device making use of 
automatic update and cursor positioning facilities. There are three 
major divisions in the system; (1) Command analysis and 
initialization, (2) Assembler- loader and (3) Interpreter - 
disassembler. The command module displays an initial screen 
describing functions available, current level of development, and 
supervises the operation of all other components of the system. The 
Assembler is a subset of Basic Assembler Language with extended 
branch mnemonics which accepts standard assembly language and the EQU 
pseudo operation. The Iriterpretor module is designed to execute any 
System/360 instruction except the SVC, Any instruction that could be 
successfully executed by a program running in problem state is 
supported. [Related documents are LI 003610, LI 003611, LI 003645, LI 
003646 and LI 003648.] (Author/SJ) 




4J.S. DEPARTMENT OF HEALTH, 
EDUCATION Si WELFARE 
OFFICE OF EDUCATION 
THIS DOCUMENT HAS SEEN REPRO- 
DUCED EXACTLY AS RECEIVED FROM 
THE PERSON OR ORGANIZATION ORIG 
INATING IT. POINTS OF VIEW OR OPIN- 
IONS STATED DO NOT NECESSARILY 
REPRESENT OFFICIAL OFFICE OF EDU- 
CATION POSITION OR POLICY. 



FINAL REPORT 
Project No. 7-1083 
Grant No. OEG-1-7-071083-5068 




INTX* 

INTERACTIVE ASSEMBLER LANGUAGE INTERPRETER USERS f MANUAL 



Preliminary Programming Manual* 
and 

Version II Extensions** 



By 

Steven S. Silver 



Institute of Library Research 
University of California 
Berkeley^ California 9^720 



September 1971 



The research reported herein was performed pursuant to a grant with 
the Office of Education , U*S. Department of Health, Education, and 
Welfare, Contractors undertaking such projects under Government 
sponsorship are encouraged to express freely their professional judg- 
ment in the conduct of the project. Points of view or opinions 
stated do not, therefore, necessarily represent official Office of 
Education position or policy. 



ZD 



CO 

o 




ERIC; 



U.S. DEPARTMENT OF 
HEALTH, EDUCATION, AND WELFARE 



Office of Education 
Bureau of Research 



# date internal report produced; 
**date internal report produced: 



July 9, 1969 
November 20, 1969 



TABLE OF CONTENTS 



P FlELIMINABY PROGRAMMING MANUAL Page 

Introduction 1 

Assembler (ASMX^l) . . . . . . 3 

Interpreter (lNTX#2) „ , , . 5 

Interpreter Internals ...... . . 9 

Appendices : 

I. Command Summary 11 

II* Instruction Classes and Micro Programmed 

Instructions. . . . i 13 

III * SVCX Instructions l4 

IV. Error Messages l8 



VERSION II EXTENSIONS 



Exe cuter 



SVCX 3 . 21 

SVCX 4 23 

SVCX 11 24 

SVCX 35 »»»«»*.»..»...#«•.•. ... 25 

SVCX 0. .***..*•.«.**«.*...**•. 26 

Register Notation in Commands Setting 26 

SI,, SS, and SF Stops. 27 

Instructions Executed Counter ............ 27 

Display of Symbolic Instruction Counter ....... 27 

First Line Dor Command Entry. ............ 28 

Message Handling 28 

Fetch Protection Extension. 28 

INX and ND. , 28 



Assembler 

USING j DROP 30 

START and QRG „ 30 

DSECT and CSECT . . . 30 

Constants 30 

Error Messages 31 

Storage Retirements , 31 

Data Set Checking 31 




. Z 



FOREWORD 



This report contains the results of the second phase (July, 

1968 - June, 1970) of the File Organization Project, directed toward 
the development of a facility in which the many issues relating to 
the organization and search of bibliographic records in on-line com- 
puter environments could be studied*. This work was supported by a 
grant ( QEG- 1-7-071083^5068) from the Bureau of Research of the 
Office of Education, U,S, Department of Health, Education, and Welfare 
and also by the University of California, The principal investigator 
was M, E. Maron 5 Professor of Librarianship and Associate Director, 
Institute of Library Research; the project director and project manager 
were, respectively, Ralph M. Shoffner and Allan J. Humphrey, Institute 
of Library Research. 

This report is being issued as seven separate volumes: 

■ Shoffner, Ralph M- , Jay L, Cunningham, and Allan J. Humphrey . 

The Organization and Search of Bibliographic Records in On-line 
Computer Systems* Project Summar y. 

* .Shoffner, Ralph M, and. Jay L* Cunningham, ede * The Organization 

and Search of Bibliographic Records: Component Studies , 

* Aiyer, Arjun K . The CIMARON SYSTEM: Modular Programs for the 

Organization and Search of Large Files * 

* Silver, Steven S. INTX : Interactive Assembler Language 

Interpreter Users f Manual . 

* Silver, Steven S. FMS: Users 1 Guide to the Format Manipulation 

System for Natural Language Documents « 

* Silver, Steven S, and Joseph, 0. Meredith. DISCUS Interactiv e 
System Users f Manual. 

* Smith, Steven F. and William Barrels on. TMS: A Terminal Monitor 

System for information Processing . 

Because of the joint support provided by the Information Process- 
ing Laboratory Project ( QEG— 1-7-071085— ^286) for the development of 
DISCUS and of TMS, the volumes concerned with these programs are in- 
cluded as part of the final report for both projects. Also, the 
CIMARON system (which was fully supported by the File Organization 
Project) has been incorporated into the Laboratory operation and 
therefore in order to provide a balanced view of the total facility 
obtained, the volume is included as part of the Laboratory project 
report. (See Maron, M.E. and Don Sherman, et al. A-n Information 
Processing Laboratory for Education and Research in Library Science : 
Phase 2 . XLR 1971.) 



I H T J£ 



Interactive Assembler Language Interpreter 



Under UHSA 



Preliminary Programming Manual 



Supported By 

The Campus Computing Network 
the Office of education 



Steven S« Silver 
Institute of Library Research 
University of California, Los Angeles, Berkeley 



-ili— 



O 

ERLC 



4 



INTRODUCTION 



INTI is an interactive programming and debugging system 
operating under UCLA's URSA interactive console system. Although 
originally designed as a debugging aid for interactive processor 
development, the addition of an on- line Assembler makes it a 
programming system in its own right. 



HARDWARE 



INTX operates only on the Computer Communications 301 
graphics display device making jse of automatic update and cursor 
positioning facilities. 



QR5ANIZATXQN 



There are three major divisions in the system: 

1) Command Analysis and Initialization, 

2) Assembler-Loader, 

3) Inter preter— Disassembler . 

The rest of this document will describe the functions and 

attributes of each of these divisions. See figure 1 for a system 
organization chart. 



COMMAND MODULE IINT^L 



The Command module displays an initial screen describing 
functions available and current level of development. The 
Command module also supervises the operation of all other 
components of the system. 

When either the Assembler or Interpreter need control 
commands analysed they must transfer control to the command 
module. In the case of the Assembler, control is not passed back 
unless specif icely requested. The Command module will pass 
control to the interpreter after it has performed command 
a nal ysis. 




-i- 






FIGURE 1 



SYSTEM STRUCTURE 






- 2 - 



ASSBHBL2R (ASHXtl) 



The Assenb ler is a subset, of Basic Asseoblsc Language with 
extended branch mnemonics. The pseudo operations currently 
available are EQU , DS, and DC. The Assembler is invoked by 
typing "ASH'* in the command modulo and it will not normally 
relinquish control until it has finished assembling. The source 
input data set must be a standard KEYPUNCH {URSA proqraa editor) 
data set (i.e. DCB- (RECJTM— FB,BLKSIZE = 4 00 , LRECL«SO) ). 



ASSEMBLER EXTERNAL D ESCR IPTION 



The assembler accepts standard assembly language and the EQU 
pseudo operation. Any legal 360 Assembler statement will be 
accepted with the following restrictions! 

1) No literals, 

2) No implied lengths, 

3) No multiplication or division in statement construction. 

There is minimal error checking. Only undefined symbols 
will suspend assembler processing (until interrupt is pressed) • 
The system has a maximum capacity of 100 symbols and a 2K 
over-all program length limitation. 



initializaiion 



A program storage area into which the program will be loaded 
for execution is obtained. 

The data set to be processed is identified by completing the 
partial data sat name on the console screen. Pressing interrupt 
will begin processing. 




T 



3- 



PASS I 



During the first scan of the input source 
generated and EQtJ statements are analysed, 
assumed to be the base register by this version 



a symbol table is 
Register 15 is 
of the isseibler. 



PASS II 



The operand field of each statement is analysed and symbolic 
references are resolved. Errors are ignored and a best guess is 
assembled in lieu of correct code. As each statement is analysed 
it is loaded into the program storage area. 

When this pass is completed register 15 is set equal to the 
start of the program. Control is returned to the command module 
with a "start execution" command supplied. 



SVCX 



The ItJTX instruction set makes use of the SVCX operation to 
invoke certain system functions supplied by the Interpreter. It 
is a four byte instruction having a HEX 51 operation code. The 
low order bits describe the operation to be performed. The 
appendix gives a detailed explaination of the function of each 
SVCX thus far implemented. 



O 

ERIC 



U' 



- 4 - 



INTERPRETER (XNTX#2) 



The Interpreter module Is designed to execute any System/360 
instruction except the SVC. Any instruction that could be 
successfully executed by a program running in problem state is 
supported. If a program check occurs# a message describing the 
failure appears on the screen and processing is suspended. The 
program under interpretation does not control its own execution 
for more than one instruction. 



SVC-SVCX 



svc's are not supported for the following reasons; 

1) Control over a program is usually lost after an SVC is 
issued# 

2) Many SVC • s are highly installation and operating system 
release dependent, making implementation difficult, 

3) System integrity can not be guaranteed during an SVC. 

To provide functions usually performed by SVC's the SVCX has 
bean defined. Detailed functional descriptions of this 

instruction will be found in the appendix. since svcx is a 
built-in function of the Interpreter its functioning code is not 
a part of the users program code. 



COMMAND INJRy 



Control states within the Interpreter are usually modified 
by explicit command. Commands are entered on the top line of the 
screen. When interrupt Is pressed the Command module will change 
the state of the Interpreter. 




-S« 



9 



FIGURE 2 



INTERPRETIVE DISPLAY LAYOUT 



COiyttlAND ENTRY LINE 



FLOATING POINT 
REGISTERS 



GENERAL 



PURPOSE 

REGISTERS 



SENSE AND STATE 
INFORMATION 



DISASSEMBLED INSTRUCTION 



INFORMATIVE MESSAGES 



STORAGE DUMP DISPLAY 





lo 



MACHINE DIS£LA£ 



The Interpreter will display the 16 general purpose and 4 
floating point registers, the condition code byte and instruction 
counter, the HEX and disassembled version of the instruction just 
executed, and a core dump of a selected area of storage. See 
figure 2 for the screen layout. 

The progress of the execution of a program can be monitored 
during each execution cycle by entering YD (Yes Display) mode. 
This mode is automatically assumed if a program check occurs. 
High speed execution can be resumed if ND (Np Display) is 
specified. 



CORE DISPLAY CON TRO L 



The core dump display is controlled by commands which set 
the Dunp's starting address directly, indirectly, based on the 
contents of a register, or based on the address of the 
instruction currently being executed. See the appendix for 
information on how to use these functions. The starting address 
of the display is always aligned to the next lowest full word 
boundary. 



IPSfifi OF JXECOTION 



The speed of display mode execution is controlled by the M T** 
(Time) command. Execution is delayed a specific number of 
seconds between instruction cycles. The next instruction can be 
executed by pressing interrupt or waiting for the time 
specification to elapse. Setting a large time estimate will 
essentially allow single stepping through a program. Turning off 
display mode will override the time specification and speed up 
e xecution • 





-7- 




EXE CUTION CO NTROL 



The ranges of execution may be redefined but the area in 
which a program may store may not. Commands are available to 
modify the instruction counter and the contents of the general 
purpose registers. 



STORA GE AN D £ET£H PRO TEC T 



Programs are permitted to execute and store only within the 
boundaries defined by the physical code loaded by the Assembler. 
All instructions that store or fetch information from storage are 
validity checked to make certain they reference core only within 
the established bounds. Branch addresses are pr e-calculat ed 
calculated and checked before use. 

1 NT X uses the pecking order established in the (JRSA time 
sharing system in the following way; Non-systems programmers 
cannot access data (fetch) or branch outside of their program 
area. If systems programmers wish the fetch protection option 
they may use the P3ET command. 



INCONSISTENCIES 



The Interpreter will give faithful 
except the BAL and BALR instruction. It is 
for the instruction length to be in 
instructions are directly executed. The 
branch address are correct. 



results in 


all cases 


possible in 


this case 


error since 


not 


all 


condition 


code 


and 




• 8 . 






13 



INTERPRETER INTERNALS 



OPERAT ION CODE ANALYS IS 



A software definjed instruction counter points to the 
instruction to be executed. The one byte operation code is used 
as an index into a table, each entry of which contains the 
character form of the operation, special flags controlling 
execution, and a displacement classifying each operation into one 
of ten types of instructions (in addition to error) . This 
information is used by the Interpreter to disassemble the 
instruction . 



DISASSEMB LY AND RESISTED ALLOCATION 



Disassembly is based on the different formats for 
representing an instruction by the Assembler (i. e. RR, SI, S3, 
etc). As the instruction is being disassembled, registers are 
fad into an allocation scheme which converts the requested 
register into a real register reference. The resulting real 
register is not within GPR*s 10 through 15. These 6 are reserved 
by the Interpreter for maintaining control over the program under 
execution. 

By using an allocation technique the user is not required to 
use a subset of the real register set. All sixteen registers 
appear to be available for use. 

In most cases the result of execution will be obtained with 
little actual Interpreter instruction modification. For example, 
any arithmetic operation not using a register above 9 will 
execute "as is**. 




-9- 

■*7 - > 



EXECUTION 



The parsed and reconstructed instruction is placed into an 
instruction storage block that is terminated by a BALR 15,10. 
Register 15 will contain, after execution, the resulting 
condition codes. Register 10 will be preloaded with the 
addresses to which control is to return to the Interpreter. If 
the instruction has not been flagged as being invalid the 
Interpreter will branch to the instruction block. Control is 
either returned to the address pointed to by register 10, passed 
to a branch address within the freshly reformed instruction, or 
passed to the SPIE routine after its execution caused a program 
check. Model 91 imprecise interrupts are correctly handled. 



MICRO - P R OGRA MMED INS£ RUCTIONS 



If the instruction is one of the twelve instructions that 
may either gain or seize control (BC, BXLE, etc) or which have 
strange properties (STM, EX, etc) then a pseudo micro-programmed 
version is executed in place of the instruction Itself. The net 
result will be equivalent. 




10 - 



14 



APPENDIX X 



C3HHAND SUHHARY 



IC-address. .... 


..... 3 e t t h e 

specified • 


instruction 


counter 


to 


the 


value 


ICR^register ... 


. , . . , Set the 


instruction 


counter 


to 


the 


value 



contained in the register specified, 
(register) =value. ... Set a General Purpose Register* 



T-v alue. ........ « ... Set the speed of execution. 

YD.., Allow the display of the state of the machine 

while interpreting. 

HD ..Turn off the machine state display, 

HE-address. ......... Set the high limit of execution. 

LE=address. Set the low limit of execution. 

ASH ................. Tra nsfer control to the Assembler. 

IX. ................. Interpret with execution. 

I NX. ............. „ .. Interpret and scan with no execution. 

PSET. ............... Reset fetch protect for system programmers. 

X .Use experimental modules (RESTRICTED). 

D=address. .......... Core dump display at address specified. 

DI-address. ......... Core dump display starting at address pointed 

to by full word at address specified. 

DR^register Core dump display starting at address 

contained in register specified. 

DE. ..... a ........... Cor e dump display starting at the address 

pointed to by the instruction counter 
(default mode) • 



Address, register, and value information can be supplied by 
combining the operators ♦ and - and either decimal or 







-ii- 

15 



hexadecimal (base 16) 
followed by a period 
instruction counter 
instruction counter, or 
dump routine. There 
command. 



data where decimal information must be 
( s ) , * is the current value of the 

when used to set a register or the 
the last address displayed by the core 
must not be any embedded blanks in the 



EXAMPLES (1+C-12. ) »*+FFF— 15. is 
setting the value of register 1 egual to 
instruction counter ♦ FFQ. 



a valid input format 
the current value of 



for 

the 





APPENDIX II 



INSTRUCTION CLASSES AND MICRO PROGRAMMED 
INSTRUCTIONS 



ilSl 


Jsge 


IBM C28-651.4-5 pJM 71 


HR 1 


OP 


R 1 , R 2 


RR2 


OP 


B 1 


RR 3 


OP 


I 


RXl 


OP 


Hi, D2 (X2, 12) 


RSI 


OP 


SI, R3, D2 (B2) 


RS2 


OP 


R 1 , D2 (12) 


SI 1 


OP 


D 1 (B 1) ,12 


SI 2 


OP 


D 1 (B 1 ) 


SS 1 


OP 


D 1 (LI ,B1) ,D2 (L2,B2) 


SS2 


OP 


Dl (L, 81) , D2 (B2) 



MICRO PROGRAMMED INSTRUCTIONS 



SVCX BALR BAL BCR BC BCTR BCT BXH BXLE BX LM SPM STM 



-13- 



3 

ERIC 



l 1 ? 



APPENDIX III 



S VCX INSTRUCTIONS 



DIRECTORY; 



SVCX 



FUNCTION 



0. ...... Console Comonlcation. 

1----- Indirect execution of INTX commands. 

2. ................. .Non-fa tal transfer to DEBUGGER (URSA S PI E 

routine) • 




-14- IQ 




SVC* 0 CONSOLE INPUT/QOTPUT 



Calling Sequence: 



LIST 



LA 


1 t LIST 


SVCX 


0 



DC F * write_addr * 

DC F* write^length* 

DC F®read_addr* 

DC F • read_length * 

DC H* 0* length of read 

DC H*0* reserved 



write_addr» 



location of area from which data will be 
written starting at the top left-most corner 
of a screen after an erase. 



wri te_lenqth . ...... .true length of write to be performed. If 

this is zero the write will be ignored. 

read^addr. .......... location of area to which data will be 

transfered. Transfer will start from the 

location of the cursor as left by the 

previous write. 

read^lenqth. • • • • ■ . • • the maximum number of characters to be 

transfered by the read. If zero no read will 
be done. 



length read ........ .the number of characters actually read by an 

issued read. 



reserved 



NQTE: 



•■•••••• will contain status flags relative to 

console I/O operations. 



All standard INTI storage and fetch protection will be 

observed in I/O operations. 




-IS- 

IS ~ 



SVCX 1 



PROGRAM C OUT ROLLED COMMAND ENTRI 



Calling Sequence: 
LA 1 0 LIST 
SVCX 1 



LIST DC C'intx_confflands* 

DC X*0* 



intx_com Bands. ..•••.Any command sequence that could normally be 

entered on the top (command) line of the I Nr X 
interpreter. 




-16- 







SVCX 2 



CONTROLLED EM TRY TO DEBUGGER 



Calling Sequence: 
SVCX 2 



COMMENT 



1NTX registers 2 through 10 are moved into the real 
registers and module iNTX#3 is entered which gets a 0C3 program 
check. 1NTX #2 # the Interpreter, is not affected by the DEBUGGER 
entry. 




- 17 - 



APPENDIX IV 



ERROR MESSAGES 



0C1 

0C2 

QC3 

0C4 

0C5 

0C6 

0C7 

0C8 

0C9 

oca 

OCB 

OCC 

OCD 

OCE 

DCF 



Operation 

Privlliged-operation 

Execute 

Protection 

Addressing 

S pecification 

Data 

Fixed-point-overflow 
Fixed— point- divide 
Deci a a 1-over flow 
Deei a al— divide 
Exponent— over flow 
Exponent— under flow 
Significance 
Floating— point— di? ide 



Out of execution area 
software detected protectiong 
SVC suppressed 
Bad S VCX instruction 
Object of execute 



***** aessaqe waiting. Please type "end* 



Software fetch violation 

Protection 

Addressing 

Specification 

Data 

Fixed— point— over flow 
Fixed— point-divide 
Exponent- overflow 
Exponent- underflow 
significance 
Floating— point-divide 



- 18 - 



ER1C 




aotOiQtaiOiCbOi&iainiCuotQiQiKMKX^ hhmmhhhhhh 



I N T X 



Interactive Assembler Language Interpreter 

Under URSA 

Version II extensions 



Supported By 

The Campus Computing Network 
The Office of Education 

OEG- 1-7-071083 Hayes 



DISCUS Project 



Steven S. Silver 
Institute of Library Research 
University of California, Los Angeles, Berkeley 




scr 1 



- 19 - 



SVCX 3 



CARD IMAGE DISK INPUT/OUTPDT 



Calling sequence: 

DA 1 # L 1ST 
SVCX 3 



LIST DC 
DC 
DC 
DC 
DC 
DS 



A (address_of_80_byte_buf far) 
P* ralative^car d_ number * 

A (card_not_f ©und_exit) 

A (addr__© f_VOL_DSN_f ield) 

X* type~of_I/0* 

XL3 reserved 



address_o£_ 8 0_byte_ bu f fer . - - . DS 80C an area which holds the card 
being operated opon. 

relative_card_n umber an integer which indicates the card 

to be operated opon (1 is the first card) 

eard__not_found_exit .......... the address specified receives 

control of the card sequence number specified does not 
exit. 

addr_,of_VOL_DSN_£ ield, ....... a 50 byte field having the following 

focnat: 

DC CL6 8 volume^naie* or XL6* 00* for cataloged. 

DC CL44 * f ull y_qualif ied__data_set_name * 

t ype_of_ I/O. ............... ..a one byte field with one or more of 

the following bits on: 

X*01* read a card 

X , 02* write a card 

X*04* reestablish the data set (i.e. reopen it 

based on the VGL_D5N field) 

reserved. .................... reserved for future expansion 



- 21 - 




34 



NOTE 



1) only one DSN— VOL field may be in effect at one time, 

2) the first reference to a data set will be equivalent 
to having X*04* type specified in addition to the read 
or write flag, 

3) storage and fetch protection are observed, 

4) major errors cause ”bad svcx ins true tion" messages 
to appear, 

5) pretest ablished URSA KEYPUNCH data sets are used; 

DCB= (RECFB-F B # BLKS 121^4 00 # LRECL=80) 

6) blocks can not be added to the end of a data set by 
this SVCX, 





-22 



svcx a 



DBS & CONSOLE SYSTEM DATA 



Calling seguencei 

LA 1 , LX ST 
SVCX 4 



LIST DS 

DS 

DS 



F address_of_your_FC& 
6C yout_ job__nuiBber 
3C your__initials 



address^of^yout^FCA A full word pointing to the start of 

the 4K block of storage reserved for the console being 
used. 

your_iob_ number The lob number being charged for 
your console use. 

y our__initials« ............... The three byte form of the initials 

used to sign on to the console system. The last 
position will be blank if two character initials were 
used. 

NOTE: Storage protection is observed. 




- 23 - 



26 



SVCX 11 



TIME OF DkY 



Calling sequence; 

SVCX 11 

1 



NOTE: 

Equivelent to an OS aacco; TIME DEC. 

2) Beqisters 0 and 1 are modified by this SVCX. 




-2h- 



27 



5 VCX 35 



WTO 



Calling sequence: 

LA 1 , L 1ST 

S VCX 3 5 



LIST DC 
DS 
DC 



H* length_of_Bessaq€_* - 4 • 
H 

C * message* 



length^of^iessage^*,^ A half word containing the length of 

the complete data list. 

message .The message you wish to output to 

the operator console, 

NOTE: 

1) The message is typed on the operators console with the prefix 

message code ,, CSM300X ,, , 

2) Reserved exclusively for systems programmers. 



O 

ERIC 



- 25 - 



5Y5TEH CHANGES 



s TCI - 0- CHAN GES- 



1) An automatic time sequencing feature has been added: 
DC F* vc it e_lengt h* 
is replaced by: 

DC H* t ime-out^wait* 

DC H * wri te__ length * 



Where "tin e— out _ time” is the tine in seconds to wait until a 
console interrupt is simulated. A real console interrupt 
overrides this parameter. A specification of less than 
three seconds is reset to 300 seconds (five minutes) . 

2) The full 800 character screen may now be used. 



REGISTER 



The contents of the general purpose registers can be 
used in the calculation of values used by the command 
module. A single Hex: or Decimal value surrounded by 
parenthesis will be treated as the contents of the 
eguivelent register. 



For example: 1C — (14, 

instruction counter to the 
less the contents of register 
the instruction counter at 
command • 



) — (A)— 3+* means set the 

value contained in register 14 
10 less 3 plus the value of 
the start of execution of the 



STORAGE REFER ENCE STOPS 



con 

COD 



exa 



To aid in program debuqqinq three "stop on storaq 
dition" commands are available. Each must be set b 
mand to a particular absolute address location. 

SI stops the machine when the instruction counter 
ctly matches the value specified 



SS stops 
pleted . 


w hen 


a 


store 


SF stops 
pleted • 


when 


a 


fetch 



at a particular location is 



from a specified location is 



Each stop may be disabled by setting it equal to zero. 
The stop time is 1 minute or the last value of T, which ever 
is longer, as with all severe errors. 



INSTRUCTI O NS EX ECU TED C OUN TER 



NX holds the number of successfully executed 
instructions since the last time NX was set. It can be set 
to any value by command and is initially set to zero when 
execution begins. 



HIGH AND LOW V ALU ES OF STO RAGE AND EXECUTION 



All storage and fetch protection checking are based on 
the limits of storage which are now displayed. Only 
execution boundaries may be changed. Storage limits may not 
be changed. 

P IS PL AX OF SYMBOL IC INSTRUCT IO N COUNTER 



If an INTX assembly was done to generate the code to be 
executed the symbol table from the assembly is left in core 
during the execution run. In addition to the Hex instrut ion 
counter the closest low value of labeled statement in the 
blank CSECT is also displayed with any appropriate 
displacements. 





27 - 



*< # 



START 



R1»B (R 2) 



line; 



i • €• i 

1 START LA 

2 B START 

Statement 2 might generate 

BC 15,34(0,14) 



the following information 



START+4 



FIRST LIME. COMMAND ENTRY 



During execution any command entered on the first line 
of the display screen will be executed no matter what the 
state of the program under execution. The cursor must be on 
the first line of the screen for data to be treated as 
command input. 



MES S AGE HANDLI NG 



When a message is sent to someone in 
explanitory error message will appear. The user 
to ignore this if he wishes but it is advisable 
INTX to find out the contents of the message. 



I NTX an 
may choose 
to leave 



FETC H FROT ECTXON EXTENSION 



Anyone can now reference any area of low core — 
than the address CVTNUCB in the CVT — without a 
protection exception. 



lower 

fetch 



IN X and JjD 



I NX 
suppress 
Execution 
command. 



will 
the i 
may 



now suppress 
ncre men ting 
continue 



the execution of instruct! 
of the instruction counter 
by issuing either an IX 



ons and 
(IC) . 
or ND 



ND now also implies the execution of IX, 



Execution 




- 28 - 



j- 



* 



31 



continues at high speed when ND i: 




> % 




specified. 



CHANGES TO THE ASSEMBLER 



USING AND CROP 



Usings are now required for all programs. Register 15 
still point to the start of the program but the user 
must ^ supply ,1 using indicating this fact. The using may 

specify up to 2 registers. Drops are limited to no more than 
3 registers at a time. 



ST i BT AND QBG 



In this assembler OHG and START are exactly the same. 
Each modifies the instruction counter within its own csect 
(or dsect) . As in the OS assembler a blank operand is 
assumed to refer to the highest value in the csect or dsect. 



DSECT AND CSECT 



A total of up to 10 csects and dsects may be used 
including the initial unspecified blank csect. Multiple 
csects are loaded in the order in which they are first 
referenced. Dsects are treated exactly like csects except 
loading is suppressed. 



CONSTANTS 



A, V and Y constants are now operational. Multiple 
constants may be specified in a single statement with the 
following restrictions: 

1) commas may not be used within the quoted or 
par enthasised lists of arithmetic constants. 

2) constants of the fora nALm(*) will use the value * 




93 



- 30 - 



calculated at the start of the expression and the same value 
will be propogated for each iteration. 



ERROR MESSAGES 



The assembler now issues error messages for most raa-jar 
syntactical errors along with a pointer to the approximate 
area of the error. Job control language in the intx program 
will not cause an error to be issued or executable code to 
be generated. 



STORAGE REQUIREMENTS 



Programs can vary in size between 2 and 8 thousand 
bytes. There is a fixed 4 thousand byte overhead for a 
symbol table passed to the executor for better debugging 
displays. 



DATA SET CHECKING 



Any data set with a second index level of CCN will be 
treated as a public data set (for assembly input only). Any 
user may reference a data set with this structure. 



- 31 - 

34