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Radio /haeti 

Service 








® 



MODEL 100 

MICROCOMPUTER 



26-3801 



PRELIMINARY 

PRODUCT 
INFORMATION 



•- 



0220 TECHNICAL SUPPORT SERVICES 



/ 



MODEL-100 



SERVICE MANUAL 



#0220 TECHNICAL SUPPORT 
DOCUMENTATION LIBRARY 



3 



TABLE OF CONTENTS 

SECTION 
NUMBER 

I INTRODUCTION 

■ SYSTEM OVER VIEW 

1. Specification 

2. Switches and Connecters 

3. Key Layout 

4. LCD character Font 

II DISASSEMBLY/REASSEMBLY 

1. Disassembly 

2. Reassembly 

III MAIN P.W. BOARD TECHNICAL DESCRIPTION 

1. LSIs 

2. Memory 

3. Address Decoding and Bank Description 

4. Memory Map 

5. I/O Map and I/O Port Description 

6. Keyboard 

7. cassette Interface Circuit 

8. Printer Interface Circiut 

9 Bar Code Reader Interface Circuit 

10. Buzzwe Control Circuit 

11. System Bus 

12. LCD Interface Circuit 

13. Clock Circuit 

14. Serial Interface Circuit 

15. Power Supply and Auto Power Off Circuit 

16. Reset Circuit 

MAIN P.W. BOARD PARTS LIST 

IV LCD P.W. BOARD TECHNICAL DESCRIPTION 

1. LCD Pannel 

2. LCD Contrl Circuit 

3. LCD Waveform 

LCD P.W. BOARD PARTS LIST 

V ILLUSTRATION PARTS CATALOG 
ILLUSTRATION PARTS LIST 



3 



VI TROUBLE SHOOTING 

1. Trouble Shooting Guide 
2.Chevking Procedure 
3. Check List 

VII PRINED WIRING BOARD 
MAIN P. W. BOARD 

LCD P. W. BOARD 



£ 



CONFIDENTIAL 



SECTION 1 

INTRODUCTION 



S" 



System Overview 
i. Specifications 
(1) Main Components 
(a) Keyboard 

71 keys (9x8 matrix) 

Alphabet keys 2 7 

Number keys 10 

Picture-control keys 7 

Function keys 8 

Special symbol keys 8 

Mode keys 5 

Other special-use keys ...... 6 

LCD display 

Display Panel . . . 240 x 64 Full-Dot matrix 

1/32 duty 
1/6.66 bias 

Dot Pitch 0.8x0.8mm 

Dot Size 0.73 x 0.73 mm 

Effective Display Area . . . 191.2 x 50.4 mm 



(b) 



(c) 



(d) 



Case 

Dimensions .... 300 
Material , . . . . ABS 

Operation Batteries 

Batteries .... 



(W) x 46.5 (L) x 215 (H) 



mm 



Operation time 



(e) 



. Four alkali-manganese batteries 
(AM-3) 

. 5 days (at 4 hours/day) 
20 days (at 1 hour/day) 
(note: with I/O disconnected) 
Memory Protection Battery (on main PWB) 



Battery .... 
Protection time 

Re char ere method 



Rechargeable Battery (3-51FT) 
About 40 days (8 KB) 
About 10 days (32 KB) 
Trickle charge by AC adaptor, 

or operation batteries 



(f) LSIs 

CPU . . . 80C35 (OKi) 

Code and pin compatible with 8085 
ROM . . . Max. 64 KB (2 Banks of 32 KB) 

STANDARD 32 KB 

OPTION 32 KB 
RAM . . . Max. 32 KB 

STANDARD 8 KB (four TC5518BF (TOSHIBA)) 

RAM PACK 

incremental 8 KB RAM PACK on PWB 
CLOCK /CALENDAR . . . yPD 1990AC (NEC) 

No leap year /No February 2 9 
(2) I/O Interface 
(a) RS-232C 

Conforms to EIA standards 
Signal . . . TXR (Transmit Data) 
RXR (Receive Data) 
RTSR (Request To Send) 
CTSR (Clear To Send) 
DSRR (Data Set Ready) 
DTRR (Data Terminal Ready) 
Programmable Items 

* Data Length . . . 6, 7 or 8 bits 

* Parity NON, EVEN or ODD 

* Stop Bit Length . . 1 or 2 bits 

* Baud Rate .... 75, 110, 300, 600, 1200, 2400,4800, 

9600, 19200 BPS 
Maximum Transmission Distance ... 5m 



Driver maximum voltage output 
Driver minimum voltage output 
Receiver maximum voltage input 
Receiver minimum voltage input 



±5V 
±3.5V 
±18V 
±3V 



7 



(b) Modem/Coupler 

Conforms to BEL103 standards 
Baud Rate . . . 300 BPS 
Programmable Items 

* Date Length . . . 6 , 7 or 8 bits 

* Parity NON EVEN or ODD 

* Stop bit .... 1 or 2 bits 

Full Duplex Answer mode / Call mode, 

switchable 
Other Functions . . . Hang Up Function 

Auto Dialer Function 
(C) Audio Cassette Interface 

Data Rate . . . 1,500 BPS 

(MARK: 2,400 Hz, SPACE: 1,200 Hz) 
(d) Printer Interface 

Conforms to Centronics Interface standards 



Handshake Signal . . . STROBE, BUSY, SELECT 
(3.) Special functions 

(a) Automatic power OFF 

When there is no program operation (awaiting command) 

for ten minutes, the power is automatically cut off. 

If the PPC is started once again, the power switch is to 

be switched OFF and then ON, thus releasing the 

automatic power OFF condition. 

The display will remain the same as before the power was 

cut off. 



V 



2. Connectors , Switches and Contrast Volume 
(1) Connectors 

RS-232C 25 pins (DB-25S) 

Printer 26 pins (FRC2-C26-L13-ON) 

Modem 8 pins (TCS-4490) 

Cassette 8 pins (TCS-4480) 

Bar Code Reader 9 pins (A-7224) 

System Bus 40 pins (IC Socket) 

AC Adaptor s.S<P (Center Minus) 

C 2) Switches 

(a) Power Switch 

This is the PPC system power switch. 



OKJ IflD OFF 





ON ED OFF 



Power OFF 



Power ON 



Fig. 1 



(b) ANS/CALL selector 

This switch is used to select the MODEM ANSWER mode or 
CALL mode. 



ams j (HDi oRiq- 



AWS ED 0RI6- 



Call mode Answer mode 

Fig. 2 



(C) Coupler/telephone selector 

This switch is used to select COUPLER (acoustic coupler 
connection) or TELEPHONE (direct connection) . 



DfR M Acp 





DIR ED acp 



COUPLER (ACOUSTIC TELEPHONE (DIRECT TELEPHONE 
COUPLER CONNECTION) LINE CONNECTION) 

Fig. 3 



;d) 



(e) 



MEMORY 3 A CK UP ■ Sri tck 

This switch is for prevention of overdischarge of the 

Ni-Cd battery for RAM back-up. The HHC will not operate 

regardless of the setting of the power switch, unless 

this switch is ON. 

Set this switch to OFF if the unit is not to be used for 

a long time. 

Note that the RAM will not be backed up when this switch 

is set to OFF. 



OM H Off 




ON H OFF 



MfEMORY-BACk UP OM 



MEMORY BACk UP OFF 

Fig. 4 
Reset switch (push switch) 

This switch initializes (resets) the system. A cold 
start can be obtained by pressing it at the same time 



the 15HIFTI ke^ cvncj |BRAKE| Ke.^ are pressed. 
(3) DISP volume 

This is for adjustment of contrast of the LCD relative to the 
viewing angle. 



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SECTION II 



DISASSEMBLY /REASSEMBLY 



*$- 



DISASSEMBLY 

(1) Disconnect the cables connected to the unit. Next, being 
careful not to scratch the key top, turn it over and remove the 
4 screws from the upper and lower cases. 

(2) Remove the upper case so that it opens to the right side. Note 
that the upper and lower cases are secured by Simps. Also, don't 
apply too much force when pulling open, because the LCD and K/B 
connectors are attached. 

(3) Remove the LCD and K/B connectors from the main PWB. 
C4) Remove the buzzer connector from the LCD PWB. 

2. K/B PWB 

(1) Remove the 5 screws, and then remove the K/B PWB. 

(2) Remove the K/B supports at the same time. 
3.LCD PWB 

(1) Remove the 4 screws, and then remove the K/B PWB. 
4-. MAIN PWB 

(1) Remove the 7 screws. 
' (2) Remove the main PWB upward. Be careful when removing the reset 
switch and battery contact spring. 



^>4> 



REASSEMBLY 
f.MAIN PWB 

(1) Align the screw positions of the lower case with the main PWB. 
Gently insert the main PWB from the rear and place the reset 
switch knob in the proper notch. 

(2) Secure the battery contact spring. 

(3) Attach the main PWB to the lower case by using the seven M3 x 8 
screws . 

2. LCD PWB 

U) Attach the LCD PWB to the upper case by using the four M3 x 3 

screws. 
(2) Insert the buzzer connector in the LCD PWB. 

3, K/B PWB 

(1) Align the 2 K/B supports with the holes in the PWB, and attach 
them so that they fit to the PWB edge. 

(2) Align the K/B supports and K/B PWB holes with the upper case 
screws. 

(3} Attach the K/B supports and K/B PWB to the upper case by using 
the five M3 x 8 screws. 
4. CASES 

(1) Turn the upper case over to the right side of the lower case. 
Be careful not to scratch the key top. 

(2) Attach the LCD and K/B connectors to the main PWB. 

(3) Then place the upper case over the lower case, taking care that 
the cable is not pulled. 

(4) Align the upper and lower cases so that the tabs fit well. 

(5) Turn the cases over, and secure them together by using the four 
M3 x 8 screws. 



2? 



SECTION III 
MAIN P.W. BOARD 



z8 



TECHNICAL DESCRIPTION 

As described below, the technical description of the Model 100 

main P.W. board is divided into 16 sections. 

1. LSIs 

2 . MEMORY 

3. ADDRESS DECODING & BANK SELECTION 

4. MEMORY MAP 

5. I/O MAP & I/O PORT DESCRIPTION 

6 . KEYBOARD 

7. CASSETTE INTERFACE CIRCUIT 

8. PRINTER INTERFACE CIRCUIT 

9. BAR CODE READER INTERFACE CIRCUIT 

10. BUZZER CONTROL CIRCUIT 

11. SYSTEM BUS 

12. LCD INTERFACE CIRCUIT 

13. CLOCK CIRCUIT 

14. SERIAL INTERFACE 

15. POWER SUPPLY & AUTO POWER OFF CIRCUIT 

16. RESET CIRCUIT 

1. LSIs 

(1) MSM80C85ARS (CPU) 

1-chip, 8-bit C-MOS Process Microprocessors 

The MSM80C85ARS (80C85) is a complete 8-bit parallel 

Central Processing Unit (CPU) . Its instruction set is 

100% software compatible with the 8080A microprocessor, 

and it is designed to improve the present 8080A's 

performance with a higher system speed. 

The 80C85 uses a multiplexed data bus. The address is 

split between the 8-bit address bus and the 8-bit data 

bus . 

For the Model 100, the data bus and address bus are 

separated by Ml (TC40H373P: octal "D" type latch) . 



The driveability of the bus line is increased by M2 
(TC40H24P: octal bi-directional b- 
(TC40H244P: octal buffer/driver). 



(TC40H24P: octal bi-directional bus buffer) and M2i 



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REG. 



men pointed 



mOWMMCOUMTIII 



«! . 

«1 ■ 



a. 



ruiMOANO CONTROL 



I I 

KB wl 



~ TT TH 

I 1(1, IQ/fl I HU 



»DO«miU»FE« 



mloa I «mrouT 
hoio SHOTS' 



TT 



5L 



OATUAOORta mitm 



¥ 



An^A, 

ADORES II 



ADOMlMMTASUi 



Fig. 1 



80C85 CPU FUNCTIONAL BLOCK DIAGRAM 



RSTS.S C 9 



AOg C 17 
AO« C 18 
AO7 C 1» 
Vss C 20 



*? 



40 


3 Vcc 


39 


3 HOLD 


38 


3 HLOA 


37 


3 CLK(OUT) 


36 


3 RESET IN 


35 


3 HEADY 


34 


3 IO/M 


33 


3 Si 


32 


3 RD 


31 


3 WR 


30 


3 ALE 


29 


3 So 


28 3 A15 


27 3 All 


26 3 A13 


25 3 A 12 


24 3 A11 


23 3 A10 


22 3 A9 


21 3 Ag 



Fig. 2 80C85 Pinout Diagram 



(a) 80C85 FUNCTIONAL PIN DESCRIPTION - 



The following describes the function of each pin: 



Symbol 

A» — Ais 
(Output, 3-state) 



Function 

Address Bus: The most significant 8 bits of the memory address 
or the 8 bits of the I/O address, 3-stated during Hold and Halt 
modes and during RESET. 



AD0-7 

(Input/Output, 

3-state) 



Multiplexed Address/Data Bus: Lower 8 bits of the memory 
address (or I/O address) appear on the bus during the first clock 
cycle (T state) of a machine cycle. It then becomes the data bus 
during the second and third clock cycles. 



ALE 
(Output) 



Address Latch Enable: It occurs during the first clock state of a 
machine cycle and enables the address to get latched into the 
on-chip latch of peripherals. The falling edge of ALE is set to 
guarantee setup and hold times for the address information. The 
falling edge of ALE can also be used to strobe the status infor- 
mation. ALE is never 3-stated. 



3o 



Symbol 

So , Si , and IO/M 

(Output) 



Function 

Machine cycle status: 

IO/M S, So Status 





1 
1 

1 




1 



1 Memory write 
Memory read 

1 I/O write 

1 I/O read 
1 1 Opcode fetch 
1 1 Interrupt Acknowledge 

* Halt 

* X X Hold 

* X X Reset 
* = 3-state (high impedance) 
X = unspecified 

Si can be used as an advanced R/W status. IO/M, So and. Si 
become valid at the beginning of a machine cycle and remain 
stable throughout the cycle. The falling edge of ALE may be 
used to latch the state of these lines. 



RD 

(Output, 3-state) 



READ control: A low level on RD indicates the selected memory 
or I/O device is to be read and that the Data Bus is available for 
the data transfer, 3-stated during Hold and Halt modes and during 
RESET. 



WR 

(Output, 3-state) 



WRITE control: A low level on WR indicates the data on the 
Data Bus is to be written into the selected memory or I/O loca- 
tion. Data is set up at the trailing edge of WR. 3-stated during 
Hold and Halt modes and during RESET. 



READY 
(Input) 



If READY is high during a read or write cycle, it indicates that 
the memory or peripheral is ready to send or receive data. If 
READY is low, the cpu will wait an integral number of clock 
cycles for READY to go high before completing the read or 
write cycle. 



Symbol 

HOLD 
(Input) 



2/ 



Function 

HOLD indicates that another master is requesting the use of the 
address and data buses. The cpu, upon receiving the hold request, 
will relinquish the use of the bus as soon as the completion of the 
current bus transfer. Internal processing can continue. The 
processor can regain the bus only after the HOLD is removed. 
When the HOLD is acknowledged, the Address, Data, RD, WR, 
and IO/M lines are 3-stated. 



HLDA 
(Output) 



HOLD ACKNOWLEDGE: Indicates that the cpu has received 
the HOLD request and that it will relinquish the bus in the 
next clock cycle. HLDA goes low after the Hold request is re- 
moved. The cpu takes the bus one half clock cycle after HLDA 
goes low. 



INTR 
(Input) 



4 INTERRUPT REQUEST: is used as a general purpose interrupt. 
It is sampled only during the next to the last clock cycle of an 
instruction and during Hold and Halt states. If it is active, the 
Program Counter (PC) will be inhibited from incrementing and 
an INTA will be issued. During this cycle a RESTART or CALL 
instruction can be inserted to jump to the interrupt service 
routine. The INTR is enabled and disabled by software. It is 
disabled by Reset and immediately after an interrupt is accepted. 



INTA 
(Output) 



INTERRUPT ACKNOWLEDGE: is used instead of (and has 
the same timing as) RD during the Instruction cycle after an 
INTR is accepted. 



RST 5.5 
RST 6.5 
RST 7.5 
(Inputs) 



RESTART INTERRUPTS: These three inputs have the same 
timing as INTR except they cause an internal RESTART to 
be automatically inserted. 

The priority of these interrupts is ordered as shown in Table 1 . 
These interrupts have a higher priority than INTR. In addition, 
they may be individually masked out using the SIM instruction. 



3Z 



Symbol 

TRAP 
(Input) 



Function 

Trap interrupt is a nonmaskable RESTART interrupt. It is re- 
cognized at the same time as 1NTR or RST 5.5—7.5. It is 
unaffected by any mask or Interrupt Enable. It has the highest 
priority of any interrupt. (See Table 1.) 



RESET IN 
(Input) 



Sets the Program Counter to zero and resets the Interrupt Enable 
and HLDA flip-flops. The data and address buses and the control 
lines are 3-stated during RESET and because of the asynchronous 
nature of RESET, the processor's internal registers and flags 
may be altered by RESET with unpredictable results. RESET IN 
is a Schmitt-triggered input, allowing connection to an R-C 
network for power-on RESET delay. The cpu is held. in the reset 
condition as long as RESET IN is applied. 



RESET OUT 
(Output) 



Indicates cpu is being reset. Can be used as a system reset. The* 
signal is synchronized to the processor clock and lasts an integral 
number of clock periods. 



Xi , Xj 

(Input) 



Xi and Xj are connected to a crystal, LC, or RC network to 
drive the internal clock generator. Xi can also be an external 
clock input from a logic gate. The input frequency is divided by 
2 to give the processor's internal operating frequency. 



CLK 
(Output) 



Clock Output for use as a system clock. The period of CLK is 
twice the Xi , X 2 input period. 



SID 
(Input) 



Serial input data line. The data on this line is loaded into ac- 
cumulator bit 7 whenever a RIM instruction is executed. 



SOD 
(Output) 



Serial output data line. The output SOD is set or reset as specified 
by the SIM instruction. 



Vcc 



+5 volt supply. 



Vss 



Ground Reference. 



93 



Nam* 



TRAP 



RST 7,5 



RST 8.5 



RST 5.5 



INTR 



Priority 



Addreis Branched To (1) 
Whan Interrupt Occurs 



24H 



3CH 



34H 



2CH 



Typa Trigger 



Rising edge AND high level until sampled. 



Rising edge patched). 
High level until sampled. 



See Note (2). 



High level until sampled. 



High level until sampled. 




Table 1. INTERRUPT PRIORITY, RESTART ADDRESS and SENSITIVITY 



(b) FUNCTIONAL DESCRIPTION 



The 80C85 has twelve addressable 8-bit registers. Four of them can function only as two 
16-bit register pairs. Six others can be used interchangeably as 8-bit registers or as 16-bit 
register pairs. The 80C85 register set is as follows: 



Mnemonic 


Register 


Contents 


ACC or A 


Accumulator 


8 bits 


PC 


Program Counter 


1 6-bit address 


BC, DE, HL 


General-Purpose 


8 bits x 6 or 




Registers: data 


1 6 bits x 3 




pointer (HL) 




SP 


Stack Pointer 


1 6-bit address 


Flags or F 


Flag Register 


5 flags (8-bit space) 



The 80C85 uses a multiplexed Data Bus. The address is split between the higher 8-bit 

Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) 

of a machine cycle the low order address is sent out on the Address/Data bus. These lower 

8 bits may be latched externally by the Address Latch Enable signal (ALE). During the 

rest of the machine cycle the data bus is used for memory or I/O data. 

The 80C85 provides RD, WR, So, Si , and IO/M signals for bus control. An Interrupt 

Acknowledge signal (INTA) is also provided. HOLD, READY, and all Interrupts are 

synchronized with the processor's internal clock. The 80C85 also provides Serial Input 

Data (SID) and Serial Output Data (SOD) lines for simple serial interface. 

In addition to these features, the 80C85 has three maskable, vector interrupt pins and one 

nonmaskable TRAP interrupt. 



w 

(c) INTERRUPT AND SERIAL I/O 

The 80C85 has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP. INTR 
is identical in function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, 
and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is non- 
maskable. 

The three maskable interrupts cause the internal execution of RESTART (saving the pro- 
gram counter in the stack and branching to the RESTART address) if the interrupts are 
enabled and if the interrupt mask is not set. The nonmaskable TRAP causes the internal 
execution of a RESTART vector independent of the state of the interrupt enable or masks. 
(See Table 1.) 

There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5 are 
high level-sensitive like INTR (and INT on the 8080) and are recognized with the same 
timing as INTR. RST 7.5 is rising edge-sensitive. 

For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal 
interrupt request. The RST 7.5 request flip-flop remains set until the request is serviced. 
Then it is resel automatically. This flip-flop may also be reset by using the SIM instruction 
or by issuing a RESET IN to the 80C85. The RST 7.5 internal flip-flop will be set by a 
pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked out. 
The status of the three RST interrupt masks can only be affected by the SIM instruction 
and RESET IN. 

The interrupts are arranged in a fixed priority that determines which interrupt is to be 
recognized if more than one is pending as follows: TRAP - highest priority, RST 7.5, 
RST 6.5, RST 5.5, INTR - lowest priority. This priority scheme does not take into 
account the priority of a routine that was started by a higher priority interrupt. RST 5.5 
can interrupt an RST 7.5 routine if the interrupts are re-enabled before the end of the 
RST 7.5 routine. 

The TRAP interrupt is useful for catastrophic events such as power failure or bus error. The 
TRAP input is recognized just as any other interrupt but has the highest priority. It is not 
affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP 
input must go high and remain high until it is acknowledged. It will not be recongized 
again until it goes low, then high again. This avoids any false triggering due to noise or 
logic glitches. Figure 3 illustrates the TRAP interrupt request circuitry within the 8085. 
Note that the servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables 
all future interrupts (except TRAPs) until an El instruction is executed. • 



36- 



external 

THAI" 

INTERRUrT 

REQUEST 



INSIDE THE 
80C85 



SCMMHT 

rntoG&A 



?> 



lP 



fir 

CLEAR 



interrupt 

REQUEST 



INTERNAL 

TRAR 
ACKNOWLEDGE 



Fig. 3 TRAP and RESET IN CIRCUIT 



The TRAP interrupt is special in that it disables interrupts, but preserves the previous 
interrupt enable status. Performing the first RIM instruction following a TRAP interrupt 
allows you to determine whether interrupts were enabled or disabled prior to the TRAP. 
All subsequent RIM instructions provide current interrupt enable status. Performing a RIM 
instruction following INTR, or RST 5.5-7.5 will provide current Interrupt Enable status, 
revealing that Interrupts are disabled. 

The serial I/O system is also controlled by the RIM and SIM instructions. SID is ready 
by RIM, and SIM sets the SOD data. 



(d) BASIC SYSTEM TIMING 

The 80C85 has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits 
of address on the Data Bus. Fig. 4 shows an instruction fetch, memory read and I/O write 
cycle (as would occur during processing of the OUT instruction). Note that during the I/O 
write and read cycle that the I/O port address is copied on both the upper and lower half 
of the address. 

There are seven possible types of machine cycles. Which of these seven takes place is 
defined by the status of the three status lines (IO/M, Si , So ) and the three control signals 
(RD, WR, and INTA). (See Table 2.) The status lines can be used as advanced controls 
(for device selection, for example), since they become active at the Ti state, at the outset 
of each machine cycle. Control lines RD and WR become active later, at the time when the 
transfer of data is to take place, so are used as command lines. 
A machine cycle normally consists of three T states, with the exception of OPCODE 
FETCH, which normally has either four or six T states (unless WAIT or HOLD states 
are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten 
possible states, shown in Table 3. 






MACHINE CYCLE 


STATUS 


CONTROL 


IO/M 


SI 


so 


TO 


wiS 


INTA 


OPCODE FETCH IOFI 

MEMORY READ {MR! 

MEMORY WRITE IMWI 

I/O READ OORI 

I/O WRITE (IOWI 

ACKNOWLEDGE 

Or INTR IINAI 

BUS IDLE ISII: OAO 

ACK. OF 

RST.TRAF 

HALT 







1 

1 

1 



1 

TS 


1 
I 


1 



1 
1 




1 



1 


1 

1 



1 






I 



1 

t 
1 

1 

TS 


1 
1 


1 
a 

1 
t 

i 

TS 


1 

1 
1 
1 
1 



1 

1 
1 



Table 2 80C85 MACHINE CYCLE CHART 



Maehina 
Suu 


| Suiy.4 8uitl ] Comrol 


1 
S1.S0 


1 i i * l 
IO/M A s -A„(ADn-AO-,lRDWR!l'STAUi e j 


|t, 


X 


X 


X j X 


i ! i 


r ! 


Tj 


X 


X 


X 1 X 


X 


X 





*fw*»T 


X 


X 


X | X 


X 


X 





T 3 


X 


X 


X X 


X 


X 





T < 


t 


0> 


X TS 


I 


! 





T S | 


1 


0' 


X ! TS 


' 


I 





T « I 


1 


<■' j X j TS 


' 1 


1 


. 


T RES6T 1 


X 


TS ! TS | TS 


TS | 


, f'o 


T MALT j 





TS-i TS TS 


TS| 


i ! o 


T HOLD i 


X TS i TS j TS 


TS ! 1 ! o ! 



3£ 



Table 3 80C85 MACHINE STATE CHART 





T . / \ T »/~~\ T »/ \ T </~" 




III/ - \IlT~ \lF~ 




CLK 


iW 






1 


*."*.. 


Y K„ IHIOX ORDER AOORESI 


X «•". 


X •°'°" X 




yv \./y~~\ 


DATA FROM MEMORY 
ll/OK»r ADORES) 

n 








-(""■""X , 


X 




ILOWOROER DATA FROM 

aooress MEMORY 
r— \ (iittTRucnoi* 


ALI 


OATA TO MEMORY 
. OR MRlfHERAL 

rv 


n 












SB 


\ / 


\ / 






s* 






\ / 




m/S 


"A 


j 


"A 












«TATm 


Y S,S. IFETCHI 


Y U (REAOI 


V 01 WRlTf 


x « 



Fig. 4 80C85 Basic System Timing 



Ambient Temperature Under Bias, 

Storage Temperature , 

Voltage on Any Pin 

With Respect to Ground 

Power Dissipation 



.-40°C to +85°C 
,-55°C to +150°C 

,-0.5°C to +7 V 
1.0 Watt 



Table 4 Absolute Maximum Ratings 



Symbol 


Parameter 


Min. 


Max. 


Units 


Test Conditions 


V,L 


Input Low Voltage 


-0.3 


+0.8 


V 




V|H 


Input High Voltage 


2.2 


Vcc+0.3 


V 




V 0L 


Output Low Voltage 




0.45 


V 


l 0L - 2mA 


Vqh 


Output High Voltage 


Z4 




V 


l 0H » -400jiA 


•cc 


Power Supply Current 




17 


mA 


Vcc=4.75-5.25 V 


>IL 


Input Leakage 




±10 


MA 


Vin - Vc; 


'lo 


Output Leakage 




±10 


ka 


0.45V < Vou, < V cc 


V IL R 


Input Low Level, RESET 


-0.3 


+0.8 


V 




V|HB 


Input High Level, RESET 


2.2 


v cc + 0.3j v 





^7 



Table 5 D.C. CHARACTERISTICS 



w 


- 


(1/2IT-45 




MIN 


; 'la 


- 


(1/2) T- 60 




MIN 


't-L 


- 


(1/2) T- 20 




MIN 


't-CK 


- 


(1/2) T- 60 




MIN 


: t LC 


- 


(1/2) T-30 




MIN 


: l AD 


- 


(5/2 + N) T - 


225 


MAX 


j f RD 


- 


(3/2 + N)T- 


180 


MAX 


*RA6 


- 


(1/2) T- 10 




MIN 


'CA 


- 


(1/2) T- 40 




MIN 


| «ow 


- 


(3/2 + N) T - 


60 


MIN 


<wo 


- 


(1/2) T- 60 




MIN 


l cc 


- 


(3/2 + N) T - 


80 


MIN 


«CL • 


- 


(1/2) T- 110 




MIN 


*ARY 


- 


(3/2) T - 260 




MAX 




- 


(1/2) T- 50 




MIN 


l HABF 


- 


(1/21T + 50 




MAX 


'HABE 


- 


(1/2)T + 50 




MAX 


'AC 


- 


(2/2) T- 50 




MIN 


'1 


- 


(1/2) T- 80 




MIN 


l 2 


- 


(1/2) T- 40 




MIN 


<RV 


- 


(3/2) T - 80 




MIN 


'lor 


- 


(4/2) T- 180 




MAX 



Table 6 Bus Timing Specification 



TABLE 7 A.C. CHARACTERISTICS 
T A - 40° C to +85° C; V cc - 5V ±10%; V ss - 0V 



~& 



Symbol 



tCYC 



t> 

tr. «f 

<XKR 

«XKF 

«AC 

<ACL 

»AO 

<AFR 

*AL 

«ALL 

<ARY 

«CA 

tec 

«CL 

tQW 

*HABE 

<HABF 

'HACK 

*HDH 

'HDS 

«INH 

<INS 

«LA 

<LC 

'LCK 

«LDR 

'LOW 

«LL 

<LRY 

tRAE 

tRD 

«RV 

«RDH 

«RYH 

«RYS 

«WD 

l WDL 



Parameter 

CLK Cycle Pe'iod 

CLK Low Tims — Standard 150 pF Loading 

CLK High Time - Standard 150 pF Loading 
CLK Rise and Fall Time 
X, Rising to CLK Rising 
X, Rising to CLK Falling 

Ai_u Valid to Leading Edge of Control"' 

Ao_» Valid to Leading of Control 

A,,_u Valid to Valid Data In 

Address Float after Leading Edge of READ (INTA) 

A,_i, Valid before Trailing Edge of ALE* 1 ' 

A,_, Valid before Trailing Edge of ALE 

READY Valid from Address Valid 

Address (A,— A,j) Valid after Control 

Width of Control Low (RD, WR, INTA) Edge of ALE 

Trailing Edge of Control to Londing Edge of ALE 

Dota Valid to Trolling Edge of WRITE 

HLOA to Bus Enable 

Bus Float after HLOA 

HLDA Valid to Trailing Edge of CLK 

HOLD Hold Time 

HOLD Setup Time to Trailing Edge of CLK 

INTR Hold Time 

INTR, RST, and TRAP Setup Time to Falling Edge of CLK 

Address Hold Time after ALE 

Trailing Edge of ALE to Leading Edge of Control 

ALE Low during CLK High 

ALE to Valid Data during Read 

ALE to Valid Data during Write 

ALE Width 

ALE to READY Stable 

Trailing Edge of READ to Re-Enabling of Address 

READ (or INTA) to Valid Data 

Control Trailing Edge to Leading Edge of Next Control 

Data Hold Time After READ INTA (7) 

READY Hold Time 

READY Setup Time to Leading Edge of CLK 

Data Valid After Trailing Edge of WRITE 

LEADING Edge of WRITE to Data Valid 



Min. 


Max. 


Unit 


320 


2000 


ns 


80 




ns 
ns 


120 




ns 




30 


ns 


30 


120 


ns 


30 


150 


ns 


270 




ns 


240 




ns 




575 


ns 







ns 


115 




ns 


90 




ns 




220 


ns 


120 




ns 


400 




ns 


50 




ns 


420 




ns 




210 


ns 




210 


ns 


110 




ns 







ns 


170 




ns 







ns 


160 




ns 


100 




ns 


130 




ns 


100 




ns 




460 


ns 




200 


ns 


140 




ns 




110 


ns 


150 




ns 


400 


300 


ns 

ns 







ns 







ns 


110 




ns 


100 




ns 




40 


ns 



Notes: 

1. A,— An address Specs apply to IO/M, So, and S, except A,-A,j are undefined during T 4 — T« of OF cycle whereas IO/M, 
So. and Si are stable. 

2. Test conditions: tcYC " 320ns C|_ » 1 50 pF 

3. All timings are measured at output voltage V t » 0.8V, Vh » 2.2V and 1.5V with 20ns rise and tail time on inputs. 



(e) WAVEFORM 



Y 



O.K 
OUTPUT 



I \ I \ / \—J V_7 



% 



Fig .. 5' Clock Timing Waveform 



39 



Read Operation 



<A J 



■a: 



x 



>j 



X 



r~'»i.— 



i 



i u_j — V 



AOOBKS > <Z/// /////y*. fATAIW |> 



-<10»- 



I— •« — . fr 



■"CA- 



fc 



^ 



_,. 



Write Operation 



-a / \ / — u_y — v 

[•— 'iCK — » 



AO -*O, 



11 



•P 



H 



H.OW- 



\ -j- 



BB 



-•u»- 



r^>: 



-<e»- 



-•wot 



->«>—■ ) 



f 



rzn 



Read operation with Walt Cyclt (Typical) - tame READY timing appllea to WRITE operation. 

"I T ' I T » • 1 T«*IT | T| 

-A I L_ 



•r+TY 



«%*Ot Y 



■) 



X 



\ I v__y \ 



X 



'urn 




z. 



\ 



-l»- 
-It- 



"WHEEL 






->«o- 
-■ce- 



$ 



J 



F.ig. 6 80C85 Rue T-i 



Hold Operation 

°4 r 



i — }_y — \ i — \ r 



i 



(AODfUtt, CONTROLS) 



I*- 'hack-* 

"H t HABf~ •• 



>-»>- 



Fig. 7 Hold Timing 



v 

h—<M, 



3t 



£s> 




IO/S IS ALSO FLOATING DURING THIS TIME. 



Fig. 8 80C85 Interrupt and Hold Timing 



w 



(2) MSM81C55RS (PIO) 

C-MOS, 2048-bit STATIC RAM with i/o PORTS and TIMER 
The i/o portion consists of three general purpose i/o 
ports. One of the three ports can be programmed to be 
status pins, thus allowing the other two ports to 
operate in handshake mode. 

A 14-bit programmable counter/timer is also included on 
the chip to provide either a square wave or terminal 
count pulse for the CPU system, depending on the timer 
mode. 

The 81C55 RAM is not used in Model 100. A timer/counter 
is used as the clock generator necessary for 
communication and to generate the melody. 



K, C 


1 




AO 


3 v ec 


K, C 


2 




39 


1 K, 


TIME K IN C 


] 




M 


J *, 


RESET C 


4 




31 


3 "^ 


«H C 


s 




* 


3«7 


TIMER OUt C 


• 




3S 


J ™. 


IO/M C 






34 


3«, 


CEORCE-C 






U 


3«. 


16 C 


• 




11 


3", 


wr C 


10 


lO 


31 


D "i 


ALE C 


" 


ir\. 


X 


]", 


no, C 


11 


U 


n 


3 >*, 


AO, C 


11 


CO 


n 


J'», 


AO, C 


'« 




" 


D'S 


AO, C 


11 




M 


3'*, 


AO, C 


'• 




18 


D'S 


AO, C 


" 




14 


3 '*> 


AO, C 


« 




13 


3 '*» 


AO, C 


11 




11 


3«i 


*» C 


20 




11 


D", 






CE 



1S»X1 

STATIC 

RAM 



TIMER CLK 
TIMS* BUT 



IT 



„M«T1 K 



1 - 




v cc I.»VI 
V„ I0VI 



Fig 9 Pin Configuration and Block Diagram 



¥2. 



(a) 81C55 PIN FUNCTIONS 



Symbol 

RESET 
(Input) 



Function 

Pulse provided by the 80C85 to initialize the system (connect to 
80C85 RESET OUT). Input high on this line resets the chip and 
initializes the three I/O ports to input mode. The width of 
RESET pulse should typically be two 80C85 clock cycle times. 



ADo_7 
(Input) 



3-state Address/Data lines that interface with the CPU lower 
8-bit Address/Data Bus. The 8-bit address is latched into the 
address latch inside the 81C55 on the falling edge of ALE. The 
address can be either- for the memory section or the I/O section 
depending on the IO/M input. The 8-bit data is either written into 
the chip or read from the chip, depending on the WR or RD input 
signal. 



CE 
(Input) 



Chip Enable: 

CE is ACTIVE LOW. 



RD 
(Input) 



Read control: Input low on this line with the Chip Enable active 
enables and ADo -7 buffers. If O/M pin is low, the RAM content 
will be read out to the AD bus. Otherwise the content of the 
selected I/O port or command/status registers will be read to the 
AD bus. 



WR 
(Input) 



Write control: Input low on this line with the Chip Enable active 
causes the data on the Address/Data bus to be written to the 
RAM or I/O ports and command/status register depending on 
IO/M. 



ALE 



Address Latch Enable: This control signal latches both the 
address on the AD _7 lines and the state of the Chip Enable and 
IO/M into the chip at the falling edge of ALE. 



IO/M 
(Input) 



Selects memory if low and I/O and command/status registers 
if high. 



&3 



PAo_ 7 ( 8 > 
(Input/Output) 

PB.-,(8) 

(Input/Output) 

PCo_ s (6) 
(Input/Output) 



These 8 pins are general purpose I/O pins. The in/out direction 
is selected by programming the command register. 

These 8 pins are general purpose I/O pins. The in/out direction 
is selected by programming the command register. 

These 6 pins can function as either input port, output port, or 

as control signals for PA and PB. Programming is done through 

the command register. When PC _ s are used as control signals, 

they will provide the following: 

PC - A INTR (Port A Interrupt) 

PC, - ABF (Port A Buffer Full) 

Pd - A STB (Port A Strobe) 

PC 3 - B INTR (Port B Interrupt) 

PC 4 - B BF (Port B Buffer Full) 

PCs - B STB (Port B Strobe) 



TIMER IN 
(Input) 



Input to the counter-timer. 



TIMER OUT 
(Output) 



Timer output. This output can be either a square wave or a pulse 
depending on the timer mode. 



Vcc 



+5 volt supply. 



Vss 



Ground Reference. 



¥£ 



SYMBOL 


PARAMETER 


MIN. 


MAX 


UNITS 


TEST CONDITIONS 


VlL 


Input Low Voltage 


-0.3V 


0.8 


V 




V,H 


Input High Voltage 


9 9 


v cc+n T 


V 




vbL 


Output Low Voltaga 




0.45 


'V 


bu " 2mA 


M3H 


Output High Voltaga 


2.4 




V 


Ioh - -400mA 


'IL 


Input Leakage 




±10 


ma 


Vim .- V cc to 0V 


"to 


Output Leakage Current 




±10 


HA . 


0.45V < V UT < V C C 


tec 


Vcc Supply Current 




5 


mA 





Table .8 D.C. characteristics 





nsec 


SYMBOL 


PARAMETER 


MIN. 


MAX. 


«AL 


Address to Latch Set Up Time 


50 




«LA 


Address Hold Time after Latch 


80 




«LC 


Latch to READ/WRITE Control 


100 




'HO 


Valid Data Out Delay tram READ Control 




170 


<AO 


Address Stable to Data Out Valid 




400 


«LL 


Latch Enable Width 


100 




*ROF 


Data Bus Float After READ 





100 


tCL 


READ/WRITE Control to Latch Enable 


20 




tec 


HEAD/WRITE Control Width 


250 




'DW 


Data In to WRITE Set Up Time 


150 




two 


Data In Hold Time After WRITE 







tRV 


Recovery Time Between Controls 


300 




twe 


WRITE to Port Output 




400 


'PR 


Port Input Setup Time 


70 




*RP 


Port Input Hold Time 


50 




«SBF 


Strobe to Buffer Full 




400 


>SS 


Strobe Width 


200 




*RB6 


READ to Buffer Empty 




400 


«S1 


Strobe to INTR On 




400 


l ROI 


READ to INTR Off 




400 


tPSS 


Port Setup Time to Strobe Strobe 


50 




'PMS 


Port Hold Time After Strobe 


120 




l SBE 


Strobe to Buffer Empty 




400 


*WBF 


WRITE to Buffer Full 




400 


*wi 


WRITE to INTR Off 




400 


<TL 


TIMER-IN to TIMER-OUT Low 




400 


«TH 


TIMER-IN to TIMER-OUT High 




400 


l HOE 


Data Bus Enable from READ Control 


* 10 




tl 


TIMER-IN Low Time 


■ ' 80 




'2 


TIMER-IN High Time 


120 





Table 9 A.C. characteristics 



«. (UadCycl* 



CT 



\ 



X 






Z 



/ "V 



re 



X 



> 



ex 



fcrzXZ 



A f 

Jf v 

r 



b. WrftaCyel* 



CtMISN 



PO/fl 



wft 



\ 



z 



X 



\ 



3: 



z 



/ — \ 



■<IA 



X 



j\ /j f 



DATA VALID 



T 



/ 



/ 



% *v ■ * > \ 



*£" 



Fig. 10 81C55 Read/Write Timing Diagram 



u 



a. Strobed Input Mod* 



rrxou 



re 



INTUT DATA 
FROM nMT 



A 



Hu- 



VL/^N 



i: 



y 



x 



\ 



\ 



\^_f 



z 



b. Strobad Output Mod* 

IF 



ETRfiU 



OR 



OUTPUT DATA 
TOKWT 



/ 



\ 



\jL^' 



\ 



\^J 



z 



X 




Fig. 11 Strobed I/O Timing 



i. Basic Input Modt 



a 



\ n 



X 



_y\_ 



b. B»»ic Output Mod* 



m 



"\ -/ 



■OATA BUS TIMING IS SHOWN IN FIQUMI 7. 



Fig. 12 Basic I/O Timing 



-- — - X i f" 



X 



LOAD COUNT! » FROM «.» 

I 1 I 




TwrrBOT 

ISOUAftf WAV! I 



NOTE 1 THt TIMf « OUTFUT IS 1 1 MOOIC IF IN AN AUTOMATIC 
ftCLOAO OOOJ IM, MOO* SIT - II 



V7 



Fig 13 Timer output Waveform Countdown from 5 to 1 



96 



(3) HD6402(UART) 

C-MOS UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER 

(a) Description 

The HD-6402 is a CMOS/LSI subsystem for interfacing computers or microprocessors 
to an asynchronous serial data channel. The receiver converts serial start, data, parity and 
stop bits to parallel data verifying proper code transmission, parity, and stop bits. The 
transmitter converts parallel data into serial form and automatically adds start, parity, 
and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. 
Parity checking and generation can be inhibited. The stop bits many be one or two or one 
and one-half when transmitting 5 bit code. 

The HD-6402 can be used in a wide range of applications including modems, printers, 
peripherals and remote data aquisition systems. CMOS/LSI technology permits operation 
clock frequencies up to 2.0 MHz (125K Baud)' an improvement of 10 to 1 over previous 
PMOS UART designs. Power requirements, by comparison, are reduced from 300 mW to 
10 raW. Status logic increases flexibility and simplifies the user interface. 



CONTROL WORD 



CHARACTER FORMAT 





TOP VIEW 




v C c C 


!• 


40 


3 TRC 


NC C 


J 


39 


3 EPE 


GNO C 


3 


M 


3 CLS1 


RRO C 


4 


37 


3 CLS2 


RSRt C 


S 


3f 


3 sas 


R8R7 C 


1 


3S 


3 PI 


RIM C 


7 


34 


3 CRl 


RBR5 C 


• 


33 


3 TBRI 


RBR4 C 


S 


32 


3 TBR7 


R8R3 C 


10 


31 


3 TBRI 


nam c 


11 


30 


3 TBRS 


RBR1 C 


12 


2» 


3 TBR4 


PE C 


1} 


21 


3 TBR3 


rt c 


u 


27 


3 TBR2 


OE C 


13 


2S 


3 TBRI 


SPO c 


1! 


2S 


3 TRO 


RRCC 


17 


24 


3 TRE 


DRR C 


11 


23 


3 TBRL 


OR C 


11 


22 


3 T8RE 


RRI C 


20 


21 


3 MR 



Fig. 14 Pin Layout 



c c 

L L P E S 

S S I f> B START DATA PARITY STOP 

2 1 E. S BIT BITS SIT BITS 



a 













1 

I 
1 
1 

! 

1 
1 

1 1 

! 1 

1 1 
1 1 
I 1 



OOD 
ODD 
EVEN 
EVEN 
NONE 
NONE 
•OOO 
ODD 
EVEN 
EVEN 
NONE 
NONE 
OOD 
ODD 
EVEN 
EVEN 
NONE 
NONE 
ODD 
ODD 
EVEN 
EVEN 
NONE 
NONE 



Table 10 Control Word Format 




a -v y — £» — "i^^w^K^V 

J __j -J __- 1 _ h __ tTTt . i>i , 

Fig. 15 Function Diagram 



Supply Voltage 

Input or Output Voltage Applied 

Storage Temperature Range 

Operating Temperature Range (Industrial ■ 



+8.0V 

GNO -0.3V to \'cc*0.3V 

-65°Ciot150°C 

-40°C to +85°C 



Table 11 Absolute Maximum Rating 



«9 



| SYMBOL 


PARAMETER 


MINIMUM 


TYPICAL 


MAXIMUM 


UNITS 


CONDITIONS 


VIM 


Logical "1" inoul Voltage 


70% V CC 






V 




VlL 


Logical "0" Inout Voltage 






20% v cc 


V 




'11 


Input Leakage 


-10.0 




+ 10.0 


M* 


0V < VlN < VCC 


VOH 


Logical "1" Ouidui Voltage 


2.4 






V 


IOH - -0.2mA 


VOL 


Logical "0" Ouipul Voltage 






0.45 


V 


IOL * 2.0mA 


10 


Output Leakage 


-10.0 




♦10.0 


fJA 


OV < VO < vcc 


ICC 


Supply Current 




1.0 


800 


MA 


V|N - GNO or VCC 
VCC - 5.25V 


ClN 


Input Capacitance* 




7.0 


8.0 


PF 


Output Ooen 


CO 


Output Capacitance* 




8.0 


10.0 


of 





Table 12 Electrical Characteristics (D.C.) 







VCC - s.ov © 
Ta - 2S°C 


VCC - 5.0V+ SX 

Ta • Industrie! 




SYMBOL 


PARAMETER . 


MIN 


TYP 


MAX 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 


'dock 


Clock Freouency 


D.C. 




2.0 


D.C. 




1.0 


MHz 




tow 


Pulie Widthj CRL, DRR. TBRL 


200 






225 






nj 


C(_ » 50bF 


'MR 


Pulie Width MR 


500 






600 






m 


See Switching Time 


'SET 


Input Date Setup Time 


60 






75 






ni 


Waveform! 1.2.3 


'HOLD 


Input Data Hold Time 


75 






90 






ns 




•EN 


Output Enable Time 






150 






190 


m 





Table 13. Electrical Characetristics 



(b) Receiver Operation 

Data is received in seriai form at the RInput. When no data is being received, RInput must 
remain high. The data is clock through the RRClock. The clock rate is 1 6 times the data 
rate. (A) A low level on DRReset clears the DReady line. (B) During the first stop bit 
data is transferred from the receiver register to the RBRegister. If the word is less than 
8 bits, the unused most significant bits will be a logic low. The output character is right 
justified to the least significant bit RBR1. A logic high on OError indicates overruns. 
An overrun occurs when DReady has not been cleared before the present character was 
transferred to the RBRegister. (C) 1 clock cycle later DReady is reset to a logic high, and 
FError is evaluated. A logic high on FError indicates an invalid stop bit was received, 
a framing error. A logic high on PError indicates a parity error. 



-BfCINNtNG OF JIMTSTO* tit 



*■' i ' m 



■ *Mi.f. at, ri ■ y 



. —.)» CLOCK CYCLES 



°"" ' lU — — — — _ RECEIVER TIMING 



■u 



0. u ! r 



(NOT TO SCALE) 



! —4 — i clock cvcli 



Fig. 16 



$-/ 



(c) START Bit Detection 

The receiver uses a 1 6X clock for timing. (A) The start bit could have occurred as much 
as one clock cycle before it was detected, as indicated by the shaded portion. The center 
of the start bit is defined as clock count 7-1/2. If the receiver clock is a symetrical square 
wave, the center of the start bit will be located within ±1/2 clock cycle, ±1/32 bit or 3.125% 
giving a receiver margin of 46.875%. The receiver begins searching for the next start bit 
at the center of the first stop bit. 



_rLn_n^Tj*i_nji_njxn^ r 



Fig.' 17 



_©i_ 



ct»n« r» it. 



— I ,11 Of* f »H 



(d) IM6402 Pin Functions 

Symbol Description 

Vcc Positive Voltage Supply 



NC 

GND 
RRD 

RBR8 



No Connection 



Ground 



A high lever en RECEIVER REGISTER DISABLE forces the 
receiver holding outputs RBR.1— RBR8 to a high impedance state. 

The contents of the RECEIVER BUFFER REGISTER appear 
on these three-state outputs. Word formats less than 8 characters 
are right justified to RBRi. 



$2 



Symbol 

RBR7 

RBR6 

RBR5 

RBR4 

RBR3 

RBR2 

RBR1 

PE 



FE 



OE 



SFD 



RRC 



DRR 



DR 



RRI 



MR 



Description 

See Pin 5 - RBR8 

See Pin 5 - RBR8 

See Pin 5 - RBR8 

See Pin 5 - RBR8 

See Pin 5 - RBR8 

See Pin 5 - RBR8 

See Pin 5 - RBR8 

A high levei on PARITY ERROR indicates received parity does 
not match parity programmed by control bits. When parity is 
inhibited this output is low. 

A high level on FRAMING ERROR indicates the first stop bit was 
invalid. 

A high level on OVERRUN ERROR indicates the data received 
flag was not cleared before the last character was transferred to 
the received buffer register. 

A high level on STATUS FLAGS DISABLE lorces the outputs 
PE, FE, OE, DR, TBRE to a high impedance state. 

The RECEIVER REGISTER CLOCK is 1 6X the receiver data 
rate. 

A low level on DATA RECEIVED RESET clears the data received 
output DR to a low level. 

A high level on DATA RECEIVED indicates a character has been 
received and transferred to the receiver buffer register. 

Serial data on RECEIVER REGISTER INPUT is clocked into the 
receiver register. 

A high level on MASTER RESET clears PE, FE, GE, and DR 
to a low level and sets the transmitter output to a high level 
after 18 clock cycles. MR does not clear the receiver buffer 
register. This input must be pulsed at least once after power up. 



S3 



Symbol 
TBRE 

TBRL 



TRE 



TRO 



TBR1 



TBR2 
TBR3 
TBR4 
TBR5 
TBR6 
TBR7 
TBR8 
CRL 

PI 

SBS 



Description 

A high level on TRANSMITTER BUFFER REGISTER EMPTY 
indicates the transmitter buffer register has transferred its data 
to the transmitter register and is ready for new data. 

A low level on TRANSMITTER BUFFER REGISTER LOAD 
transfers data from inputs TBR1-TBR8 into the transmitter 
buffer register. A low to high transition on TBRL indicates data 
transfer to the transmitter register is busy, transfer is auto- 
matically delayed so that the two characters are transmitted 
end to end. 

A high level on TRANSMITTER REGISTER EMPTY indicates 
completed transmission of a character including stop bits. 

Character data, start data and stop bits appear serially at the 
TRANSMITTER REGISTER OUTPUT. 

Character data is loaded into the TRANSMITTER BUFFER 
REGISTER via inputs TBR1-TBR8.. For character formats 
less than 8 bits the TBR8, 7 and 6 inputs are ignored correspond- 
ing to the programmed word length. 

See Pin 26 - TBR1 

See Pin 26 - TBR1 

SeePin26-TBRl 

See Pin 26 - TBR1 

See Pin 26 - TBR1 

See Pin 26 -TBR1 

See Pin 26 - TBR1 

A high level on CONTROL REGISTER LOAD loads the control 
register. 

A high level on PARITY INHIBIT inhibits parity generation. 
Parity checking and forces PE output low. 

A high level on STOP BIT SELECT selects 1.5 stop bits for 5 
character format and 2 stop bits for other lengths. 



Symbol 
CLS2 



CLS1 
EPE 

TRC 



i* 



Description 



These inputs program the CHARACTER LENGTH SELECTED 
(CLS1 low CLS2 low 5 bits) (CLS1 high CLS2 low 6 bits) (CLS1 
low CLS2 high 7 bits) (CLS1 high CLS2 high 8 bits). 

See Pin 37 - CLS2. 

When PI is low, a high level on EVEN PARITY ENABLE 
generates and checks even parity A low level selects odd parity. 

The TRANSMITTER REGISTER CLOCK is 1 6X the transmit 

data rate. 



•J.LOC.K filflGRAM , 




■::a> 



Fig. 18 



RMdCr<*UI 



A^iesx 



a, 



"out 



ixs: 



££ 



-->^« 



& 






"MM//////////,. 



'A 



OUTUT 0»T* v*WO 



Fig. lP\ Timing Waveform 



£-r 



mitt Crcli 1. 



y "- 






=1, 



ET, 



x\\\\\\\\\HM^W 



^^ 



""■/ 



JL 



,./ 



Hit** iwiwawi 



X 



»o» "' 



'OK "1 



OAT* IN ITA1LI 



V|N 



X 



Wriu Cyeta 2. 



mffr, (Eiii 



i7i or, i£i,i 



X 



xwwwwww mi., 



It -,?S r V|L 



«IL 



•wflJI 



_V|L 



OOUT 



m/T/mm, 







: UNKNOWN 



Noie: (1! R/W is high for a Read Cycle. 

(2) twP is specified as the logical "ANO'jjr C£_l_. CE2 and R/W. 

twp is measured (rom lhe latter of CH t. CE2 or R/W going low to the earlier of CE 1 . CE2 or 

R/W going high. 

!3) 'OH. IDS are measured (rum trie earlier ol CS 1.CE2 or R/W going high. 

(4) If lha CE~i, or CE2 low transition occurs simultaneously with or latter from the R/W low tran- 
sition in a Write Cycle 1 . the output bulfers remain in a high impedance state in this period. 

(5) If the CE~i or CE2 high transition occurs prior to or simultaneously with the R/W high transition 
in a Write Cycle 1. the output buffers remain in a high impedance state in this period. 

(6! If the R/W is low or the R/W low transition occurs prior to or simultaneously with the CE i or 
CE2 low transition, the output Ouflers remain in a highjmpedance state in this period. 

(7) A write occurs during the overlap ot a low CE I . low CE 2 and low fl/W. 
In write cycle 2. write is controlled oy either CEl or CE2. 



Fig. 20 



A, — A,. 


Aadrcss inputs 


R/W 


Read/Write Conirol Input 


«,.£¥, 


Olio Enable Inputs 


I/O, -I/O, 


Data Inpui/Ouipul 


v 00 


Power («5VI 


GND 


Ground 



^. 



Table 14 Pin Names 



MOOE 


CE", 


cT, 


R/W 


A, — A, , 


I/O, - , | POWER 


Read 


I 


L 


M 


Steele 


O.I» Out Irjoo 


Write 


L 


L 


I 


Stable 


Data In ! I nr)n 


•• Standby 1 


* 


H 


• 


• 


High Impedance Inn*. 


"Standby 2 


H 


* 


• 


* 


High Impedance [ lfj DS 



Table 15 Operation Mode 



Note: VHorL 



: Dua Retention Mod* 



SYMBOL 


ITEM 


RATING 


Vno 


Power Supply Voltage 


, -iJ.3V_?.QV 


VlN 


Input Voltage 


-0.3V~V DO +0,:)V 




V,/o 


Input/Output Voltage 


-0.3V~V Dr ,-K>iv 


Pn 


Power Dissipation (Ta • BS'CI 


O.BWI0.45WI- 


T<rrn 


Storage Temperature 


-55"C - 150"C 




TfiPB 


Operating Temperature 


-30"C - 85" C 


Twioeh 


Soldering Temperature • Time 


260'C ■ 10 sec 





Table 16 Absolute Maximum Rating 



SYMBOL 



vaa_ 



Vw 



PARAMETER 



Power Supply Voltage 



Inp ut High Voltage 
input Low Voltage 



iaa_ 



Data Retention Voltage 



4,5 



2.2 



-0.3 



Plastic FP • 0.45W 



5.0 



5.5 



UNIT 
V 



Vpn«0.3 I v_ 



5.5 



Table 17 Recommended D.C. operating Conditions 



SYMBOL 


PARAMETER 


CONDITIONS 


MIN. 


TYP. MlN 1 UNIT 


'|L 


Input Leakage Currtytt 


osv IN sv OD 


_ 


- I tl.O 


|lA 


'lO 


I/O Leakage Current 


CU.-Vm.ov^Vkj^Voo 

Voh - 2.4V 




- 




15.0 


MA 


l(3H 


Output High Current 




-1.0 


-2.0 


_ 


mA 


tot. 


Output Low Current 


V OL -0.4V 


~1T~ 


3.0 


mA 


Jdbsj 

! OOS3 


Standby Current 


CE, -2.2V or CE, "2.2V 


- 


1.0 


3.0 


mA 


CE", - Vdo -0 5V or 
CE"t -V 00 -0.5V 

V 0o ■ 2 ~ 5.5V 


TC5518BPL 
/80L/BFL 


ITa-25"C 
Ta-60'C 


- 


- 


0.2 


mA 


— 


- 


1.0 


M 


TC5518BP/ 
BD/SF 


Ta-25°C 


_ 


0.05' 


1.0 


Ta-SO'C 


- 


- 


5.0 


Ta-85*C 


„ 


„ 


30 


'ooot 

'oooj 


Operating Current 


tcydi ■ 200m. C"E"t - 
CE", - OV. tour - OmA 


Vin - V, H /V„. 




- 


30 




Vin - Vnn/GND 




„ 


_25 _J 

10 




toooa 


tcvd,- lui.CE, - 
CE", • OV. Iout - OmA 


v, N - v,„/v, L 


- 


_ 


mA 


■'0DO4 


VlN - Voo/'GNO 


- 


5 





Table" 18 D.C. Characteristics 



1 SYMBOL 


PARAMETER I MIN. 


TYP. 


MAX i UNIT 


1 Qn 


Input Capacitance ! — 


5 


10 


pF 


| C|/o 1 Inpui/Ogtpul Capacitance | 


5 


10 


SP 1 



£7 



Table 19 Capacitance 



And Crete 



SYMBOL 


PARAMETER 


MIN 


TYP. 


| MAX. 


UNIT 


tnr 


Reed Cycle Tim* 


200 


1 


1 


ns 


. t*rc 


AceeeiTime 


- 


- 


I 200 


ni 




CE ! to OutduI Valid 


- 


- 


; 200 


ns 




CE , to Output Vain) 


- 


- 


I 200 


ns 




CE i or t£ , to Output Active 


10 


- 


! - 


ns 


too 


Output Mioh-i trom Deselection 


- 


- 


1 60 


ns 


tflM 


Output Motel trom Address Change 


20 


- 


1 


ns 



Write Crete 



SYMBOL 


PARAMETER 


1 MIN. 


TYP. 


MAX. 


UNIT 


twe 


Write CrcJe Time 


1 200 


- 




ns 


twr 


Write Puis* Width 


! 150 


- 




ns 


*AW 


Address Set up Time 


i 


- 


- 


ns 


lyVB 


Write Recover Time 


i 


- 


_ 


ns 


>OOW 


Outoui High-Z Irom R/W 


. 


- 


60 


ns 


<OEW 


Output Active irom R/W 


; io 


- 


- 


ns 


IDS 


Oata Set uo Time 


1 90 


- 


- 


ns 


tnw 


Oau Hold Time 


1 


- , 


" 1 


ns 



Table 20 A.C. Characteristics 



SYMBOL 


PARAMETER 


MIN. 

2.0 " ' 


TYP 


MAX. 


UNIT 


Von 


Data Retnmion Piiwiir Siii'i»*v vniimni 




5 


V 


iTcssiem/ 


T« - JE-'C 






U2 


few 


stanby current ibdl/Wl 


Ti-60*;. 


- 


10 


\TcssmPi 

BD/BP 


1«-2S*C 


HI 


t« - eo'i: 


! 


lj u 


t.-es"c 


. ■ . i 

..2 J. .-. 


m. 


From Chip UewiliH.tiuit tu Uuiu ltniu«ittitii Mode 


us 


tft 


Recover Time 


I«C<>! 


. r. 


- 


HI 



Nom(I) <RC - fl«ml Cvet« Tiiim 



Table 21 Data retension Characteristics 



OATA WETSNTION MODI 




N«m 131 « ih* V 1M l«v*l of CEj (CE ,) k 2.2V, Our ln» tn» 0«M>d ifwt tl»» Vqq vt»tt*tj* i* totng C 
curtani fle*r«- 



i from 4.6V to 2.7V, !qq S1 



Fig. 21 



MEMORY 

The memory of Model 100 consists of a 32-KB ROM and a 32-KB 

RAM (standard 8 KB with 8 KB increments each) , and a 32-KB 

BANK ROM (optional) 

(1) RAM (Random Access Memory) 

Model 100 has a RAM Pack consisting of four 2 KB RAMs 

(each 2048 X 8 bit ) mounted on the ceramicmother board 

for a total of 8 KB (8192 X 8 bit) . 

the standard equipment RAM pack is the M9 ,with the M8 , 

M7 and M6 providing increased capacity. 

The internal wiring diagram of the RAM pack is shown in 

Fig. 22 . 

The specifications for the 2 KB S-RAM used are given 

below. 



% 



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t~ 2 ... -a.Q.o.o.a 2 



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6o 



(2) ROM (Read Only Memory) 

The ROM used in Model 100 is a synchronous 3 2-KB (256 K 
bit) memoly. Operated by a single 5V power supply, the 
access time is 600nsec (max) . 
The ALE (Address Latch Enable) is used as the 
synchronous signal with CPU. 

The BASIC program is included in the standard ROM. 
Also, the BIOS program is included in the standard ROM 
for operation of the LCD, printer, etc. 
An optional ROM can be connected to the special IC 
socket by removing the ROM cover on the case under the 
Model 100. 

Various type of application program can be entered in 
the optional ROM. 

ADDRESS DECOING AND BANK SELECTION 

(1) Address decoding for RAM. chip selection 

Although four 8-KB RAM packs are attached to Model 100, 

16 chip select signals are necessary' because 16X2 KB 

RAMs are actually used . 

Moreover , because the RAM area is positioned from 8000H 

to FFFFH (see memory map) ,- the control signal is formed 

by IC/M ,A15and A14 , as shown in Fig. 23, and the 16 

chip- select signals are formed by A13 ,A12 and All. 

M5 (TC40Hl39:dual 2 to 4 line decorder /demultiplexer) 

is used to make the control signal, and M3 and M4 

(TC4 0H133: 3 to S line decorder /demultiplexer) are used 

to r-:ks the 16 chip select signals. 



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(8000 



for, RAM chip 
H^87FF H ) 



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C6 'A 



Address decording for RAM chip 16 
(F800 H-\.FFFF H ) 



Active line with high-level 
Active line with low-level 



Fig .23 



(2) ROM chip selection and BANK selection 

The ROMs (both standard and optional ) used in Model 100 
are the 3 2-KB 1-chip type. And , as can be seen~on~the 
memory map ,the address space is positioned from 0000H 
to FFFFH. Consequently ,the A15 signal and bank selection 



signal (STROM) are formed by the chip-select signals. 
As shown in Fig. 24, ADO is latched by Ml 4 (TC40H175: 
quad "D" type F/F) ,by using the WR signal and Y6 signal 
(see I/O port description ), forming the STROMsignal, 
and the chip-select signal of each ROM is formed from 
the IO/M signal by M5 (TC40H139) . 
The standard ROM is selected by the L STROM signal, and 



6*X 



the optional ROM by the H STROM signal. 




ADO 



40HI75- 
M14 



I — 



&l£-i 



RESET 



L2- 



Ais 



*°/m 



STRoM 

Iii 



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4-0H131 

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Standard ROM chip selection 



Optional ROM chip selection 



Active line with high-level 
Active line with low-level 



Fig. 24 Standard and Optional ROM selection 



63 



4 Memory Map 



0000 H J777777777777777 



J (3£KB 7 te) ^satcnoN 



7FFPh 
30O0H 

<?FFFH 
A000H 

B"FFFH 
C0OOH 

OFFFH ( 
E06OH ^? 



'/'///"/ ///ss/s 



STANDARD 
ROM 






'/, BANK 



OPTION 
fcAM 4f^ 
(gfc Byte) 



OpTloU 
RAM #2 

CSK Byte) 



feAM *1 

C9K Byte) 



OpTlOfvi 
ROM 

(32< B/te) 



RAHtf-lCZK&yte) 



t^frW^ 



? RAM ff>4 ', 



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kwfrgfr*^ 



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FFKFtf 



F 

L 






-- STANDARD 



Additional of optional RAMs are from the upper address 



Fig . 25 



I/O Map and I/O Port Description 

As shown in Fig. 26, the I/O address decode circuit decodes 
address signals A12 to A15 and the IO/M signal by the 3 -*■ 8 
decoder IC (40H138) . Because the LCD driver select signal Y7 
is active "H", the output of 40H138 is inverted by 40H000. The 
uses of the select signals (YO to Y6 and Y7) of the I/O 
device and the I/O addresses are shown in Table 22 



6<£ 



■ss 


Signal 


Active 
level 


Application 


7FH 








Free area for RAM file (optional) and other 
select signals of circuits made by user 


3I'K 


YO 


L 


Device-select signal "for optional I/O 
controller unit 


yFH 


Yl 


L 


Device-select signal for optional answering 
telephone unit 


AFH 


Y2 


L 


Bit 0: for ON/OFF of relay for signal 
selection of telephone unit 

Bit 1: used for' 'generation of ENABLE signal 
of LSI (MCI 4412) for MODEM 


BFH 


Y3 


L 


PIO (81C55) chip-select signal 


CFH 


Y4 


L 


ENABLE signal.. for data input/output port 
of UART (IM6402) 


DFH 


Y5 


L 


ENABLE signal for .each status set and 
read port of UART 


LTH 


Y6 


L 


ENABLE signal for STROM ,and REMOTE; 
md input data from Keyboard . 

Also, strobe signal for printer and clock. 


FF1-I | Y7 


H 


ENABLE signal for LCD driver LSI (HD14403) 



TABLE 22 



6s 



T/6 



MS 



6 


CO 

3 . 


15 . 




14 


M 4- 


'3 , 


'J° s' 


' 2 » 


*, 


<> » 


/0 . 


2 


<? r 


l 


7 « or- 




T'^M 



H 
XI 

Y2 
T3_ 
T4 

Y6 



^ 



13 



^ 



r7 



Fig. 26 



The I/O address of each port of PIO (81C55) in Table 22 is 
shown in Table 23 below. 



Address 


Port or resistor 


BOH or B8H 


Command/ status (internal) 




B1H or B9H 


Port A 


B2H or BAH 


Port B 


i B3H or BBH 


Port C 


i B4H or BCH 


Timer . lower byte 


B5H or BDH 


Timer upper byte 


B6H, B7H, B8H and B9H 


Not used 



Table 23 



6 . Keyboard 

Key strobe signals are emitted from PBO and PAO - PA7 of 

81C55, and the return signals from the keyboard pass through 
the octal bus buffer IC (40H244) to the CPU. The data input 
port I/O address at this time is EOH - EFH. 
Condition of pressing T key is shown in Fig .27 



66 



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7. Casstte Interface 

The cassette interface circuitry is divided into sections: the 
modulation section for modulation of the data into the 
recording signal , the demodulation section for return of the 
play back signal to data , and remote section for control of 
the cassette tape recorder. 
(1) Modulation 

After the serial data emitted from the SOD terminal of 
the CPU (80C85) is inverted by the inverter (M34) , the 
DC componentis cut by C63, the data passes through the 
integrator composed of R51 and C64,and, after voltage 
division to the cassette AUX input level by R54 and R55, 
it is input at the AUX terminal. (see Fig. 28) 
CMT connector 



(2) 




R54 R51 
1?K . 2^ 



ciS K34. 



, C63 
i5 0.1A 
•* 

o 
d 




nnnr 



SOD 



*7 



Fig. 28 

Demodulation 

The signal input from the cassette recorder's earphone 
jack passes through the D5 and D6 clamp circuit , is 
emitted from the comparator circuit composed of the 
operation-amplifier IC (TL64 :M30) ,and then, after 
being subject to waveform shaping and inversion by the 
Schmitt trigger type inverter (M34) , is input to the SID 
terminal of the CPU . Here D7 serves to clamp the negative 
voltage output of the comparator . (see Fig. 29) 




^nni^ 



SID 



4,8 



(3) Remote 

The REMOTE signal output is changed to "L" level as a 
result of the write-in of data "1" to bit 3 of the 
output port (40H175: M14) specified by I/O addresses EOH 
- EFH, and, as a result of T6 switching ON, the relay 
(RY1) energized ,and the casstte tape recorder operates. 
(See Fig. 30) 



CMT connector 



REM1 
REM2 




WR* 



Fig 



Printer Interface 

The printer interface circuit conforms to Centronics 

Standards. 

As shown in Fig. 31', the BUSY signal from the printer is read 

from PC2 of 81C55. If the condition is NOT BUSY (PC2: "L" 

level), the 8-bit data is sent to PAO - PA7 of 81C55, and 

then, as a result of data "1" write-in to bit 1 of the output 

port (40H175: M14) indicated by I/O address EOH - EFH, T8 is 

switched ON and an "L" level STROBE signal is sent to the 

printer. 

When the printer receives this STROBE signal, the BUSY signal 

changes to- "H" level, indicating that the printer is busy. The 

CPU then waits until this BUSY signal becomes "L" level. 

When the BUSY signal becomes "L" level, the CPU ceases output 

of the PAO - PA7 data of 81C55, and the output of 1 byte of 

print data is completed. 

If the printer is in the ON-LINE condition, the BUSY signal is 

"H" level, and is "L" level if the printer is in the OFF-LINE 

condition, so that transmission of print data to the printer 

is prohibited. 



A£>1 2 



BUSY 
PAO 7 



k 



5 



STROBE 



^7 




PCI «- 



Fig. 31 

Bar Code Reader Interface 

The input signal from the bar code reader is subjected to 
waveform shaping and inversion by the Schmitt type inverter 
(M34), and is input tc the 81C55 PC3 and 80C85 RST 5.5 
terminals. When the bar code reader reads the first white 
part of the bar code, an "L" signal from the bar code is 
input, ar.d is then inverted by M34, after which RST 5.5 
interruption occurs to indicate the start of data input. Then, 
when the bar code reader is moved on the bar code, the "H" 
signal (which corresponds to white bar codes) and the "L" 
signal (which corresponds to black) are input, and the 
inversion signal is input to PC3 of 81C55 as serial data. (See 

Fl 9' 32<) BLACK LINE 

- - / , WHITE LINE 



Fig. 32 




\ 



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/ 



JUU 



€>J 



■ STROBE 


-Q-WD 




• PDO 




. <fr/\/D 




• PDI 




(5-ND 




PD2 




QrND 


PD3 


V- 


<TND 


! M 


PD4 


- T 


frUD 


'? 


P0 5 


(J 


$ND 




PD6 


r-' 


$ND 


iu 


PPT 


h- 


Q-MD 





BUSY 



1-4 

ex. 




BLACK LINE 



WHITE LINE 



7o 



10- Buzzer Control Circuit 

There are two ways in which the buzzer can be sounded by the 
buzzer control circuit. One is by emitting a signal from PB5 
of 81C55 at a frequency which sounds the buzzer, and the other 
is by using the timer output of 81C55. 

(1) Signal from PB5 of 81C55 

With PB2 of 81C55 at "H" level in the circuit diagram 
(Fig. 33) , the buzzer is sounded by the repeated -OFF and 
ON switchings (of the transistor for buzzer drive)' 
caused by the output from PB5 of "H", "L", "H", "L" . . 
signals synchronized with the frequency for sounding the 
buzzer. 

(2) Using 81C55 timer output 

With PB5 at "H" level in the circuit diagram (Fig. 33) , 
the buzzer is sounded when, with the 81C55 timer in the 
square-wave output mode and set to the value 
corresponding to the frequency which will sound the 
buzzer, PB2 is switched to "L" , causing the square-wave 
pulse emitted from the Timer Out (To) terminal of 81C55 
to be applied to the base of the transistor for buzzer 
drive. 
PB2 uses this as the buzzer ON/OFF control signal. 




(1) Signal from PB5 of 81C55 




(2) Using 81C55 timer output 



Fig. 33 



11. System Bus 

In order to expand the use of external devices, the 40-pin 
system bus is made up of a 40-pin DIP type IC socket. As shown 
in Table 24 , the 80C85 address bus, data bus and control bus 
can all be connected from the system bus to the external 
system, thus making system expansion easy. In addition, the 
optional I/O control unit and RAM file unit can be connected 
to this system bus. 



Pin No. 


Signal 


Input or output 


Pin No. 


Signal 


Input or i 


1 


VDD 





40 


VDD 





2 


GND 





39 


GND 





3 


ADO 


In/output 


38 


AD1 


In/output 


4 


AD2 


In /output 


37 


AD3 


In/output 


5 


AD4 


In/output 


36 


AD5 


• In/output 


6 


AD6 


In/output 


35 


AD7 


In /output 


7 


A8 


Output 


34 


A9 


Output 


8 


A10 


Output 


33 


All ' 


Output 


9 


A12 


Output 


32 


A13 


Output 


10 


A14 


Output 


31 


A15 


Output 


11 


GND 





30 


GND 





12 


RD* 


Output 


29 


WR* 


Output 


13 


IO/M* 


Output 


28 


SO 


Output 


14 


ALE* 


Output 


27 


SI 


Output 


15 


CLK 


Output 


26 


Y0 


Output 


16 


®* 


Output 


25 


RESET* 


Output 


17 


INTR 


Input 


24 


INTA 


Output 


18 


GND • 





23 


GND 





19 


RAM RST Output 


22 


NC 


. 


20 


NC 


— — 


21 


NC 


— — — 






Table 24 


(Note: 


NC = no 


connection 



?z 



The following is an explanation of each signal in Table 24 
except the CPU signal. 

(A)* signal (pin 16) . . . NAND output signal of the RD 

signal and WR signal; used 
by optional RAM file 
RAM RST signal (pin 19) . . Enable signal (external 

C-MOS RAM) ; used by optional 
RAM file 
YO signal (pin 26) . . . Device select signal of 

optional I/O controller unit 

Table 25 , below, shows the DC characteristic of each system 
bus signal. 

i SO, SI, YO, CLK • Signals other than at 

left 

-level output voltage (VOH) 2,4V min (IOH=-400uA) 4.95 V min (IOH=-lpA) 

level output voltage (VOL) 0.45 V max (IOL=2mA) 0.05 V max (IOL=lyA) 

-level output current (IOH) -400pA min (VOH=2.4 V) -0.8 m A min (VOH=4.5 V) 

level output current (IOL) 2 mA min (VOL=0.45 V) 4.0 mA min (VOL=0.5 V) 

-level input voltage (VIH) . 4.0 V min 

level input voltage (VIL) 1.0 V max 

Table 25 
Note: Values shown in Table 25 are at normal temperature (Ta = 25°C) 
and power (VDD = 5.0 V) 



7b 



12. LCD Interface 

The LCD interface circuit is the interface circuit between the 
LCD driver and the CPU. (See Fig. -34.) 

The following signals are necessary for the interface with the 
LCD driver. 



Fig. 34 




sH 



R1Ss3 V31 R154' 
33K 50K(B) 10K 



ADO - AD7 . . . For write-in of control data or display 

data to the LCD driver; signal line for 
read-out from driver 
Y7 . . . LCD driver enable signal 
PAO - PA7, PBO, PB1 . . . Chip enable signal for each 

LCD driver 
SI . . . Indicates whether data is being written into 
(SI = "L") the LCD driver or read out (SI = 
"H" ) 



7tf~ 



A8 . . . Register-select signal in the LCD driver; 
AD0-AD7 data are display data when A="H" 
and are command or status data when 
A8="L". 
E . . . NAND output signal of RD signal and WR signal; 
indicates the timing of the LCD driver data 
read/write . 
V2 . . . Voltage to keep the LCD driver voltage standard; 
LCD display can be changed by changing the V2 
voltage by VR2 . 

Figure' 35 shows the operating timing of each signal, 
Refere to the LCD PWB Technical Description for detailed 
characteristics and operation of the LCD 'and LCD driver. 




DB0~DB7 



DB0~-D&7 



13. Clock Circuit 

A clock LSI (UPD1990AC) is used in the clock circuitso that 
the time can be set and read by BASIC command. 



•£$"■ 



(1) Specification of yPD1990AC 

The uPD1990AC is a C-MOS integrated circuit with a clock 
function which has been designed for connection to a 
microcomputer . 

This IC independently measures the month, date, day of 
the week, hour, minute and second, and will output and 
input these time data freely upon command from the 
microcomputer. By employing this IC, the microcomputer 
is freed from performing clock functions and can be 
devoted exclusively to other complex operations. 
The uPD1990C employes the oscillation of a 32.768-kHz 
crystal as a reference. All functions are enclosed in a 
14-pin dual in-line package. 

(a) Features 

. Marks time (hours, minutes & seconds) and calendar 

(months, date and day of the week) . 
. Serial inputting and outputting of data 

(Input & output code: All digits are binary coded' 

decimals, except the month, which is a hexa-decimal 

code) 
. The reference frequency is 32.768 kHz, which is 

generated by a crystal oscillator circuit. 
. Provided with timing pulse outputs. (Selection of 64 Hz, 

256 Hz or 2048 Hz is possible.) 
. By using the CS (chip selection) terminal, multi-chip 

applications are possible. 

(b) Function specifications 

. Reference frequency (X'tal osc.) 

32.768 kHz 
. Data 

Hours, minutes, seconds, months, date and days of the 

week ("hours" by 24 hour system) (automatic adjustment 

of long and short months) . 



96 



. Data input-output and clock 

Serial input, serial output 

Data input and output in synchronization with the clock 

input from CLK 
. Time pulse output 

Either 64 Hz, 256 Hz or 2048 Hz can be selected by 

command. 
. Mode selection 

Selected according to input to CO - C2. 

C2=0 Register control (control of data input-output) 

C2-1 TP control (control of time pulses) & test control 
(control of test mode) . ■ 

Commands are latched by the STB (strobe) input 
. Chip select 

CLK and STB inputs prohibited by CS input 
. Prohibition of data output 

DATA OUT terminal will become high impedance when the 

OUT ENABL is input. Has no relation with other actions. 
(c) Terminals 

. Input terminals 

DATA IN Data input of. 40-bit shift register 

CLK Shift clock input of 40-bit shift 

register 

CO - C2 Command input (3 bit) 

STB Strobe input 

CS Chip select input (Prohibits CLS & STB) 

OUT ENBL Output control input 

(Makes the DATA OUT high impedance by 
inputting low level) 
. Output terminals 

DATA OUT Data output of 40-bit shift register 

TP Time pulse output 

. Oscillation terminals 

XTAL 1 Oscillation inverter input (OSC IN) 

XTAL 2 Oscillation inverter output (OSC OUT) 
. Power supply terminals 

VDD Plus power supply 

GND (Vss) Common line 



W4- 

CI 


2 


CO 


3" 


STB 


|4 



cs [7 
DATA IN [? 



o 
o 
c- 
cr 

a. 

3 



» t*| * VJ/ 



H *TAL 2 
TTj OUT ENBL 

jo]TP 

3 DATA OUT 



?7 



8 CLK 



Fig. 36 



(d) BLOCK DIAGRAM 

OUT ENBL 



CLK O 



OATA 
IN 



XTAL i o 
X TAL 2 C- 



c 2 o- 
Ci o- 
Cq o- 



cs o- 



3 

i— 3 I 



40 Bit Shift Register 



Multiplexer 



OSC 



CLK 

SD 

PS 



i i 



D/W 
PS 



Month 

— |ps 



HD«e 
PS I 



Hour 

I 



Mrn 



Z" 



Time Counter 
15 Stage Binary Divider 



TEST 
1 



JHz 



32Hz 



64HZ 



:56Hz 



Z>s-8Hz 



V_ 



rO 



COMMAND 
Latch/Decoder 





STB 



GND 



vdd 



I ■lllllllll j |^IH_^ 



DATA 

OUT 



N -channel 
Open Drain 



Multiplexer 



~"~" w^^"~ """^J 



TP 



N-channel 
Open Drain 



f osc « 32.768 kHr 
V 0D - 2.0 to 3.6 V 



Fig. 37 



(e) ■ Ccntnand input timing diagram 

CAN CHANG £ ---.STABLE 



•Cj.Ci.Co 



cs 



STB 



CAN CHANGE 



7g 



NEW COMMAND- 
VAUD 






*SU' 



%- 



•'SI 



V|H- 
VlL 



— — tHLD 



C 



-*STB1- 
'STB2 — 



Fig. 33 



T STBi: 5 m* MIN. (tsTB2 " 4 ° ms MIN. When Time flesd MODE) 

'SU : 2 mi MIN. 

t H LD= 2ms MIN. 

td : 4 m$ MAX. 



FOR REFERENCE 



Commands designated by Co, Ci and C2 will be written into the latch when the STB terminal becomes high 
level, and will be held until a different command of the same group is written-in. 

(f) Data input/output timing diagram 



Register Mode (C 2 . C, . Cq) set to [001 ] . (Shift Mode) 
CS--H- 



CIK 



DATA 
IN 



OUT 
ENBL 



DATA 
OUT 




"I" SEC 



(Note) 



J I ill < ! > 

! I 
i i 



I i I 
0123456789 1071 



Fig. 39 



f- 



* \> 



MM 



D/W 



-H f 



"10"ScC , -r-V!N. , , 



IN 



MONTH 



h 



D/W 



MONTH 



tx. 



33 34 35 36 37 33 39 



July 16 (Sun.) 

2 Hours 24 Minutes 

35 Seconds. 



INPUT 
TIMING 



November 25 (Sat.) 
2"Hours 23 Minutes 
49 Seconds. 



OUTPUT 
TIMING 



Written-in data LSB ("H"l 

appears at output. 



ff 



CLK 



DATA 
OUT 



DATA 
IN 



V|H- 



V(H 



V|L~/ 



a 



^ 



l DSU tDHl 



-**■© 

: Vih" 



tDSU : 2m»MIN. I FOR REFERENCE 

*DHLD : 2vsMIN. 



Fig. 40 

(2) Clock Control Circuit 

As shown in Fig. 41, when Model 100 is in the operable 

condition (RESET is "H" level) , cpmmmands and data can 

be input to UPD1990AC "(MIS) from ,and output to , the CPU 

at will. 

In addition , because battery voltage VB is applied to the 

UPD1990AC power supply, the clock functions even when the 

Model 100 power switch is OFF. 

The clock LSI C0-C2 terminals and DATA IN and CLK terminals 

are connected to the 81C55 PA0-PA4 terminals ,and the DATA 

OUT terminal is connected to the 81C55 PC0' .terminal. The 

STB signal is provided from' bit 2 of the output port 

made by Ml 4 (40H17 5) . The TP output signal is connected 

to the RST7.5 interruption input terminal of' the CPU. 

Square waves are output from the TP (4 ms cycle) ,and one 

key scan occurs every 4 ms because of the RST7.5 interruption 

to the CPU. 



Sb 



(a) Time Set Sequence 

The CPU sets UPD1990AC to the data input mode with TOO " 
pattern of C0-C2 and strobe signal which is generated by AD2 



,Y6 and WR*- signals passing through Ml 4 

Then , the CPU sends the data of time and date information 

to the DATA IN terminal of UPD1990AC with timing clock (PA3) 

Si.' 
Adz 




C19 
0.047-A 



Pi 

12v J 7 

T"""~ CO CI C2 OATACtK 



Fig. 41-1 Data Input 



o i 



< 



r^ 



20P 



3~I* 



C17 



-u 



20P 



AT 



At last, The CPU sets to the timer set mode with "010" pattern 
of C0-C2, and strobe signal. 



Fig. 41-2 Counter set 







C19 

0.047A 



0-L DATAOTP CS 5T& 
CO CI C2 DATA CMC 



B X7XT£~7T 



C18 

HI— 



20 P 



l3 f C !l20P 



iH 



nr 






< 



(b) Time Read Sequence 

The CPU sets UPD1990AC to the counter mode w 
pattern of C0-C2,and strobe signal. 



8/ 



:h "110" 



Fig. 41-3 Counter Read 




C19r 

0.047^ 



T 14- 

.F~ 






OE DATAOTP C^ STS 

pfVl^OAC MIS 

CO Ct C2 DATA CMC 

————————— 



C18 
-it— 



20P 



13 X - 20P 



iH 



TTT 

Then the CPU sets to the data output mode with "100" pattern 
of C0-C2, and reads the data of tiir and date information from 
the DATA OUT terminal. At the sa . time , the CPU sends the 
PA3 signal passing through 81C55 for the timing clock. 



rtr 



Fig. 41-1 Data Output 




C19 
0.047/4 



rl 



*12v J" 7 



OE OATAOTP CS STD 
CO Ct C2 OATACLK 

T OT T"™r"T~T 



i^*-H C il 3 -' 



>p 



a 



13 



CI 






,!*a 



1—1 CN| 

<f if. 






14 Serial Interface 

The serial interface circuitry is divided into three 

parts. One is the serial control circuitry , which 
controls the changes and transmission/reception of data 
(parallel data and serial data ) between the CPU and the 
MODEM and RS-232C circuits , the second is RS-232C 
interface Circuit, and the third is MODEM circuit. 
(1) Serial Control Circuit 

As shown in Fig. 42-1, serial control of the Model 100 
is done by the UART LSI (IM6402) ,and the CPU begins data 
transmission/reception after the control word , which 
determines the mode (transmission/reception) , is 
written into the control register, selected by the Y5 
signal. _ 



8Z 



— 4. 

rs — < 



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CD 



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17 






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22 



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,11 
,25 

20 



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EPE. 

PI 

CLSI 
CLS2 
CRL 

TBRE 

0E 

FE 
PE 



<* >- DRR I% 



CM 



DR 
TRO 
MR 
RRI 



o 



TBRJL 



RBRI ^.AD<Tj 
RBR2 ii-/W>l 
RBR3 ffrz 
RBR4 ^03 
RBR5 ^c>4 
RBR6 jAt»S 
RBR7 ftfl* 
R8R3 ^DfJ 



23 



26 



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*|ap2 

TBR5 22/P4 V- 
TBRt |l A p5 
TBR7s=>U>6 
TBR5 ^P?: 



io $2fe- 



13 — w 
FID* 



XA. 



^jEwL 



Control Register Load Cycle 



Fig. 42-1 



For transmission , the conditio of IM6402 TBRE signal from bit 4of the 
status input port (M23) selected by the Y5 signal is read, and , if it Qv 
is "L" , it waits until it is "H". (shown in Fig. 42-2) 



[ ffW/V /»/////////////// »/ /;;//; /////;/ //// //h 






YS 



RJ> 



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IZ < << 



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40 



— 2ij, TBRE 
la. A .- 



SBS <* J- drrHS 
EPE. 

PI 
as i 

CLS2 
CRL 



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13 



Staus Read Cycle 
Fig. 42-2 



, 25 
20 

H 



OS 
FE 
PE 



eg 

2 



o 

^*- 

DR- 2T 
TRO M 
MR 
RRI 



RBRI &-N>G\ 
RBR2 ii-/«>l 
RBR3 £-AP2 

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R8R& t^PS 
RBR7 ^6 
R8R3 ^kt>rJ 

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TBK2 gA Pl 



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TBfc4 
TBR5^'p4 

TBR'tI^ 
TBi 






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T4 



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When the TBRE signal becomes "H" , data transmission is then possible , 
so that if the transmission data is written into the transmitter buffer 
register (TBR1-TBR8) , the data is output as serial data , including 
the start , parity and stop bits from the TRO terminal . (shown in Fig4 2-3] 






*£- %o Ifl * *» N — oT 
a O <». C>> O A ft A 



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22 



40 



SBS <* 

EPE. 

PI 



^ DRR 1% 



15 



14 



13 



inmuirL js. 

2) 
20 
16 



CLS2 
CRL 



TBRE 
OE 
FE 
PE 



CO 



RBRI &-ADG\ 
RBR2 JLL^pt 

RBR3 i2-AP2 
RBR4- 3-A°3 
R6R5 £*p4 
RBR6 ^\J>S 
RBR7 ^fiTX 
RBR3 Ht\dtJ 



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TRO 
MR 
RRI 



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o 

r 



23 



fl 



TBR3 ?£ A p 2 
TBR4 SIJJ3 
TBR5 ^ p4 
TBRt ^i^p5 
TBR7H»p6 
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J3 — 



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1 . 

1 



r4 




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&A 



Data Transmission fvrlo 



& 



For reception ,when the reception data enters the RRI 

terminal , the DR terminal changes from "L" to "H" ,and 

the.RST6.5 interruption notifies the CPU that reception data 

has entered IM6402, as shSwn in Fig. 42-4. 

The CPU read the OE, FE and PE signals from the status input w- 

port (M23) ,and , if trere is no error when the serial data 

is received , the reception data from the receive buffer 

register selected. by Y4 can be read as 8-bit parallel 

data. 

The IM6402 serial transmission/reception reference clock 

signal is taken from the TO terminal by setting the 

81C55 timer. 



YS- 







TBRI 5;/Vft 
TDK.3 &y»Z 

TPRt 2Ltf>5 
TBR8 ^At>7, 



£D* 



f4 



v i n 



7r* 



Data Reception Cycle 



Fig. 42-4 



In addition , the status input port bit 5 RP signal is held as 
an option for MODEM operation. 



Table 2 6 below sWows the signal correspondence between the 

and status bit and control register of IM6402. 

TABLE 2 6 

Data Bus Control Register 

ADO SBS (Stop Bit Select) 

ADl EPE (Even Parity Enable) 

AD2 PI (Parity Inhibit) 

AD3 CLS1 (Character Length Selected 1) 

AD4 CLS2 (Character Length Selected 2) 



lata 



Status Bit 



;us 



$£- 



OE (Overrun Error) 
FE (Framing Error) 
PE (Parity Error) 
TBRE (Transmitter 



Buffer Empty) 



ADS 
AD 6 

AD 7 



Then , because the serial input/output port which forms IM64 02 is one channel 
only, the circuit shown in Fig. 43 is multiplexed to RS-232C and the MODEM. 
RS-232C signal (PB3 terminal of 81C55 ) determines whether the serial port 
is to Be used as RS-232C or as MODEM. When the RS-232C signal is "L"',the 
serial port is used as RS-232C ,when it is "H" , the port is used as MODEM. 
The reception signal , including the control signal , is demultiplexed at M3 
and the transmission signal is multiplexed at M24 and M26. 
The CTS and DSR signals (as the serial port ) are input to PC4 and PC5 of 
8lC55,and the CD signal is input from bit of the status input port (M23) . 
Output signals DTR and RTS are output from PB6 and PB7 of 81C5 5. 




i 3 M2 ^ ~*" TxM 



RXR 
CTSR 
DSRR 



Fig. 43 



RS232C MODE 




MODEM MODE 



[2) 



RS-232C Circuits 



M3S 
4584. 



(JND— <J)—j 



8 I &6K »," 





R80 33I 



C71 003946(^1 YLAR 
'33*072 OJ039* StylYLArf 

Ts?T~ M24(g) 

33KC73 0.039* 5QMYLAR 



3U 



19^*/ 
R6S DTR 



33 K 



4 V • 
lOOkl-fcj-, 1S2076 

D9 
R138 



100K 



010 



-& 39 f . 
100K HcH> 1S2076 



D8 



1S2076 



M 33(H) 
M 33(S) 
M33(2) 



<? ND —O-j R92 18K J. " 

- -1. — ~ ...—I Jtf^ 

C75,C76,C77: 47 < 4ie v (N.P) 



Fig. 44 



In the RS-232C -transmission circuit, after the DC 
component, is- removed- from the IM6402 TRO signal and the 

■ .4....-! ■■ ■-'.'■■■.■.::■■■;-■ 'uw ■■ • ?.' ? i % ■ • - ■ - : - » 

RTS:; signal and -from the DTR signal by the coupling 
capacitor 



V signals'. 



(0.039 ■uF 50 V) , the signals are leveled to ±5 
.';£y :'tiie Schmitt trigger type inverter IC (M35) , 
and are output as RS-232C transmission signals. 
In the RS-232C reception circuit, the DSRR, CTSR and R x 
R signals from the external RS-232C line are subjected 
to waveform shaping. and inversion by M35 and the diode 
(IS1535) , and then converted to +5 V GND level signals, 
after which they are demultiplexed by 40H157 (M33) and 



converted to CTS, DSR and RRI signals which can be 



9? 



controlled by the CPU. 

Table 27 shows the application of each signal of the 

RS-232C circuits. 



Table 21. 



Symbol 


Name 


TXR 


Transmit Data 


RXR 


Receive Data 


RTSR 


Request to Send 


CTSR 


Clear To Send 


DSRR 


Data Set Ready 


DTRR 


Data Terminal R 



Application 
Data Output from RS-232C 
Data input to RS-232C 



The information below concerns the RS-232C driver and 

receiver". 

Maximum distance transmission .... 5 M 
Driver maximum ; output voltage ... ±5 V 

. Driver minimum^ output voltage ... ±3.5 V 
Receiver maximum input voltage ... ±18 V 
Receiver minimum input voltage ... ±3 V 
In conformity to EIA standard RS-232C 



«?«p 



J MODEM CIRCUITRY 
The modem circuity consists of the modulation/demodulation LSI, the 
transmission filter, the reception filter, and other circuits. 
(0-) Modulation/demodulation LSI 



Th*MC14412eomalnsa eomplm FSK IFreoueney-Shirt Keying) 
modulator and demodulator compatible with both foreign IC.C.I.T.T. 
standards! and U.&A. low speed (0 to 600 (bpi) communication, 
networks. 

• On Chip Crystal Oscillator 

• Echo Supprtnor Disable Ton* Generator 

• Original* and Answer Modal 

• Simplex, Half-Oupltx, and Full Duple* Opiratlon 

• On Chip Sin* Warn Generator 

• Modem Self Ttft Mod* 

• Singl* Supply: Voo " <•"> «<» '8 Vde MC14412FP, MCU412FL 

Voo * 4.7» 10 8.0 Vde MC14413VP, MC14412VL 

• Selactabl* Oata Rates: 0-300, 0-300. 0400 bpi 

• Post Detection Filter 

• TTL or CMOS Compatible Input! and Outputs 

TYPICAL APPLICATIONS: 

• Stand Atom Low-Sp**d Modamt 

• Built-in Low Sp**d Modems 

• Rtmot* Terminals. Acouitleal Couplers 

• Credit Verification 

• Point of Sal* 

• Remote Oata Collection 

• .Remote Process Control 

• Radio Oata Transmission 



Ox<Hrt 
Oki. 



Traftfmtt .._ 



1 Mil 
OmUUW 



P^P»fep ^ Lrrs.7- 

i ._ i f a ■ J [ eraquancv 



Tranwnll 
Oala 



TTL^vnue 
OtaaMa 



«oo- 



■•••in O*o Mw> eo » 



Oata 
Vqo 



""■"EJr 



Q! 



U. 



Daw M«t* 
datwater 



■wff«r«*j 
Ovt»ut 

ft«tiM«r 



Pfta* 



ILOCX Of AO ft AM 



SlMWtM 



TraMwntt C*rr**w 



XT 



,=1 



Woo- "" '• 
V„ - Fin a 



Fig. 45 



*T 





rm ASSIGNMENT 






A.Cr 


V 00 


— It 




$T 


TTJ.O 


— — l» 




"•"out 


Tnw 


i 14 




0"k< 


icti* 


13 




M*wt 
fluOau 


I«aM> 

T» 

Oata 

M*M 


— — — U 
— 10 




vss 


fie* 


— — t 



Fig .46 Pin Assignment 



TrammltOata 
P«r«Jtaf Format 




r 




"" ~1 


T« 










Terminal 
Tranwnittar 


TuOata | 


-Ma4wlatov 


Ouoteaar 


Tetacttiona 




1 Car 

1 «« 




F! 


Network 






UC14411 






IK 


T*rm«na* 


Ra Oata i 


Ownawjlata* 


■afwhiatf 

Fit tec 

and LlrwHef * 


Format 




_ J 


Car 








Racaiwa Data 
PareHal Format 


L_ 












Fig. 47 Application 



To 

Data Terminal < 
Equipment 



11 


13 


10 


„ 14 


15 


2 


J 


• 


— Ui- 




Mode 
Tvoa 

TTLO 
IT 

■!■ Oata 

Ms Oata Rata 

"lawn 



To 

S Telephone 



- Oamocfu later 



Fig. 48 



Input Output Signals 



MAXIMUM RATINGS t Voltseos mftranead to V ss . f 


in 81 




Ratine 


Symkol 


Value 


Unit 


OC Supply Voltefe* MC14412FP 
MC14412VP 


v OO. . 


-0.5 to IS 
-0.5 io 6.0 


Vde 


Input Votteoaa, AH Inputs 


V|„ 


v OD*°* w 
V S S -0 5 


Vde 


OC Current Drain per Pin 
(except Pin 8. 71 


1 


10 


mAdc 


OC Currtnt Onto (Pin B. 71 


! 


35 


mAde 


Operating Temperature Range 


Ta 


-40 TO »«5 


"C 


Storage Temperature Rang* 


T «. 


-8510*150 


°C 



fe> 



ELECTRICAL CHARACTERISTICS 



Choracteriitie 


Symbol 


Voo" 
Vde 


-40»C 


»»«*C 


♦8 


."C 


Unit 


Min 


Mai 


Mln 


Typ 


Ma« 


Min 


Max 


Output Voltage "0" Level 


vol 


5.0 


- 


0.05 


- 





0.05 


- 


0.05 


Vde 


v in * Voo «* ° 




10 


- 


O.OS 


- 





O.OS 


- 


O.OS 




"1" level 




15 


-' 


0.05 


- 





0.05 


- 


0.05 




vom 


5.0 


4.95 


- 


4.95 


5.0 


_ 


4.95 


- 


Vde 


V|„-0orV 00 




10 


9.95 


- 


9.95 


10 


- 


9.95 


_ 








IS 


14.95 


- 


14.95 


15 


- 


14.95 


- 




Input Voltage* "0" Laval 


VlL 


















Vde 


(V - 4 5-or 0.5 Vdcl 




5.0 


- 


1.5 


- 


2.25 


1.5 


- 


1.5 




(V -9.0or 1.0 Vdcl 




10 


- 


3.0 


- 


4.50 


3.0 


_ 


3.0 




IV - 13.5 or t. 5 Vdcl 

"1- Laval 




15 


- 


4.0 


- 


8.75 


4.0 


- 


4 




VlH 


















Voc 


(V • 0.5 or 4.5 Vdcl 




5.0 


3.5 


- 


3.5 


2.7S 


_ 


3.5 


_ 




(V - 1.0 or 9.0 Vdcl 




10 


7.0 


- 


7.0 


530 


_ 


7.0 


_ 




IVo" 13 Of 13.5 Vdcl 




15 


11.0 


- 


11.0 


8.35 


_ 


1'.0 


_ 




Pint 12.15 




5 to IS 


0.75 


- 


O.S 


2.0 


- 


0.85 


- 




Output Oriva Currant w 


!OH 


















mAdc 


IV H • 2S) (Pin 7| 




5 


-0.S2 


— 


-0.5 


-1.5 


- 


-0.3S 


- 




(V H ■ »-5l 




10 


-0.62 


- 


-0.5 


-1.0 


_ 


-0J5 


_ 




CVrjH • 13.51 
(V 0L ■ 0.41 




15 


-I.S 


- 


-1.5 


-3 5 


- 


-1.1 


_ 




'OL 


4.75 


2.3 


- 


2.0 


4.0 


_ 


1.6 


- 


mAde 


(V 0L - 0.51 




10 


5.3 


- 


4.5 


10 


- 


3.6 


_ 


1 


(V f LSI 




IS 


15 


- 


13 


35 


- 


10 


- 


1 


Input Currant (Pin IS " Voo* 


Mr. 


- 


- 


- 


- 


: 0.00001 


:0.l 


- 


- 


wAdc 


Input Pull-Up Hetlsior Sourca Currant 


IP 


5 


2SS 


- 


250 


460 


- 


20S 


_ 


uAdc 


(Pin 15 - Vjs. V|„ - 2.4 Vdcl 






















Pint 1,2.5.6.10.11.12.13.14 






















Input Capacitance 


Cin 


- 


- 


- 


- 


5.0 


- 




- 


pF 


Total Supply Currant 


"T 


5 


_ 


4.5 


- 


1.1 


40 




3.5 


mAdc 


(Pin1S"V 00 l 




10 


- 


13 


- 


4.0 


12 


_ 


11 








15 


- 


27 


- 


8 


25 


- 


33 




Modulatorr'Oemoduiaior Frequency 


ACC 


5 to IS 


_ 


- 


— 


0.5 


_ 


_ 


„ 


X 


Accuracy 






















(Excluding Crystal) 






















Transmit Carrier Output 


V2H 


Sto 10 


_ 


„ 


-JO 


-26 




_ ' 




dB 


2nd Harmonic 




10 to 15 


- 


- 


-IS 


-32 


_ 


.. 


_ 




Transmit Carrier Output 


Vout 


5 


- 


_ 


0.2 


0.30 


- 


- 


_ 


VRM3 1 


Voltaoa Mi. ■ 100 Mil 




10 


- 


- 


0.5 


O.SS 


_ 


- 


- 




(Pin 31 




15 


- 


- 


1.0 


1.5 


- 


- 


- 


1 


Racalva Carriar Rita and 


n-LH. 


5 


_ 


15 


- 


- 


15 


1 


15 1 


ns 1 


Fall Times (Pin 11 


>THL 


10 


- 


S.O 


- 


- 


5.0 


! 


" 1 


| 






15 


- 


4.0 


" 


1 


4.0 


- 1 


40 | 


1 



Table 2S 



?/ 



General 

Fig. 50 shows the MODEM in a system application .The data to be transmitted 

is presented in serial format to the modulatorfor conversion to FSK signals 

for transmission over the telephone network. The modulator output is 

buffered/amplified dividing the 600 ohm telephone line. 

The FSK signal from the remote MODEM is received via the telephone line 

and filtered to remove extraneous signals such as the local Transmit Carrier . 

This filtering can be either a bandpass which passes only the desired band 

of frequencies or a notch which rejects the known interfering signal, the desired 

signal is then limited to preserve the axis crossings and fed to the demodulator 

where the data is recovered from the received FSK carrier. 

Pin Functions 

symbol function 

type The type input selects either the. U.S. or C.C.I.T.T. 

operational frequencies for both transmitting and 
receiving data . When the type input ="1" , the U.S. 
standard is selected and when the type input ="0", 
the C.C.I.T.T. standard is selected. 

Tx Data Transmit data is the binary informatibninput. Data 

entered for transmission is modulated using FSK 
techniques. When operating the U.S. standard (TYPE="1") 
a logic "1" input level represents a Mark When operating 
in the C.C.I.T.T. standard (TYPE="0") a logic "1" 
input level represents a Mark. 

Tx Car The transmit carrier is a digital -synthesized sine wave 

derived from a 1.0MHz oscillator reference. The frequency 

characteristics are as follows: 

United States Standard TYPE="1" 

Transmit Frequency ECHO ="0" 

Mode Tx Data Tx Car 

Originate "1" Mark "1" 1270Hz 

Originate "1" Space "0" 1070Hz 

Answer "0" Mark "1" 2225Hz 

Answer "0" Space "0" 2025Hz 

C.C.I.T.T. Standard TYPE="0" 

Transmit Frequency ECHO="0" 

Mode Tx Data Tx Car 

; Channel "1" Mark "1" 980Hz 

No.l "1" Space "0" 1180Hz 

Channel "0" Mark "1" 1650Hz 

No. 2 "0" Space "0" 1850Hz 

Table 29 



symbol 



Echo Suppressor TYPE="0" 
Disable Tone ECH0="1" 

Mode Tx Data Tx Car 



Chan. No.2"0" "1" 

Table 30 
function 



?Z 



2100Hz 



Tx Enable 



MODE 



ECHO 



Rx Data 



Rx Car 



Rx Rate 



SELF TEST 



Reset 



The transmit carrier output is enabled when the Tx enable 

input ="1" . No output tone can be transmitted when 

Tx enable ="0". 

The mode input selects the pair of transmitting and 

receive frequencies used during modulation and demodulation . 

When mode="l", the U.S. originate is selected (type input 

="1") or the C.C.I.T.T. channel No. 1 (type»"0") . 

When mode ="0", the U.S. answer mode is selected (type 

="1") or the C.C.I.T.T. channel No. 2 (type input ="0"). 

When the Echo input ="1" (type ="0",Mode ="0", 

Tx Data ■?"!") the demodulator will transmit a 2100 Hz" 

tone for the disabling line echo suppressors. During 

normal data transmission, this input should be low="0". 

The receive data output is digital data resulting from 

demodulation the Receive Carrier. 

The receive carrier is the FSK input to the demodulation . 

This input must have either C mos or TTL compatible 

logic level input (see TTL pull up disable) at a duty 

cycle of 50%i4%,that is a square wave resulting from the 

signal limiter. 

The demodulatorhas been optimized for signal to noise 

performance at 200, 300, and bps.The receive carrier 

must change frequency for more than half of the selected 

data rate period before the receive data output will change. 

Data Rate 
0-200bps 
0-300bps 
0-600bps 

When a high level (ST="1") is placed on this input , 

the demodulator is switched to the modulator frequency. 
This input is provided to desrease the time of the chip. 
In normal operation , . this input may be used to disable 
the demodulator (Reset="l") - otherwise it should be 
tied low="0". 



; rate 


Type 


i»i ii 


"0" 


"1" 


n-i ii 


"0" 


hi ii 



symbol 

Osc in, Osc out 



TTLD 



function 

A 1.0 MHz crystal is required to utilizethe on chip 

oscillator . A 1.0MHz square wave clock can also be 

applied to the Osc in input- to satisfy the clock 

requirement. When utilizing the 1.0 MHz crystal, 

externalparastic capacitance , including crystal 

shunt capacitance , must be <, 9PF at the crystal 

input 

To improve TTL interface compatibility, all of the 

inputs to the MODEM have controllable P-channel 

devices which act as pull-up registors when TTLD input 

is low ("0" . when the input is taken high ("1") 

the pull up is disabled, thus reducing power dissipation 

when interfacing with C-MOS. 



?3 



# 



M teffl»roc«*torl 








, 






«aad Ontv 
Memory 


















Random 
Ace an 

Memory 


















Mttfttn 
Ad*0i«r 


















AClA 


, 






f 1 





. Til«afion« 
Network 



Aridreaa Data 
But Sua 



Fig. 49 System Block Diagram 




n 



Modulation/demodulation LSI and peripheral circuitry 

(HUH* 

CARRIER FREQUENCY A 3 



C61 



yv\ 117 Tx^(p 

0.0047,612v 



T 



oc&i 



AMS 



,6 






7 



/o 



CARRIER FREQUENCY ?! !o 



2125Hz 



"VPP 



JTRtfATE 

rrte 

CVjTTPE 

"t RSET 
•5* SVfTST 



(0 id *> 



vss 



// 



Fig. 50 
(ORIGIN. MODE) 



\z 



w 






r 



The Rx Rate and Type terminals of 1MC14412 -(M31) pull up to VDD. 

The baud rate is set to 300 bps, and the U.S. Standard is 

selected. 

Because the ECUO and SELF TEST terminals are not needed, they 

are grounded (level = 0) . 

The Q output (EN signal) of the port (M36) selected, by bit 1 of 

the Y2 port is input to the ENABLE terminal until the unit is in 

the modem mode. 

In addition, the signal designated by the ORIG-ANS switch is 

input to MODE input, thus switching to the originate mode or the 

answer mode. 

Transmission filter circuit 




• 



C6.0 3300P 150v 



Fig. 51 




R43 

*w 



10K(F) 

T4 
2603 



TL 



£*£f 10K 




/ 



C61 12 v 0.0047/^ 

si 



yfr 



• 



9Sr 

(d) Reception filter and comparator circuitry 

As shown in Fig. 52, the reception circuit input signal passes 

through the coupling capacitor (C40) ,is then amplified, passes 

through the 3-stage band-pass filter (composed of an active 

filter) , is then amplified once again , passes through the 

comparator , and, then after being changed to a square wave, is 

input at the RX CAR terminal of MC14412. 

The intermediate frequencies of the 3-stage active filter 

are shown in the chart below. 

The switching of the intermediate frequency for the .originate 

mode and the answer mode is accomplished by switching T2,T3 

and T5 ONor OFF according to the ORIG- ANS switch setting, 

thus changing the value of R16,R28 and R25. 

The transmit carrier signal output from the TX CAR terminal 

is DC by C61,and the signal level is adjusted to -26.5 dB by 

the control (VR2) . The signal then passes through the transmission 

filter (band-pass filter) and is sent to the telephone line 

or the acoustic coupler. 

The transmission filter is composed of an active filter 

consisting of an operation amplifier ,and the intermediate 

frequency must be switched according to the mode (originate 

or answer) . 

Depending on the ORIG-ANS switch setting ,the transistor T4 ' 

is ON or OFF, so that R42 is 2.3K for the answer mode, and the 

synthesis resistance of the R42 and R4 5 value determines the 

originate mode . 

The intermediate frequency of the active filter is 117 0Hz 

for the originate mode ,and 2125Hz for the answer mode. 



% 







t^-o^p-i 



(e) 



Other circuits 



97 



The transmission signal and the reception signal are directly 

connected to the connector (TxM, ExM) during the acoustic 

coupler mode, but, during the direct telephone mode, are 

connected to the secondary side of the driver transformer, and 

the primary side of this transformer is connected to the , 

telephone' line via the connector. (TxMD, RxMD) 

The ACP-DIR switch is used for selection of the acoustic coupler 

or telephone line. 

RY3 is a relay that, when the Model 100 is used in the terminal mode, 

avoids interference from the audio input signal from the 

telephone receiver by- separating the signal (TL) from the 

telephone receiver. RY2 separates the modem circuit and the 

telephone at the conclusion of use in the terminal mode and is 

used as an automatic dialer. 

T26 is switched OFF when the optional answering phone is used, 

and it separates the pull-up resistor R100 (in the input signal 

line of the acoustic coupler) from the V line. 

The other signals (WR and RD) of the modem connector are used 

when the optional answering telephone is used. 







RT5M 



... a. 

R22 620n > , KAmfrr^ 

^ 430a I j i M30C7J 



UJ RXMD— 6 
o 



IWI— <j> 



*r C4-Q 



Fig. 53-1 Acousticc Coupler Mode 



f» 



Dal -Tun^ 

IS2076 T24 

-^2603 R134 






^^J ^ I i ^ % NN ^"* U.O .£. 




R49 

**nr RT5M 



l-^-M30(7) 



u"l RX.'ID— <!>>■ 



' R*M -9 



^ f&K* 



-^ C4-0 



Fig. 53-2 Direct Telephone and Terminal Mode 



15 . Power Supply and Auto Power OFF Circuit 

For Model 100, ±5 V is the pow, r supply of the logic. 

This power is supplied by the DC/DC converter. 

In addition, a special feature of Model 100 is the 

Automatic Power OFF function. 

This circuit is shown in Fig. 54. 

The circuits will be described by dividing them into the 

circuit which supplies the power, and the low-power 

detection and automatic power OFF circuits. 

(1) DC/DC Converter Circuit 

OT2 is a converter tranformer which oscillates T21 and 
T22 and generates voltage at the secondary side of the 
transformer. 

At the same time the power is switched ON, a very slight 
collector current flows to T21 and T22. A voltage 
between pins 7 and 9 of the converter transformer is 
generated, and the T2 2 base potential becomes positive; 
in other words, the base polarity becomes biased in the 
forward direction. This voltage causes the T21 and T22 
base current to flow, and the collector current is 
increased. Although the collector current is increased 
in this way, when it can longer increase, because of 
transistor saturation resistance and converter coil 
resistance, the voltage between pins 7 and 9 begins to 
attenuate, and, as a result, the base current and 
collector current attenuate, causing T21 and T22 to be 
cut off all at once because of the reverse playback 
action. 

Until immediately before the transistor is cut off, 
excitation current flows to the transformer. 
Because the current is suddenly cut off as a result of 
the transistor cut-off, a counter vol -cage is generated. 
the distributed capacity of the coil is charged, and, as 
a result, an oscillation voltage is generated at the 
base coil. 

Then, when the base potential progresses to a half cycle 
of the oscillation voltage, it is biased in the forward 
direction, T21 and T22 are switched Ob: once again, ana 
oscillation such as that shown in Fig. 55 occurs. 



?? 



SQQ 



In this way, AC voltage corresponding to the number of 
windings is generated at the secondary side of the 
converter, and this voltage is rectified and smoothed by 
D13, D15, C84 and C85. 

Moreover, the voltage fluctuations of VDD (+5 V) are fed 
back to the primary side of the oscillation transistor 
by T13, D4, R121 and C92 in order to improve stability. 
C81 and R126 are a differentiation circuit designed to 
make the playback operation of the oscillation 
transistor easier. AC short circuits the circuit, so 
that the oscillation frequency is affected by the 
time-constant of this C and R. 

In this circuit, because feedback is applied by VDD, 
which makes stability difficult, VEE (-5 V) is 
stabilized by R97 and D14. (The voltage at both ends of 
C85 is about -7 V.) 
(2) Low-Power Detection and Automatic Power OFF Circuitry 
The low-power detection circuit illuminates an LED 
warning lamp when the battery voltage decreases. If it 
continues to decrease, the system power will be switched 
OFF./ just before the voltage' becomes so low that the 
converter cannot operate. 

There is more than 2 minutes between the time when the 
LED lamp illuminates and the system is switched OFF (if 
no I/O devices are connected) . 

Battery voltage is detected by splitting the resistance 
of R144, R108, R105 andRH6.. when battery voltage (V L ) 
becomes 4 V ±0.1 V, T16 is switched OFF, T17 is switched 
ON, T19 is driven, and the LED illuminates. (The LED is 
located on the LCD PWB.) 

When V_ becomes 3. 7v ±0.1 V, T14 is switched OFF, T15 
is switched ON, and LPS changes from "H" to "L." This 
signal is inverted by M27,and is fed to the TRAP terminal 

of 80C35. If the --.CPU acknowledges this signal , sends 
the P.C.S. signal passing through the PB4 of 81C55 after 
the internal operations. 



to/ 



The P.C.S. signal is active "H". 

When P.C.S. becomes "H", the Q output of M28 (4013: "D" 
type F/F) becomes "H" , TZO operates, and the oscillation 
of the converter is stopped. 

If there is no operation for 10 minutes or more 
(awaiting a command for 10 minutes or more) , P.C.S. is 
output from PB4 of 81C55. 

When the power switch is switched OFF, T18 is switched 
OFF, the M28 RESET terminal becomes "L" and oscillation 
is resumed by switching the power switch ON. If, 
however, the power is reduced by the L.P.S. signal, 
battery replacement is necessary. R123 and R112 are 
resistors to provide hysteresis. 



/*i 



D23 i_* X A. 

1S2004FC "— 9-f— O- 







/oa 



16 



Reset Circuit 



This circuit supplies the CPU RESET signal and also 

the RAM RST signal as the RAM protecting signal when the 

power decreases. 

The circuit diagram is shown in Fig. (jg . 

RIO 3 and C78 delay the introduction of input power so 

that Til is switched ON and T10 is switched OFF about 

msec after VDD is activated, with the result that the 

RESET signal changes from "L" to "H". This RESET 

waveform is inverted by T9 and is the RAM RST signal. 



R141 provides hysteresis to the RESET signal. 

Thermistor THz suppresses RESET signal fluctuations due 

to temperature. 

T25 receives the signal during automatic power OFF, 

short-circuiting both ends of C78, and resets the 

system. 

The RESET signal is active "L", and the RAM RST signal 

is active "H." 



i 



A 



R«* 



Si i a 



41-HHHW' 

D20_ 

1S2076 

Q Z5C78 



3W 



<>— * 



rm 




R102 



RAM RST 



C68 
1000P 



M28CI3J 



(T9.T25 C2603) 



Fig. 56 



RESET circuit diagram 



MAIN P.W.B ASSY PARTS LIST (cont'd) 



/otf> 



SYMBOL DESCRIPITION 

Ml TC4 0H373P CMOS LOGIC IC 

M2 TC40H245P CMOS LOGIC IC 

M3 TC4 0H138P CMOS LOGIC IC 

M4 TC40H138P CMOS LOGIC IC 

M5 TC40H139P CMOS LOGIC IC 

M6 RAM.BACKKOBT.ION1CMOS 8KB 

M7 BAM PACK (OPTION) CMOS 8KB 

M8 RAM PACK (OPTION) CMOS 8KB 

M9 RAM PACK CMOS 8KB 

M10 SYSTEM BUS IC SOCKET 

Mil OPTION ROM CMOS 32KB 

Ml 2 ROM CMOS 32KB 

M13 IC40H032P CMOS LOGIC IC 

M14 TC40H175P CMOS LOGIC IC 

M15 TC40H244P CMOS LOGIC IC 

Ml 6 . TC4 0H138P CMOS LOGIC IC 

Ml 7 TC40H000P CMOS LOGIC IC 

Ml 8 UPD1990AC CMOS TIMER 

M19 80C85 CMOS CPU 

M20 TC40H367P CMOS LOGIC IC 
H21 . TC40H244P CMOS LOGIC IC 

422 IM64 02 CMOS UART 

423 TC40H244P CMOS LOGIC IC 

424 TC40H032P CMOS LOGIC IC 
■125 81C55 CMOS PIO 

42 6 TC4 0H002P CMOS LOGIC IC 

127 4011 CMOS LOGIC IC 

428 4 013 CMOS LOGIC IC 

129 TL064CN O.P AMP 

130 TL0 64CN O.P AMP 

131 MC14412 CMOS MODEM 

132 TC40H244P CMOS LOGIC IC 

133 TC40H157P CMOS LOGIC IC 

134 HD14584 CMOS LOGIC IC 

135 HD14584 CMOS LOGIC IC 
13 6 4 013 CMOS LOGIC IC 
>1 1S2076 SILICON DIODE 



MANUFAC TURER'S 
PART NUMBER 

QQ040373AT 
QQ040245AT 
QQ040138AT 
QQ040138AT 
QQ040139AT 
QQHX1003A6 
QQHX1003A6 
QQHX1003A6 
QQHX1001A6 



RADIO SHACK 
PART NUMBER 



QQ040032AT 

QQ040175AT 

QQ040244AT 

QQ040138AT 

QQ04 000 0AT 

QQ001990BA 

QQ008085A5 

QQ040367AT 

QQ040244AT 

QQ006402AZ 

QQ040244AT 

QQ040032AT 

QQ008155A5 

QQ040002AT 

QQ004011AT 

QQ004013AT 

QQM00064AU 

QQM00064AU 

QQ014412AM 

QQ040244AT 

QQ040157AT 

QQ014584AT 

QQ014584AT 

QQ004013AA 

QDSS2076#B 



MAIN P.W.B ASSY PARTS LIST (cont'd) 



/Og" 



SYMBOL 

D2 
D3 
D4 
D5 



D12 
D13 
D14 
D15 
D16 
D17 
D18 
D19 



D22 
D23 
Tl 
T2 

■1 

Til 
T12 

T13 

" 
T17 

T18 

T19 

T20 

T21 

T22 

T23 

T24 

T25 

T26 

T27 

T28 

XI 

X2 

X3 



DESCRIPTION 

1S2 07 6 SILICON DIODE 
1S2076 SILICON DIODE 
RD4.3EL3 ZENER DIODE 
1S2076 SILICON DIODE 



1S2076 SILICON DIODE 
ERA81-004 SILICON DIODE 
RD5.1EL1 ZENER DIODE 
1S2076 SILICON DIODE 
1S2076 SILICON DIODE 
1S2076 SILICON DIODE 
ERZ-C10K201 ZNR 
1S2076 SILICON DIODE 



MANUFACTURE ' S 

QDSS2076#B 
QDSS2076#B 
QDZ4R3EL3A 
QDSS2076#B 



QDSS2076#B 
QDS81004XZ 
QDZ5R1EL1A 

.QDSS2076#B 
QDSS2076#B 

-QDSS2076#B 
QNHDK201AN 
QDSS2076#B 



1S2076 SILICON DIODE 
1S2004FC SILICON DIODE 
2SA1115 TRANSISTOR 
2SC2603 TRANSISTOR 

1 

2SC2603 TRANSISTOR 
2SA1115 TRANSISTOR 
2SC2603 E-RANK TRANSISTOR 

2SC2603 E-RANK TRANSISTOR 
2SC2603 TRANSISTOR 
2SA1115 TRANSISTOR 
2SC2603 TRANSISTOR 
2SC1384 S-RANK TRANSISTOR 
2SC2603 E-RANK TRANSISTOR 
2SC2603 TRANSISTOR 
2SC2603 TRANSISTOR 
2SC2603 TRANSISTOR 
2SA1115 TRANSISTOR 
2SC2603 TRANSISTOR 
2SA1115 TRANSISTOR 
32.7 68KHZ CRYSTAL 
4.9152MHZ CRYSTAL 
1-OMHZ CRYSTAL 



QDSS2076#B 
QDSS2004X4 
QTA1115XAE 
QTC2603XAE 



QTC2 6 03XAE 
QTA1115XAE 
QTC2603XCE 

I 

QTC2603XCE 
QTC2603XAE 
QTA1115XAE 
QTC2603XAE 
QTC13 8 4XHN 
QTC2603XCE 
QTC2603XAE 
QTC2603XAE 
QTC2603XAE 
QTA1115XAE 
QTC2603XAE 
QTA1115XAE 
XTR1A1001X 
XBR1A1003X 
XAZ1C2001X 



RADIO SHACK 
PART NUMBER 



MAIN P.W.B ASSY PARTS LIST (cont'd) 



/o6 



SYMBOL 

OT1 

OT2 

TH1 

TH2 

RY1 

RY2 

RY3 

MR1 

MR2 

MR3 

MR4 

MR5 

MR6 

MR7 

VR1 

VR2 

Rl 

R2 

R3 

R4 

R7 
R8 

■■ 
R12 

R13 

R14 

R15 

R16 

R17 

R18 

R19 

R20 

R21 

R22 

R23 

R24 

R25 



DESCRIPTION 

E6732B DRIVER TRANS 
TN22A CONVERTOR TRANS 
TD5-C312D1 -THERMISTOR 
TD5-C310D1 THERMISTOR 
FBR2011CD005M RELAY 
764D5/1AS-T RELAY 
7 64D5/1BS-T RELAY 
100KX8 RESISTOR NETWORK 
100KX8 RESISTOR NETWORK 
100KX8 RESISTOR NETWORK 
33KX8 RESISTOR NETWORK 
100KX8 RESISTOR NETWORK 
100KX8 RESISTOR NETWORK 
100KX8 RESISTOR NETWORK 
K091A 50K (B) VOLUME 
VM6CK-PV(ls) 50K(B) VOLUME 
IK 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 



33K 1/4W 5% CARBON FILM 
IK 1/4W 5% CARBON FILM 



IK 1/4W 5% CARBON FILM 
1.4K 1/4W 1% M-OXIDE FILM 
10K 1/4W 5% CARBON FILM 
121K 1/4W 1% M-OXIDE FILM 
4.31K 1/4W 1% M-OXIDE FILM 
285K 1/4W 1% M-OXIDE FILM 
568K 1/4W 1% M-OXIDE FILM 
7.5K 1/4W 5% CARBON FILM 
4 7 OK 1/4W 5% CARBON FILM 
620 OHM 1/4W 5% CARBON FILM 
43 OHM 1/4 W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
1.4 5K 1/4W 1% M-OXIDE FILM 
3.2K 1/4W 1% M-OXIDE FILM 

1 ATJ» 1 /ATS! 1 CL STTl TiVS f\-Kt T?s*r V «# 



MANUFACTURER'S 
PART NUMBER 

TDZ19A002K 

TC12RZ001B 

QHQ5C310ZP 

QHQ5C310ZP 

ZRA265101Z 

ZRA164102Z 

ZRA164101Z 
RAB104M08X 
RAB104M08X 
'RAB104M08X 
RAB333M08X 
RAB104M08X 
RAB104M08X 
RAB104M08X 
RV9A503B01 
RPSNB50303 
RD25PJ102X 
RD25PJ333X 
RD25PJ333X 
RD25PJ333X 



RD25PJ333X 
RD25PJ102X 



RADIO SHACK 
PART NUMBEr 



RD25PJ102X 

RQBPF14 01X 
RD25PJ103X 

RQBPF1213X 

RQBPF4311X 

RQBPF2853X 

RQBPF5683X 

RD25PJ752X 

RD25PJ474X 

RD25PJ621X 

RD25PJ431X 

RD25PJ103X 

RQBF1451X 

RQBF3201X 
nm en ti n t v 



MAIN P.W.B ASSY PARTS LIST (cont'd) 



/Q?> 



• 



YMBOL 



R27 

R28 

R29 

R30 

R31 

R32 

R3 3 

R34 

R3 5 

R3 6 

R37 

R38 

R39 

R40 

R41 

R42 
3 

R44 

R4 5 

R46 

R47 

R48 

R49 

R50 

R51 

R52 

R53 

R54 

R55 

RS6 

R57 



i 

R62 



~4 



R68 
R69 
R70 



DESCRIPTION 

3. OIK 1/4W 1% M-OXIDE FILM 

7.72K 1/4W 1% M-OXIDE FILM 

242K 1/4W 1% M-OXIDE FILM 

421K 1/4W 1% M-OXIDE FILM 

68K 1/4W 5% CARBON FILM 

22 OHM 1/4W 5% CARBON FILM 

10K 1/4W 5% CARBON FILM 

IK 1/4W 5% CARBON FILM 

330K.1/4W 5% CARBON FILM 

680 OHM 1/4W 5% CARBON FILM 

18 OK 1/4W 5% CARBON FILM 

209K 1/4W 1% M-OXIDE FILM 

IK 1/4W 5% CARBON FILM* 

10K 1/4W 5% CARBON FILM 

560 OHM 1/4W 5% CARBON FILM 

3. OIK 1/4W M-OXIDE FILM 
10K 1/4W 1% M-OXIDE FILM . 

242K 1/4W 1% M-OXIDE FILM 

7.72K 1/4W 1% M-OXIDE FILM 

3 3K 1/4W 5% CARBON FILM 

15M 1/4W 5% CARBON FILM 

68K 1/4W 5% CARBON FILM 

3.3K_1/4W 5% CARBON FILM 

3.3K 1/4W 5% CARBON FILM 

2.2K 1/4W 5% CARBON FILM 

Ik 1/4W 5% CARBON FILM 

100K 1/4W 5% CARBON FILM 

12K 1/4W.5% CARBON FILM 

470 OHM 1/4W 5% CARBON FILM 

10K 1/4W 5% CARBON FILM 

33K 1/4W 5% CARBON FILM 



33K 1/4W 5% CARBON FILM 

620 OHM 1/4W 5% CARBON FILM 

33K 1/4W 5% CARBON FILM 



33K 1/4W 5% CARBON FILM 

NOT USED 

3 3K 1/4W 5% CARBON FILM 



■MANUFACTURER ' S 
PART NUMBER 

RQBF3011X 

RQBF7721X 

RQBF2423X 

RQBF4213X 

RD25PJ683X 

RD25PJ220X 

RD25PJ103X 

RD25PJ102X 

RD25PJ334X 

RD25PJ681X 

RD25PJ184X 

RQBPF2093X 

RD25PJ102X 

RD25PJ103X 

RD25PJ561X 

RQBPF3 011X 
RQBPF1002X 

RQBPF2423X 

RQBPF7721X 

RD25PJ333X 

RD25PJ156X 

RD25PJ683X 

RD25PJ332X 

RD25PJ332X 

RD25PJ222X 

RD25PJ102X 

RD25PJ104X 

RD25PJ123X 

RD25PJ471X 

RD25PJ103X 

RD25PJ333X 

I 

RD25PJ333X 
RD25PJ621X 
RD25PJ333X 



RD25PJ333X 



RADIO SHACK 
PART NUMBEF 



RD25Pj:vnx 



So& 



SYMBOL 

371 

R72 

R7 3 

R74 

R75 

R7 6 

R77 

R78 

R79 

R8 

R81 

R82 

R83 

*84 

*85 

*8 6 

*87 

*88 

189 

*90 

191 

192 

193 

194 

595 

196 

197 

L98 

199 

iroo 

L101 
1102 
1103 
:104 
.105 
.106 
107 
108 



DESCRIPTION 

33K 1/4W 5% CARBON FILM 
IK 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
10 OK 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
10 OK 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
100K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
10 OK 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
6.2K 1/4W 5% CARBON FILM 
6.2K 1/4W 5% CARBON FILM 
6.2K 1/4W 5% CARBON FILM 
15K 1/4W 5% CARBON FILM 
5.6K 1/4W 5% CARBON FILM 
18K 1/4W 5% CARBON FILM 
68K 1/4W 5% CARBON FILM 
5.6K 1/4W 5% CARBON FILM 
100 OHM 1/4W 5% CARBON FILM 
18K 1/4W 5% CARBON FILM 
27 OHM 1/4W 5% CARBON FILM 
18K 1/4W 5% CARBON FILM 
5.6K 1/4W 5% CARBON FILM 
2.2K 1/4W 5% CARBON FILM 
4.3K 1/4W 5% CARBON FILM 
100K 1/4W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
56K 1/4W 5% CARBON FILM 
2.7K 1/4W 1% M-OXIDE FILM 
150K 1/4W 5% CARBON FILM 
68K 1/4W 5% CARBON FILM 
22. 6K 1/4W 1% M-OXIDE FILM 



MANUFACTURER'S 
PART NUMBER 

RD25PJ333X 

RD25PJ102X 

RD25PJ333X 

RD25PJ333X 

RD25PJ104X 

RD25PJ333X 

RD25PJ333X 

RD25PJ104X 

RD25PJ333X 

RD25PJ333X 

RD25PJ104X 

- RD25PJ333X 

RD25PJ104X ' 

RD25PJ333X 

RD25PJ103X 

RD25PJ333X • 

RD25PJ622X 

RD25PJ622X 

RD25PJ622X 

RD25PJ153X 

RD25PJ562X 

RD25PJ183X 

RD25PJ683X 

RD25PJ562X 

RD25PJ101X 

RD25PJ183X 

RD25PJ271X 

RD25PJ183X 

RD25PJ562X 

RD25PJ222X 

RD25PJ432X 

RD25PJ104X 

RD25PJ1Q3X 

RD25PJ563X 

RQBPF2701X 

RD25PJ154X 

RD25PJ683X 

RQBPF2262X 



RADIO SHACK 
PART NUMBE. 



• 



MAIN P.W.B ASSY PARTS LIST (cont'd) 



/0? 



m 



YMBOL 



m 




R109 
R110 
Rill 
R112 
R113 
R114 
R115 
R116 
R117 
R118 
R119 
R120 
R121 
R122 
R123 
124 
125 
R126 
R127 
R128 
R129 
R130 
R131 
R132 
R133 
R134 
R135 
R136 
R137 
R138 
R139 
R140 
141 
142 
R143 
R144 
R145 



DESCRIPTION 

56K 1/4W 5% CARBON FILM 
15 OK 1/4W 5% CARBON FILM 
15 OK 1/4W 5% CARBON FILM 
1.8K 1/4W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
100K 1/4W 5% CARBON FILM 
150K 1/4W 1% M-OXIDE FILM 
100K 1/4W 5% CARBON FILM 
100K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
82K 1/4W 5% CARBON FILM 
5.6K 1/4W 5% CARBON FILM 
470 OHM 1/4W 5% CARBON FILM 
1.8K 1/4W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
27 0. OHM 1/4W 5% CARBON FILM 
22K 1/4W 5% CARBON .FILM 
33K 1/4W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
22K 1/4W 5% CARBON FILM 
IK 1/4W 5% CARBON FILM 
150K 1/4W 5% CARBON FILM 
NOT USED 

3.3K 1/4W 5% CARBON FILM 
68K 1/4W 5% CARBON FILM 
62K 1/4W 5% CARBON FILM 
100K 1/4W 5% CARBON FILM 
10 OK 1/4W 5% CARBON FILM 
100K 1/4W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
1M 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
15K 1/4W 5% CARBON FILM 
15K 1/4W 5% CARBON FILM 



MANUFACTURER ' S 
PART NUMBER 

RD25PJ563X 

RD25PJ154X 

RD25PJ154X 

RD25PJ182X 

RD25PJ103X 

RD25PJ333X 

RD25PJ104X 

RQBPF1503X 

RD25PJ104X 

RD25PJ104X 

RD25PJ333X 
RD25PJ823X 
RD25PJ562X 
RD25PJ471X 
RD25PJ182X 
RD25PJ103X 
RD25PJ103X 
RD25PJ271X 
RD25PJ223X 
RD25PJ333X 
RD25PJ103X 
RD25PJ223X 
RD25PJ102X 
RD25PJ154X 

RD25PJ332X 
RD25PJ683X 
RD25PJ623X 
RD25PJ104X 
RD25PJ104X 
RD25PJ104X 
RD25PJ103X 
RD25PJ105X 
RD25PJ333X 
RD25PJ333X 
RD25PJ153X 
RD25PJ153X 



RADIO SHACK 
PART NUMBEE 



MAIN P.W.B ASSY PARTS LIST (cont'd) 



//c? 



SYMBOL 

R146 
R147 
R148 
R149 
R150 
R151 
R152 
R153 
CI 

C4 
C5 

I 
C8 

C9 

CIO 

Cll 

C12 

i 
i 

I 

C16 

C17 

:i8 
:i9 
:20 
:2i 
:22 
:23 

121 

:28 
:29 
:30 

:3i 

:35 
:36 

'37 



DESCRIPTION 

33K 1/4W 5% CARBON FILM 
180 OHM 1/2W 5% CARBON FILM 
180 OHM 1/2W 5% CARBON FILM 
56K 1/4W 5% CARBON FILM 
470 OHM 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
10K 1/4W 5% CARBON FILM 
33K 1/4W 5% CARBON FILM 
0.047UF 12V CERMIC CAPACITOR 



0.047uF 12V CERMIC CAPACITOR 
luF 10V TANTALUM CAPACITOR 



luF 10V TANTALUM CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
.luF 12V CERMIC CAPACITOR 
-O-lTlF 12V CERMIC CAPACITOR 
0.047uF 12V CERMIC CAPACITOR 



0.047uF 12V CERMIC CAPACITOR 
20pF 50V CERMIC CAPACITOR 
20pF 50V CERMIC CAPACITOR 
0.047UF 12V CERMIC CAPACITOR 
500pF 50V CERMIC CAPACITOR 
500pF 50V CERMIC CAPACITOR 
500pF 50V CERMIC CAPACITOR 
500pF 50V CERMIC CAPACITOR 



500pF 50V CERMIC CAPACITOR 
0.047uF 12V CERMIC CAPACITOR 
lOpF 50V CERMIC CAPACITOR 
lOpF 50V CERMIC CAPACITOR 
0.047UF 12V CERMIC CAPACITOR 



0.047uF 12V CERMIC CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
O.luF 12V CERMIC CAPACITOR 



MANUFACTURER ' S 
PART NUMBER 

RD25PJ333X 
RD50TJ181X 
RD50TJ181X 
RD25PJ563X 
RD25PJ471X 
RD25PJ333X 
RD25PJ103X 
RD25PJ333X 
CBD1B473MU 

CBD1B473MU 
CSSC010MDC 

I 

CSSC010MDC 
CBG1B104MM 
CBG1B104MM 
CBG1B104MM 
CBD1B473MU 



RADIO SHACK 
PART NUMBE 



m 



CBD1B4 73MU 
CCGB200KCT 
CCGB200KCT 
CBD1B473MU 
CCGB501kCT 
CCGB501KCT 
CCGB501KCT 
CCGB501KCT 

I 

CCGB501KCT 
CBD1B473MU 
CCGB100DCT 
CCGB100DCT 
CBD1B473MU 

CBD1B473MU 
CBG1B104MM 
CBG1B104MM 



MAIN P.W.B ASSY PARTS LIST(cont'd) 



•'/ 



SYMBOL 

) 

C38 

C39 
C40 
C41 



C46 
C47 

C48 
C49 
C50 
C51 
C52 
C53 
C54 
C55 
C56 
57 
C58 
C59 
C60 
C61 
C62 
C63 
C64 
C6 5 
C66 
C6 7 
C63 
C59 
C70 
C71 
C72 
C7 3 

I 74 
"C75 

C76 

C77 
C78 



DESCRIPTION 

lOOpF 50V CERMIC CAPACITOR 
0.047uF 12V CAPACITOR 
0.0047UF 50V 5% MYLAR CAPACITOR 
33 0pP 50V 10% MYLAR CAPACITOR 



33 00pF 50V 10% MYLAR CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
10UF 16V ELYT CAPACITOR 
lOuF 16V ELYT CAPACITOR 
0.047uF 12V CERMIC CAPACITOR 
luF 50V N.P ELYT CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
10 uF 16V ELYT CAPACITOR 
10 UF 16V ELYT CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
3300pF 50V 10% MYLAR CAPACITOR 
3 300pF 50V 10% MYLAR CAPACITOR 
0.0047uF 50V 5% MYLAR CAPACITOR 
0.0 luF 25V 20% CERMIC CAPACITOR 
O.luF 50V 10% MYLAR CAPACITOR 
0.0 47uF 50V 10% MYLAR CAPACITOR 
0.0 47uF 12V CERMIC CAPACITOR 
0.0 47UF 12V CERMIC CAPACITOR 
O.C47uF 12V CERMIC CAPACITOR 
1000 pF 50V CERMIC CAPACITOR 
IGOOpF 50V CERMIC CAPACITOR 
O.luF 12V CERMIC CAPACITOR 
0.039UF 50V 10% MYLAR CAPACITOR 
0.039uF 50V 10% MYLAR CAPACITOR 
0.0 39uF 50V 10% MYLAR CAPACITOR 
0.047UF 12V CERMIC CAPACITOR 
4 7uF 16V N.P ELYT CAPACITOR 
4 7uF 16V N.P ELYT CAPACITOR 
47ur 16V N. P. ELYTl" CAPACITOR 
3.3i:F 50V ELYT CAPACITOR 



MANUFACTURER ' S 
PART NUMBER 

CCGB101JLT 
CBD1B473MU 

CQMB472JTH 
CQMB332JTH 



RADIO SHACK 
PART NUMBER 



CQMB3 32JTH 
CBG1B104MM 
CBG1B104MM 
CEVD100ADN 
CEVD100ADN 
CBD1B473MU 
CEAD010NLN 
CBG1B10 4MM 
CEVD100ADN 
CEVD100ADN 
CBG1B10 4MM 
CBG1B10 4MM 
CBG1B10 4MM 
CQMB332JTH 
CQMB33 2JTH 
CQMB4 72JTH 
CBD1E10 3MM 
CQMB10 4KTH 
CQMB4 7 3KTH 
CBD1B47 3MU 
CBD1B473MU 
CBD1B47 3MU 
CK5B10 2KBT 
CK<JB10 2KBT 
CBG1B10 4MM 
CQMB3 9 3KTH 
CQMB3 9 3KTH 
CQMB3 9 3KTH 
CBD1B47 3MU 
CEAD470NLX 
CEAD4 70NLX 
CEAD4 70NLX 
CEVG3R3ALN 



MAIN P.W.B ASSY PARTS LIST (cont'd) 



//Z 



SYMBOL 



DESCRIPTION 



MANUFACTURER ' S 
PART NUMBER 



RADIO SHACKl 
PART NUMBE 



m 



C79 


0.047UF 12V CERMIC CAPACITOR 


CBD1B473MU 


C80 


0.047uF 12V CERMIC CAPACITOR 


CBD1B473MU 


C81 


lOOOpF 50V CERMIC CAPACITOR 


CKCFB10 2KBT 


C82 


4.7uF 25V ELYT CAPACITOR 


CEVE4R7ADN 


C8 3 


4 70uF 10 V ELYT CAPACITOR 


CEAC471ACX 


C84 


4 70uF 6.3V ELYT CAPACITOR 


CEAB4 71ACX 


C85 


4.7uF 35V ELYT CAPACITOR 


CEAF4R7ACX 


C86 


3.3UF 50V ELYT CAPACITOR 


CEVG3R3ALN 


C87 


O.luF 12V CERMIC CAPACITOR 


CBG1B10 4MM 


C88 


500pF 50V CERMIC CAPACITOR 


CCGB501KCT 


C89 


500 pF 50V CERMIC CAPACITOR 


CCGB501KCT 


C90 


luF 50V ELYT CAPACITOR 


CEVG010ADN 


C91 


0.047uF 12V CERMIC CAPACITOR 


CBD1B4 73MU 


C92 


0.47uF 50V ELYT CAPACITOR 


CEVGR47ADN 


C93 


100 pF 50V 10% MICA CAPACITOR 


CMDA10 1KXB 


C94 


0.0047uF 25V CERMIC CAPACITOR 


CBD1E472MM 


C95 


O.luF 250V 20% POLYESTER 

CAPACITOR 


CQHD10 4MEN 


C96 


O.luF 250V 20% POLYESTER 

CAPACITOR 


CQHD10 4MEN 


C97 


1000 pF 50V 10% CERMIC 

CAPACITOR 


CKSB10 2KBT 


C98 


lOOOpF 50V 10% CERMIC 

CAPACITOR 


CK5B10 2KBT 


C99 


O.luF 12V CERMIC CAPACITOR 


CBG1B10 4MM 


C100 


2200pF 50V 10% CERMIC 

CAPACITOR 


CBD1H222KM 


C101 


luF 10 V TANTALUM CAPACITOR 


CSSC010MDC 


SW1 


SSP32201 SLIDE SWITCH 


SS0 20259ZA 


SW2 


SSB3420 4 SLIDE SWITCH 


SS040213ZA 


SW3 


SKM 22-0 3 SLIDE SWITCH 


SS0 20260ZL 


SW4 


SPJ312U PUSH SWITCH 


SP01ABA0 6A 


SW5 


SSP32201 SLIDE SWITCH 


SS020259ZA 


CN1 


5268-10Ax2 CONNECTOR 


YJF10S0 50Z 


CN2 


A-7224 CONNECTOR 


YJF0 9S0 39Z 


CN3 


TCS4 480 CONNECTOR 


YJF0 8S0 33Z 


CN4 


TCS4 4 90 CONNECTOR 


YJF0 8S0 34Z 


CN5 


FRC2-C26-L13-ON CONNECTOR 


YJF26S010Z 


CN6 


DB-25S CONNECTOR 


YJF25S007Z 



MAIN P.W.B ASSY PARTS LIST (cont'd) 



"3 



SYMBOL DESCRIPTION 

CN7 HU-30P-2G-L13 

3-51FT Ni-cd BATTERY 
HECO 34 2-01-010 JACK 
A-8878A-28S-1H IC SOCKET 



MANUFACTURER » S 
PART NUMBER 

YJF30SO06Z 
ZBN0 3610 2Y 
YJB0 3S0 01Z 
YSC28S002Z 



RADIO SHACK 
PART NUMBER 



IC SOCKET 

IC SOCKET 
IC SOCKET 
BATTERY TERMINAL (A) ' 
BATTERY TERMINAL (B) 
BATTERY SUPPORT 



MW361SN001 
MW361SN00 2 
VS118SB001 



y/^ 



SECTION IV 



LCD P.W. BOARD 



/vjr* 



TECHNICAL DESCRIPTION 

The technical description of the Model 100 LCD PWB is divided 

into the following 3 sections. 

1. LCD PANNEL 

2. LCD CONTROL CIRCUIT 

3. LCD WAVE FORM 

1. LCD PANEL 

Liquid crystal is a substance midway between a liquid 
and a solid, although its appearance is much like a 
liquid. From an electrical and optical stand point, it 
possesses the properties of a crystal. Items which use 
this liquid crystal are liquid crystal display elements. 
The LCD used in Model 100 is a TN (Twisted Nematic) type 
of liquid crystal. Its basic construction is shown in 
Fig. 1. 



Electrode / 

/ / 



/ 



U^u'.J crystal 

"Front PoUrizer 



!/. ■ 






.• /■'/.' .' -i 


/ 


/ 

r 


7 




V** "~ 


— 


III """" *"* ~"* ■*"" 


l, M( 


\ 




V 




!-- 


■:■ : T 




_____ U-, 




fce-flector 
Re<\r PoU riser 
Rear- $kss 



Fig. 



The principle by which it functions can be briefly 
expressed as "an electric shutter with relation to 
light". In other words, if voltage is applied, the 
transmission of light is blocked, and, if voltage is not 



//£ 



applied, light is passed, so that letters and numbers 

are displayed. 

The operation theory is shown in Fig. 2. 

(1) The optical activity (twisting) of light is used, 
and the liguid-crystal . display element is 
sandwiched between the two polarization plates. 
The polarized axes of the upper and lower plates 
are placed at right angles to each other. 

(2) As shown in Fig. 2 (a), if voltage is not applied, 
the liquid-crystal molecules between the upper and 
lower plates twist 90° to distribute light. 

This results in a 90° optical movement of the 
light. 

(3) In other words, when voltage is not applied, light 
is transmitted, and when voltage is applied, light 
is interrupted. 



(a) when voltage is CrV 



Cb) wWen voltage is ON 



molecules 

/ 

10° turn f 



V 



nature light 




^ 



L 



Fig. 2 



v/y*//.. 



/ 



Front pola riser 



Front <%la.ss 
Klectrode 



Rear <jlass 



"Blecti-ocie 
Rear piUrlier^ 



6 



ON 



li^ht is passed 



MM/ 



li^Jrfc is interrupted 

AarK (black) 



//J 



The LCD used in Model 100 is composed of electrodes in a 
matrix arrangement (back scan 64, segments 4 80). Refer 
to Fig. 3. 

Because this LCD operates on a 1/32 duty time-division 
drive, the upper 32 and lower 32 back scanning is 
performed by the same signal. 




n 240 



IT' J2 240' 



Com«*on 



Segment 



Segment 



Common 






16 




Fig. 3-' 



LCD electrodes 



The angle of the field of vision is 30° in the range 

that contrasts. K = (brightness of non-illuminated 

segment) / (brightness of illuminated segment) 1.4 or 
more. 



"B 



This range can be set at will from 0° to 90° by setting 
the LCD drivejvoltage by using the DISP control. 

LCD Voltage 

7 6*30* 



Fig. 4 




LCD VoHrA^e 
low 



Caution 

The polarization plate attached to the surface of the 

LCD panel is scratched very easily, and so must be 

handled with great care. 

To clean contacts or the display surface, slightly 

damapen a soft cloth with benzine and wipe gently. Do 

not use organic solvents such as alcohol. 



// 



/ 



LCD CONTROL CIRCUIT 

Refer to the LCDPWB circuit diagram while 

reading this section. 

ICs Mil and Ml 2 (HD44103) are back-scan driver ICs. The 

timing signal -necessary for. the display is generated by 

the built-in oscillator and by C5 and RIO, and this 

timing signal is also supplied to the segment driver 

side for control of the display. 

There are 16 HD44103 "back-scan signal outputs. Mil and 

M12 are cascade connected, and a 1/32 duty back-scan 

signal is made. By using a C and "R only at the Mil 

side, a timing signal is generated, and Ml 2 is 

controlled by that signal. Mil can then be considered 

to be the master IC and M12 the slave. The basic 

oscillation frequency is about 430 kHz. 

Fig. 5 shows the internal logic composition. 

? 

r 20 



LCD Driver 



DL O"*- 



* Lo^/C. 



FRMO*- 



M 



o»- 



O— "OSC 



I 



zo 



20 5-barS bi-c/irecfi'«i J 
stii-ft register 



Lojic 



Lojic 



CLK C— L0| 

Fig. 



W 



d\ 






ZL 



» diVi der 



-o DK 




frame irc$."*ncy Pu y 
selected Selecter 

HD44103 internal logic 



TUT 



-O Q-ND 



/2x> 



The timing signals are M, FRM, 0., 0_ and CL. The M 

signal is the signal which inverts the LCD drive 

waveform one image at a time to change it to AC. 

Because the continuous application of DC to the LCD 

would shorten the element life, an alternating electric 

field is applied to the liquid crystal surface during 

drive in order to make the waveforms symmetrical and 

make the DC component as small as possible. 

The FRM signal is the display repeat frreuency, the 

signal which sets the number of scans per second. 

For Model 100, FRM ^=70 Hz. 

The 1 and 2 signals are the locks for HD44102 RAM 

operation. 

The CL signal is the shift lock for the shift register. 

ICs Ml - M10 (HD44102) are segment driver ICs that cause 

the display data sent from the CPU board to be memorized 

in the built-in RAM and automatically generate the 

liquid-crystal drive signal. 

One bit of data from the built-in RAM corresponds to one 

dot of illumination or non-illumination on the display. 

The driver output is 50. 

The transfer of the display data is accomplished by 

8-bit parallel data. This IC has several types of 

commands, and the D/I (H: data, L: command) signal 

distinguishes between commands and data. 

Fig. 6 shows the internal logic composition. 



/%/ 



£ 
p /l 



DB 



°~7 a 



u 



u 



*-*-*• 



BUS)' 



0-»- 









*1 



Yl ~50 



2 



LCD Driver 



♦*■ 



*— ^ 



5-0 



-«. A gob/te p^e 



A 5ot 7 te 1 r*3 e 



1 



A gob/te 2p°^e 



£ 5-0 t/te 3 pa^e 



-J 






V/DD 
Vl 

-. O \/ 3 

-• VEE 

L — ° ( *~' JD 

o FR.M 



Lojic 



-0 M 



ci.k(*i,to 



Fig. 6 HD44102 internal logic 



Because Model 100 has 240 segments each (upper and 

lower) , the M5 and M10 segment output Y41 - Y50 becomes 

NOCONNECTION. The power supplied to these ICs, in 

addition to V DD (+5 V) and V £E (-5 V) , also includes VI 

- V6. 

V DD and V EE are the power supplies which operate the IC 

logic, and VI - V6 make the LCD signal. 

VI - V6 are made by the resistance splitting of Rl , R2 , 

R3, R4 and R5 , and, by passing through operation 

amplifier M13 (HA17902) , lessen the output impedance of 

the power supply. 



7.22- 



C3, C4, C6, C7 and C8 augment the peak current during 

LCD illumination. 

Rll, R12 and R13 are resistors for IC latch-up 

prevention. 

This board also includes a low-power detection LED and 

buzzer connectors. 



/*3 

LCD WAVEFORM 

In order to drive the liquid-crystal elements by the 1/32 duty 
line-sequential drive method, the LCD of Model 100 makes 
sequential selection of the 32 scanning electrodes. 
For each dot, the display signal passes through the signal 
electrodes and is applied 3 2 times for one display. At this 
point the signal is necessary at each dot only one time, and the 
signals for the other 31 times correspond to other dots on the 
same signal electrode. 

Because liquid-crystal elements have a cumulative response 
characteristic (a response characteristic corresponding to the 
sum total of the effective voltages of the voltage pulses 
applied for some tens of msec to some hundreds of msec) , the 
voltage applied for 32 times is all applied as effective 
voltage, so that the content (the ON or OFF contrast) of the dot 
in question is affected by crosstalk (display information) from 
other dots on the same display line. 

In order to suppress such crosstalk, it is necessary that the 
voltage applied as effective voltage to the liquid-crystal in 
question be maintained at a constant level for each dot on the 
matrix regardless of whether the signals of the other dots 
(applied 32-1) are ON or OFF, so that a voltage average is 
realized through a combination of voltage levels when the 
scanning signal and display signal are selected and not 
selected. 

An appropriate algebraic method for each condition can be used 
to determine the voltage combinations applied to the element 
(the voltage averaging method) in order to obtain the maximum 
display contrast while suppressing crosstalk between the 
liquid-crystal elements. The combination of the liquid-crystal 
elements and the combination of the two types of non-applied 
voltages and the resulting potential difference actually applied 
to the liquid-crystal are shown in (a) and (b) of table 1. 



Signal electrode 

Scanning 
electrode • 



Selection 



Non- 
selection 



VO 



VO/a 



Selection 



+ VO 



VO/a 



[a) 



Non-selection 



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2V0/a 



(1 - 2/a)V0 



- VO/a 



Signal electrode 



Scanning 
electrode 



Selection 



Non- 
! selection 



Selection 



VO 



- VO 



[l-l/a)V0 - VO/a 



(b) 



Non-selection 



' (1 - 2/a)V0 



- (1 - 2/a)V0 



+ VO/a 



Table 1: Liquid-crystal voltages and voltages applied to each 

electrode by the voltage averaging method 
As can be understood by studying Table 1, the voltages applied 
to the liquid-crystal (32-1 time for non-selection) are averaged 
to ±V0/a regardless of whether the signal voltage is selected 
(other segments are ON) or not selected (other segments are 
OFF) . 

In addition, the waveform is inverted, resulting in alternating 
drive, by alternating the (a) and (b) applied voltages. 



/2£r 



Here VO represents the maximum voltage applied to the scanning 
electrode and signal electrode, and, for Model 100, is the 
potential difference between VI and V2. 

In addition, a is the bias coefficient which determines, from 
the stand point of contrast, the. maximum ratio between the 
illumination voltage and the non-illumination voltage. 

When that ratio is greatest in relation to the effective ON and 

OFF voltages, a = 6.66. 

Thus, for VI, V2, V3 , V4 , V5 and V6 : 

VI a 

V2 = V 

V3 » 2/aV 

V4 = (1 - 2/a)V 

V5 = (1 - l/a)V 

V6 = a/aV 

The following figures show the drive waveform for illumination 

and non-illumination. 



Fig 7 



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LCD P.W.B ASSY PASRTS LIST (cont'd) 



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DESCRIPTION 



HD44102B L.C.D DRIVER IC 



HD44102B L.C.D DRIVER IC 
HD44103B L.C.D DRIVER IC 
HD44103B L.C.D DRIVER IC 
HA17902P O.P AMP 
10K 1/8W 2% CHIP RESISTOR 
10K 1/8W 2% CHIP RESISTOR 
26. 5K 1/8W 2% CHIP RESISTOR 
10K 1/8W 2% CHIP RESISTOR 
10K 1/8W 2% CHIP RESISTOR 
100K 1/8W 5% CHIP RESISTOR 

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100K 1/8W 5% CHIP RESISTOR 
220 OHM 1/8W 5% CHIP RESISTOR 
220 OHM 1/8W 5% CHIP RESISTOR 
100 OHM 1/4W 5% CARBON FILM . 
O.luF 25V CHIP CAPACITOR 



O.luF 25V CHIP CAPACITOR 
18pF 25V CHIP CAPACITOR 
O.luF 25V CHIP CAPACITOR 



O.luF 25V _. CHIP CAPACITOR 

LR20 2-C L.C.D 

L.C.D CONNECTOR 

L.C.D HOLDER 

SLP-135B L.E.D 

CONNECTOR ASSY 

5267-0 2A CONNECTOR 

BUZZER KBS-27DB-3AU 

HOUSING 5264-0 2 

CONN TERMINAL526 3-BT 



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SECTION VII 
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Model 100 
Preliminary Diagnostics 



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MEMORY DIAGNOSTICS 



Description 

Model 100 Memory Diagnostics consists of two machine level programs 
and is designed to test the ROM and RAM of the TRS-80 Model 100 
Portable Computer. 



Quick Reference 

IMPORTANT NOTE: ALL USER FILES WILL BE DELETED FROM THE MODEL 100 
MEMORY BY THE USE OF THESE PROGRAMS. IF THERE ARE ANY FILES THAT YOU 
WISH TO RETAIN, SAVE THEM FIRST ! ! ! ! . 

1) Prepare cassette player and cassette tape 

2) Power up the Model 100 

3) At the Model 100 power-up menu type 'BASIC <ENTER> ' OR position 
the cursor over the word 'BASIC and press <ENTER> 

4) In BASIC type 'POWER CONT <ENTER> ' 

5) Type 'CLEAR 200, 60000 <ENTER> ' 

6) Type ' CLOADM "MEMLO" <ENTER> ' 

7) Once the program loads without error, type 'CALL 61440 <ENTER> ' 

8) At the Model 100 Memory Diagnostics title page, press any key 

9) The menu will then appear on the display, Type '1' to execute the 
ROM CRC Check or type '2' to execute the RAM Check 

10) For the ROM CRC Check, the current CRC is A2D4 
New checksums can be listed here: 

11) After completing the tests, press <CTRLXBREAK> and the reset 
switch simultaneously 

12) Repeat steps 3-11 above using the following changes for steps 5, 
6 and 7 : 

5) Type 'CLEAR 200, 5 9000 < ENTER > ' 

6) Type 'CLOADM "MEMHI" <ENTER> ' 

7) Once the program loads without error, type 'CALL 59136 
< ENTER > ' 



The Programs 

Model 100 Memory Diagnostics consists of two programs called MEMLO and 
MEMHI. The only functional difference between the programs is the 
area of RAM which they test. The only visible difference is in the 
version numbers; MEMLO is version 1.0.0 LO and MEMHI is version 1.0.0 
HI. MEMLO checks RAM beginning at the first available RAM location 
and ending at EFFF hex. MEMHI checks RAM beginning at EB76 hex and 
ending at F5F0 hex. Note that F5F1 hex through FFFF hex is not 
checked under this software. 

The following directions apply to either program, except where 
specified . 



IMPORTANT NOTE: ALL USER FILES WILL BE DELETED FROM THE MODEL 100 
MEMORY BY THE USE OF THESE PROGRAMS. IF THERE ARE ANY FILES THAT YOU 
WISH TO RETAIN, SAVE THEM FIRST ! ! ! ! . 



Loading and Executing 

1) Prepare cassette player and cassette tape " 

2) Power up the Model 100 

3) At the Model 100 power-up menu type 'BASIC <ENTER> ' OR position 
the cursor over the word 'BASIC and press <ENTER> 

4) In BASIC type 'POWER CONT <ENTER> ' 

5) Type 'CLEAR 200, 59000 <ENTER> ' 

6) Type * CLOADM "MEMLO" <ENTER>' to load MEMLO or type ' CLOADM 
"MEMHI" <ENTER>' to load MEMHI 

7) Once the program loads without error, type 'CALL 61440 <ENTER> ' 
to execute MEMLO or type 'CALL 59136 <ENTER> ' to execute MEMHI 



The Menu 

After executing the program program, the screen will display the 
program name, the program version number, the copyright date, and the 
amount of RAM available to the system. To proceed to the menu, press 
any key. At this point press '1' to perform the ROM CRC Check or 
press '2' to perform the RAM Check. You can exit the program at any 
time by pressing <CTRLXBREAK> and the reset switch simultaneously. 



ROM CRC Check 

After pressing the '1' key at the menu, the program will display 
'CRC =' and pause for a few seconds before displaying the ROM CRC. 
Once the test is complete, press any key to return to the menu. 

The CRC generated by this test is a simple 16 bit sum of all the bytes 
of ROM (from 0000 hex through 7FFF hex). 

The current ROM CRC value is A2D4 

New Checksums can be listed here: 



RAM Check 

After selecting option '2' from the menu, the program will clear the 
screen and display the RAM test as they are executed. There are three 

tests that are performed, the first of which is the 00 Fill. This 
test fills the section of RAM being tested with zeros and then read 
the RAM to make sure that the zeros were written. The second test is 
the FF Fill and operates in the same manner, except that it uses FF 
hex to fill memory instead of zero. 

The last test is the Rotating fill. This tests fills RAM with a 
sequential pattern from 01-FF hex until all RAM that is being tested 
is filled and the checks to see that the same sequence is read back 
from the RAM. It makes 255 passes, each pass beginning the sequence 
with a different value. (The first pass will begin the sequence with 
1,2,3,4,5...; The second pass will begin the sequence with 
2,3,4,5,6..., etc. ) . 

The following table shows the amount of time that each RAM Check will 
take for each RAM size available for Model 100. 



Program 


8K 


16K 


24K 


32K 


MEMLO 


2 . 1 min. 


4 . 2 min. 


6 . 3 min . 


9 . 4 min . 


MEMHI 


3 min. 


3 min. 


3 min. 


3 min. 



All times are approximate 



MODEL 100 BASIC Test 



Overview 

The Model 100 BASIC test program is an automated test that 
automatically test each subsection of the machine except for the 
expansion buss and the RAM. Use the MEMLO and MEMHI programs for RAM 
test. Most of the test are in BASIC and are simple to modify or to 
write into another test program for exersizing a specific area of the 
machine. Some of the test are machine code routines that are called 
from the BASIC program. 

Loading 

Turn on the power to the Model 100 and make sure the standard menu is 
displayed. BASIC should be in the top left corner of the menu. Use 
the arrow keys to insure the the cursor is positioned over the word 
BASIC and hit the <ENTER> key. 

If the main menu is NOT displayed, try pressing <F8>. This should 
return you to the menu. If not, you may have to press <RESET> on the 
back panel of the machine. 

Once in BASIC, prepare the MODEL 100 TEST TAPE and a tape recorder. 
Type CLOAD<ENTER> and the program should begin loading. If the 
machine finds the program, it will display: 

Found: TEST 
OK 

DO NOT REMOVE THE CASSETTE FROM THE PLAYER. If there were any 

errors, try adjusting the volume control. 

After loading successfully, type RUN<ENTER> . The program will then 
load the machine code routines from the cassette. At the completion 
of loading, a menu will appear and the cassette may now be removed. 



Running the test 

The menu will look, like the following: 

1-ALL 5 -SOUND TEST 

2-CHECK SUM 6-RS232C TEST 

3-LCD TEST 7-PRINTER TEST 

4-CLOCK TEST 8-BAR CODE READER 

0-ABORT (RETURN TO BASIC) 



Hitting the <1> key will cause all the test to executed sequent ial 1 v . 
As a general rule, hitting the <SPACE 3AR> will exit most test and 
continue with the next test in the AUTO mode. 

If you do not have all the equipment necessary for an AUTO test, you 
may want to run the tests individually. 

CHECK SUM If! 

This test does a quick check sum of the ROM. If in doubt, or if there 
is a ROM revision, use the check sum test on the MEMHI / MEMLO tape. 

LCD TEST If 3 

This test puts patterns into the LCD display memory. This just 
verifies that every dot can be turned on. If in doubt, try directly 
addressing a point on the screen with your own BASIC program. 

CLOCK TEST //4 

Displays the time and beeps every second. Hit the <SPACE BAR> to exit 

SOUND TEST 115 

This test produces notes in an ascending scale and then a descending 
scale on the buzzer. 

RS232C TEST Ifb 

This checks the RS232C port by looping at 19200, 9600, and 75 Baud. 
The loopback connector must be installed. If there is no RTS-CTS 
loop, the test will halt, the buzzer will sound, and a message: 
RTS-CTS NG! Will be displayed. It there is a DATA error, The baud 
rate at which the test failed will be displayed. Hit the <SPACE 3AR> 
to exit. 

The loopback connector is a DB-25 connector with pins 2-3 connected 
(the data) and pins 4-5 connected (RTS-CTS) 



PRINTER TEST C/7 



Tais senas a. stn 
OXLIME and READY. 



:haraeters to the printer, 



Printer must be 



BAR CODE READER #8 

This test displays number patterns that the bar code reader is being 
swept over properly. Make sure that the wand is moved smoothly over 
the pattern and check, the number displayed with what the pattern 
should be.