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TECHNICAL MEMORANDUM (NASA) 87
MODIFIED TIMING MODULE FOR LORAN-C RECEIVER
Hardware documeatation Is provided for Che modified
Loran-C Clmlng module, which uses InterrupC-driven
software coaCrol in determining loop sample times.
Computer loading is reduced by eliminating polled
operation of the timing loop.
(Ohio Oniv.) 11
HC A02/HF A01
Robert W. Lllley
Avionics Engineering Center
Department of Electrical and Computer Engineering
Athens , Ohio 45701
(Revised August 1983)
NASA Langley Research Center
Hampton, Va 23665
(Contract NSR 36-009-017)
The original design for the Ohio University Loran-C receiver featured
a software /hardware locked-loop signal processor, based upon the Mostek
50395 timing integrated circuit (IC) [1,2]. This IC provides a six-digit
binary-coded decimal (BCD) counter and a BCD register compared to generate
an output pulse when the register and counter contents are equal. Operated
at 1 MHz, this timing circuit permits microcomputer-selected sample times
to be precisely set within a one-second counter interval, with a resolution
of one microsecond.
In order to accomplish the data load for the IC register, the computer
must detect that the IC digit scan oscillator has selected the appropriate
4-bit BCD digit, and then strobe the new digit data into the register. The
IC design requires a scan oscillator frequency of no higher than 20 kHz,
which places a lower limit on the time required to load all six digits. In
practice, the complete register load requires approximately 500 microse-
The original receiver design makes all six IC digit strobe signals
available to the microcomputer, which then strobes the new digit data into
the register after detecting the presence of the appropriate strobe signal*
This operation must take place in order to preset the next loop sample
time, triggered by the EQUAL pulse from the Mostek IC. Therefore, the
register load must be performed between each Loran-C pulse. The technique
of polling the digit strobe lines to detect the next digit to be loaded
requires full attention from the microcomputer, delaying background pro-
The modified circuit described in this technical memorandum combines
all six-digit strobes into one master strobe signal, which appears as an
interrupt to the microcomputer. Therefore, once a digit is loaded into the
IC register, the computer is free to process background code while awaiting
the next digit strobe interrupt. See figure 1 for a block diagram.
This modification is required, to permit the single processor (a MOS
Technology 6502) to perform ^1 required computations for the entire
Loran-C process. Expansion of the receiver from a three-station tracker to
full five-station operation would cause over 20 percent of processor power
to be lost to the strobe polling operation, causing a reduction in naviga-
tion data output rates, and a reduction in the number of pilot-oriented
features which could be added using the single processor.
Full hardware documentation is provided in this document for the cir-
cuit card implementing the Loran-C timing loop, and the receiver event-mark
and ra-track functions. This documentation is to be combined with overall
receiver drawings to form the as-built record for this device. Computer
software to support this module is integrated with the remainder of the
receiver software, in the LORFROM program.
r. . , 3 ' ■
OF POOR ; '<
Figure 1. Block Diagram, Lorar>-C Timing Module.
II. CIRCUIT DESCRIPTION
Figure 2 shows the complete logic diagram for the Loran-C timing
module. To Che far left are signal descriptors for Che system computer, an
MA.I SuperJolt based upon the MOS Technology 6502 with 6320 peripheral
Interface adapter (PIA). All connections, except for CLOCK and IRQ, are
made through the 6520 PIA. Figure 3 gives a summary of PIA pin assignments,
useful In software design and coding. The Mostek 50395 chip description Is
given as figure 4, and pinouts are shown In figure 5.
Referring to figure 2, note that seven lines provide data and control
signals to the Mostek IC (U3). All these signals are output by the com-
puter as TTL-compatlble signals, and must be changed to the 12-volt MOS
specification required by U3. This conversion Is performed In open-
collector drivers U1 and U2, pulled up to 12v through 680-ohm resistors.
These lines carry the four data b its f or register digits Ra, Rb, Rc and Rd.
The LR (Load Register) strobe and SET (Set digit counter to most-
significant digit) signals.
The timing chip U3 Is wired for free-running counter, counting up, and
is driven by the CLOCK, which is a buffered version of the main microcom-
puter clock (a temperature-compensated crystal oscillator). The scan
oscillator which generates the digit strobes to Indicate the load window
for each register digit Is set to 20 kHz using the capacitor at pin 21.
Digit strobes, one for each register BCD digit, are output by U3 at pins 24
through 29 and are immediately NORed by U6. Note that this 8-lnput NOR Is
a CMOS chip running at 12v to eliminate the need for the six voltage divi-
ders used In the previous design to return the MOS levels from U3 to TTL
levels. The combined digit strobe Is then returned to TTL levels. Inverted
by U7 and applied as a clock to the U8 D flip-flop lutch.
The Q output of the U8 latch Is high after receipt of a digit strobe,
which causes the output of the U7 Interrupt combiner gate to go low,
causing an Interrupt (IRQ) condition at edge connector pin 19. Once the
computer program has serviced this Int errupt , the digit strobe Interrupt
latch U8 Is cleared by a low signal at CLRD, or pin 12. The computer soft-
ware simply counts Interrupts from the digit strobe latch, recognizing that
the digit strobes appear In fixed order from digit one through six.
Appropriate signals are then placed on the Ra - Rd lines and the U3 control
lines to achieve the full register load.
Once the register Is fully lo aded , the digit strobe Interrupts are
disabled by placing a low level on CLRD, forcing the U8 latch Into reset
conditio n. Th e U5 Loran-C interrupt and data latches are then enabled by
bringing CLRP high. When the free running counter In U3 reaches the
register value Just loaded, U3 Issues an EQUAL pulse for one clock period
(one ps) which clocks the U5 latches. The output of the IRQ combiner gate
in U7 goes low since the Q output of the U5 Inte rrupt latch always goes
high upon clocking. An interrupt Is signaled at IRQ to the computer. LDAT,
latched by the U5 Loran-C latch, ass umes t he Instantaneous value of the
Loran-C digital waveform received at LRIN from the receiver front-end
- 3 -
or!g;!VA*, r; :
I Z I I OF POOR QUALITY
Z Z Z
T pin 38,39 N/C
aK^Ld *D "c *8 ''a
u3 - MOSTEK 50395
7 |W ? +5V
uS 2 , J— , 2^
1.1k (H-1 1
y ] 70p,«:
. 01 " inofc .
(H-1) R-l 6
Figure 2. Loran-C Timing Board for Updated RF Board Only.
OF POOR QUALITY
- 5 '
- 6 -
ORIGINAL PAGu ?3
OF POOR QUALITY
BCD IN Cg
Figure 5. MOSTEK 503V5 Pinouts,
- 7 -
module. Note that LRIN is processed by U4 to set a pulse width o£ approxi-
mately 70 ys. before It Is sampled. This pulse width Is necessary to pro-
vide a guard time after the leading pulse edge to permit successful pulse
tracking, and to minimize Initial search time. Since the various front-end
processors designed to date have presented various pulse widths, this U4
mono-stable multivibrator has been provided to equalize the waveform before
The remainder of the circuit, U12, deals with receiver features
Included for evaluation. The event latch Is driven by a front-panel push-
button to place on the receiver output tape a unique mark so output data
may be correlated with flight events. The retrack latch, also operated by
pushbutton, signals the computer that the operator wishes to restart the
Loran-C search process. To minimize contact bounce, these latches are con-
figured to operate on the pushbutton release cycle.
Once the computer program has serviced the Loran-C sampl e interrupt
thus generated, the U5 latches are disab led by a ..ow at CLRP and the digit
strobe Interrupt Is enabled by a high on CLRD. Another register load
In this manner, successive samples may be taken of the Loran-C Input
waveform at times which are precisely controlled by the microcomputer. The
prograsimer may now select algorithms for detecting received Loran-C chains
and stations by varying the sample time and observing the result at LDAT.
The module pictorial appears In figure 6, giving placement of ICs
and other major components.
- 8 -
Low clears retrack & event latches.
High indicates user event mark, cleared by CLRL.
High indicates user retrack, cleared by CLRL.
Input Loran-C pulses from front-end.
TTL, open-collector, pulled up to 5V on this board
4-bit BCD digit load for U3 register.
Load 50395 (U3) Register strobe.
Set U3 to MSD for data load.
1 ^filz clock, from microcomputer.
Low clears digit strobe IRQ latch.
Low clears Loran data latch.
Loran data - loop sample output.
Combined IRQ from loop and digit strobes.
Equal pulse, for monitoring.
Figure 6. Pictorial and Signal Glossary.
- 9 -
 Lillay, R. W. and D. L. McCall, "A l>oran**C Prototype Navigation
Receivar for General Aviation,” paper (No. 81-2329), preaented at the
AlAA/li7.E Fourth Digital Avlonlca Syatema Conference, November 1981.
 Lllley, R. W. and D. L. McCall, "A Loran-C Prototype Navigation
Receiver for General Aviation," (NASA) Technical Memorandum 80,
Avlonlca Engineering Center, Department of Electrical and Computer
Engineering, Ohio Unlveralty, Auguat 1981.
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