Skip to main content

Full text of "cogar :: S-100-2 Cogar System 4 System Programmers Manual Dec72"

See other formats


SYSTEM A® 



PROGRAMMER'S 



MANUAL 



PROGRAMMER'S REFERENCE MANUAL 

This publication is designed to be used as a reference manual by 
programmers using the Cogar System 4® Processor. The manual is divided 
into three parts. Part I defines the unique features of the machine 
which are relative to the programmer, as well as providing a machine 
specification summary. Part II provides general information on the usage 
of each group of instructions in the instruction set repertoire. Part III 
defines each instruction in detail, and provides the timing and an example 
of how each instruction may be used in context with surrounding instructions, 
in both Source and Object coding. A summation of all the instructions in 
the repertoire is contained on the Cogar System 4 Instruction Reference 
Card. 

Other publications relating to software for the Cogar System 4 are: 

Batch Assembler Operating Instructions ; which contains the step-by- 
step instructions for creating a self-loading program tape, which 
has been assembled as part of an Object-String background. 

Standard Cogar Library Functions ; which contains descriptions and 
operating instructions for the Language Base Library and the I/O 
Libraries. 

The programmer should be familiar with the content and design objectives 
of the above documents in order to make full use of the capabilities of 
the Cogar System 4 Processor. 



COGAR SYSTEM 4 IS A REGISTERED 
TRADEMARK OF COGAR CORPORATION 



PROGRAMMER'S REFERENCE MANUAL 

Table of Contents 

Paai 

COGAR INSTRUCTION DESCRIPTION INDEX c. 

SPECIFICATION SUMMARY e. 

SECTION I. GENERAL 

System Features 1 

Language Features 1 

lOS Features 2 

Assembl er Features 2 

Display 3 

Keyboard 4 

Cartridge Tapes 4 

Operator Control s 7 

SECTION II. INSTRUCTION USAGE 

Subroutine Control 8 

Registers 11 

Addressing 11 

Symbol s ; 13 

DPL-1 Instruction Classes 14 

DPL Punctuation 16 

Literal Notations 16 

Standard C4 Program Record (Mini -Tape) 17 

Subroutine Relocatability 19 

Tape I/O Character Queue 19 

SECTION III. INSTRUCTION DESCRIPTIONS 

General 21 

Class j9: Jump 22 

Class 1: Branch 26 

Class 2 : Transfer 46 

Class 2: Ordinary Arithmetic 50 

Class 3: Boolean Arithmetic 54 

Class 3: Compare 60 

Group 1 : I/O Functions 62 

Group 2 : Data Modify 68 

Group 3 : Compay^e 73 

Group 3: Select 74 

Group 4: Control Functions 81 

Notations for DPL-3B Constants 85 

DPL-1 Pseudo Instructions 86 

DPL-1 Branch and I/O 95 

APPENDIX 1 01 



COGAR INSTRUCTION SET INDEX 



Mnemonic Name 

ADA Add to Accumulator 

ADD Add Storage to Storage 

ADX Add to Index Register 

ANA Logical 'AND' to Accumulator •• 

BRE Branch on Equal • • 

BRH Branch on High 

BRL Branch on Low • • • 

BRU • • • • Branch Unconditional 

COM • • • • Compare Storage to Storage • 

CPA Compare Accumulator 

CPI Clear Processor Interrupt ••• •' 

CPX Compare Index Regi ster 

DIV •••• Divide 

DPI '='' Disable Processor Interrupt 

EJT Eject to Top of Form 

END End Segment •••••• • • • • • 

ENT •••• Enter Control Function - 

EPI Enabl e Processor Interrupt • • 

EQU • • • • Equate Symbol • 

ERA Exclusive 'OR' to Accumulator 

EXB • • • ' Exit and Branch 

EXU Exit Unconditional 

GET •••• Get Data (Read) 

I0C-C#3 ••• I/O Keyboard ••••• 

IOC-C#N ••• I/O Mini-Tape • 

I0C-C#4 • • • Display Control 

IRA •••• Inclusive 'OR' to Accumulator 

LDA •••• Load Accumulator 

LDX • • • • Load Index Regi ster • • 

LIA Load Instruction Address • 

LPS Load Processor Status -.••••.. 

LSW • • • • Load Sense Swi tches • • • 

MOV Move Storage to Storage • • 

MUL •••• Multiply • 

ORG Origin Location Counter 

OVL Overlay 

PCL-PRT ••• Line Printer Control 

PCL-TYP • • • Typewriter Control 

PUT Put Data (Write) 

SAC Set Arithmetic Condition — • 

SAN Shift & Logical 'AND' to Accumulator 

SBE Stack and Branch on Equal ' 

SBH Stack arM Branch on High 



Format 



Page 



DPL-1 •• 


• 50 


DPL-2 •• 


■ 69 


DPL-1 • • 


• 51 


DPL-1 •• 


• 54 


DPL-1 • • 


• 27 


DPL-1 •• 


• 28 


DPL-1 •• 


• 29 


DPL-1 •• 


• 25 


DPL-2 •• 


• 73 


DPL-1 •• 


• 60 


DPL-1 • • 


• 45 


DPL-1 • • 


• 61 


DPL-2 • • 


• 72 


DPL-1 •• 


42 


DPL-1 •• 


94 


DPL-1 •• 


• 93 


DPL-1 ••• 


88 


DPL-1 •• 


43 


DPL-1 •• 


■ 90 


DPL-1 •• 


• 56 


DPL-1 ••• 


34 


DPL-1 ••• 


• 35 


DPL-2 ••' 


62 


DPL-1 ••• 


98 


DPL-1 ••■ 


95 


DPL-1 •• 


• 99 


DPL-1 ••• 


58 


DPL-1 ••■ 


46 


DPL-1 • • • 


47 


DPL-1 •• 


■ 48 


DPL-1 •• 


• 41 


DPL-1 • • ■ 


40 


DPL-2 • • • 


68 


DPL-2 ••■ 


71 


DPL-1 •• 


86 


DPL-1 •• 


91 


DPL-2 •• 


84 


DPL-2 •• 


• 83 


DPL-2 •• 


• 64 


DPL-1 • • 


- 39 


DPL-1 •• 


• 55 


DPL-1 •• 


• 31 


DPL-1 •• 


' 32 



COGAR INSTRUCTION SET INDEX 



Mnemonic Name Format Page 

SBL Stack and Branch on Low DPL-1 ••• 33 

SBU Stack and Branch Unconditional DPL-1 ... 30 

SEG Identify Segment DPL-1 .-• 87 

SEL-EQL Selcect Equal DPL-2 ... 76 

SEL-HGH .... Select High DPL-2 ... 77 

SEL-LOW Select Low DPL-2 ... 75 

SEL-NEQ Select Not Equal DPL-2 ... 79 

SEL-NH6 .... Select Not High DPL-2 ... 78 

SEL-NLW Select Not Low DPL-2 ... 80 

SEL-UNC Select Unconditional DPL-2 ... 74 

SER Shift and 'EOR' Accumulator DPL-1 ... 57 

SET Set Page DPL-2 ... 81 

SIR Shift and 'lOR' Accumulator DPL-1 ... 59 

SMC Set Memory Control DPL-1 ... 37 

SMS Set Memory Section DPL-1 ... 36 

SSC Set Memory Section and Control DPL-1 ... 38 

STA Store Accumul ator DPL-1 ... 49 

SUA Subtract from Accumulator DPL-1 ... 52 

SUB Subtract Storage to Storage DPL-2 ... 70 

SUX Subtract from Index Register DPL-1 ... 53 

TCL ...... Tape Control Command DPL-2 ... 82 

TLJ Test Literal and Jump DPL-1 ... 22 

TLX Test Literal and Exit DPL-1 ... 24 

TMJ Test Mask and Jump DPL-1 ... 23 

TMX Test Mask and Exit DPL-1 ... 25 

USE Use External Source Segment DPL-1 ... 92 



SPECIFICATION SUMMARY 



Size 



10 inches high (25 cm) 
18.5 inches wide (47 cm) 
24 inches deep (60 cm) 



Weight 


60 pounds (27 kg) 


Power 


115 VAC ±10%, 220 VAC 




48 to 62 Hz 




2.5 amps average 



:10% 



Environment 10% to 80% relative humidity without 

condensation 
60°F to 95°F Operating Temperature 
0°F to 150°F Storage Temperature 

Ventilation 30 cubic feet per minute air flow 

4 inches air flow clearance on all sides 
1000 BTU per hour heat dissipation 

Processor 45 instruction types plus I/O 

3 to 6 [jls Instruction cycle time 
1 Accumulator 

7 Index Registers per 2K of memory 
16 Member Instruction Address Stack 
Hardware Bootstrap Loader 



IVIemory 



i6K bytes capacity 
Random Access Read/Write 
Non-Destructive Read-Out 
Monolithic Semiconductor 



Keyboard Software configurable 

Hall effect keys 
N-Key rollover capability 
Audible cue 

Visual Display 5 inch CRT 

4 or 8 line display, with interleave 

capability 
32 characters per line 
5x8 matrix under program control 

Tape System 10 ips write tape speed 

1600 bpi density, phase modulation 
2 mechanically independent transports 
Read after Write, CRC, phase checks 
Automatic threading 
Write interlock switch 
Rewind: 40 ips rewind and forward or 
rewind search 



Tape Cartridges 



100 ft. computer grade tape 

900 records of 136 characters each 

Write/Erase Protection 



SECTION I. GENERAL 



1 . SYSTEM FEATURES 



The Cogar System 4 is a compact, operator-oriented, general purpose data 
processing system. It combines, in a single unit, an input keyboard, 
magnetic tape transports, CRT visual display, I/O interface, solid state 
memory and a versatile processor. The System architecture closely in- 
tegrates the functioning of all sub-systems and features transparency of 
graphics and coding. All major system functions are under program control 
The processor structure is designed to optimize byte handling and inter- 
pretation, and provides automatic threading of recursive subroutines. 

The nature of the processor design and its relationship to the other 
system components make the Cogar 4 heavily dependent on software. This 
means that the system is uniquely flexible in the jobs it can perform and 
is especially adaptable for various operator and interfact applications. 
It also means that software is an essential ingredient that must be as 
fully and carefully integrated into the System as the other components. 

The Cogar 4 is a binary machine using 8-bit bytes in its memory organ- 
ization and most hardware data paths. Its operations are highly memory 
oriented and are designed to take advantage of the performance of its 
semiconductor storage. 

2. LANGUAGE FEATURES 

The language base for the Cogar System 4 is flexible, easy to learn and 
use, yet permits the programmer to take full advantage of the System 4's 
power. The Cogar Language Base is comprised of a comprehensive set of 
"Pre-packaged" functions to facilitate modular program construction. 
The Cogar Assembler provides linkage between these functions and the 
specialized routines necessary to a given application. 

Programs are written and assembled in symbolic notation, with the 
final stage of the assembly effecting a merge of the specialized 
routines and the pre-packaged background functions. This method of 
assembly allows easy and rapid modification or correction of programs 
or the re-configuration of a program to accomodate different peripheral 
devices or the selection of a new or modified graphic set, or key- 
board configuration. 



The DPL-1 instructions for the Cogar 4 are machine level instructions 
that are directly executed while the DPL-2 commands are executed inter- 
pretively by a resident software monitor. DPL-1 instructions are two 
bytes long and must occur on even byte boundaries. DPL-2 commands are 
four bytes long and should also occur on even boundaries. When DPL-1 and 
DPL-2 are intermixed, a new language is formed called DPL-3. The batch 
assembler for DPL-3 is known as DPL-3B. A subset of the DPL-2 monitor 
that handles I/O function is known as the I/O Supervisor or lOS. This 
manual describes DPL-1 and lOS as assembled on DPL-3B. 

In order to be able to tailor the system for optimum use with particular 
applications, many device functions have been designed for program control. 
The codes generated by the keyboard, for example, correspond not to the 
key character , but to the key location . A translate table is located in 
the processor memory and is used to convert a key code into a character 
code. The user program can easily modify the translate table and can thus 
produce any desired code for any key. 

The visual display uses a 5 x 8 dot matrix to form each display character 
and has cursor control with each character. The dot matrix is stored in 
the processor memory so that any possible 5 x 8 combination may be 
generated by the user program to be displayed for any character code. 
The standard dot pattern uses a 5 x 7 dot matrix to form the desired 
character. This provides for a space between the character and the cursor. 

The Cogar 4 provides an unusually efficient subroutine control mechanism 
that is easy to use, yet offers powerful capabilities. 

3. lOS FEATURES 

Cogar has designed an Input/Output Supervisor to provide easy access for 
the user to a set of standard I/O routines. The flexibility of the system 
peripheral device operations is still available for special applications, 
but most I/O operations can be accommodated by the I/O Supervisor. lOS 
is a memory resident software monitor that is accessed using the ENT:IOS 
pseudo command. It performs a complete single operation and automatically 
returns control to the user program. 

4. ASSEMBLER FEATURES 

Computer programs must always eventually be expressed in machine language. 
The machine only understands binary numbers and programs so expressed are 
called Object programs. There are some circumstances when it is desirable 
for the system user to be able to write Object instructions directly. 
Most of the time, however, it is much more efficient to use an instruction 
language that is easily interpreted by the user. The mnemonic expressions 
used to represent the Object language form a Symbolic language. An 
Assembler is a program that translates a Symbolic program into an Object 
program. 



Since the programmer spends much of his time communicating with the 
Assembler, it is useful to supply commands that control the operations 
of the Assembler itself. These commands are called Pseudo instructions 
and normally do not result in any Object coding. Another class of Pseudo 
instructions used in the Cogar 4 Assembler to control executive monitor 
operations does generate Object coding. 

The Cogar Batch Assembler, known as DPL-3B, provides many features de- 
signed to streamline the programming process. Comments may be inserted 
in the Symbolic program to help identify the operations taking place. 
Instructions, data, constants and locations may all be referred to 
symbolically. Diagnostics are generated to help identify errors in the 
program. Editing, display and printing of both Object and Symbolic 
programs are available as part of the DPL-3B package. 

The Cogar Assembler also handles the appropriate translations, controls, 
and linkages for the lOS and DPL-3 monitors. 

DISPLAY 

Keyboard Transparency : 

The Cogar System 4 is designed to provide code hardware transparency. 
Any keyboard character may be automatically translated to any desired 
code and any dot matrix pattern may be displayed for a given character 
code. These functions are directly under software control and are thus 
available to the programmer. 

Selective Blanking : 

The commonly used internal key and character codes in standard Cogar 
software are shown in Table 1. Notice that the high order octal digit 
is always zero. This digit corresponds to the bits six and seven of 
the character byte. These two bits are used to provide added features 
for the CRT display. If a 1 is inserted in bit 7 (changing the code for 
A, for example, from 015 to 215) of a character in the CRT buffer area, 
that character will be displayed on the screen as a blank. 

Cursor Underscore : 

If a 1 is inserted in bit 6 (changing the code for A, for example, from 
015 to 115) of a character in the CRT buffer area, that character may be 
displayed with an underline. The underline feature must be enabled by 
adding octal 1 to the second octal digit of the display base enable func- 
tion codes. Thus, to permit underlines in display base 2 the normal 
display enable of IOC, C#3; 023 becomes IOC, C#4; 033. The underline 
feature is a convenient means of providing a cursor. 



Selective Interlace: 



Dann 



fl 9Q 
V ■ ■ ■ 



■'jr oco J 






Memory areas displayed are program selectable from any one of 16 memory 
Pages (256 bytes per Page) 3 with provision for half 
play only or for selective interlace of half-Pages. 

KEYBOARD 

When a character key is depressed on the keyboard after a Transfer Byte 
IOC, it causes a key code to be loaded into the accumulator. The NUM 
(numeric), CTRL (control) and ALPHA (alphabetic) are three special keys 
that act on bits 6 and 7 of the key code for any key pressed while one 
of them is held down. NUM turns on bit 6, CTRL turns on bit 7, and 
ALPHA turns on both 6 and 7. If none of the special keys are activated, 
bits 6 and 7 remain off. The following procedure may be used to translate 
the key code residing in the accumulator into a character code. 



The 6th and 7th 



are taken care of as follows: 



6th bit on: 
7th bit on: 

6th and 7th bits on: 



do not change 

turn 7th bit off (reset after translation, if 
desired). 

turn 6th and 7th bits off (reset after trans- 
lation, if desired). 



b. Store the result in an index register 

c. Add to the index register the displacement within the page of the 
beginning of the translate table. The standard translate table in 
page 05, for example, starts at location decimal 064, therefore, add 
decimal 064 to the value of the index register containing the key 
code before translation. 

d. Load the Accumulator using indexed addressing and the page where 
the translate table resides. The Accumulator now contains the 
character code for the key that was depressed. The translate table 
may be designed by the user to supply any desired 8 bit character 
code including ASCII, EBCDIC, etc. 

CARTRIDGE TAPES 



The resident software I/O Supervisor provides for the actual reading, 
writing and tape positioning of the Mini-Tape. The user will often want 
to test the status of the tape drives for his own purposes. For example, 
to check the presence of a cartridge on a particular tape drive, first 
execute a Status instruction (IOC, C#N; 016), then test with a mask of 
020 (TMJ, +NN; OCT:020). If the condition is satisfied, the cartridge 
is not present. Any of the status byte conditions may be tested by first 
loading the status of the device in question into the accumulator, and 
then testing it against the literal mask specified. 







00 01 02 03 


04 05 06 07 10 


^ 




-SCRATCH AREA- 
13 14 15 




^ 


OCf 


lUENCE STORAGE AREA 
21 22 23 24 








-^ 






— 


START BOOTSTRAP LOAD 




11 12 


16 17 


20 


25 26 27 


30 31 


32 33 34 


35 36 37 


40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57* 60 ,61 62 63 64 65 ,66 67' 70 71 72 73 74 75 76 77 ( 






000 
100 
200 
300 
000 
100 

200 
300 
000 
100 
200 
300 
000 
100 
200 
300 




XR1 


XR2 


XR3 


XR4 


XR5 


XR6 


XR7 


CRC 


1 


2 


3 


4 


5 


6 


7 


































SP0 


SPl 


SP2 


SP3 


SP4 


SP5 


SP6 


1 
SP7 


SP8 

i 


SP9 


SPIO 


SP11 

, [ , 


SPl 2 


SP13 


SP14 

1 


SP15 


PAGE 00 






































































































































































END 


BOOT 


STRAP 


LOAD 
















































































































' 












































































































































































r" 


































































PAGE 01 
































































































































































































































































































































[. 








































































* 1 


m F 


R06R 


M ST 


iRTS 


























































































































































































































































PAGE 02 








































































































































































































































































* 1 


(TERR 


UPT 






























































































































































































































































PAGE 03 
























































































r- SPARE 

/ 1 ' 




























































































































Jlj 


/ ^ 












































CRT m 

DOT PATTERN 


000 
100 
200 
300 
000 


SP 
000 


oTo 


010 



070 


4 


2 
162 


3 
042 


4 
030 


5 
047 


6 
074 


7 
141 



066 


9 
106 


,?4 


177 


C 
076 


D 
177 


E 
177 


F 
177 


G 
076 


H 
177 


1 
000 


J 
060 


K 
177 


L 
177 


177 


N 
177 


G 
177 


P 
177 


Q 
07? 


177 


s 

042 


T 
001 


U 
007 


V 
007 


W 
177 


X 
143 


Y 
007' 


Z 
141 


000 


# 
074 


@ 
1)14 


flin 


% 
143 


$ 

044 


* 
052 


000 


ODD 


> 

101 


/ 
040 


034 


) 
000 


7 

000 


034 


024 


ODD 


1 
ODD 


ODD 


000 


000 


100 


002 


& 

060 


1 
000 




000 


010 


010 


101 


102 


111 


101 


024 


1^5 


112 


021 


111 


111 


022 


111 


101 


101 


111 


Oil 


101 


010 


101 


100 


010 


100 


002 


006 


101 


Oil 


101 


Oil 


105 


001 


100 


030 


040 


024 


010 


121 


130 


167 


062 


010 


023 


052 


034 


140 


DID 


042 


020 


042 


000 


002' 


042 


024 


007 


ODD 


007 


000 


000 


100 


002 


116 


000 


PAGE 04 


000 


010 


170 


101 


177 


111 


111 


022 


105' 


111 


Oil 


111 


111 


021 


111 


101 


101 


111 


Oil 


101 


010 


177 


100 


024 


100 


014 


010 


101 


Oil 


121 


031 


111 


177 


100 


140 


030 


010 


170 


111 


070 


000 


052 


010 


010 


177 


076 


140 


024 


024 


010 


101 


101 


001 


177 


024 


ODD 


137' 


007 


066 


133 


100 


002 


131 


177 




000 


010 


010 


101 


100 


111 


111 


177 


105 


111 


005 


111 


05 f 


022 


111 


101 


101 


101 


001 


111 


010 


101 


100 


042 


100 


002 


060 


101 


Oil 


041 


051 


12f 


001 


100 


030 


040 


024 


010 


105 


000, 


167 


072 


010 


144 


052 


034 


000 


042 


010 


004 


000 


042 


131 


042 


024 


007 


ODD 


000 


066 


073 


100 


002 


046 


177 




KEYPUNCH ^ 

TRANSLAIlE TABLE 


000 


010 


010 


076 


000 


106 


066 


020 


071 


060 


003 


066 


036 


174 


066 


042 


076 


101 


001 


171 


177 


000 


077 


101 


100 


177 


177 


177 


006 


136 


106 


042 


odi 


007 


007 


177 


143 


007 


103 


000 


024 


074 


010 


143 


022 


052 


ODD 


101 


000 


002 


000 


034 


006 


000 


024 


000 


ODD 


000 


000 


ODD 


100 


016 


120 


000 




100 
200 


000 


START 
201 


061 


% 
053 


* 
055 


< 
057 


MINUS 
206 


DUP 

297 


Q01 


/ 
0(1 


P.SEL 
212 


REL 
213 


BSR 
214 


i.O.F. 
215 


Q 
035 


W 
043 


E 
021 


R 
036 


T 
040 


Y 
045 


U 
041 


1 
025 



033 


P 
034 


BSF 
230 


L/Z 
231 


ERR ^ 
232 


000 


000 


ODD 


ODD 


A 
015 


S 
037 


D 
020 


F 
022 


G 
023 


0^. 


J 
026 


K 
027 


L 
030 


SKIP 
250 


HOME 
251 


BLK 
QOO 


Z 
046 


000 


ODD 


X 
044 


000 


C 
017 


V 
042 


B 
016 


N 
032 


M 
031 


047 


056 


COR 
267 


SPACE 
000 


EOJ 
271 














PAGE 05 


000 


^ART 
201 


050 


047 


$ 
054 


>ERI0l 
056 


MINUS 
206 


DUP 
207 


001 


1 

003 


».SEL 
212 


REL 
213 


BSR 
214 


E.0.F 
215 


002 


074 


) 
063 


065 


T 
040 


1 
077 


1 
004 


2 
005 


3 
006 


& 

076 


BSF 
230 


L/Z 
231 


ERR 
232 


000 


000 


000 


ODD 


A 
015 


> 
060 


072 


073 


075 


071 


4 
007 


5 
010 


6 
Oil 


SKIP 
250 


HOME 
251 


BLK 
000 


Z 
046 


000 


000 


? 
064 


ODD 


067 


066 


! 
070 


( 
062 


7 
012 


8 
013 


0?. 


COR 
267 


SPACE 
000 


EOJ 
271 
















300 
000 
100 
200 
300 





































































































































































































































































PA^06 








































































































































































































































































































































































































000 
100 
200 
300 


































































































































Pf GE 07 






























































■ 




























































































































































































































































.. _ . 
















1 




























1 
































01 02 03 04 



06 07 08 09 10 



12 13 



16 17 18 19 20 21 22 23 24 25 26 27 



28 29 30 31 32 33 
STACK POINTER 



34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5f 52 53 54 55 56 57 58 59 60 61 62 63 



DECIMAL NOTATION 



ou 

START 



m^ 
^ 






* 



0^ 

MINUS 



DUP 



PROG 
SELKT 



PEL 



BKSP^ 
RECORd 



END 
FILE 



-^ LOC:040 0778 



I R#1 |r#2 |R#3 I R#4| R#5| R#6 I R#7 h 

' I I ' I ' I ' I ' I ' I 



INDEX REGISTER ARRAY 
(one per section) 



^ 

^ 



32] 



a 



w 






ERROR 



W 



A 



M" 



NUM 



R 



CTRL 



D 

w 



43 



' F 



c 



u 



V 



H 



H" 







30] 

BKSP 
FIELD 



fX 



N 



K 



M 



M] 
SKl'P 



_66] 

9 



CORR 



.^ 



LEFT 
ZERO 



HOM 



EOJ 



ALPHA 



LEVEL 
LEVEL 1 
LEVEL 2 
LEVEL 3 
LEVEL 4 
LEVEL 5 
LEVEL 6 
LEVEL 7 



P05 



P06 



P07 



m 



U 



xM 



P15 



P16 
P17 



P26 



m 






P35 



P36 



P40 



P42 



P43 



P45 
P46 



P47 



P50 



P51 



P52 



P53 



P57 



P60 



P61 



P62 



PBS 



P70 



P72 



P75 



P76 



P77 



^SPACE BAR 

Figure lb. Standard Keypunch Keyboard Layout. 



SECTION SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 SECTION 8 SECTION 7 
•- 4K ^ I 



*SHADrO AREA^ OISPLAYABLE PAGES 



Figure Ic. Memory Map Layout. 



TABLE I. KEY AND CHARACTER CODES FOR COGAR 4 KEYPUNCH KEYBOARD. 



KEY 


KEY 


CHAR 


KEY 


KEY 


CHAR 


KEY 


KEY 


CHAR 


KEY 


KEY 


CHAR 


KEY KEY 


CHAR 




CODE 


CODE 




CODE 


CODE 




CODE 


CODE 




CODE 


CODE 


CODE 


CODE 


Space 070 


000 


A 


037 


015 


N 


063 


032 


9 


065 


047 


) 120 


063 


- 


010 


001 


B 


062 


016 





026 


033 


9 


103 


047 


? 156 


064 


+ 


116 


002 


C 


060 


017 


P 


027 


034 


# 


102 


050 


i 121 


065 





111 


003 


D 


041 


020 


Q 


016 


035 


(3 


002 


051 


= 161 


066 


1 


124 


004 


E 


020 


021 


R 


021 


036 


% 


003 


053 


" 160 


067 


2 


125 


005 


F 


042 


022 


S 


040 


037 


$ 


104 


054 


! 162 


070 


3 


126 


006 


G 


043 


023 


T 


022 


040 


* 


004 


055 


' 144 


071 


4 


145 


007 


H 


044 


024 


U 


024 


041 


. 


105 


056 


: 141 


072 


5 


146 


010 


I 


025 


025 


V 


061 


042 


. 


066 


056 


; 142 


073 


6 


147 


Oil 


J 


045 


026 


W 


017 


043 


< 


005 


057 


- 117 


074 


7 


164 


012 


K 


046 


027 


X 


056 


044 


> 140 


060 


-, 143 


075 


8 


165 


013 


L 


047 


030 


Y 


023 


045 


/ 


on 


061 


& 127 


076 


9 


166 


014 


M 


064 


031 


Z 


053 


046 


( 


163 


062 


1 123 


077 



CONTROL KEYS 



KEY 


KEY 
CODE 


CHAR 
CODE 


KEY 


KEY 
CODE 


CHAR 
CODE 


KEY 


KEY 
CODE 


CHAR 
CODE 


START 


001 


201 


BKSP RECORD 


014 


214 


HOM 


051 


251 


MINUS 


006 


206 


END FILE 


015 


215 


CORR 


067 


267 


DUP 


007 


207 


BKSP FIELD 


030 


230 


EOJ 


071 


271 


PROG SELECT 


012 


212 


ERROR 


032 


232 


LEFT ZERO 


031 


231 


REL 


013 


213 


SKIP 


050 


250 









Write Pin Enable 

A Write Pin Sensor in the SYSTEM 4 requires that if a tape is to be 
written on^ the write plug must be in the proper position. Otherwise, 
tape will not move and no write operation can be performed on that deck 
until a cartridge is inserted with the write pin in place. 

Physical End of Tape Sensing 

The SYSTEM 4 tape cartridges contain a reflective spot to notify the 
program that during a write operation, the Physical End of Tape is 
approaching. The user may write beyond this point if so desired. The 
Mini-tape VvTite Software function detects this condition and provides 
the tape status for the user to test. Once the EOT is detected, this 
condition remains set until a Rewind operation is initiated. 

OPERATOR CONTROLS 

A Switch Well located beneath the CRT screen contains eight sense 
switches^ a Program Load/Program Interrupt switch, and a System Reset 
switch. 

Sense Switches 

These eight toggle switches may be manually set by the user to any 
combination of eight bits. The setting of these switches may then be 
tested by the user program at selected times, to control specialized 
applications. 

Program Load/Program Interrupt Switch 

This toggle switch initiates a tape load cycle when pushed toward the 
CRT (Momentary position), or initiates a Program Interrupt when set in 
the ON position (away from the CRT screen). 

With the switch set to ON, the user program may test the condition to 
provide automatic linkage to the Interrupt Routine. Return to the point 
of interrupt will occur after the interrupt routine has been completed, 
and an Exit instruction to the Stack Level established by the interrupt 
has been executed. 

System Reset Switch 

When this push button switch is pressed, a System Reset pulse is 
generated which resets the Stack Pointer to Stack Level 1 and forces 
the instruction address to P02-000 where processing is then initiated. 



SECTION II. INSTRUCTION USAGE 



SUBROUTINE CONTROL : 

The Instruction Address Stack (IAS) is located in memory and consists of 
sixteen Instruction Address Words (lAW) of two bytes each. Access to the 
Stack is under control of a four-bit register called the Stack Pointer. 
The current instruction address is contained in the lAW indicated by the 
Stack Pointer. 

During sequential instruction operations, the Instruction Address is re- 
trieved from the lAW, used to locate the current instruction, incremented 
by two, and inserted back into the I AW. For branch operations, a new 
Instruction Address is inserted into the current lAW and execution con- 
tinues with the new address. 

To enter a subroutine, the Stack Pointer is incremented so that it now 
points to a new lAW location and the subroutine address is inserted in the 
Stack as the new lAW. Normal sequential operation then proceeds. Note 
that the content of the previous lAW has not been disturbed and may be 
returned to by simply decrementing the Stack Pointer with an Exit instruc- 
tion. Thus it is not necessary to provide space in the sub-routine for 
return address storage. If more than 16 levels of stack and branching 
has occured an automatic wrap-around to stack level 1 will be initiated. 

Figure 2 is a diagram of the IAS and shows the actual octal locations of 
the stack bytes in page JQJ9. Assume that the Stack Pointer is indicating 
lAWl as the location of the current Instruction Address. Sequential or 
Branch operations of the mainline program change the contents of lAWl but 
do not affect the Stack Pointer. When the mainline program encounters 
a Stack and Branch instruction, however, the Stack Pointer is incremented 
to indicate IAW2 and the Branch address is inserted into IAW2. If the 
Stack and Branch instruction was located at Page 10, location 52, lAWl 
will now contain the coding to indicate Page 10, location 52, and IAW2 
will become the current location counter. The subroutine indicated by 
IAW2 may reference other subroutines in which case IAW3, IAW4, etc. may 
be used. When the IAW2 subroutine is finished, an Exit instruction is 
executed which simply decrements the Stack Pointer and returns program 
control to lAWl at the instruction following the original Stack and 
Branch. If the exit instruction was located at Page 13, location 220, 
IAW2 will be left with the coding for Page 13, location 220. A subsequent 
mainline Stack and Branch would insert a new Branch address into IAW2. 

Note that the low order bit of the location may be on. This bit must be 
removed, by using the "ANA" instruction if the user desires to use this 
address after a load processor status operation (See "LPS" instruction) 



lAWl 



IAW2 



IAW3 



IAW4 



IAW5 



Octal Loc. 




DPL Page 


Address: jO4j0 
CONTENT: BSSq 




Address: j041 
CONTENT: ,01.08 


Address: J342 
CONTENT: 2218 


Address: 043 
CONTENT: 01 83 


Address: 044 
CONTENT: 


Address: 045 
CONTENT: 


Address: 046 
CONTENT: 


Address: 047 
CONTENT: 


Address: 05j0 
CONTENT: 


Address: 051 
CONTENT: 


^ - 


" ' 





" " 


lAWl 5 


Address: 074 
CONTENT: 


IAW16 


Address: 076 
CONTENT: 



Address: 07 5 
CONTENT: 



Address: 077 
CONTENT: 



J 



o 



stack Pointer 



Figure 2., Snapshot of Instruction Address Stack after completion 
of EXU Instruction (See Example). 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



PI 0-050: 
P10-052: 
PI 0-054: 
P13-174: 
P13-176: 
PI 3-200: 
P13-220: 



200-024. 
123-174. 
237-054. 
230-01 1 . 
203-234. 
014-027. 
140-000. 



01-010. EAB: LDA, 

01-020. SBU: 

01-030. STA, 

01-040. DLY: STA, 

01-050. LDX, 

01-060. TLJ, 

01-070. EXU: 



R#0; OCT: 024. 
DLY. 

R#7; Pll. 
R#0; L#l. 
R#3; DEC:156. 
+12; (K). 





Byte 1 


(Octal Loc.) 








Byte 2 


( DPL Page) 






LOCATION 


U 
Bit 


V 
Bit 


Section 
Number 


Page 
Number 

































INSTRUCTION LOCATION 
(Octal 000 to 376) 



MEMORY CONTROL 



= Direct Address 

within Section 0, Page 0. 

1 = Direct Address 

within current section. Page 0. 



RELOCATABLE BRANCH CONTROL 



= Normal processing, 

1 = Relocatable Branch functions. 

(See SMC Instruction) 



SECTION NUMBER 



Section through Section 7. 



PAGE NUMBER 



Page through Page 7 (within a section) 



Figure 3. Instruction Address Word Layout. 



10 



REGISTERS : / 

The Cogar 4 contains one general purpose accumulator that is eight bits 
(one byte) long. Almost all of the nonbranch DPL-1 instructions refer 
to the accumulator. It is the major center for processor activity 
and the primary pipeline for data flow to and from the memory and the 
peripheral devices. 

The Cogar 4 contains seven one-byte index registers for each memory 
section available. They are often used as address displacements in 
indexed addressing, but may also be used as general purpose registers. 
A few of the DPL-1 instructions act directly on the index registers, 
but there is much more flexibility than those instructions imply because 
the registers are located in memory, They may thus be addressed by all 
memory reference instructions. The accumulator can retrieve, manipulate 
and restore the contents of any index register. 

The hardware condition register contains the results of Test and Compare 
instructions. It may be set to High, Equal or Low and retains its status 
until a new Test or Compare is executed. The operation of DPL-1 con- 
ditional Branch instructions depends on the status of the hardware con- 
dition register. 

ADDRESSING : 

The Cogar 4 contains 4K, 8K or 16K bytes of memory, with an lAW 16 bits 
long. Indirect addressing may operate anywhere within this range. The 
total memory capacity is divided into eight Sections of 2j048 bytes each, 
requiring 11 bits to fully address. Branch operations (if not preceded by 
a "SMS" instruction) may refer only to locations within a Section. Each 
Section is further divided into eight pages of 256 bytes each, requiring 
eight bits to fully address. Direct addressing (page JO of the current 
control section) or relocatable subroutines (branch operations with 
page J0 assigned) may refer to one page only. 

The object formats shown with the instruction descriptions include the 
following Binary Notations: 

Z = 1 bit frame 

Y = 2 bit frame 

X = 3 bit frame 

JJ = 4 bit frame 



11 





Instruction Addressing: 

All instruction addressing is relocatable page oriented. The address 
specification, in octal notation (object), is Pnn-LLL where nn = SL, 
S is the Section number, L is the Level number and LLL is the byte 
location within the page. 

All instructions are retrieved from memory using the current Instruction 
Address Word, and all instruction addressing involves modification of the 
lAW. 

For sequential execution of instructions, one of the sixteen lAW's within 
the Stack is incremented by two during each instruction cycle. Instruc- 
tions may be executed sequentially within a Section or across Section 
boundaries. It is important to note that when instructions cross a 
Section boundary, the branch functions, if executed, will transfer con- 
trol to the Section that was previously set. Other functions are not 
affected. A "Set Memory Section" instruction is used to change the 
section context of the I AW for branch instructions. 

A jump to a new instruction location uses relative instruction addressing 
by adding or subtracting up to 15 instruction locations to or from the 
current lAW. A Jump may be across a Section Boundary. 

ADDRESS NOTATIONS 




AAA 


DDD = Absolute Address, in decimal notation 

SSS = Symbolic Address 

RRR = Symbolic Branch Reference 

NNN = Address Adjustment for Symbolic 
Addresses, in decimal notation 




PPP 


Pnn = Absolute Page Number, in decimal notation 
SSS = Symbolic Page Number 









12 



Data Addressing : 

Data is addressed by an instruction in three different modes: 
Immediate, Direct and Indexed. 

When using the Immediate Addressing Mode, the operand itself, instead 
of the operand address, is assembled within the instruction as a self- 
defining literal . The literal represents data rather than an address 
of data. Literals provide a means of entering constants into a program 
by specifying the constant in the operand of the instruction in which 
it is used. Immediate Addressing is differentiated from Direct Addressing 
by the operand form. 

Direct Addressing Mode uses the instruction operand as the address of a 
byte location for all page numbers within level j0. This mode is 
utilized by specifying in the operand, any form of Direct Address 
notation. All DPL-1 functions may take this form of operand except 
Class and Class 1 Instructions. 

The Indexed Addressing Mode provides a method of addressing data any- 
where within memory. An Indexed Address is composed of a displacement 
address contained in a specified index register plus a base address con- 
tained in the operand. The register specifies the location within a 
page and the operand specifies the page within memory. The index register 
in use may be unchanged, incremented by one or decremented by one follow- 
ing the indexed operation. There are three forms of register notation 
used to specify this option. X may be any integer from 1 through 7. 

R#X = Retain Register Value 

I#X = Increment Register after 
Instruction Execution 

D#X = Decrement Register after 
Instruction Execution 

When an overflow occurs (I#X), the overflow bit is lost and the register 
contains octal jajDjD. When an underflow occurs (D#X), the result is the 
two's compliment of the underflow count. 

SYMBOLS : 

Program elements, such as instructions or constants, may be referenced 
in an instruction by specifying the absolute address of the element. The 
form for this type of reference is Pnn, LLL. Pnn specifies the page in 
2 digit decimal notation from jO0 to 63 and LLL specifies the location 
within the page in 3 digit decimal notation from JOJ0JO to 255. 



13 



It is often more convenient to refer to program elements symbolically. 
In the DPL-3B Assembler, a symbol is a combination of characters used to 
represent a program element. Symbols are defined through their use in 
the label field of an instruction or through the EQU pseudo instruction. 
A Symbol may be used only once in a label field within one program. When 
a symbol is used as an instruction operand, it must be defined somewhere 
in the program. A symbol must be comprised of three non-blank alpha- 
numeric characters with the first character non-numeric. If the first 
character is "P", the following characters must be alphabetic. The 
total number of symbols plus ORG statements plus page boundaries crossed 
by sequential program operation is limited to a maximum of 128. 

Address adjustment may be used for convenience and to cut down on the 
number of symbols defined. A signed numeric adjustment in decimal bytes 
from fi to 255 may be appended to a symbolic reference or may be used re- 
lative to the current location. An "*" (asterisk) is used to indicate 
the location of the first byte of the current instruction. 

The I/O Control Instruction micro-codes provide for control , status 
and data exchange between the processor and its interface devices. Tape 
channels may be selected, tape motions initiated, and read or write 
commanded; the keyboard may be read or beeped; the CRT may be enabled or 
disabled ; the I/O interface transmission may be started or stopped, and 
data or control bytes written. With the CRT enabled, the data content 
of any memory page which has a section or level number of less than 5 
may be displayed in four-line consecutive mode, eight-line consecutive 
mode, or eight-line interleaved mode. Several status checks are avail- 
able for the processor to interrogate. Most normal I/O operations will 
use the I/O Supervisor, but special purpose routines may be constructed 
from the IOC instructions and there are several operations, like key- 
board beep, that are not available from the lOS. 

5. DPL-1 INSTRUCTION CLASSES : 

The DPL-1 instruction set includes all hardware instructions and is div- 
ided into four general classes covering all types of operations required 
of a general purpose processor. 



Class 
Class 1 
Class 2 
Class 3 



Jump and Conditional Exit Instructions 
Branch, Linkage-Control, and I/O Instructions 
Data-Transfer and Arithmetic Instructions 
Boolean and Compare Instructions 



14 



Class 0: Jump Instructions : 

Jump instructions transfer control within a context to a location 
relative to the current instruction location. All Jump Instructions are 
conditional and depend on the result of a test of the contents of the 
accumulator. The test comparison, the test mask, the Jump direction and 
the jump increment are all specified in the instruction. The Jump in- 
crement is expressed in the instruction itself as the octal number of 
two-byte instructions to be jumped. However, the Batch Assembler uses 
a decimal byte count for the Jump increment. Test results are stored 
in the hardware condition register. For the TMJ and TMX instructions, 
an unconditional Jump or Exit, and the setting of the condition register 
to equal , can be effected by using a test mask of zero. 

Class 1: Branch, Linkage-Control, and I/O Instructions : 

Branch instructions transfer control outside a context to any section 
address. Branch instructions replace the current lAW with a new instruc- 
tion address. Stack and Branch instructions introduce a new instruction 
address in a new lAW and preserve the contents of the previous lAW for 
return linkage. Direct Branch instructions may be conditioned by pre- 
vious test or compare operations. The conditional instructions allow 
powerful data-dependent decisions to be made. The Exit and the Exit and 
Branch instructions are used to return from subroutines. They decrement 
the stack pointer and thus change program control to the next previous 
lAW. 

Class 2: Data Transfer and Arithmetic Instructions : 

This class of instructions includes the Load and Store operations that 
allow data to be moved between memory and the accumulator or index 
registers. These instructions use immediate, direct, or indexed address- 
ing modes. When loading or storing using indexed addressing, the 
specified index register may be automatically incremented or decremented. 

The arithmetic instructions in this class include Binary add and subtract 
operations on the accumulator or the index registers. Immediate, direct, 
or indexed addressing may be used. Automatic increment or decrement of 
index registers may be specified when using indexed addressing. All 
operations are available for use with the accumulator. Some operations 
may also be performed on index registers. 



15 



Class 3: Boolean and Compare Instructions : 

The Boolean instructions in this class include immediate, direct or 
indexed addressing of And, Inclusive Or, and Exclusive Or operations. 
The immediate instructions allow for up to seven right circular shifts 
of the accumulator prior to operation with the literal. 

The Compare instructions compare the contents of the accumulator with 
a location specified by immediate, direct or indexed addressing. Any 
index register may be compared with a literal. The comparison results 
are stored in the condition register and may be tested by any following 
conditional Branch instruction. In indexed addressing of both Boolean 
and Compare instructions, the specified index register may be auto- 
matically incremented or decremented. 

PPL PUNCTUATION : 

Rather than an implicit syntax, the DPL grammar provides an explicit 
syntax by use of punctuation. Four punctuation characters are used: 
the semi -col on, the comma, the colon and the period. 

The semi -col on is used as an imperative terminator or a major field 
delimiter. It usually separates the instruction field from the operand 
field. 

The comma is used as a minor field terminator. It separates multiple 
field instructions or operands. 

The colon is used as a declarative terminator. It follows instruction 
labels, pseudo instructions and constant designators. 

The period is used as a closing terminator and defines the end of the 
symbolic instruction. 

LITERAL NOTATIONS : 

Literal notations may be classified as explicit terms or as implicit 
terms. Explicit literals are self -defining because they include the 
specific value to be used. The four explicit literal forms are 
Character, Octal, Hexadecimal, and Decimal. They provide a means of 
specifying values or bit configurations without equating the values to 
symbols. The value of an explicit literal is assembled into an in- 
struction. The value of a symbolic constant resides in memory and its 
address is assembled into an instruction. 



16 



Literals that are assigned a value by the DPL-3B Assembler use five 
forms of address constants in which AAA is a symbolic address. These 
are: ADCrAAA, ADL:AAA, ADPrAAA, IDPrAAA, and DDR: AAA. These address 
constants are used primarily to define the actual address of a 
symbolic reference. When the literal form ADR, IDR, or DDR is used 
in conjunction with an R#0 or an R#X, instruction, the DRL page value 
of AAA is assembled as the operand; either with no indexing tag, or 
with incrementing or decrementing tag, respectively. If the form ADL 
is used, the address location value within the page is assembled as 
the operand. 

When the literal form ADC is used in conjunction with an R#0 

instruction, the DPL page value, in increment form, is assembled as 

the operand. If used in conjunction with an R#X instruction, the 

symbolic address location within the page is assembled as the operand. 

8. STANDARD C4 PROGRAM RECORD (Mini-Tape) 

The Standard Mini-Tape Record is comprised of an 8-byte label, generated 
by the Mini-Write Software Function, followed by 128 bytes of data. The 
8-byte label when read into (or written from) memory resides in Rage 00, 
locations OSOg thru OSZg. The first byte of the Record Header contains 
a sequence number. The sequence number is automatically checked by 
the Mini-Read Software Function to provide a method of automatically 
bypassing any "CIG" (Character in Gap). This sequence number may also 
be used to adjust search counters when utilizing the high-speed 
capability to locate multiple records by continuation. Byte-2 contains 
the control function. A value other than those specified below may be 
inserted by the user for specialized functions. Bytes 3 and 4 are not 
used by the Standard Mini-Read/Write, and can, therefore, contain any 
value as established by the user. 



17 



Bytes 5 through 8 of a program record contain the Segment ID and the 
Page Designator. Through usage of these bytes, an overlay record can 
easily be located and loaded into memory. Bytes 5 through 8 are not 
used in a data file. 



8 bytes 
(Header) 



128 Bytes (Data) 



\ 



X 



\ 



X 



x 



X 



X 



X 



X 



Not 
Used 



Not 
Used 



-:i^ 



Page 
Alloc, 



Binary Sequence 
Number starting 
with 001 and 
.continually 
incremented with 
wraparound 



(Not used in Data Files) 



DPL Page of 
Record 
Program ID. 

This ID is inserted by 
the 0-String Generation 
Phase from the "SEG" ID 
or the "OVL" ID. (Not used 
in data files.) 



Control Byte. 

375=End of Program Load 

377=End of File Indicator 



Segment Page 
Allocation 



l=Rel oca table 
0=Non-Rel oca table 



0=Lower half of Page 
(OOOg thru 1778 ) 

l=Upper half of Page 
(2008 thru 3778 ) 



Figure 4. Standard Mini -Tape Record Layout. 



18 



9. SUBROUTINE RELOCATABILITY 

A method has been provided to allow the user to write subroutines that 
may be executed within any Page without re-assembling the subroutine 
for that Page. By executing a SET Memory Control Command that sets the 
Relocatable Branch Control (RBC) Bit, any Branch, Stack and Branch or 
Exit and Branch Instruction given with Page specified in the Branch 
Address will cause the Branch to occur within the current Section and 
Page of the program. If any Page other than is specified in the 
Branch Address, the RBC-Bit is Inactive and a normal Branch function 
will occur. 

10. TAPE I/O CHARACTER QUEUE 

The SYSTEM 4 tape logic contains an 8-bit chararacter buffer that will 
hold a character for 512 usee, allowing this much time for other 
processing before the user must return to the I/O operation. 



19 



For DPL-1 instructions that use Immediate Addressing, the following 
forms may be used in symbolic coding to specify the literal value: 



(K) Where K is a valid keyboard character 

OCT:NNN Where NNN is a one-byte constant in OCTAL 
notation from jOjOjO to 377. 



HEX:HH Where HH is a one-byte constant in HEXA- 
DECIMAL notation from 0JO to FF. 

DEC:NNN Where NNN is a one-byte constant in DECIMAL 
notation from 000 to 255. 



ADP:AAA Where AAA is an address constant for a PAGE 
in symbolic notation (without Auto Indexing). 

IDP:AAA Where AAA is an address constant for a PAGE 
in symbolic notation (with Increment Auto. 
Indexing). 

DDP:AAA Where AAA is an address constant for a PAGE 
in symbolic notation (with Decrement Auto. 
Indexing). 

ADLrAAA Where AAA is an address constant for a 
LOCATION in symbolic notation. 

ADC: AAA An address constant for labels, in symbolic 
notation (will generate page or location 
dependent on the Instruction form). 

AAA+NNN Where AAA is an address constant for a 

location in symbolic notation, and NNN is 
offset ± from that location. 



20 



SECTION III. INSTRUCTION DESCRIPTIONS 



The instructions described in this section of the manual are 
presented in the same order as they appear on the Cogar System 4 
Instruction Reference Card, and fall in the following four categories: 

1. DPL-1 Instructions. These instructions perform all the data 
manipulation and control tasks allowed by the hardware. 

2. lOS Commands. These instructions provide access to the standard 
software I/O routines, using the I/O Supervisor. 

3. Pseudo Instructions. These instructions provide programmer 
control over the DPL-3B Assembler, and the resident monitors. 

4. Constants. Byte constants or string constants may be generated 
using these notations. 



21 



•DPL-1 



CLASS JD: JUMP 



TEST LITERAL AND JUMP 



OBJECT 1 1 SOURCE 


000JJJ5-LLL 1 1 TLJ, +NNN; Literal. 
]OjO0JJl-LLL II TLJ, -NN; Literal. 




WHERE: 



AND: 



J J is the jump count in 4 Bit 
Binary notation, indicating 
the number of 2-Byte instructions 
to be jumped. 

LLL is an 8 Bit Literal. 



WHERE: NN is the jump count in 
decimal notation, indic- 
ating the number of bytes 
to be jumped. 

NOTE : This jump count must 

always be an even decimal 
number (Max:30). 



DESCRIPTION : 

The Accumulator is compared to the byte of immediate data (literal), and 
the result is indicated in the condition register. Comparison is binary, and 
all codes are valid. If the resulting condition register is equal, a jump for- 
ward (+) or a jump backward (-) up to 15 two-byte instruction locations is 
performed. If however the resulting condition register is not equal (high or 
low), the next sequential instruction is executed. The character in the 
Accumulator is not changed. Once set, the condition register remains unchanged 
until modified by the next jump or compare instruction that reflects a different 
condition code. 

NOTE : The condition register contains the true arithmetic condition (high or 
low) after an unsuccessful jump (unequal condition). 




ACCUM > LITERAL 
ACCUM < LITERAL 
ACCUM = LITERAL 



TIMING: 



EXAMPLE; 



3 Microseconds if the jump is not performed. 

4 Microseconds if the jump is performed. 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



PI 5' 
P15-JD02: 
PI 5-J004 : 
P15-JO06: 



012-015. 
013-016. 
006-015. 
004-017. 



01-120. 
01-130. 
01-140. 
01-150. 



TLJ, 
TLJ, 
TLJ, 
TLJ, 



+10; 
-10; 
+06; 
+04; 



(A). 

OCT:016. 
DEC:013. 
HEX:0F. 



COMMENTS 

JUMP IF 
ACCUM IS 
EQUAL 



22 



•DPL-l 



CLASS 0: JUMP 



TEST MASK AND JUMP 



OBJECT 1 1 SOURCE 


001JJ0-MMM i i TMJ, +NN; LT-MASK. 
001JJ1-MMM II TMJ. -NN; LT-MASK. 




WHERE: 



AND: 



J J is the jump count in 4 Bit 

Binary notation, indicating 

the number of 2-Byte Instructions 

to be jumped. 

MMM is an 8 Bit Literal Mask. 



WHERE: NN is the jump count in 
decimal notation, indic- 
ating the numter of bytes 
to be jumped. 

NOTE : This jump count must 

always be an even decimal 
number (Max:30). 



DESCRIPTION: 



The state of the Accumulator bits selected by a mask is used to set the con- 
dition code. 



The byte of Immediate Data (Literal-Mask) is used as an eight-bit mask. The 
bits of the mask are made to correspond one for one with the bits of the 
character in the Accumulator. A mask bit of one indicates that the corresponding 
Accumulator bit is to be tested. When the mask bit is zero, the corresponding ' 
Accumulator bit is ignored. When any of the Accumulator bits thus selected are 
zero, the Condition Register is made unequal. When the selected bits are 
all-one, the Condition Register is made equal. If the resulting Condition 
Register is equal, jump forward (+) or jump back (-) up to 15 two-byte in- 
struction locations. On the resulting Condition Register not equal (high or 
low), execute the next sequential instruction. The character in the Accumulator 
is not changed. Once set, the Condition Register remains unchanged until modi- 
fied by an instruction that reflects a different condition code. 
NOTE: The content of the Condition Register is unpredictable after an un- 



successful jump (unequal condition). 




TIMING: 3 Microseconds if the jump is not performed. 
4 Microseconds if the jump is performed. 




EXAMPLE: 




PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 


COMMENTS 


PI 5-010: 050-016. 02-010. TMJ, +08; OCT :01 6. 
PI 5-012: 051-050. 02-020. TMJ, -08; DEC:040. 
PI 5-01 4: 076-377. 02-030 TMJ, +30; HEX:FF. 


JUMP IF 
MASK IS 
EQUAL 



23 



•DPL-1 



CLASS 0: 



OBJECT 



-LLL 



TEST LITERAL AND EXIT 



SOURCE 



I 

I TLX, 0jO0; Literal 




WHERE: LLL is an 8 bit Literal. 



DESCRIPTION: 



The Accumulator is compared to the byte of immediate data (literal), and the 
result is indicated in the Condition Register. Comparison is binary, and all 
codes are valid. If the resulting Condition Register is equal, then a special 
form of exit, (conditional exit) is performed, which completes the return 
linkage established by the last executed stack and branch instruction. The 
stack pointer is decremented to the preceding stack level, which contains the 
address of the last stack and branch instruction executed. This address is 
then incremented by 2 bytes, which establishes the address of the instruction 
following the stack and branch instruction, and a new location counter value. 
This value is the new instruction address, where processing continues. 

The exit function may return within a section or outside a section without 
any special consideration, since the stack contains the page and location of 
the return address. 

NOTE : The Condition Register contains the true arithmetic condition (high 
or low) after an unsuccessful Jump (unequal condition). 




ACCUM > LITERAL 
ACCUM < LITERAL 
ACCUM = LITERAL 



TIMING : 3 Microseconds if the Jump is not performed. 
4 Microseconds if the Jump is performed. 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P15-J916 
PI 5-020 
PI 5-022 
PI 5-024 



000-017. 
000-013. 
000-016. 
000-377. 



02-090. 
02-100. 
02-110. 
02-120. 



TLX, 000; (C). 

TLX, 000; OCT:013. 

TLX, 000; DEC:014. 

TLX, 000; HEX:FF. 



COMMENTS 

EXIT IF 
ACCUM IS 
EQUAL 



24 



•DPL-l 



CLASS 0: 



TEST MASK AND EXIT 



OBJECT 



04jD-nMM 



++ 



SOURCE 



I I I HA, 
I I 



; LT-MASK. 




DESCRIPTION: 



WHERE: MMM is an 8 bit Literal Mask. 



The state of the Accumulator bits selected by a mask is used to set 
condition code. 



the 



The byte of Immediate Data (Literal-Mask) is used as an eight-bit mask. The 
bits of the mask are made to correspond one for one with the bits of the char- 
acter in the Accumulator. A mask bit of one indicates that the corresponding 
Accumulator bit is to be tested. When the mask bit is zero, the corresponding 
Accumulator bit is ignored. When any of the Accumulator bits thus selected 
are zero, the Condition Register is made unequal. When the selected bits 
are all one, the Condition Register is made equal. If the resulting Condition 
Register is equal, then a special form of exit, (conditional exit) is performed, 
which completes the return linkage established by the last executed stack and 
branch instruction. The stack pointer is decremented to the preceding stack 
level, which contains the address of the last stack and branch instruction 
executed. This address is then incremented by 2 bytes, which establishes the 
address of the instruction following the stack and branch instruction, and a 
new location counter value. This value is the new instruction address, where 
processing continues. 

The exit function may return within a section or outside a section without any 
special consideration, since the stack contains the page and location of the 
return address. 



NOTE : The content of the Condition Register is unpredictable after an un- 



successful Jump (unequal condition). 




TIMING: 


3 Microseconds if the Jump is not performed. 

4 Microseconds if the Jump is performed. 




EXAMPLE: 






PPP-LLL: 


MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 


COMMENTS 


PI 5-026: 
PI 4-030: 
PI 5-032: 


040-010. 02-180. TMX, 000; OCT:010. 
040-310. 02-190. TMX, 000; DEC:200. 
040-240. 02-200. TMX, 000; HEX:A0. 


EXIT IF 
MASK IS 
EQUAL 



25 



•DPL-l 



CLASS 1: BRANCH 



BRANCH UNCONDITIONAL 



OBJECT 1 1 SOURCE 


1 1 ; RRR+NNN. 
1JZ)X-YXYJ0 1 1 BRU , Pnn; LLL. 
1 1 ; *+NNN. 

1 1 




WHERE: 



AND: 



10X is the command, in which 
X is the page. 

YXY is a 7 bit address. 



WHERE: RRR is a symbolic address 
AND: NNN is a decimal byte dis- 
placement. 
AND: nn is a decimal page. 
AND: LLL is a decimal location 
AND: * is the location of the in- 
struction itself. 



DESCRIPTION : 

The unconditional branch is performed by introducing a branch address as a 
new instruction address, regardless of the setting of the Condition Register. 

The Branch Address may be represented in symbolic notation, as an absolute 
address; or as a relative address. The Branch Address may be any location within 
the current section. "OUT-OF-SECTION" branching is achieved by preceding the 
branch instruction with a SET MEMORY SECTION (SMS) instruction, or a SET memory 
SECTION & CONTROL (SSC) instruction. "WITHIN-A-PAGE" branching relocatability 
is achieved by preceding the branch instruction with a SET MEMORY CONTROL (SSC) 
instruction in which the RELOCATABLE BRANCH CONTROL (RBC) bit is set. 
(i.e.: C#l or C#3). The hardware condition register remains unchanged after 
execution of a branch function. 

TIMING: 4 Microseconds. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P15-J334: 
P15-J336: 
P15-JD4JD: 
PI 5-042: 
P15-JQ44: 



1)?)5-J042. 
1J05-J036. 
107-00)0. 
15JO-000. 
106-144. 



03-030. 


BRU; 


INI. 




03-040. 


BRU; 


*+0. 




03-050. 


BRU, 


P15; 


000 


03-060. 


INI: SMS; 


S#0. 




03-070. 


BRU, 


P06; 


100 



COMMENTS 

WITHIN A 
SECTION 

OUT OF A 
SECTION 



26 



•DPL-1 



CLASS 1: BRANCH 



BRANCH ON EQUAL 



OBJECT 1 1 SOURCE 


1 ! ; RRR+NNN. 
IjOX-YXYl 1 1 BRE , Pnn; LLL. 
1 1 ; *+NNN. 




WHERE: IjOX is the command, in which 

X is the page. 
AND: YXY is a 7 bit address. 



WHERE: 
AND: 



AND 
AND 
AND 



RRR is a symbolic address. 
NNN is a decimal byte dis- 
placement. 

nn is a decimal page. 
LLL is a decimal location. 
* is the location of the in- 
struction itself. 



DESCRIPTION : 

The conditional branch instruction, branch on equal, is performed when the con- 
dition register, set by a previous compare or test instruction, is found to be 
equal. If this condition is not satisfied, the next sequential instruction is 
executed. The conditional branch is performed by introducing a branch address 
as a new instruction address. 

(Refer to "BRU" for Basic Rules of Branching). 

TIMING : 3 Microseconds if the branch is not performed. 
4 Microseconds if the branch is performed. 

EXAMPLE: 



PI 5-046: 
P15-J350: 
PI 5-052: 
PI 5-054: 
PI 5-056: 



105-051. 
150-000. 
340-200. 
106-145. 
150-010. 



SEQ. NO. 


LAB: VERB 


OPERANDS 


COMMENTS 


03-130 


BRE; 


IN2. 


WITHIN SECT 


03-140. 


IN2: SMS; 


S#0. 


OUT OF A 


03-150. 


CPA, 


R#0; OCT: 200. 


SECT. IF 


03-1 60. 


BRE, 


P06; 100. 


EQUAL-ELSE 


03-170. 


SMS; 


S#l. 


RESET SECT. 



27 



•DPL-1 



CLASS 1: BRANCH 



BRANCH ON HIGH 



OBJECT II SOURCE 


1 1 ; RRR+NNN. 
11X-YXYJ0 M BRH , Pnn; LLL. 
M ; *+NNN. 




WHERE; 
AND: 



IIX is the 
which X is 
YXY is a 7 



command, in 
the page, 
bit address. 



WHERE: 
AND: 



AND 
AND 
AND 



RRR is a Symbolic address. 
NNN is a decimal byte dis- 
placement. 

nn is a decimal page. 
LLL is a decimal location. 
* is the location of the in- 
struction itself. 



DESCRIPTION : 

The conditional branch instruction, branch on high, is performed when the con- 
dition register, which has been set by a previous compare or test instruction, 
is found to be high. If this condition is not satisfied, the next sequential 
instruction is executed. 

(Refer to "BRU" for Basic Rules of Branching). 

TIMING : 3 Microseconds if the branch is not performed. 
4 Microseconds if the branch is performed. 

EXAMPLE: 



P15-JO6J0: 
PI 5-062: 
P15-J064: 
PI 5-066: 
P15-07JD: 



115-062. 
150-000. 
340-200. 
116-144. 
150-010. 



SEQ. NO. 


LAB: VERB 


OPERANDS 


COMMENTS 


04-030. 


BRH; 


*+02. 


WITHIN SECT 


04-040. 


IN3: SMS; 


S#0. 


OUT OF A 


04-050. 


CPA, 


R#0; OCT: 200. 


SECT. IF 


04-060. 


BRH, 


P06; 100. 


HIGH-ELSE 


04-070. 


SMS; 


S#l. 


RESET SECT. 



28 



•DPL-1 



CLASS 1 : BRANCH 



BRANCH ON LOW 



OBJECT 1 1 SOURCE 


i i ; RRR+NNN. 
IIX-YXYI 1 1 BRL , Pnn; LLL. 
1 1 ; *+NNN. 

1 1 




WHERE: 11 X is the command, in which 

X is the page. 
AND: YXY is a 7 bit address. 



WHERE: RRR is a Symbolic address. 

AND: NNN is a decimal byte dis- 
placement. 

AND: nn is a decimal page. 

AND: LLL is a decimal location. 

AND: * is the location of the in- 
struction itself. 



DESCRIPTION : 

The conditional branch instruction, branch on low, is performed when the con- 
dition register, set by a previous compare or test instruction, is found to be 
low. If this condition is not satisfied, the next sequential instruction is 
executed. The conditional branch is performed by introducing a branch address 
as a new instruction address. 

(Refer to "BRU" for Basic Rules of Branching) 

TIMING: 3 Microseconds if the branch is not performed. 





4 Micros 


econds i 


f the branch is performed. 




EXAMPLE : 












PPP-LLL: 


MP1-MP2- 


MPS- 


-MP4. 


E SEQ. NO. LAB: VERB OPERANDS 


COMMENTS 


PI 5-072: 
PI 5-074: 
PI 5-076: 
PI 5-100: 
P15-102: 


115-075. 
150-000. 
340-200. 
116-145. 
150-010. 






04-130. BRL; IN4. 
04-140. IN4: SMS; S#0. 
04-150. CPA, R#0; OCT: 200. 
04-160. BRL, P06; 100. 
04-170. SMS; S#l . 


WITHIN SECT 
OUT OF A 
SECT. IF 
LOW-ELSE 
RESET SECT. 



29 



.DPL-1 



CLASS 1: BRANCH 



STACK AND BRANCH 
UNCONDITIONAL 



OBJECT 1 1 SOURCE 


1 ; RRR+NNN. 
12X-YXYja SBU , Pnn; LLL. 

; *+NNN. 




WHERE: 12X is the command, in 

which X is the page, 
AND: YXY is a 7 bit address. 



WHERE: 

AND: 

AND: 

AND: 

AND: 



RRR is a symbolic address. 
NNN is a decimal byte displacement, 
nn is a decimal page. 
LLL is a decimal location. 
* is the location of the instruc- 
tion itself. 



The Stack and Branch Unconditional Instruction is performed regardless of the 
setting of the condition register. 

DESCRIPTION : 

The stack and branch instructions are in contrast with the branch instructions, 
in that the stack and branch instructions preserve the current value of the 
location counter which is present in the current stack; this is performed by 
incrementing the stack pointer to the next stack level and creating a new 
location counter value containing the branch address as a new instruction ad- 
dress, within that stack. Thus, the return linkage between sub-routines is 
established. For the stack and branch function there are sixteen levels of 
stacks that the stack pointer can address, of which fifteen levels of stacks may 
temporarily preserve the return linkages for fifteen levels of stack and 
branching. 

TIMING: 3 Microseconds 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P15-1J34 
P15-1J36 
P15-11J3 
PI 5-1 12 
PI 5-1 14 



125-112. 
125-112. 
127-J0JO0. 
150-jOjaj3. 
126-144. 



05-JD40. 


SBU; 


INS. 


05-J050. 


SBU; 


*+j54. 


155-06)?). 


SBU, 


P15; J0 


J05~)D7)D. 


IN5: SMS; 


S#J[). 


JO5-08)D. 


SBU, 


P)D6; 1 



COMMENTS 

WITHIN A 
SECTION 

OUT OF A 
SECTION 



30 



•DPL-1 



CLASS 1: BRANCH 



STACK AND BRANCH EQUAL 



OBJECT 1 1 SOURCE 


i i ; RRR+NNN. 
12X-YXY1 1 1 SBE , Pnn; LLL. 
1 1 ; *+NNN. 

1 1 




WHERE: 12X is the command, in which 

X is the page. 
AND: YXY is a 7 bit address. 



WHERE: 
AND: 



AND 
AND 
AND 



RRR is a symbolic address. 
NNN is a decimal byte displace- 
ment. 

nn is a decimal page. 
LLL is a decimal location. 
* is the location of the in- 
struction itself. 



DESCRIPTION : 

The conditional stack and branch, stack and branch equal, is performed when the 
condition register, set by a previous compare or test instruction, is found to 
be equal. If the condition is not satisfied, the next sequential instruction 
is executed. 

(Refer to "SBU" for Basic Rules of Stack and Branching). 

TIMING : 3 Microseconds if the stack and branch is not performed. 
4 Microseconds if the stack and branch is performed. 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: 



P15-116: 
P15-12JZ): 
P15-122: 
PI 5-1 24: 



125-121. 
15j0- 0)0)2). 
34J0-2J0J8. 
126-145. 



PI 5- 126: 15jD-01jei. 



J05- 
JSI5- 
J05- 
J05- 



14jO. 
15ja. 
16J9. 
17J3. 



jO5-18j0. 



INS: 



VERB 


OPERANDS 


COMMENTS 


SBE; 
SMS; 
CPA, 
SBE, 
SMS; 


*+jD2. 

S#JD. 

R#jO; 0CT:2W. 

pj06; ^m. 

S#l. 


WITHIN SECT 
OUT OF A 
SECTION IF 
EQUAL-ELSE 
RESET SECT. 



31 



•DPL-l 



CLASS 1 : BRANCH 



STACK AND BRANCH ON HIGH 



OBJECT 1 1 SOURCE 


1 1 ; RRR+NNN. 
ISX-YXYjZ) II SBH , Pnn; LLL. 
1 1 ; *+NNN. 




WHERE: 


13X is the command, in 


WHERE: 




which X is the page. 


AND: 


AND: 


YXY is a 7 bit address. 


AND: 
AND: 
AND: 



RRR is a symbolic address. 
NNN is a decimal byte displace- 
ment. 

nn is a decimal page. 
LLL is a decimal location. 
* is the location of the 
instruction itself. 



DESCRIPTION : 

The conditional stack and branch, stack and branch on high, is performed when 
the condition register, set by a previous compare or test instruction, is found 
to be high. If the condition is not satisfied the next sequential instruction 
is executed. 

(Refer to "SBU" for Basic Rules of Stack and Branching) 

TIMING : 3 Microseconds if the stack and branch is not performed. 
4 Microseconds if the stack and branch is performed. 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E 



P15-13)3: 
P15-132: 
P15-134: 
PI 5-1 36: 
P15-14JD: 



135-132. 
15jD-jZ))30. 
34)a-2jOja. 
136-144. 
15)D-JD1JD. 



SEQ. NO. 


LAB: 


VERB 


OPERANDS 


COMMENTS 


J06-jO4ja. 




SBH; 


IN7. 


WITHIN SECT 


j95-05jO. 


IN7: 


SMS; 


S#jO. 


OUT OF A 


J06-JD6JD. 




CPA, 


R#^; OCT: 2)0)3. 


SECTION IF 


jZ)6-JJ)7)D. 




SBH, 


P^6; 1)90. 


HIGH-ELSE 


06-jD8jO. 




SMS; 


S#l . 


RESET-SECT. 



32 



•DPL-l 



CLASS 1: BRANCH 



STACK AND BRANCH ON LOW 



OBJECT 



13X-YXY1 



SOURCE 



SBL 



. DDD_lMMM 

, PnnT LLL. 
; *+NNN. 




WHERE: 13X is the command, in which 

X is the page. 
AND: YXY is a 7 bit address. 



WHERE: 


RRR is a symbolic address. 


AND: 


NNN is a decimal byte dis- 




placement. 


AND: 


nn is a decimal page. 


AND: 


LLL is a decimal location. 


AND: 


* is the location of the in 




struction itself. 



DESCRIPTION : 

The conditional stack and branch, stack and branch on low, is performed when 
the condition register, set by a previous compare or test instruction, is found 
to be low. If the condition is not satisfied the next sequential instruction 
is executed. 

(Refer to "SBU" for Basic Rules of Stack and Branching) 

TIMING : 3 Microseconds if the stack and branch is not performed. 
4 Microseconds if the stack and branch is performed. 

EXAMPLE: 



PI 5-1 42: 
P15-144: 
P15-146: 
P15-150: 
P15-152: 



135-145. 
150-/300. 
340-200. 
136-145. 
150-010. 



SEQ. NO. 


LAB: 


VERB 


OPERANDS 


COMMENTS 


06-140. 




SBL; 


INS. 


WITHIN SECT 


06-150. 


INS: 


SMS; 


S#0. 


OUT OF A 


06-160. 




CPA, 


R#0; OCT: 200. 


SECTION IF 


06-170. 




SBL, 


P06; 100. 


LOW-ELSE 


06-180. 




SMS; 


S#l. 


RESET SECT. 



33 



•DPL-1 



CLASS 1: BRANCH 



EXIT AND BRANCH 



OBJECT 1 1 SOURCE 


' ' ; RRR+NNN. 
16X-YXYJ0 ' ' EXB , Pnn; LLL. 
] j ; *+NNN. 

1 1 




WHERE: 16X is the command, in 


WHERE 


which X is the page. 


AND: 


AND: YXY is a 7 bit address. 


AND: 




AND: 


DESCRIPTION: 





RRR is a symbolic address. 

NNN is a decimal byte displacement. 

nn is a decimal page. 

LLL is a decimal location. 



The exit and branch instruction combines the functions of the exit instruction 
and the branch unconditional instruction. This form of exit does not perform 
the return linkage established by the preceding stack and branch instruction. 
The stack pointer is decremented to the preceding stack level. The address 
specified in the operand is then used to establish a new location counter value 
within that stack. This value is the new instruction address within the current 
section, where processing continues. 



TIMING: 4 Microseconds 



EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P15-154: 165-156. 
PI 5-1 56: 15JD-J0JOJD. 
P15-160: 166-144. 



J07-JJI5J3. 
J07-06J3. 
j37-07j3. 



EXB; *+jD2. 
SMS; S#jO. 
EXB, Pj06; 



COMMENTS 

WITHIN SECT. 
OUT OF A 
SECTION 



34 



•DPL-1 



CLASS 1: BRANCH 



EXIT UNCONDITIONAL 



OBJECT 



TT 

+4- 



SOURCE 



"X Afh (hfAffi 



I I 

I I 

I I 
I I 



EXU; 000. 




.WHERE: 
AND: 



140 is the command, 

000 is the 8-Bit Operand 



DESCRIPTION : 

This form of exit, exit unconditional, performs the return linkage established 
by the last executed stack and branch instruction. The stack pointer is decre- 
mented to the preceding stack level, which contains the address of the last 
stack and branch instruction executed. This address is then incremented by 2 
bytes which establishes the address of the instruction following the stack and 
.branch instruction, and a new location counter value. This value is the new 
instruction address, where processing continues. 

The exit function may return within a section or outside a section without any 
special consideration, since the stack contains the page and location of the 
return address. 

The condition register is not changed by this instruction. 



TIMING: 


4 Microseco 


ids. 












EXAMPLE: 


















PPP-LLL: 


MP1-MP2- 


MPS 


-MP4. 


E SEQ. NO. 


LAB: 


VERB 


OPERANDS 


COMMENTS 


P15-162: 


150-000. 






07-130. 




SMS; 


S#0. 


LINK OUT OF 


P15-164: 


126-144. 






07-140. 

*07-150. 

07-160. 




SBU; 
ORG: 


OUT. 
P06, 100. 


A SECTION 


P06-144: 


213-006. 






07-170. 


OUT: 


LDA, 


I#3; P01. 




P06-146: 


140-000. 






07-180. 




EXU; 


000. 


RETURN 



35 



•DPL-l 



CLASS 1: BRANCH 



SET MEMORY SECTION 



OBJECT 



1 510-jOXjO 



SOURCE 



SMS; S#X. 




WHERE: X is the section number (0-7), 



DESCRIPTION: 



The set section instruction provides a means of transferring control from the 
current section to an outside section. A branch function (Branch, Stack & 
Branch or Exit & Branch) preceded by an SMS command will transfer control to 
the address defined by the branch address and the section specified in the 
set section operand. 

Note that once the SMS instruction has been executed, transfer to that section 
will only be made when an unconditional branch function is executed or a 
conditional branch function that is found to be true. 

The condition register is not changed by this instruction. 

TIMING : 4 Microseconds. 

EXAMPLE : 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P15-)DjO0: 15jO-0j50. 
P15-JD02: Ij02-)0)5)D. 



)38-j07j0. 
J08-j08j0. 



SMS; S#jO. 

BRu, pj02; mm. 



COMMENTS 

SET SECTION jO 
BRANCH PAGE 2 



36 



•DPL-l 



CLASS 1 



SET MEMORY CONTROL 



OBJECT 



151-YjDja 



SOURCE 



SMC; C#Y, 




WHERE: Y = jO Resets U & V control bits, 

Y = 1 Sets V Bit, Resets U Bit, 

Y = 2 Sets U Bit, Resets V Bit, 

Y = 3 Sets U and V Bits. 



DESCRIPTION : 

When the U bit is set to jO, the address of the index registers is memory 
location 1-7 and direct addressing is only available in page of section jO. 
When the U bit is set to 1, the effective index register address is location 
1-7 of the section where the indexed instruction is being executed. Like- 
wise the effective direct address is page J0 of the section where the direct 
address instruction is being executed. 

When the V bit is set to 1 any branch, stack & branch or exit & branch in- 
structions given with page J0 specified in the branch address will cause the 
branch to occur within the currrent section and page of the program. If any 
page other than is specified in the branch address, the V bit control is 
inactive and a normal branch will occur. For example, assume that the V bit 
is set and a branch instruction located in page 5 specifies a branch to page 
location AAA. The resulting branch will be, to page 5 location AAA. If the 
branch address specified was page 6 location BBB, then the resulting branch will 
be to page 6 location BBB. If a program resides in any page other than page 
and a branch to page is desired, the V bit must be inactive. 

An exit or exit and branch operation will restore the control bits to the value 
associated with that stack level. A stack and branch operation will not affect 
the control bits. 

TIMING: 4 Microseconds. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



PI 5-004: 151-300. 
PI 5-006: 230-200. 
PI 5-010: 100-100. 



08-140. 

08-150. 

08-160. 

*O8-170. 



SMC; C#3. 
STA, R#0; 128. 
BRU, P00; 064. 



COMMENTS 

SET U,V CONTROL 
STORE PAGE 10 
BRANCH TO 
PAGE 15-100/OCT 



37 



•DPL-1 



CLASS 1 



OBJECT 



152-YX0 



SET MEMORY SECTION & CONTROL 



SOURCE 



SSC, S#X; C#Y 




DESCRIPTION: 



WHERE: X is the section designation 

Y is the control bit designation 



This instruction performs both the set memory section operation of SMS and 
set memory control operation of SMC. 



TIMING: 



EXAMPLE: 



4 Microseconds. 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 

P15-JD12: 152-JD30. J09-)93J3. SSC, S#3; C#)D. 

J39-J04ja. 
P15-J314: 152-36J0 09-JD50. SSC, S#6; C#3. 

*J59-JD60. 



COMMENTS 

SET SECT. 3 & 
RESET U & V-BIT 
SET SECT. 6 & 
SET U & V-BITS 



38 



•DPL-1 



CLASS 1 



SET ARITHMETIC CONDITION 



OBJECT 



SOURCE 



1 53-000 



SAC; 



SAC 



DESCRIPTION : 

This instruction will force the arithmetical condition registers of the pro- 
cessor to an equal, high or low condition, dependent upon the state of bits 
4 and 5 of the accumulator at the time of the SAC instruction. 

The condition forced by the SAC instruction for a given state of bits 4 and 5 
of the ACC is given below. 



ACCUMULATOR BITS 
7 6 5 4 3 2 1 JO 



CONDITION FORCED 





1 


Equal 








1 


High 











Low 








1 1 


Equal 






TIMING: 


4 Microseconds. 








EXAMPLE: 










PPP-LLL: 


MP1-MP2-MP3-MP4. 


E SEQ. NO. LAB: VERB 


OPERANDS 


COMMENTS 


PI 5-01 6: 
PI 5-020: 


200-020. 
1 53-000. 


09-120. LDA, 
09-130. SAC; 


R#0; OCT: 020. 
000. 


LOAD COND. CODE 
SET COND. HIGH 



39 



•DPL-l 



CLASS 1 



LOAD SENSE SWITCHES 



OBJECT 



154- 



SOURCE 



LSW; 0JOJO. 




DESCRIPTION : 

The load sense switch instruction will load the state of 8 toggle switches 
(located in the switch well under the CRT screen) to the accumulator. Switch 
is loaded to ACC Bit 0, switch 1 to ACC Bit 1, etc. 

TIMING : 4 Microseconds. 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



P15-)922: 
P15-JD24: 



154- 
044-004. 



09-190. 
09-200. 



LSW; 
TMJ, 



+04; OCT: 004. 



LOAD S.S. 
TEST SW. #2 



40 



DPL-1 



CLASS 1 



LOAD PROCESSOR STATUS 



OBJECT 



155- 



SOURCE 



LPS; 0013. 




DESCRIPTION 

This instruction loads a processor status word into the accumulator. The 
following shows the accumulator bits and their respective meaning. 

ACCUMULATOR 



7 6 

Program Interrupt Switch — ' 
(This bit is set whenever 
the program interrupt 
switch is in the interrupt 
position. It is reset when- 
ever the interrupt switch 
is in the neutral position. 
Therefore, this switch could 
also be used as a sense switch.) 

STACK LEVEL 




Stack Pointer Address (Level to 15) 
—•Arithmetic Condition Register (See SAC Inst) 
Interrupt Overflow (See EPI Instruction) 







4 



PA5E LOC. 40 
T^I^INQ ; 4 microseconds 
EXAMPLE : 



A 
C ; G 

^E 



I'O 
7 1 

710 



42 44 46 50 
Current Stack — 



52 



54 
J 



56 60 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



P15-J026: 
P15-J03J0: 
P15-J032: 
P15-J034: 
P15-J036: 
P15-J04p: 
P15-J042: 
P15-JD44: 
P15-J046: 
P15-J05JO: 
P15-J052: 



1 55-jOjOjO 
3JD7-J036 
36jO-jO4j0 
23j0-j0j01 
261 -J0J02 
21 1 -J0j02 
3J0J3-376 

211- 



3JD6-377 
23j0-je)ja3 



*lj0-/)5j0. CALCULATE ADD. OF LAST STACK & BRANCH INST. 

Ij0-J06j0. LPS; jOjOjO. CALCULATE ADDR. 

Ij0-J07j0. SAN, S#7; 0CT:j036. OF CURRENT 

l/)-j08jO. IRA, R#jO; OCT:/)4jO. STACK (LOC.) 

Ij0-j09j0. STA, R#jO; R#l . SAVE IN R#l . 

IjO-ljOjO. SUX, R#l; OCT:jOj02. PREVIOUS STK LV 

IjO-lljO. LDA, I#l; PjOjD. RETRIEVE LOC. 

Ij0-12j0. ANA, R#J0; 0CT:376. FROM PRIOR STK 

1J0-13J0. STA, R#J0; R#2. REMOVE LO BIT 

10-14ja. LDA, R#l; PjOjO. RETRIEVE PAGE 

1J0-15J3. SAN, S#6; 0CT:377. OCTAL FORM-SHFT 

ljg-160. STA, R#jO; R#3. FOR DPL PG R-FM 



41 



•DPL-1 



CLASS 1 



DISABLE PROCESSOR 
INTERRUPT 



OBJECT 



156-0jOjO 



SOURCE 



DPI; 




DESCRIPTION 

The disable processor interrupt instruction will 
branch that occurs upon receipt of an interrupt, 
interrupt. 



inhibit the auto stack and 
It does not disable the 



If the Disable Processor Interrupt (DPI) was executed prior to the Enable 
Processor Interrupt (EPI) Instruction, and the interrupt is activated, the 
interrupt will occur only immediately following the execution of an EPI 
instruction. 

TIMING: 4 Microseconds. 



42 



.DPL-1 



CLASS 1 



ENABLE PROCESSOR INTERRUPT 



OBJECT 



156- 



SOURCE 



EPI; 




DESCRIPTION : 

Within the SYSTEM 4 hardware structure, there are two mechanisms which provide 
for the interrupting of normal instruction processing. 

One is designed primarily for use by the programmer. The Interrupt Switch is 
located in the Switch Well under the CRT screen and can be activated by pushing 
the PROGRAM LOAD Toggle Switch in the opposite direction of the PROGRAM LOAD. 
Another interrupt cannot be generated until the switch is moved to the off 
position and then on again. Also an external interrupt will not be effective 
unless the interrupt switch is off. Two levels of interrupts may be preserved 
by the interrupt logic prior to the execution of an Enable Processor Interrupt 
(EPI) Instruction. Additional interrupts will cause the interrupt overflow 
indicator to be set (see 'LPS' Instruction). 



An external interrupt input is provided for use by external devices, 
activated by a pulse from an external device. 



This is 



For each interrupt (external or program) an EPI Instruction must be previously 
executed. After execution, that level of interrupt will be reset. If the 
interrupt is activated after the execution of the Enable Processor Interrupt (EPI) 
Instruction, an automatic Stack and Branch operation to Section 0, Page 3, 
Location 000 will occur. Therefore, the user program to process the interrupt 
condition must be initialized in Page 03-000. The return to the point of 
interrupt can be effected by an Exit (EXU) instruction to that Stack level. 
(Refer to Stack and Branch Unconditional). 

NOTE: If the Disable Processor Interrupt (DPI) was not executed prior to the 
Enable Processor Interrupt (EPI) Instruction, and the interrupt is 
activated, the interrupt will occur after the execution of the current 
instruction. 



INTERRUPT LOCK OUT 

An interrupt will not occur during any of the following conditions, 
they do not inhibit the interrupt, they simply delay the auto Stack 
until the condition is completed. These conditions are: 

1) Tape movement (Read/Write/Rewind/Search) 



However, 
and Branch 



43 



EPI (cont'd.) 



INTERRUPT LOCK OUT (cont'd.) 



2) If the keyboard is made ready (i.e. by depressing a key and a Read from 
the keyboard has not been executed). In this case, the interrupt will 
occur immediately following the keyboard Read Instruction. 

3) During a Set Section or Set Section and Control operation. 

4) Interrupt Disable has been set (see Disable Processor Interrupt (DPI) 
Instruction). 

TIMING: 4 Microseconds. 



44 



•DPL-1 



CLASS 1 



CLEAR PROCESSOR INTERRUPT 



OBJECT 



1 56-m2 



SOURCE 



CPI; 




DESCRIPTION : 

An interrupt overflow condition occurs when more than two interrupts have been 
activated before the execution of an Enable Processor Interrupt (EPI) in- 
struction. This condition may be tested through the use of the Load Processor 
Status (LPS) Instruction. 

By execution of a Clear Interrupt instruction, the interrupt overflow indicator 
will be cleared. 

TIMING: 4 Microseconds. 



45 



DPL-1 



CLASS 2: TRANSFER 



LOAD ACCUMULATOR 



OBJECT 1 1 SOURCE 


2JD0-LLL 1 1 LDA, R#0; Literal. 
21J0-YXX II LDA, R#jO; AAA+NNN. 
211-YXZjOjO 1 1 LDA, R#X; PPP. 
21I-YXZ1J0 1 1 LDA, I#X; PPP. 
21I-YXZ11 1 1 LDA, D#X; PPP. 
2M-nim 1 LDA, R#X; AAA+NNN. 




WHERE: 

AND: 

AND: 
AND: 

AND: 

AND: 
AND: 



WHERE: 



AND 



2J0J3 is an immediate address 

command. 

LLL is any form of literal 

notation. 

210 is a direct address command. AND 
YXX is an 8-bit location address 
within a level zero page. AND 

211 is an indexed address AND 
command. 

I is any index (1-7). AND 

YXZ is a 6-bit base page 

address. AND 



AND 



R#0 is the immediate or 
direct indicator. 
AAA is a direct address 
page within level #0. 
NNN is a decimal byte dis- 
placement. 

X is any register (1-7). 
PPP is a decimal page 
notation. 

I-Increment register by 001 
after execution. 
D-Decrement register by 001 
after execution. 
R-Register value unchanged 
after execution. 



DESCRIPTION: 



Load the Accumulator with the value specified by the immediate, the direct or the 
indexed address. The immediate form of this instruction provides the means of 
specifying machine values or bit congigurations as part of the instruction. 
Literal terms may be used to specify such program elements as immediate data, 
masks, and addresses. The direct form of this instruction allows the user to 
directly address any level zero page. By supplying the base page as the operand 
and by specifying the index register containing the address displacement within 
that page, the user can address any location within the memory. 

The condition register value remains unchanged after execution of this 
instruction. 



TIMING : 
EXAMPLE 



4 Microseconds when literal form is used. 
6 Microseconds when literal form is not used. 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



PI 5-054: 200-200. 
PI 5-056: 200-066. 
PI 5-060: 200-064. 

PI 5-062: 210-200. 
PI 5-064: 210-007. 

PI 5-066: 213-040. 
PI 5-070: 213-042. 
PI 5-072: 213-043. 



11-030. 
11-040. 

050. 

060. 

070. 

080. 



11 

*11 

11 

11 



*1 1-090. 
11-100. AAA: 
11-110. 
11-120. 



LDA, 
LDA, 
LDA, 

LDA, 
LDA, 

LDA, 
LDA, 
LDA, 



R#0; 
R#0; 
R#0; 

R#0; 
R#0; 

R#3; 
I#3; 
D#3; 



OCT: 200. 
ADL:AAA. 
ADP:AAA. 

128. 

R#7. 

P08. 
P08. 
P08. 



COMMENTS 

IMMEDIATE 
ADDRESSING 



DIRECT 
ADDRESSING 

INDEXED 
ADDRESSING 



46 



.DPL-1 



CLASS 2: DATA TRANSFER LOAD INDEX REGISTER 



OBJECT 



20I-LLL 



SOURCE 



LDX, R#X; Literal. 




WHERE: I is any register (1-7). 

AND: LLL is any form of literal notation. 



DESCRIPTION: 



Load the specified index register with the value indicated by the immediate 
address. The primary use of this instruction is to establish the address 
displacement, within a page, for the indexed addressing instructions. Any 
form of literal notation may be used. 

The condition register value remains unchanged after execution of this 
instruction. 



TIMING: 


4 Microseco 


ads 










EXAMPLE: 














PPP-LLL: 


MP1-MP2-MP3 


-MP4. 


E SEQ. NO. 


LAB: 


VERB 


OPERANDS 


P15-JD74: 


201-JD17. 




11-180. 




LDX, 


R#l; OCT: 01 7 


P15-JD76: 


2JD2-017. 




11-190. 




LDX, 


R#2; DEC:015 


P15-^m^. 


2)2)3-017. 




11-200. 




LDX, 


R#3; HEX:0F. 


PI 5-1 02: 


2m-017. 




12-010. 




LDX, 


R#4; (C). 


P15-1JZ)4: 


205-110. 




12-020. 




LDX, 


R#5; ADL:BBB 


P15-1J36: 


206-102. 




12-030. 




LDX, 


R#6; BBB-06. 


P15-njQ: 


207-066. 




12-040. 


BBB: 


LDX, 


R#7; I DP: BBB 



COMMENTS 



47 



•DPL-l 



CLASS 2. 



LOAD INSTRUCTION ADDRESS 



OBJECT 1 1 SOURCE 


22l-m 1 1 LIA, R#X; jQjO)0. 
22I-LLL 1 1 LIA, R#X; Literal. 

1 1 




WHERE: I is any register (1-7) 

AND: LLL is any form of Literal Notation. 



DESCRIPTION: 



This instruction will transfer the 8 least significant bits of the current in- 
struction address to the specified index register. If the instruction literal 
is 0)00, then the section and page of the current instruction address is trans- 
ferred to the accumulator. If the literal is not 000, then the literal is 
transferred to the accumulator. 



TIMING : 4 Microseconds 
EXAMPLE: 



PPP-LLL: 


MP1-MP2-MP3-MP4. 


E SEQ. NO. 


LAB: VERB 


OPERANDS 


COMMENTS 






*12-lj0)3. 


LOAD INSTRUCTION ADDRESS 


(MAIN ROUTINE) 




^ 


*12-n)3. 


MONITOR, FIXED, NON-RELOCATABLE. 






*1 2-1 2)3. 








P15-112: 


151-2P)3. 


12-13)3. 


SMC; 


C#2. 


SET CONTROL 


P15-114: 


2)31-123. 


12-140. 


MTR: LDX, 


R#l; MTR+)37. 


SET POINTER 


PI 5-1 16: 


231-)364. 


12-15)3. 
*12-16J0. 


STA, 


R#l ; MTR. 


(ACCUM CONTAINS 
PAGE NUMBER) 


PI 5-1 2)3: 


21jO-j3)D6. 


12-17)3. 


LDA, 


R#)3; R#6. 


DATA PAGE 


PI 5-1 22: 


237-mfli' 


12-18)3. 


STA, 


R#7; P)3j0. 


INSERT PAGE 


P15-124: 


14)D-)D)5J0. 


12-19J0. 
*12-20J0. 


EXU; 


J0)3j0. 








*13-)31j0. 


RELOCATABLE SUBROUTINE. 








13-)320. 


ORG: 


PI 4, J0J0)3. 


ACM. CONTAINS PG 


P16-J9j0j0: 


227 -f)m. 


13-)33)3. 


SUB: LIA, 


R#7; nm. 


R#(~ADDR + 1 


PI 6-0)32: 


247-)3)36. 


13-)34)3. 


ADX, 


R#7; OCT: 0)36. 


ADJUST 


P16-)304: 


125-114. 


13-)35)3. 


SBU; 


MTR. 




P16-)DjD6: 


354-j3)32. 


13-)36)3. 
*13-)37)3. 


SBl: CPA, 


I#4; P00. 


PAGE CHANGED 
AT OBJECT-TIME 



48 



•DPL-1 



CLASS 2: DATA TRANSFER STORE ACCUMULATOR 



OBJECT ^ 


1 SOURCE 1 


23J0-YXX 


1 STA, 


R#0; AAA+NNN. 


23I-YXZ00 


i STA, 


R#X; PPP. 


23I-YXZ110 


1 STA, 


I#X; PPP. 


23I-YXZ11 


1 STA, 


D#X; PPP. 


23I-YXZ00 


1 STA, 


RJX; AAA+NNN. 




WHERE: 
AND: 



AND 
AND 
AND 



230 is a direct address command. 
YXX is an 8-bit location address 
within a level zero page. 

231 is an indexed address command. 
I is any index (1-7). 

YXZ is a 6 bit base page address. 



WHERE: 

AND 

AND 
AND 

AND 

AND 

AND 



AAA is a direct address 
page within level #J0. 
NNN is a decimal byte dis- 
placement. 

X is any register (1-7). 
PPP is a decimal page 
notation. 

I-Increment register by jOjOl 
after execution. 
D-Decrement register by JO01 
after execution. 
R-Register value unchanged 
after execution. 



DESCRIPTION: . 



Store the contents of the Accumulator into the address specified by the direct 
or indexed address contained in the instruction operand. The direct form of 
this instruction allows the user to directly address any location within a 
level zero page. By supplying the base page address as the operand and by 
specifying the index register containing the address displacement within that 
page, the user can address any location within the memory, thus performing 
the function of indexed addressing. 

The condition register value remains unchanged after execution of this in- 
struction. 

TIMING: 6 Microseconds. 



EXAMPLE : 














PPP-LLL: 


MP1-MP2-MP3-MP4. 


E SEQ. NO. 


LAB: 


VERB 


OPERANDS 


COMMENTS 


P16-J01JD: 


23je)-144. 


13-14i). 




STA, 


R#J3; 1J0J3. 


DIRECT 


P16-J012: 


23J3-JDJ37. 


13-15J0. 
*13-16JD. 




STA, 


R#J3; R#7. 


ADDRESSING 


P16-jai4: 


231-197)3. 


13-17ja. 




STA, 


R#l; OCC. 


INDEXED 


P16-016: 


231-J037. 


13-18JD. 




STA, 


D#l; P)D7. 


ADDRESSING 


P16-)32JD: 


231-JD36. 


13-190. 


CCC: 


STA, 


I#l; PjD7. 





49 



DPL-1 



CLASS 2: ORDINARY ARITHMETIC ADD TO ACCUMULATOR 



OBJECT 




SOURCE 


240-LLL 


1 I ADA, 


R#0; Literal. 


250-YXX 


1 1 ADA, 


R#0; AAA+NNN. 


25I-YXZ00 


1 1 ADA, 


R#X; PPP. 


25I-YXZ10 


1 1 ADA, 


I#X; PPP. 


25I-YXZ11 


1 1 ADA, 


D#X; PPP. 




WHERE: 

AND; 

AND: 
AND: 



AND 
AND 
AND 



240 is an immediate address 

command. 

LLL is any form of literal 

notation. 

250 is a direct address command. 
YXX is an 8-bit location address 
within a level zero page. 

251 is an indexed address command, 
I is any index (1-7). 

YXZ is a 6-bit base page address. 



DESCRIPTION: 



WHERE: R#0 is the immediate 

or direct indicator. 
AND: AAA is a direct address 

page within level #0. 
AND: NNN is a decimal byte 

displacement. 
AND: X is any register (1-7). 
AND: PPP is a decimal page 

notation. 
AND: I-Increment register by 

001 after execution. 
AND: D-Decrement register by 

001 after execution. 
AND: R-Register value remains 

unchanged after execution. 



Binary add to the Accumulator the value specified by the immediate, the direct, 
of the indexed address. The immediate form of this instruction provides the 
means of specifying machine values or bit configurations as part of the 
instruction. The direct form of this instruction allows the user to directly 
address any level zero page. By supplying the base page address as the 
operand and by specifying the index register containing the address displacement 
within that page, the user can address any location within the memory, thus 
performing the function of indexed addressing. In the event of an overflow 
condition, the overflow character is lost. 

The condition register value remains unchanged after execution of this 
instruction. 



TIMING: 



EXAMPLE: 



4 Microseconds when literal form is used. 
6 Microseconds when literal form is not used. 



PPP-LLL. MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P16-022: 
PI 6-024: 
PI 6-026: 
P16-030: 
P16-032: 



240-004. 
250-12^7. 
253-004. 
253-072. 
253-007. 



14-060. 
14-070. 
14-080. 
14-090. 
14-100. 



DDD: 



ADA, 
ADA, 
ADA, 
ADA, 
ADA, 



R#0; (1). 

R#0; R#7. 

R#3; P01. 

I#3; DDD. 

D#3; P01. 



COMMENTS 

ADD IMMEDIATE 
ADD DIRECT 
ADD INDEXED 



50 



.DPL-1 



CLASS 2: ORDINARY ARITHMETIC 



ADD TO INDEX 
REGISTER 



OBJECT 



24I-LLL 



SOURCE 



ADX, R#X; Literal. 




WHERE: I is any register (1-7) 

AND: LLL is any form of literal notation. 



DESCRIPTION: 



Binary add to the index register specified, the value indicated by the immed- 
iate address. In the event of any overflow condition, the overflow character 
is lost. 

The condition register value remains unchanged after execution of this 
instruction. 

TIMING : 4 Microseconds. 

EXAMPLE : 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P16-J034: 241-jt)j04. 
P16-036: 242-j3)a4. 
P16-)Z)4)D: 243-372. 



14-16)0. EEE: ADX, R#l ; (1). 
14-17)3. ADX. R#2; OCT:jOj04. 

14-180. ADX, R#3; HEX:FA. 



COMMENTS 

BINARY ADD 
TO INDEX 
REGISTER 



51 



•DPL-1 



CLASS 2: ORDINARY ARITHMETIC 



SUBTRACT FROM 
ACCUMULATOR 



OBJECT 1 1 SOURCE 


260-LLL ' ' SUA, R#]0; Literal. 
27)5- YXX ' ' SUA, R#jO; AAA+NNN. 
27I-YXZJO0 ! ' SUA, R#X; PPP. 
27I-YXZ1J5 I SUA, I#X; PPP. 
27I-YXZ11 SUA, D#X; PPP. 




WHERE: 

AND: 

AND: 
AND: 



AND 
AND 
AND 



26]D is an immediate address 

command. 

LLL is any form of literal 

notation. 

27)9 is a direct address command. 

YXX is an 8-bit location address 

within a level zero page. 

271 is an indexed address command. 

I is any index (1-7) 

YXZ is a 6-bit base page address. 



WHERE: R#0 is the immediate or 
direct indicator. 

AND: AAA is a direct address 
page within level #J0. 

AND: NNN is a decimal byte dis- 
placement. 

AND: X is any register (1-7) 

AND: PPP is a decimal page no- 
tation. 

AND: I-Increment register by JO01 
after execution. 

AND: D-Decrement register by J301 
after execution. 

AND: R-Register value unchanged 
after execution. 



DESCRIPTION: 



Binary subtract from the Accumulator, the value specified by 
direct or the indexed address. The immediate form of the in 
the means of specifying machine values or bit configuration 
struction. The direct form of this instruction allows the u 
address any location within a level zero page. By supplying 
address as the operand and by specifying the index register 
address displacement within that page, the user can address 
the memory, thus performing the function of indexed addressi 
plement results from an underflow condition. The condition 
remains unchanged after execution of this instruction. 



the immediate, the 
struction provides 
as part of the in- 
ser to directly 

the base page 
containing the 
any location within 
ng. The two's com- 
register value 



TIMING: 


4 Microseconds when literal 
6 Microseconds when literal 


form 
form 


is used, 
is not used. 




EXAMPLE: 










PPP-LLL: 


MP1-MP2-MP3-MP4. E SEQ. NO. 


LAB: 


VERB OPERANDS 


COMMENTS 


P16-m2: 
P16-ja44: 
P16-JD46: 
P16-)a5jD: 


26)9-jDjD4. 15-je)4jO. 
27JD-J0JD7. 15-JD5J0. 
273-J0JD4. 15-J06J0. 
273-j37j3. 15-)370. 


FFF: 


SUA, R#0; (1) 
SUA, R#7. 
SUA, R#3; PjJIl 
SUA, R#3; FFF. 


SUB. IMMED. 
SUB. DIRECT 
SUB. INDEXED 



52 



•DPL-1 CLASS 2: ORDINARY ARITHMETIC 



SUBTRACT FROM INDEX 
REGISTER 



OBJECT 



-H- 



SOURCE 



I I 
i i 
26I-LLL I I SUX, R#X; Literal. 

I I 



SUX 



WHERE: I is any register (1-7). 

AND: LLL is any form of literal notation. 

DESCRIPTION : 

Binary subtract from the index register specified, the value indicated by the 
immediate address. The two's complement results from an underflow condition. 
The condition register value remains unchanged after execution of this 
instruction. 

TIMING : 4 Microseconds. 

EXAMPLE : 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P16-J052: 
P16-J054: 
P16-J056: 
PI 6-jD6)D. 



261-]e)J04. 

262- fum. 

262-J017. 
263-144. 



15. 
15' 
15' 
15' 



■ISjO. 
•14jO. 
•15j0. 
•16jO. 



GG6; 



SUX, 
SUX, 
SUX, 
SUX, 



R#l; 
R#2; 
R#2; 
R#3; 



(1). 

OCT:j0j34. 
HEX:|3F. 
DEC: 100. 



COMMENTS 

BINARY 

SUBTRACT FROM 
INDEX REG. 



53 



•DPL-1 



CLASS 3: 

BOOLEAN ARITHMETIC 



LOGICAL "AND" TO 
ACCUMULATOR 



OBJECT 1 


SOURCE 1 


3jD)ei-LLL 1 
31J0-YXX 1 
311-YXZjOjD 1 
311-YXZljO 1 
31I-YXZ11 1 


ANA, 
ANA, 
ANA, 
ANA, 
ANA, 


R#0; Literal. 
R#jO; AAA+NNN. 
R#X; PPP. 
I#X; PPP. 
D#X; PPP. 




WHERE: 

AND: 

AND: 
AND: 

AND: 
AND: 
AND: 



30)0 is an immediate address 

command. 

LLL is any form of literal 

notation. 

310 is a direct address command. 
YXX is an 8-bit location address 
within a level zero page. 

311 is an indexed address command, 
I is an index (1-7). 

YXZ is a 6-bit base page address. 



DESCRIPTION: 



WHERE: R#jO is the immediate or 
direct indicator. 

AND: AAA is a direct address 
page within level #0. 

AND: NNN is a decimal byte dis- 
placement. 

AND: X is any register (1-7). 

AND: PPP is a decimal page 
notation. 

AND: I- Increment register by 0JO1 
after execution. 

AND: D-Decrement register by JO01 
after execution. 

AND: R-Register value remains un- 
changed after execution. 



Logical "and" to the Accumulator the value specified by the immediate, direct or 
indexed address. The immediate form of this instruction provides the means of 
specifying machine values of bit configurations as part of the instruction. The 
direct form of this instruction allows the user to directly address any level 
zero page. By supplying the base page address as the operand and by specifying 
the index register containing the address displacement within that page, the 
user can address any location within the memory, thus performing the function of 
indexed addressing. The value of the operand is treated as an unstructured 
logical quantity, and the value is applied bit by bit to the Accumumulator. The 
bit position in the result (Accumulator) is set to one if the corresponding bit 
positions in the Accumulator and the operand both contain a one; otherwise, the 
result bit is set to zero. (Result is one if both are ones). All operand values 
and results are valid. The condition register value remains unchanged after 
execution of this instruction. 



TIMING: 



EXAMPLE: 



4 Microseconds when literal form is used. 
6 Microseconds when literal form is not used. 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



P16-J362: 
P16-062: 
P16-J066: 
P16-J07J0: 
P16-072: 



300-025. 
310-007. 
314-030. 
314-032. 
314-033. 



*1 6-020. 
16-030. 
16-040. 
16-050. 
15-060. 
16-070. 



LOGICAL "AND" TO ACCUMULATOR. 



ANA, R#0; OCT: 026. 

ANA, R#0; R#7. 

ANA, R#4; P06. 

ANA, I#4; P05. 

ANA, D#4; P06. 



IMMEDIATE 
DIRECT 
INDEXED 
ADDRESSING 



54 



•DPL-1 



CLASS 3: 

BOOLEAN ARITHMETIC 



SHIFT & LOGICAL "AND" TO 
ACCUMULATOR 



OBJECT 



SOURCE 



3JSI-LLL i i SAN, S#X; Literal 

I I 
I I 
I I 

LL 



SAN 



WHERE: I is the bit shift count (1-7), 
AND: LLL is any literal notation. 

DESCRIPTION: 



WHERE: X is the bit shift count (1-7). 



This form of the logical "and" instruction performs a right circular shift of 
the bits in the Accumulator, by the number of bits specified in the shift counter, 
before the logical "and" of the literal to the Accumulator is performed. 

All literal values and results are valid. The condition register value remains 
unchanged after the execution of this instruction. 

TIMING: 4 Microseconds. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 

P16-074: 303-026. 



COMMENTS 



*16-12j0. SHIFT AND LOGICAL "AND" TO ACCUMULATOR. 
16-13)0. SAN, S#3; OCT:026. 



.1 1 JQ 0..1 1. 



'1 jO 1 ^ 1 
jO 1 1 1 
1 



Initial Accumulator Value 



Accumulator Value after a Shift of 3. 

Literal Value 

Accumulator Value after the logical "AND" of OCT: 025. 



55 



DPL-1 



CLASS 3: 

BOOLEAN ARITHMETIC 



EXCLUSIVE "OR" TO ACCUMULATOR 



OBJECT 1 


SOURCE 1 


320-LLL 1 


ERA, 


R#)ZI; Literal. 


330-YXX 1 


ERA, 


R#jO; AAA±NNN. 


33I-YXZ00 1 


ERA, 


R#X; PPP. 


331-YXZljZ) 1 


ERA, 


I#X; PPP. 


33I-YXZ11 1 


ERA, 


D#X; PPP. 




WHERE: 
AND: 
AND: 
AND: 

AND: 

AND: 
AND: 



320 is an immediate WHERE: 

address command. 

LLL is any form of AND: 

literal notation. 

33ja is a direct AND: 

address command. 

YXX is an 8-bit location AND: 

address within a level AND: 

zero page. AND: 

331 is an indexed 

address command. AND: 

I is an index (1-7). 

YXZ is a 6-bit base AND: 

page address. 



R#0 is the immediate or direct 

indicator. 

AAA is a direct address page within 

level zero. 

NNN is a decimal byte displacement 

X is any register (1-7). 

PPP is a decimal page notation. 

I-Increment register by 001 after 

execution. 

D-Decrement register by 001 after 

execution. 

R-Register value remains unchanged 

after execution. 



DESCRIPTION : 

Exclusive "or" to the Accumulator the value specified by the immediate, direct 
or indexed address. The immediate form of this instruction provides the means 
of specifying machine values or bit configurations as part of the instruction. 
The direct form of this instruction allows the user to directly address any 
level zero page. By supplying the base page address as the operand and by 
specifying the index register containing the address displacement within that 
page, the user can address any location within the memory. The value of the 
operand is treated as an unstructured logical quantity, and the value is 
applied bit by bit to the Accumulator. A bit position in the result 
(Accumulator) is set to one if the corresponding bit positions in the 
accumulator and as specified by the operand, are unlike; otherwise, the result 
bit is set to zero. (Result is one if unlike). All operand values and results 
are valid. The condition register value remains unchanged after execution of 
this instruction. 



TIMING: 


4 Microseconds when literal 


form is used. 






6 Microseconds when literal 


form is not used. 




EXAMPLE: 








PPP-LLL: 


MP1-MP2-MP3-MP4. E SEQ. NO. 


LAB: VERB OPERANDS 


COMMENTS 




*^7-mfi. 


EXCLUSIVE "OR" TO ACCUMULATOR 


P16-je)76: 


32J0-J026. 17-J07jO. 


ERA, R#0; OCT: 026. 


IMMEDIATE 


P16-1J0J3: 


33i3-j0jD7. 17-J08J0. 


ERA, R#0; R#7. 


DIRECT 


P16-lje)2: 


334-JD3J3. 17-JD9J0. 


ERA, R#4; P06. 


INDEXED 


P16-1JD4: 


334-JD32. 17-ljOjO. 


ERA, I#4; P06. 


ADDRESSING 


P16-1)D6: 


334-JZI33. 17-110. 


ERA, D#4: Pj06. 





56 



•DPL-1 



CLASS 3: BOOLEANE ARITHMETIC SHIFT AND "EOR" 

ACCUMULATOR 



OBJECT 



-H- 



SOURCE 



09T_I I 1 

\JI- X ~UUL. 



SER, S#X; Literal 




WHERE: I is the bit shift count (1-7). 
AND: LLL is any literal notation. 



DESCRIPTION: 



WHERE: X is the bit shift count (1-7) 



This form of the exclusive "or" instruction performs a right circular shift of 
the bits in the Accumulator, by the number of bits specified in the shift 
counter, before the exclusive "or" of the literal to the Accumulator is per- 
formed. All literal values and results are valid. The condition register 
value remains unchanged after execution of this instruction. 

TIMING: 4 Microseconds 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



P16-lliD: 327-jZ)26. 



.1,1 JZ) P J 


3 1 jD 1. 






, — J= 


^r^ 



*17-16ja. SHIFT AND "EOR" ACCUMULATOR 
17-17J0. SER, S#7; 0CT:je)26. 



Initial Accumulator Value 



1 jO ja 1 ^ 1 1 
jD JD 1 1 1 ja 
1 j3 JD 1 1 1 j3 1 



Accumulator Value after a Shift of 7. 

Literal Value 

Accumu.lator Value after the exclusive "OR" of OCT:026. 



57 



DPL-1 



CLASS 3: 

BOOLEAN ARITHMETIC 



INCLUSIVE "OR" TO ACCUMULATOR 



OBJECT 1 


SOURCE 1 


360-LLL 1 


IRA, 


R#0; Literal. 


370-YXX 1 


IRA, 


R#J0; NNN. 


370-YXX 1 


IRA, 


R#)a; AAAiNNN. 


37I-YXZ00 1 


IRA, 


R#X; PPP. 


37I-YXZ10 1 


IRA, 


I#X; PPP. 


371-YXZn 1 


IRA, 


D#X; PPP. 




WHERE: 
AND: 
AND 
AND 

AND: 

AND: 
AND: 



360 is an immediate address 

command. 

LLL is any form of literal 

notation. 

370 is a direct address 

command. 

YXX is an 8-bit location 

address within a level zero 

page. 

3"! is an indexed address 

command. 

I is an index (1-7). 

YXZ is a 6-bit base page 

address. 



WHERE: R#0 is the immediate or direct 

indicator. 
AND: AAA is a direct address page 

within level zero. 
AND: NNN is a decimal byte displacement 

AND: X is any register (1-7). 

AND: PPP is a decimal page notation. 

AND: I-Increment register by 001 

after execution. 
AND: D-Decrement register by 001 

after execution. 
AND: R-Register value remaining 

unchanged after execution. 



DESCRIPTION: 



Inclusive "or" to the accumulator the value specified by the immediate, direct, 
or indexed address. The immediate form of this instruction provides the means 
of specifying machine values or bit configurations as part of the instruction. 
The direct form of this instruction allows the user to directly address any 
level zero page. By supplying the base page address as the operand and by 
specifying the index register containing the address displacement within that 
page, the user can address any location within the memory. The value of the 
operand is treated as an unstructured logical quantity, and the value is ap- 
plied bit by bit to the accumulator. A bit position in the result (accumulator) 
is set to one if the corresponding bit position in the accumulator or as 
specified by the operand, either contain a one; otherwise, the result bit is 
set to zero. (Result is one if either are one). All operand values and results 
are valid. The condition register value remains unchanged after execution of 
this instruction. 



TIMING: 



EXAMPLE: 



4 Microseconds when literal form is used. 
6 Microseconds when literal form is not used. 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



P16- 
P16- 
P16- 
P16- 
P16- 



112: 
114: 
116: 
12jO: 
122: 



36j0- 
37j0- 
374- 
374- 
374- 



026. 

mi. 

J03J0. 
032. 
J033. 



*18-ljO0. 
18-lljO. 
18-120. 
18-130. 
18-140. 
18-1 5j0. 



INCLUSIVE "OR" TO ACCUMULATOR. 



IRA, R#0 

IRA, R#JD 

IRA, R#4 

IRA, I#4 

IRA, D#4 



0CT:JD26. 

R#7. 

PJ06. 

P06. 

PJ06. 



IMMEDIATE 
DIRECT 
INDEXED 
ADDRESSING 



58 



"DPL-l 



CLASS 3: BOOLEAN ARITHMETIC 



SHIFT AND "lOR" 
TO ACCUMULATOR 



OBJECT 1 1 SOURCE 


36I-LLL 1 : SIR, S#X; Literal. 
1 i 




WHERE: 
AND: 



I is the bit shift count. 
LLL is any literal notation. 



WHERE: X is the bit shift count. 



DESCRIPTION : 

This form of the inclusive "or" instruction performs a right circular shift of 
the bits in the Accumulator, by the number of bits specified in the shift counter * 
before the inclusive "or" of the literal to the Accumulator is performed. All 
literal values and results are valid. The condition register value remains un- 
changed after execution of this instruction. 

TIMING: 4 Microseconds. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 

PI 6-1 24: 364-026. 



COMMENTS 



*18-2]0j3. SHIFT AND INCLUSIVE "OR" TO ACCUMULATOR. 
19-01j8. SIR, S#4; OCT:j026. 



1 1 ja JO JD 1 JD 1 



JO 1 JO 1 1 1 JO )J) 
)3 j8 JO 1 j8 1 1 JO 
jD 1 1 1 1 1 JO 



Initial Accumulator Value 



Accumulator Value after a Shift of 4 

Literal Value 

Accumulator Value after the inclusive "OR" of OCT:026. 



59 



DPL-1 



CLASS 3: COMPARE 



COMPARE ACCUMULATOR 



OBJECT 


1 SOURCE 1 


3419- LLL 


1 CPA, 


R#0; Literal. 


350-YXX 


1 CPA, 


Rm AAAiNNN. 


35I-YXZ0JZ) 


1 CPA, 


R#X; PPP. 


35I-YXZ10 


1 CPA, 


I#X; PPP. 


351-YXZn 


1 CPA, 
1 


D#X; PPP. 




WHERE: 340 is an immediate address WHERE: 

command. 
AND: LLL is any form of literal AND: 

notation. 
AND: 35ja is a direct address AND: 

command. 
AND: YXX is an 8-bit location ad- AND: 

dress within a level zero AND: 

page. AND: 

AND: 351 is an indexed address 

command. AND: 

AND: I is any index (1-7). 
AND: YXZ is a 6- bit base page AND: 

address. 



R#0 is the immediate or direct 

indicator. 

AAA is a direct address page within 

level zero. 

NNN is a decimal byte displacement 

X is any register (1-7). 

PPP is a decimal page notation. 

I-Increment register by 001 after 

execution. 

D-Decrement register by 001 after 

execution. 

R-Register value unchanged after 

execution. 



DESCRIPTION : 

Compare the contents of the Accumulator to the value specified by the im- 
mediate, direct or indexed address. The immediate form of this instruction 
provides the means of specifying machine values or bit configurations as part 
of the instruction. The direct form of this instruction allows the user to 
directly address any level zero page. By supplying the base page address as 
the operand and by specifying the index register containing the address dis- 
placement within that page, the user can address any location within the 
memory. The character in the Accumulator is not altered. The condition reg- 
ister value is changed to reflect the high, low or equal result of the compare 
instruction. Once set, the condition register remains unchanged until mod- 
ified by an instruction that reflects a different condition code. 



TIMING: 


4 Microseconds 


when literal 


form 


is us 


ed. 






6 Microseconds 


when literal 


form 


is not used. 




EXAMPLE: 














PPP-LLL: 


MP1-MP2-MP3-MP4. E SEQ. NO. 


LAB: 


VERB 


OPERANDS 


COMMENTS 


P16-126: 


34J0-J026. 


19-15JD. 




CPA, 


m-, (J). 


IMMEDIATE 


P16-13J0: 


350-jajO7. 


19-16J0. 




CPA, 


R#J0; R#7. 


DIRECT 


P16-132: 


34J0-136. 


19-17J0. 




CPA, 


R#J0; ADL:CPT. 




P16-134: 


354-JO3J0. 


19-18/). 




CPA, 


R#4; P)Z)6. 


INDEXED 


P16-136: 


354-)332. 


19-190. 


CPT: 


CPA, 


I#4; Pj06. 


ADDRESSING 


P16-14J0: 


354-J033. 


19-2jOjO. 




CPA, 


D#4; Pj06. 





60 



•DPL-1 



CLASS 3: COMPARE 



COMPARE INDEX REGISTER 



OBJECT 1 1 SOURCE 


34I-LLL i ' CPX, R#X; Literal. 




WHERE: I is any index register (1-7). WHERE: X is any register (1-7). 
AND: LLL is any literal notation. 

DESCRIPTION : 

Compare the contents of the index register specified to the byte of immediate 
data (literal). Comparison is binary, and all codes are valid. The value of 
the index register is not altered. 

The condition register value is changed to reflect the high, low, or equal re- 
sult of the compare instruction. Once set, the condition register remains un- 
changed until modified by an instruction that reflects a different condition 
code. 

TIMING : 4 Microseconds. 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P16-142: 343-0106. 
P16-144: 343-146. 



20-jZ)6/). CRT: CPX, R#3; (3). 
20-JD7JD. CPX, R#3; CRT+04. 



COMMENTS 

IMMEDIATE 
ADDR. LOC. 



61 



•DPL-2 



GROUP 1: I/O 



GET DATA (READ) 



OBJECT 1 1 


SOURCE 


J017-YXX-J5XX-YXX 1 1 
jZ)17-YXX-2XX-YXXI 1 
jD17-YXX-]D12-YXXl 1 


GET; NNN, T#N, MMM. 
GET; NNN, M#N, MMM. 
GET; NNN, KBD, MMM. 




WHERE: 
AND: 



AND: 



NNN is the decimal size. 

T#N, M#N, or KBD is the device number 

of the Mini -Tape, the Maxi-Tape, or 

the Keyboard, respectively. 

MMM is the left-most high order decimal 

address of the receiving field. 



DESCRIPTION: 



A Read operation is initiated at the I/O device, and the data is transferred 
from the device into memory. Page destination is initially set to 01 but may 
be changed with a SET PAGE Instruction. The Page remains at this setting until 
a different SET PAGE Instruction is executed. Any data continuing past a Page 
boundary will be wrapped around to the beginning of the Page. 

MAXI-TAPE : 

When retrieving records from Maxi-Tape, the same number of bytes as contained in 
the tape record must be specified by the size operand within the instruction. 
The size may be up to 256 bytes for Maxi-Tape. Data is placed in memory in 
ascending order of addresses within the "Into" Page which is currently set, 
starting with the address specified in the instruction. 

MINI-TAPE : 

When retrieving records from Mini -Tape, the physical record length must be 136 
bytes. The standard Mini-Tape record is comprised of an 8-byte label, generated 
by the Mini -Write software function, followed by 128 bytes of data. Because the 
label is generated by the software and not by the user, it is not included in 
the record size operand. Therefore, when reading the standard Mini -Tape record, 
specify 128 (number of data bytes) as the size. Although a Mini-Tape record 
may contain a maximum of 128 bytes of data, it may be desirable to read a lesser 
number of characters into the input buffer. By specifying a lesser number in the 
size operand, only the number of characters specified will be stored into the 
I/O area indicated by the user. The remainder of the record will be read and 
used to check for tape errors and CRC Check but these characters will not be 
stored into the I/O Buffer. The 8-byte label is automatically read into Page 00 
Locations 0308 thru 0378. The data portion of the record is placed in memory in 
ascending order of addresses within the "Into" Page which is currently set, 
starting with the address specified in the instruction. An automatic sequence 
check is made on the first byte of the label. If the record contains the wrong 
sequence number (i.e. a record was skipped), the error condition will be set. 



62 



GET (cont'd.) 



KEYBOARD 



When retrieving data from the keyboard, the same number of bytes as contained 
in the size operand must be entered. The keyboard Supervisor provides for 
corrections to be made to data entered. By depressing the "CORR" key on the 
keyboard, the point of entry will be backspaced one location within the current 
Page. The size operand may specify up to 256 bytes for the keyboard operation. 
Data is placed in memory in ascending order of addresses within the "Into" Page 
which is currently set, starting with the address specified in the instruction. 

Device assignment is as follows: 



DDD 


DEVICE NAME 


SYMBOLIC CODE 


OBJECT CODE 


Standard 
Pair 1 


Mini -Tape 1 
Mini -Tape 2 


T#l 
T#2 


J0J31 
JDJ2)2 


Optional 
Pair 2 


Mini -Tape 3 
Mini -Tape 4 


T#3 
T#4 


J0j03 
JOJ04 


Optional 
Pair 3 


Mini -Tape 5 
Mini -Tape 6 


T#5 
T#6 


m 


Optional 
Pair 4 


Mini -Tape 7 
Mini -Tape 8 


T#7 
T#8 


jaija 




Keyboard 


KBD 


012 




Maxi -Tapes 


M#N 


2px 



EXAMPLE; 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



PI 5-, 

P15- 

P15-jDlje): 

P15-je)14: 

PI 5-02^: 

P15-ja24: 



P15-J33J0: 14jO- 



15jO-jOj3ja-122-jOj04. jOl-ljOjO. 

JDJO5-JO06-012-J066. J91-llj0. 

jai7-2jOjD-jOj01-J0jDJD. j91-12jD. 

)ajD4-i2)J2n-017-W. JD1-13J0. 

j0]D4-0)34-017-144. 01-14jO. 

15jD-)31j0-ljD5-03jZI. J01-15JD. 

jOl-160. 



ENT: 
SET; 
GET; 
SEL; 
SEL; 
ENT: 



DPL-3. 

PAG:Fj01,Tj02. 

128,T#1, 

L0W,P15, 

HGH,P15,1) 

DPL-1 . 



EXU; JD00. 



SET PAGE 
READ INTO PG2 
EOC RECORD? 
TAPE ERROR? 
RECORD OK 
RETURN 



63 



•DPL-2 



GROUP 1: I/O 



PUT DATA (WRITE) 



OBJECT 1 1 SOURCE 


]027-YXX-YXX-jOXX ' ' PUT; NNN, MMM, T#N. 
JD27-YXX-YXX-2XX M PUT; NNN, MMM, M#N. 
027-YXX-YXX-JD13 1 1 PUT; NNN, MMM, PRT. 




WHERE: 
AND: 



AND: 



NNN is the decimal size. 

MMM is the left-most high order 

decimal address of the sending 

field. 

T#N, M#N, or PRT is the device 

number of the Mini -tape, the Maxi- 

tape, or the Printer; respectively. 



DESCRIPTION: 



A Write operation is initiated at the I/O device, and the data is transferred 
from memory to the device. The Page source is initially set to 01, but may be 
changed with a SET PAGE Instruction. The Page remains at this setting until a 
different SET PAGE Instruction is executed. Data can be written from any 
Location within a Page. Any data continuing past the Page boundaries, based on 
the size operand, will be wrapped around to the beginning of the Page. 

MAX I -TAPE : 

When writing records to Maxi-Tape, the actual number of bytes desired to be 
written must be specified by the size operand within the Instruction. The size 
may be up to 256 bytes for Maxi-Tape. Data in memory is fetched in an ascending 
order of addresses, within the "From" Page which is currently set, starting with 
the address specified in the Instruction. 

MINI-TAPE : 

When writing records to Mini -Tape, the physical record length will be 136 bytes. 
The standard Mini-Tape record is comprised of an 8-byte label, generated by the 
software function, followed by 128 bytes of data. Because the label is generated 
by the software and not by the user, it is not included in the record size 
operand. Therefore, when writing'the Standard Mini-Tape record, specify 128 
(number of data bytes) as the size. Although a Mini -Tape record may contain a 
maximum of 128 bytes of data, it may be desirable to write a lesser number of 
characters from the input buffer. By specifying a lesser number in the size 
operand, only the number of characters specified will be written from the I/O 
area indicated by the user. The remainder of the record will contain Octal 
zeroes. Thie complete 136 byte record will be used to check for tape write 
errors. 



64 



PUT (cont'd.) 



MINI -TAPE (cont'd.) 



The 8-byte label is automatically written from Page 00 locations OSOs thru 
037o. The record sequence number is automatically generated by the Mini- 
Write software function. The remainder of the label may be controlled by the 
user. The data portion of the record is written from memory in ascending 
order of addresses within the "From" Page which is currently set, starting 
with the address specified in the Instruction. 

PRINTER : 

When printing, the actual number of bytes desired to be printed must be 
specified by the size operand within the Instruction. The size may be up 
to 256 characters. Data in memory is fetched in an ascending order of add- 
resses, within the "From" Page which is currently set, starting with the 
address specified in the Instruction. 

In order to execute a control command for the Print Function as part of the 
data, the control byte must have the high-order bit present (Ref . I/O 
Instruction) (i.e. to execute an "Index Function for the typewriter, 
either execute PCL; Pjai , PRT, lOX, or Place OCTAL 212 as a character in 
the print buffer). 

There will be an automatic Carriage Return after each print command. 

Device assignment is as follows: 



ODD 


DEVICE NAME 


SYMBOLIC CODE 


OBJECT CODE 


Standard 
Pair 1 


Min" 
Mini 


-Tape 1 
-Tape 2 


T#l 
T#2 


J0J01 
j0jD2 


Optional 
Pair 2 


Min- 
Mim 


-Tape 3 
-Tape 4 


T#3 
T#4 


J0J93 

fum 


Optional 
Pair 3 


Min- 
Mini 


-Tape 5 
-Tape 6 


T#5 
T#6 


JOJ06 


Optional 
Pair 4 


Min- 
Mim 


-Tape 7 
-Tape 8 


T#7 
T#8 


m7 
mm 




Printer 


PRT 


iD13 




Maxi -Tapes 


M#N 


2jax 



65 



PUT (cont'd.) 



EXAMPLE ; 



PPP-LLL: 


MP1-MP2-MP3-MP4. 


E SEQ. NO. 


LAB: VERE 


5 OPERANDS 


COMMENTS 


P15-J032: 


150-000-122-004. 


02-020. 


ENT 


DPL-3. 




PI 5-036: 


005-056-006-066. 


02-030. 


SET" 


, PAG:F11,T01. 


SET PAGE 


PI 5-042: 


027-200-000-001 . 


02-040. 


PUT: 


, 128,000,T#1. 


WRITE 


PI 5-046: 


004-001-017-000. 


02-050. 


SEL' 


, LOW, PI 5,000. 


EOF(REF.SPOT) 


PI 5-052: 


004-004-017-144. 


02-060. 


SEL: 


, HGH,P15,100. 


TAPE ERROR? 


PI 5-056: 


150-010-105-062. 


02-070. 


ENT: 


DPL-1 . 


RECORD OK 


PI 5-062: 


140-000. 


02-080. 


EXU: 


. 000. 


RETURN 



66 



GET & PUT 



LINKAGE: 



The GET or PUT Functions may be used in a DPL-1 context in conjunction with 
the Pseudo (ENT:IOS) or it may be used in a DPL-3 context (ENT:DPL-3). 

RETURN STATUS (DPL-3) 

If the software condition value (POO-377) is "=", function good. 

If the software condition value (POO-377) is ">", tape 8-retry error 
(or Read Sequence error). 

If the software condition value (POO-377) is "<", file mark read. 

The above conditions may be tested by the software by using the "SEL;" 
commands. 

Location POO-0178 contains the Status Byte - Refer to the Instruction Reference 
Cards for Error Conditions. 

Return Status (IGS) 

The return from ENTiIOS will set the status in the hardware condition 
register and can be tested using DPL-1 corresponding to the above conditions. 



67 



•DPL-2 



GROUP 2: DATA MODIFY 



MOVE 
STORAGE TO STORAGE 



OBJECT 



037-YXX-YXX-YXX 



SOURCE 



MOV; NNN, AAA, BBB. 




WHERE: 


NNN is 


the decimal size. 


AND: 


AAA is 


a decimal or symbolic 




"from" 


address. 


AND: 


BBB is 


the decimal or symbolic 




"into" 


address. 



DESCRIPTION : 

The DPL-2 move instruction is used for a storage-to-storage move where the data 
specified by the A-operand is moved to the address specified by the B-operand 
address. In storage-to-storage movement the fields may overlap in any desired 
way. Movement is left to right through each field a byte at a time. 

The "from" and "into" page are initialized as page one. To move "from" a page, 
or "into" a page other than page one, a SET PAGE instruction must have been 
previously executed. The page remains at this setting until a different SET 
PAGE instruction is executed. 

The A-operand and the B-operand may be within the same page or in different pages, 
Any data continuing past page boundaries will be wrapped around to the beginning 
of the page. 

The software condition value remains unchanged. 

The hardware condition register is inpredictable after execution of any in- 
struction executed in DPL-3 or lOS Mode. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



PI 5-064: 150- 

Pl 5-070: 005-012- 

PI 5-074: 037-012- 



122- 

006-066. 

040-040. 



02-1 5j&. 
02-160. 
02-170. 



ENT: DPL-3. 

SET; PAG:F02,T01. 

MOV; 010,032,032. 



COMMENTS 

MOVE 10 CHAR. 
FROM PAGE 2 
TO PAGE 1 



68 



•DPL-2 



GROUP 2: DATA MODIFY 



ADD STORAGE- 
TO-STORAGE 



OBJECT 



TT 



SOURCE 



I I 

JD47-YXX-YXX-YXX ' ' ADD; NNN, AAA, BBB. 

I I 
I I 

U 




DESCRIPTION: 



WHERE: NNN is the decimal size. 

AND: AAA is a decimal or symbolic addend 

1 address. 

AND: BBB is a decimal or symbolic addend 

2 address. 
(AAA+BBB)=BBB 



The ADD command adds a decimal value specified by the A-operand to a decimal 
value specified by the B-operand for the number of bytes indicated by the size 
operand. The A-operand value and the B-operand value must be the same size. The 
A-operand value and the B-operand value may contain a sign although it is not in- 
cluded in the size count. Addition is algebraic. The results of the addition 
displaces the previous contents of the B-operand field and any overflow character 
is lost. The octal value of 001 (-) is the minus sign. Any other value is 
assumed to be positive. If the A-operand field contains a minus sign, a sign 
position must be reserved in the result field. 

The A-operand field and the B-operand field may be within the same page or 
different pages as specified by a Set Page instruction. 

The software condition value is unchanged. 

The hardware condition register is unpredictable after execution of any in- 
struction executed in DPL-3 or lOS Mode. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 

P15-llOjO: 047-J003-J0iOjO-lJ00. 03-040. ADD; 003,000,064. 

*03-050. 

*03-060. 600 + (B-OPERAND) 

*03-070. 200 - (A-OPERAND) 
*03-080. 

*03-090. 400 + (B-OPERAND RESULT) 



COMMENTS 



69 



•DPL-2 



GROUP 2: DATA MODIFY 



SUBTRACT STORAGE- 
TO-STORAGE 



OBJECT 



057-YXX-YXX-YXX 



SOURCE 



SUB; NNN, AAA, BBB. 




WHERE: NNN is the decimal size. 
AND: AAA is a decimal or symbolic 

subtrahend address. 
AND: BBB is a decimal or symbolic 

minuend address. 

(BBB-AAA) = BBB 



DESCRIPTION; 



The SUB command subtracts a decimal value specified by the A-operand from a 
decimal value specified by the B-operand. The A-operand value and the B-operand 
value must be the same size. 

The A-operand value and the B-operand value may contain a sign, although it is 
not included in the size count. Subtraction is algebraic. The result of the 
subtraction displaces the previous contents of the B-operand field and any 
overflow character is lost. 



The octal value of 0JO1 (-) is the minus sign. Any other value is assumed to be 
positive. A sign position must be reserved in the result field. 

The A-operand and the B-operand fields may be within the same page or different 
pages as specified by a set page instruction. 

The software condition value is unchanged. 

The hardware condition register is unpredictable after execution of any in- 
struction executed in DPL-3 or lOS Mode. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. 1^0. LAB: VERB OPERANDS 

P15-1J04: J557-JDJD3-)3JDJD-1J0)3. J)3-150. SUB; 0)D3,jO)DjO,jO64. 

*^3-16ja. 

*J03-17)D. 2j0jD - (B-OPERAND) 

*03-180. 1JO0 + (A-OPERAND) 
*03-19j3. 

*je)3-2jDjO. 3m - (B-OPERAND RESULT) 



COMMENTS 



70 



.DPL-2 



GROUP 2: DATA MODIFY 



MULTIPLY 



OBJECT 1 1 SOURCE 


067-YXX-YXX-YXX 1 1 MUL; NNN, AAA, BBB. 




WHERE: NNN is the decimal size. 

AND: AAA is a high order decimal or 

symbolic multiplier address. 
AND: BBB is a high order decimal or 

symbolic multiplicand address. 



DESCRIPTION: 



The MUL command multiplies a decimal value specified by 
decimal value specified by the A-operand (A x B) for the 
dicated by the size operand. The multiplier may contain 
not included in the size count. An unsigned multiplier 
The extended product area, the size of the multiplicand 
with decimal zeros, must be reserved immediately followi 
If the multiplicand field is to contain a sign, it must 
following the product area. An unsigned multiplicand fi 
positive. The octal value of jOjOl (-) is the minus sign, 
assumed to be positive. If the Multiplier contains a mi 
must be reserved in the product field. The sign result 
algebraic. 



the B-operand by a 
number of bytes in- 
a sign, although it is 
IS assumed to be positive, 
field plus one, filled 
ng the multiplicand field, 
appear immediately 
eld is assumed to be 
Any other value is 
nus sign, a sign position 
in the product field is 



The product result of the multiplication displaces the previous contents of the 
multiplicand field and is right justified with left zeros in the product field. 

Unit Position of the Multiplier Field is: AAA+NNN-jDjOl . 
Unit Position of the Multiplicand Field is: BBB+NNN-JZ)01 . 
Unit Position of the Product Field is: BBB+2xNNN. 

The multiplier and the multiplicand fields may be- within the same page or diff- 
erent pages as specified by a set page instruction. 

The software condition value is uhchanged. 

The hardware condition register is unpredictable after execution of any in- 
struction executed in DPL-3 or lOS Mode. 



EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



PI 5-1 10: 005-J306-J0JO6-066. m-j06jO. 
PI 5-1 14: j067-0]03-0je)0-ljOjO. 04-070. 



SET; PAG:F01,T01. 
MUL; 003,000,064. 



COMMENTS 



71 



DPL-2 



GROUP 2: DATA MODIFY 



DIVIDE 



OBJECT 



077-YXX-YXX-YXX 



SOURCE 



DIV; NNN, AAA, BBB, 




WHERE: 
AND: 

AND: 



is the decimal size. 
AAA is a decimal or symbolic divisor 
address. 

BBB is a decimal or symbolic dividend 
address. 



DESCRIPTION: 



The DIV command divides a decimal value specified by the B-operand by a decimal 
value specified by the A-operand for the number of bytes indicated by the size 
operand. The size of the dividend field must be twice the size of the divisor 
field plus one. The dividend field must be right justified and have at least one 
leading zero. The maximum value of the dividend is the result of the maximum 

value of a multiply of the same size. (999 )2. The divisor and the dividend 

fields may contain a sign although it is not included in the size count. The 
size count is the size of the divisor. An unsigned field is assumed to be 
positive. Division is algebraic. The octal value JOJOI (-) is the minus sign. 
Any other value is assumed to be positive. If the divisor contains a minus sign, 
a sign position must be reserved in the quotient field. 

The quotient result of the division desplaces the previous contents of the divi- 
dend field and is left justified. The size of the quotient is the size of the 
divisor. The remainder is placed immediately following the quotient. 



Unit Position of the Divisor Field is: 
Unit Position of the Dividend Field is: 
Unit Position of the Quotient Field is: 



AAA+NNN-JOJOI 

BBB+2xNNN. 

BBB+NNN-i301 



The divisor and the dividend fields may be within the same page or different pages 
as specified by a Set Page instruction. 

The software condition value is unchanged. 

The hardware condition register is unpredictable after execution of any in- 
struction executed in DPL-3 or lOS Mode. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



PI 5-1 2)0: jaj05-jOj06-jOjZ)6-j066. 04-130. 
P15-124: J077-JDJD3-J0j3j0-1JDJ3. J04-I4j0. 



SET; PAG:F)Dl,Tj01, 
DIV; JOJ03, 000,064. 



72 



DPL-2 GROUPS: COMPARE 



COMPARE STORAGE-TO-STORAGE 



OBJECT 



0JZ»3-YXX-YXX-YXX 



SOURCE 



I COM; NNN, AAA, BBB, 



11 




WHERE: 
AND: 



AND: 



NNN is the decimal size. 
AAA is the high order decimal or 
symbolic address of the compare 
field. 

BBB is the high order decimal or 
symbolic address of the field com- 
pared to. 



DESCRIPTION : 

Within the current page setting established by a set page instruction, compare 
the data specified by the A-operand address to the data specified by the B- 
operand address for the number of bytes indicated by the size operand. The 
comparison operation proceeds left to right through each field a byte at a time 
and ends when an inequality is found or end of field is reached. Comparison is 
binary, with a collating sequence based on ascending binary values. All codes 
are valid. Memory is not altered as a result of this operation. A field that 
overflows a page boundary will wrap around to the beginning of the page. 

The software condition register is memory location PJ80 377o. This will contain 
an octal j360 for> , )857 for < or (366 for =. The "SEL" instructions will test 
these conditions. 

The result of the compare operation is indicated by the software condition value. 



HIGH 


AAA- 


> 


BBB 


LOW 


AAA 


< 


BBB 


EQUAL 


AAA 


— 


BBB 



EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



PI 5-1 30: 
PI 5-1 34: 
P15-140: 
PI 5-1 44: 
P15-150: 



005-002 -1976-066. 
003-012-150-310. 
004-002-006-000. 
004-000-014-000. 



05-010. 
05-020. 
05-030. 
05-040. 
05-050. 



C02: 



SET; PAG:F00J15, 

COM; 010,002,200. 

SEL; EQL,P06,000. 

SEL; UNC,P12,000. 

A/N: (COMPARE XX) 



73 



•DPL-2 



GROUP 3: SELECT 



SELECT UNCONDITIONAL 



OBJECT 1 1 SOURCE 


004-000-YXX-YXX 1 1 SEL; UNC, RRR. 

1 1 PNN, LLL. 

1 1 




WHERE: RRR is a symbolic address. 
AND: NN is a decimal page. 
AND: LLL is a decimal address. 



DESCRIPTION: 



The Select (Branch) Uncondition command is used in a DPL-3 context to transfer 
control to a new instruction location regardless of the setting of the software 
condition value. 

The DPL-2 commands are executed in an interpretive mode and therefore are not 
limited to section boundaries. In the interpretive mode the SEL command may be 
used to transfer control to any DPL-2 command or to any DPL-1 command except the 
DPL-1 branch functions and the jump functions. DPL-1 branch functions and jump 
functions can only be used in the DPL-1 mode of operation (ENT:DPL-1). The 
branch address may be represented as a symbolic address or as an absolute 
address. The software condition value remains unchanged. 



EXAMPLE: 












PPP-LLL: 


MP1-MP2-MP3-MP4. 


E SEQ. NO. 


LAB: VERB 


OPERANDS 


COMMENTS 


PI 5-162: 
P15-166: 


J304-)D)D0-JO17-W. 

0m-w-jai5-i66. 


JD5-11)Q. 
05-1 2J?). 


SEL; 
Sj31: SEL; 


UNC,P15,0JD0. 
UNC,SJ51. 





74 



DPL-2 



GROUP 3: SELECT 



SELECT LOW 



OBJECT ! 1 SOURCE 


1 1 

1 1 

jDj84-0i81-YXX-YX)^ 1 SEL; LOW, RRR. 

1 1 PNN, LLL. 

1 1 

1 i 




DESCRIPTION: 



WHERE: RRR is a symbolic address 
AND: NN is a decimal page. 
AND: LLL is a decimal address. 



The conditional branch command, select LOW, is used in a DPL-3 context to trans- 
fer control to a new instruction location if the software condition register 
previously set by a DPL-2 compare or a DPL-2 I/O instruction is found to be LOW. 
If the condition is not satisfied, the next sequential instruction is executed. 

(Refer to "SEL;UNC" for Basic Rules of Select Branching) 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



05-180. SEL; LOW,P15,P0j0. 
05-1 9j5. S02: SEL; LOW,S02. 



COMMENTS 



PI 5-1 72: 004-001 -01 7-f 
PI 5-1 76: 004-001-015-176. 



75 



DPL-2 



GROUP 3: SELECT 



SELECT EQUAL 



OBJECT 1 1 SOURCE 


j3|84-)802-YXX-YXX 1 | SEL; EQL, RRR. 

1 1 PNN, LLL. 




WHERE: RRR is a symbolic address 
AND: NN is a decimal page. 
AND: LLL is a decimal address. 



DESCRIPTION : 

The conditional branch command, select EQUAL, is used in a DPL-3 context to 
transfer control to a new instruction location if the software condition value 
previously set by a DPL-2 compare or DPL-2 I/O instruction is found to be 
EQUAL. If the condition is not satisfied, the next sequential instruction is 
executed. 

(Refer to "SEL;UNC" for Basic Rules of Select Branching) 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 

PI 5-202: )8jZ)4-)Z)00-jD17-0JZ)0. 06-05)3. SEL; EQU,P15, 
PI 5-206: 004-002-015-206. 06-060. S03: SEL; EQL,S03. 



COMMENTS 



76 



DPL-2 



OUP 3: SELECT 


SELECT HIGH 


OBJECT 1 


SOURCE 


004-004-YXX-YXX j 

1 


SEL; HGH, RRR. 

PNN, LLL. 




WHERE: RRR is a symbolic address. 
AND: NN is a decimal page. 
AND: LLL is a decimal address. 



DESCRIPTION: 



The conditional branch command, select HIGH, is used in a DPL-3 context to 
transfer control to a new instruction location if the software condition value 
previously set by a DPL-2 compare or DPL-2 I/O instruction is found to be HIGH. 
If the condition is not satisfied, the next sequential instruction is executed. 

(Refer to "SEL;UNC" for Basic Rules of Select Branching) 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 

P15-212: 0)34-0134-017-1900. 06-120. SEL; HGH,P15,000. 
PI 5-21 6: 004-004-015-216. 06-130. S04: SEL; HGH,S04. 



COMMENTS 



77 



DPL-2 



GROUP 3; 



SELECT 



SELECT NOT HIGH 



OBJECT 1 1 SOURCE 


j3ja4_jD14_YXX-YXX 1 1 SEL; NHG, RRR. 

1 1 PNN, LLL. 




DESCRIPTION; 



WHERE: RRR is a symbolic address. 
AND: NN is a decimal page. 
AND: LLL is a decimal address. 



The conditional branch command, select NOT HIGH, is used in a DPL-3 context to 
transfer control to a new instruction location if the software condition value 
previously set by a DPL-2 compare or DPL-2 I/O instruction is found to be LOW 
or EQUAL. If the condition is not satisfied, the next sequential instruction 
is executed. 

(Refer to "SEL;UNC" for Basic Rules of Select Branching) 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



P15-222: 
P15-226: 



JDj34-)314-017- 
004-014-1315-226. 



06-200. 
07-010 



S05; 



SEL; 
SEL; 



NHG, PI 5, 
NHG,S05, 



78 



DPL-2 



GROUP 3: SELECT 



SELECT NOT EQUAL 



OBJECT 



SOURCE 



I 
004-01 2-YXX-YXX ! ! SEL;NEQ, RRR 



I 



PNN, LLL, 




DESCRIPTION: 



WHERE: RRR is a symbolic address. 
AND: NN is a decimal page. 
AND: LLL is a decimal address. 



The conditional branch command, select NOT EQUAL, is used in a DPL-3 context to 
transfer control to a new instruction location if the software condition value 
previously set by a DPL-2 compare or DPL-2 I/O instruction is found to be LOW 
or HIGH. If the condition is not satisfied, the next sequential instruction is 
executed. 

(Refer to "SEL;UNC" for Basic Rules of Select Branching) 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



PI 5-232: |3jD4-|ai2-jDl 7-000. 07-070. SEL; 

P15-236: 004-012-015-236. 07-080. S06: SEL; 



NEQ, PI 5,000. 
NEQ,S06. 



79 



DPL-2 



GROUP 3: SELECT 



SELECT NOT LOW 



OBJECT 1 1 SOURCE 


PJZi4-011-YXX-YXX 1 1 SEL;NLW, RRR. 

j 1 PNN, LLL. 

1 1 




DESCRIPTION: 



WHERE: RRR is a symbolic address. 
AND: NN is a decimal page. 
AND: LLL is a decimal address. 



The conditional branch command, select NOT LOW, is used in a DPL-3 context to 
transfer control to a new instruction location if the condition value previously 
set by a DPL-2 compare or DPL-2 I/O instruction is found to be HIGH or EQUAL. 
If the condition is not satisfied, the next sequential instruction is executed. 

(Refer to "SEL;UNC" for Basic Rules of Select Branching) 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 

P15-242: jZ)04-jZ)l 1-017-13)3)8. )37-14)3. SEL; NLW,P15,)3)3)3. 
P15-246: )3J34-)31 1-1315-246. J37-15)Z). S)D7: SEL; NLW,Sp7. 



COMMENTS 



80 



•DPL-2 



GROUP 4: SET PAGE 



SET PAGE 



OBJECT 



JZ)05-FFF-TTT-III 



SOURCE 



I SET; PAG: FNN, TNN. 



11 




WHERE: 

AND: 

AND: 



FFF is the DPL A-Operand WHERE: 

(from) page. 

TTT is the DPL B-Operand AND: 

(to) page. 

Ill is the DPL Instruction 

page. 



FNN is the decimal page setting 
for the A-Operand data instructions. 
TNN is the decimal page setting 
for the B-Operand data instructions, 



DESCRIPTION : 

The A-Operand and the B-Operand, in the DPL-2 data functions, specify an address 
within a page where the data resides. The set page instruction provides a means 
of controlling the setting of that page as a base address. The page setting for 
the A-Operand and the B-Operand may be the same page or they may be different 
pages regardless of the section. Only operands that specify data use the page 
setting. The page setting is unchanged until another set page instruction is 
executed reflection different pages. 

The software condition value is unchanged. 

The hardware condition register is unpredictable after execution on any in- 
struction executed in DPL-3 or lOS Mode. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



P15-252: 
P15-256: 
P15-262: 



jOjD5-je)06-j376-066. 
J037-J01 2-024-1 12. 
037-1004-012-024. 



JO8-010. Sj08: SET 
08-02J0. MOV 

08-JO30. MOV 



PAG:F01,T15. 
010,020,074. 
004,010,020. 



COMMENTS 

MOVE CHAR. 
FROM PAGE 1 
TO PAGE 15 



81 



DPL-2 



GROUP 4. I/O CONTROL 



TAPE CONTROL COMMANDS 



OBJECT SOURCE I 


007-001 -0XX-001| , TCL 
007-001 -2XX -001 TCL 
007-001 -2XX-002 TCL 
007-001 -2XX-003 TCL 
007-001-2XX-004| 1 TCL 

1 1 


, 001, T#N, BSP. 
, 001, M#N, BSP. 
; 001, M#N, RWD. 
; 001, M#N. RWI. 
; 001, M#N, WFM. 




WHERE: N is a decimal tape device number, 
AND: BSP is a backspace record function, 
AND: RWI is a maxi-tape rewind with 

interlock function, 
AND: RWD is a maxi-tape rewind without 

interlock function, 
AND: WFM is a maxi-tape write file mark. 



DESCRIPTION: 



These commands control the basic tape operations for the device specified 

in the instruction. The backspace function (BSP) applies to all tape I/O 

devices. The backspace function backspaces the device specified by one 
record . 

The two rewind functions and the write file mark function apply only to 
maxi-tape devices. The rewind with interlock function (RWI) rewinds the 
maxi-tape specified and takes the device off-line. After the device has 
been set off-line, manual intervention is required to return the device 
to on-line status. The rewind without interlock function (RWD) rewinds 
the maxi-tape specified, but does not take the device off-line. The write 
file mark function (WFM) writes a special hardware 3-byte file mark 
for the maxi-tape specified. 



EXAMPLE: 



PPP- 


-LLL: 


MP1-MP2- 


-MP3-MP4. 


E SEQ. NO. 


LAB: VERE 


i OPERANDS 


COMMENTS 


P15- 


■266: 


JO07-001- 


-001-001. 


08-100. 


TCL- 


, 001 


,T#1 


,BSP. 


BKSP MINI-1 


P15- 


■272: 


007-001- 


-201-001. 


08-110. 


TCL; 


. 001 


,M#1, 


,BSP. 


BKSP MAXI 


P15- 


■276: 


007-001- 


-202-002. 


08-120. 


TCL: 


. 001 


,M#2, 


,RWD. 


RWD MAXI W/INTL 


P15-302: 


007-001- 


-203-003. 


08-130. 


TCL- 


. 001 


,M#3 


,RWI. 


RWD MAXI -NO INT 


P15- 


■306: 


007-001 ■ 


-204-004. 


08-140. 


TCL: 


. 001 


,M#4,WFM. 


WR.FILE MK-MAXI 



82 



DPL-2 



GROUP 4. 



TYPEWRITER CONTROL (TYPES I & II) 



OBJECT SOURCE 


007-001-013-002 , PCL; 001, PRT, BSC. 
007-001-013-003 PCL; 001, PRT, RRS. 
007-001-013-004 PCL; 001, PRT, CRT. 
007-001-013-006 PCL; 001, PRT, BRS. 
007-001-013-011 PCL; 001, PRT, TAB. 
007-001-013-012 PCL; 001, PRT, IDX. 




DESCRIPTION : 

These commands will control the paper and carriage positioning on the 
IBM 73)8 and 735 typewriters. 

Backspace carriage one character position. 

Red ribbon shift (optional on 735). 

Carriage return. 

Black ribbon shift (optional on 735). 

Position carriage to the first tab stop. 

Index paper one line. 



002 


(BSC) 


003 


(RRS) 


004 


(CRT) 


006 


(BRS) 


011 


(TAB) 


012 


(IDX) 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



PI 5-31 2: JO07-JDJO1-JO1 3-011. JO8-2J9J0. 

PI 5-31 6: 027-01 2-00J3-01 3. JO9-010. 

PI 5-322: 007-001 -JD13-JO04. 09-JO20. 

PI 5-326: 007-001-013-012. 09-030. 

PI 5-332: 004-000-015-312. 09-040. 



CPT: PCL; 001, PRT, TAB. 

PUT; 01 0,000, PRT. 

PCL; 001, PRT, CRT. 

PCL; 001, PRT, IDX. 

SEL; UNCCPT. 



COMMENTS 

TAB ONE FIELD 
PRINT 10 CHAR. 
CARRIAGE RETURN 
INDEX ONE LINE 



83 



.DPL-2 



GROUP 4 



LINE PRINTER CONTROL 
(TYPE II) 



OBJECT 1 1 SOURCE 


jO]O7-jO01-jai3-jO6]Ol 1 PCL; jOjOl , PRT, TOF. 
J0j07-J0j01 -jOl 3-JO70 1 1 PCL; 0jOl , PRT, LFD. 




DESCRIPTION : 

These commands control the paper positioning on the medium speed line printers, 

]O60 (TOP) When this command is given the paper will slew 
to "top of form". 

jO70 (LFD) This command will feed one line of paper. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



PI 5-336: J027-1 
PI 5-342: 004 
PI 5-346: 007 
PI 5-352: 



013. 

017-000. 

013-070. 

-015-336. 



09-100. 
09-110. 
09-120. 
09-130. 



WTT: PUT 
SEL 
PCL 
SEL 



064 ,000, PRT. 
HGH, PI 5,000. 
001, PRT, LFD. 
UNCWTT. 



COMMENTS 

PRINT 64 CHAR. 
PRINT ERROR 
ADVANCE 1 LINE 



84 



NOTATIONS FOR DPL-3B CONSTANTS 

These statements are used to enter data constants into memory, to define and 
reserve areas of memory, and to specify the address of relocatable symbols. 
The statements may be named by symbols so that other program elements can 
refer to the fields they generate. 

The forms OCT, DEC, HEX and A/N may specify one constant or a string of 
constants. 

The form DSA provides a method of reserving specified areas of memory for 
future reference. The contents of the reserved area is not disturbed. 

The form ADC provides a means of storing the address components of relocatable 
symbols. ADC generates a two-byte constant, containing the DPL code of the 
page and the octal code of the location of the symbol. 

CONSTANT NOTATIONS 

OCT: (NNN-NNN-NNN-etc.) 

A byte-string constant in octal notation where the maximum number 
of terms is six. 

HEX: (HH-HH-HH-etc.) 

A byte-string constant in Hex notation where the maximum number 
of terms is eight. 

DEC: (NNN-NNN-NNN-etc.) 

A byte-string constant in decimal notation where the maximum number 
of terms is six. 

A/N: (XXXXXXX... etc.) 

A string of keyboard characters where the maximum number of 
characters is 24. 

DSA: (NNN) 

Define Symbol area where NNN is decimal number of bytes required up 
to 256. 

ADC: (AAA+NNN) 

Address constant for labels in symbolic notation. This instruction 
generates two-bytes. The first byte contains the DPL page of the 
address specified in increment form. The second byte contains the 
location. 



85 



DPL-1 



PSEUDO 



ORIGIN LOCATION COUNTER 



OBJECT 1 1 SOURCE 


' ' ORG: PNN, LLL. 
' ' ORG: PNN. 




WHERE: NN is the decimal page of 
the program origin. 

AND: LLL is the decimal location 
within the page. 

AND: Where LLL is not specified 
location 000 is assumed. 



DESCRIPTION 

The assembler uses the decimal term specified by the operand to alter the 

setting of the location counter for the current segment. This value should 

be on a half-word boundary if instruction statements are to follow. 

ORG instruction must appear following each SEG (segment) 

statement, and may appear elsewhere within the segment. 

tion is omitted following SEG or OVL, the assembler sets 

tion address to zero. The ORG operand specifies a page 

either an absolute address, or as an implied address of location 000 within 

the page specified, if the location is not included in the operand. Each 

ORG statement is considered one label of the 128 possible labels. 



The 
or OVL (overlay) 
If the ORG instruc" 
the initial instruc- 
and location as 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



IJO-JOIJO. 
1J0-J32J0. 
IJO-PSJO. 
1JZ)-04JO. 
Ije)-J05j0. 



PI 2-1 
P12-20JZ): 



OVL 


PID. 


ORG 


PljO. 


A/N 


: (J012). 


ORG 


: PljO, 128 


A/N 


: (XXX). 



COMMENTS 

OVERLAY ID 
ORIGIN PljD, 



ORIGIN PljO. 128 



86 



•DPL-1 



CLASS: PSEUDO 



IDENTIFY SEGMENT 



OBJECT 1 1 SOURCE 


1 1 SEG: RID. 
1 1 




WHERE: PID is any 3 character segment 
identification. 

DESCRIPTION : 

A segment is a block of program coding that can be relocated independently of 
other coding if linkage addresses are changed where necessary. The concept of 
program segmenting is a consideration at coding time, assembly time, and at 
object generation time. By using the form of the Branch functions specifying 
the absolute address to which control is to be passed at execution time, 
external segments may be referenced. In assembled multi-segment programs, seg- 
ments may symbolically address locations in other segments. A program is com- 
posed of at least one segment, and the SEG or OVL pseudo must be the first in- 
struction encountered during assembly which is immediately followed by an ORG 
pseudo. Any three characters may be used for segment identification. The SEG 
identification is contained in all subsequent source instructions up to the 
end of the segment. The SEG identification assigned by the SEG pseudo is used 
in conjunction with the USE pseudo to retrieve external segments at object 
generation time. 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



P1J0-J5J3J5: 200- 



10-lljO. 
1JZ)-12J0. 
1JO-13J0. 



SEG: PID. 
ORG: PJ08, 000, 
LDA, R#0; OCT: 



SEGMENT ID 
START LOCATION 



87 



DPL-1 



PSEUDO 



ENTER CONTROL FUNCTION 



OBJECT 1 1 SOURCE 


15JD-YXX-10X-YXX 1 1 ENT: DPL-1. 
1 5JD-j8j8jZ)-l 22-004 1 1 ENT: DPL-3. 
15)3-JDJ8JZ)-1 23-18134 ll ENT: I OS. 

1 1 




WHERE: 15ja-YXX is the section. 



DESCRIPTION: 



WHERE: DPL-1 is a machine executable mode, 
AND: DPL-3 is an interpretive mode. 
AND: IDS is the I/O supervisor. 



ENT : 

The ENT pseudo instructions change the operating context for the program in- 
structions. There are three forms of the ENT pseudo and each generates Branch 
linkage code to the appropriate control point. 

ENT:DPL-1 switches the instruction environment from interpretive DPL-3 mode 
into direct execution DPL-1 mode. DPL-1 mode is the normal hardware context 
and executes instructions at machine speed. Only DPL-1 and Pseudo instructions 
may be executed in DPL-1 mode. This pseudo will be an SMS and a BRU to the 
next instruction in sequence. 

ENT:DPL-3 switches the instruction environment from direct DPL-1 mode into 
interpretive DPL-3 mode. In DPL-3 mode any DPL-1 instruction except Class j3, 
Class 1 and any DPL-2 statement may be executed under control of a resident 
software monitor. Exit from DPL-3 mode is accomplished only with an ENT:DPL-1 
pseudo instruction. 

ENT:IOS switches control temporarily from a DPL-1 context into the Input/Output 
Supervisor for the execution of one I/Ofunction. The DPL-2 I/O commands 
(GET, PUT, SET, TCL, PCL) are used to specify the I/O operation. Following 
execution, control is automatically returned to DPL-1 mode and the succeeding 
instructions. 

lOS : 

The Input Output Supervisor is a resident monitor program used to provide 
complete I/O functions for DPL-1 programs. The ENT:IOS pseudo instruction is 
used to turn program control over to the Supervisor. After one complete I/O 
function has been performed, program control is automatically returned to the 
using DPL-1 program. The I/O function to be performed is specified using a 
GET, PUT, PCL or TCL command from the DPL-2 instruction set. A SET;PAG command 
may precede the I/O function command where required. 



(continued) 



88 



ENT (cont'd.) 



The I/O buffer page for the Supervisor is set initially to page 01. The 
SET;PAG command changes the page context for the GET and PUT commands where 
desired. 



All index registers in section are used by the lOS during its operation and 
their contents lost. Any valuable data contained in these index registers 
should be saved by the user progrom before calling the Supervisor and restored 
by the user program after return from the lOS. 



The Supervisor uses the software status byte as 
return to the user program. This condition may 
"SEL" command. Equal condition means that the 
fully completed. High condition indicates that 
condition means that a file mark or end of file 
a tape read operation. When a high condition i 
branch to an error routine. The software statu 
gnose an error that occurred during a mini -tape 
byte contains the value eight, a retry failure 



a status indicator upon its 
be tested by using the DPL-2 

I/O function has been success- 
an error has occurred. Low 
record has been detected during 

s encountered the user should 

s byte (Pj3j3-0178) can help dia- 
read or write. If the status 

is indicated. 



Refer to the Cogar System 4 Instruction Reference Card for explanation of the 
status byte. 



EXAMPLE : 

PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



PI 0-002: 
PI 0-004: 
P10-010: 
P10-014: 
PI 0-020: 
P10-024: 



201-012. 

150-000-122-004. 

017-200-001-200. 

037-012-200-226. 

047-012-226-310. 

150-010-100-030. 



PI 0-030: 150-000-123-004. 

PI 0-034: 005-006-076-042. 

PI 0-040: 017-200-001-000. 

PI 0-044: 201-030. 



10-190. 
10-200. 
11-010. 
11-020. 
11-030. 
11-040. 
*1 1-050. 
11-060. 
11-070. 
11-080. 
11-Ji 



LDX, 

ENT 

GET 

MOV 

ADD 

ENT 

ENT 
SET 
GET 
LDX, 



R#l; HEX:0A. 

DPL-3. 

128,T#1,128. 

010,128,150. 

010,150,200. 

DPL-1 . 

lOS. 

PAG:F01,T15. 
128,T#1,000. 
R#l, DEC:024. 



(OPTIONAL INST) 
AUTOMATICALLY- 
ENTERS DPL-1 



89 



DPL-1 



PSEUDO 



EQUATE SYMBOL 



OBJECT 1 1 SOURCE 


I LAB: EQU: PNN, LLL. 
1 1 LAB: EQU: RRR. 




WHERE: LAB is a symbolic label. 
AND: NN is the decimal page. 
AND: LLL is the decimal location 

within the page. 
AND: RRR is a symbolic reference, 



DESCRIPTION 

The EQU pseudo instruction defines a symbol by assigning it to either an 
absolute location or another symbol. The EQU instruction is the means of 
equating symbols to registers, relocatable expressions, and other arbitrary 
values. 

The EQU operand may be represented as an absolute expression, or as a sym- 
bolic label present in the context of the program unit. 



EXAMPLE : 



PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. LAB: VERB OPERANDS 



COMMENTS 



P12-0J00: 231-052. 
P12-jOjD2: im-jOjZ)0. 



11-16J0. 




SEG 


: ABC. 




11-170. 




ORG 


: P10. 




11-180. 


E01: 


EQU 


P12, 


000 


11-190. 


E02: 


EQU, 


XYZ. 




*1 1-200. 










12-010. 


XYZ: 


STA 


, l#l; 


P10 


12-020. 




BRU; 


E01. 





EQUATE E01 TO 
AN EXTERNAL 
SEGMENT 
E02-INTERNAL 



90 



•DPL-1 



CLASS: PSEUDO 



OVERLAY 



OBJECT 



SOURCE 



OVL: RID. 




WHERE: PID is any 3 non-blank character 
overlay identification. 



DESCRIPTION: 



The OVL pseudo names a section of program coding in the same way that SEG 

pseudo does, and restrictions are identical. Program overlays must be considered 

at coding time. 

In contrast to the SEG segment, which generates object coding into the main body 
of the program, the OVL segment generates overlay records outside the main body. 

At object generation time, each OVL segment is inserted into the object string 
tape, in the order that they occur, following the records used in loading the 
full memory. The overlay records are retrieved into memory, under user program 
control, using the normal I/O procedures. 



EXAMPLE: 


LAB: 


VERB 


OPERANDS 




PPP-LLL: MP1-MP2-MP3-MP4. E SEQ. NO. 


COMMENTS 


12-JO80. 




SEG: 


PID. 


MAIN BODY OF 


12-JD90. 




ORG: 


PI JO, J0JD0. 


PROGRAM 


*^2-^m. 










*12-110. 










12-12J0. 




OVL: 


XYZ. 


1ST OVERLAY 


12-130. 




ORG: 


PJ32, jbfDfD. 


RECORD 


*12-140. 










12-15J0. 




END: 


*+J0. 


(MUST HAVE E 



91 



DPL-1 



CLASS: PSEUDO USE EXTERNAL SOURCE SEGMENT 



OBJECT 



SOURCE 



USE: PID. 




WHERE: PID is an external 
SEG identifier. 



OVL or 



DESCRIPTION 



The US 
fined 
progra 
tion t 
identi 
ment n 
genera 
string 
The us 
the so 
by the 
the US 
unti 1 
segmen 
counte 
place, 
i n i t i a 



E pseu 
segmen 
m. Th 
ime, G 
fy the 
ame es 
tion t 

gener 
er is 
urce p 

USE 
E oper 
an END 
t spec 
red (n 
When 
ted by 



do instru 
t or over 
e retriev 
an be eff 

3 positi 
t a b 1 i s h e d 
ime, when 
ation of 
then inst 
rimer tap 
perand. 
and will 

pseudo i 
ified by 
ested USE 

a segmen 

using th 



ction 
lay th 
al of 
ected 
on nam 
on th 
a USE 
the cu 
ructed 
e cont 
The fi 
cont in 
nstruc 
the US 
) the 
t is c 
e most 



i denti 
at is 
these 
only i 
e in t 
e sour 

pseud 
rrent 

to CO 
a i n i n g 
rst se 
ue the 
tion i 
E pseu 
same i 
omplet 

curre 



f i e s an 
to form 
segments 
f the as 
he USE 
ce prime 
is enc 
source p 
ntinue p 

the ide 
t of ide 

object 
s reache 
db, anot 
nterrupt 
ed, the 
ntly int 



independent 
part of the 
, at object 
sembler is 
perand with 
r tape. At 
ountered, t 
rimer is in 
recessing , 
ntif i cation 
ntifiers th 
generation 
d . If, wit 
her use pse 

procedure 
trail back 
errupted so 



ly de- 
current 
genera- 

able to 
a seg- 
object 

he object 

terrupted. 

using 
speci f ied 

at s a t i s f y 

process 

h i n the 

udo is en- 

takes 

must be 

urce primer. 



LIBRARY 500RC6- 
PRIMfiR CONTAiMS 

5e<»MBNT : -A8C'; 




NEwuv A$sKfs/\eueo 

«CORCB-F>RlMerR. 
CONTACKJIMG- A, 

"use" PSEUOO. 



r 



USE :a6c 

iMre^OPT O-'STRlNfr GeNfi^^A-ritklsl^ 
AND IM»-nATff A SeA^CM f=OQ, 
THE SEGMEMT •♦A8c'* 6J>4 
ANOTHER LieftAR.Y SOURCE- Ppl/ueRy 
COfs(TAIM(f<<& THfi S6C9M6Kr ; •«a8C V 




92 



•DPL-1 



WHERE; 
AND: 

AND: 



CLASS: PSEUDO 



END SEGMENT 



OBJECT 1 1 SOURCE 


IjOX-YXX ' ' END: PNN, LLL. 
10X-YXX 1 END: RRR. 




10X is a Branch command. 
X is the page within 
Section I. 
YXX is the location. 



WHERE: NN is the decimal page address. 
AND: LLL is the decimal location. 
AND: RRR is a symbolic reference. 



DESCRIPTION : 

The END pseudo instruction is used to define the end of a program segment or 
overlay and to identify the starting address for program execution. This 
starting address may be different than the origin address and is specified as an 
absolute or symbolic address within Section I. For multiple segment programs, 
the starting address from the last encountered END instruction is used. 

The END pseudo generates a Branch Unconditional instruction to the address 
specified by the operand. 

At object generation time, this generated Branch instruction is inserted into the 
background in the corresponding location of Page 2, locations 2 and 3, and is 
used as the entry point within the section assigned (PjO2-0jOj0) at execution time. 
If the format (END:*+jO.) is used, this branch address will not be inserted into 
the background. This format is commonally used to terminate and overlay. 

EXAMPLE: 



PPP-LLL: MP1-MP2-MP3-MP4. E 



Plj0-je)j0j3: 174-jOll 



SEQ. NO. LAB: VERB 


OPERANDS 


COMMENTS 


13-14JD. SEG: 


XYZ. 




13-150. ORG: 


P08, 000. 




*13-160. 






*13-170. 






13-180. BGN: IOC, 


C#4; 011. 


DISPLAY 


*13-19^. 






*1 3-200. 






14-010. END: 


BGN. 


LINK TO BEGIN 



93 



'DPL-1 



PSEUDO 



EJECT 



OBJECT 



SOURCE 



EJT: 000. 




DESCRIPTION: 

The EJT pseudo instruction causes the printer to go to Top of Form before 
printing out the next instruction, during a Source Listing operation. It 
thus allows the programmer to set up the listings in easily read formats. 
The Sequence Number for this instruction, but not the instruction itself, 
is printed on the Source Listing. 



94 



DPL-1 



CLASS 1 : BRANCH AND I/O 



MINI -TAPE 



OBJECT 1 1 SOURCE 


17j0f ) II 

171 VFFF II IOC, C#N; FFF. 

172 \ II 

II 




WHERE: FFF is Function Code WHERE: 



N=jD Current tape channel selected, 
N=l Tape cartridge #1 selected. 
N=2 Tape cartridge #2 selected. 



TIMING: 4-6 Microseconds 

FFF (Function Codes) DESCRIPTION 

jQjO0 FOR^'ARD, SLOW, ERASE 

Start Tape Forward with Erase. This command sets the run direction 
and the erase control for the selected tape channel. This command 
initiates a Tape Write Routine. Since the Erase is active, the 
tape will be erased until subsequent write data commands. After 
this command is given, a time delay of approximately 30 M sec should 
be given to allow the tape to reach a stable speed of 10 in/sec. be- 
fore the writing df data is begun. 

mi FORWARD, SLOW 

This Instruction starts the selected tape forward with Erase condi- 
tion off. This instruction generally initiates a tape read sequence. 

002 FORWARD, FAST 

This command sets the run, forward, and high speed control in the 
tape electronics starting the tape forward at 40 inches/sec. 

ms REVERSE, SLOW 

This command sets the run control, resets the high speed and forward 
control, starting the tape reverse normal speed. When the Forward 
Control is in reset state, the erase function is inhibited preventing 
the erasing of data on any tape reverse condition. When in reverse 
if the clip comes home, (tape rewound) the run control is reset 
stopping tape motion. 

REVERSE, FAST 

This command is identical to the reverse normal command except the 
tape is driven at high speed 40 inches/sec. 



95 



IOC 

FFF (Function Codes) DESCRIPTION CONTINUED 

005 STOP 

This command resets the run control stopping tape. Again, the 
channel may or may not be specified. 

m7 TAPE TRANSFER BYTE AND 
207 TAPE TRANSFER BYTE, SKIP 

This command controls the transfer of characters to and from the 
tape interface. The transfer is controlled by a Busy or Not Ready 
condition within the tape controls and can be executed in two modes. 
Stall on Busy, and Skip on Busy. When executed in the Stall if Busy 
mode, the program stalls at the transfer byte instruction until a 
tape sprocket is generated indicating that a byte has been written or 
read. In the Skip on Busy mode, the program automatically skips the 
next sequential instruction if a character has not been received.* 

When a program is in a Read or Write subroutine, a Transfer Byte 
instruction must be given eyery 512 us. I.E. - the loop from trans- 
fer byte to transfer byte must not exceed 512 us. 

010 WRITE MODE 

This command sets the write operation and begins the timing sequence 
that controls the writing frequency, loads and shifts the tape buffer 
and generates the sprockets to drop the stall condition. 

This command will follow the start forward normal with erase command, 
the time delay and any set-up commands. Included in the set-up in- 
struction should be a loading of the ACC with the first to be written. 
Immediately following the write set should be a transfer byte command. 
The write set must be given only once in a write sequence. 

011 READ MODE 

This command activates the tape read circuitry within the tape systems. 
It has to be executed only once in a normal tape read sequence. The 
setting of the Read condition/resets the Write condition. 

012 REWIND 

This command will set a rewind F/F for the specified tape or the 
current tape which will be reset only by the clip-in signal. This 
permits overlapped rewinds or rewinding one tape while performing 
an operation on the other tape. 

*NOTE: The Accumulator value is destroyed after execution of a "Skip/ 
Busy" Instruction. 



96 



FFF (Function Codes) DESCRIPTION: Continued 

016 SELECT DECK 1 IF N=l , DECK 2 IF N=2 & LOAD ITS STATUS (PAIR 1) 

026 SELECT DECK 3 IF N=l , DECK 4 IF N=2 & LOAD ITS STATUS (PAIR 2) 

036 SELECT DECK 5 IF N=l , DECK 6 IF N=2 & LOAD ITS STATUS (PAIR 3) 

046 SELECT DECK 7 IF N=l , DECK 8 IF N=2 & LOAD ITS STATUS (PAIR 4) 

These commands will Select a Tape Deck and load its status 

in the Accumulator. If N=0, the status of the current deck 
will be loaded. 



7 6 5 4 3 2 10 



Not Used 
EOT 



Clip Out 

Tape - Cartridge Out 

Tape Runaway 

I/O STATUS 

Tape Error 



Keyboard Error 



This instruction will end a read sequence. After the status has been 
loaded to the Accumulator, the Read, Runaway and Tape Error will be 
reset. It is important that this command be given before stopping 
tape and before the end of the block. Either of these conditions 
gives an energy dropout and a resulting tape error. 



This instruction may ask for either channel 
or the current channel. A specific channel 
rewind test to determine end of rewind. It 
the error status on both decks of a selected 
command will reset the error. A Tape error 
of a block of data if a significant crossing 
window or any energy dropout of 2 ms occurs 
runaway condition occurs if the read F/F is 
detected for approximately 5 sec at normal s 
speed. These conditions set the tape error 
respectively. 



of one of the 4 PAIRS 
command is useful in a 
is not possible to check 

pair since the first 
occurs during the reading 

falls outside of the data 
during a write check. A 
set and no energy is 
peed or 50 M sec at high 
F/F and the runaway F/F 



When either F/F is set the tape logic forces the generation of sprockets 
from the internal timing rather than data, to allow the program loop 
to finish. 

The runaway condition will also reset the run F/F, stopping tape. 



97 



DPL-1 



CLASS 1 : BRANCH AND I/O 



KEYBOARD 



OBJECT 



173-FFF 



SOURCE 



IOC, C#3; FFF, 




TIMING: 



6 Microseconds. 



WHERE: FFF is the Function Code 



FFF (Function Codes) Description 

mi KEYBOARD TRANSFER BYTE AND 
2)37 KEYBOARD TRANSFER BYTE, SKIP 

This command controls the transfer of characters from the keyboard 
interface to the accumulator. The transfer is controlled by a Busy or 
Not Ready condition within the keyboard controls and can be executed in 
two modes. Stall on Busy, and Skip on Busy. When executed in the Stall 
Busy mode, the program stalls at the transfer byte instruction until a 
keyboard sprocket is generated indicating that a byte is ready to be 
transferred. In the Skip on Busy mode, the program automatically skips 
the next sequential instruction if a character has not been received. 

NOTE: The Accumulator value is destroyed after execution of a "Skip 
if Busy" Instruction. 

1313 BEEP 

This command will produce an electronic beep. This may be used for 
feedback to the operator after a keystroke, an error tone, etc. 

016 LOAD STATUS 

This command will load a status word to the ACC. The J) bit signals a 
keyboard error. The other bits reflect the I/O and current tape status. 



if 



98 



DPL-1 



CLASS 1 



DISPLAY CONTROL 



OBJECT 



174-FFF 



SOURCE 



IOC, C#4; FFF. 




WHERE: FFF is the function code. 



DESCRIPTION: 



The function code has the following structure: 
FFF = SS-LIU-DLM 



WHERE: 



is the section bits of the page to be displayed. 

is the level bits of the page number to be displayed. 

is the interleave bit in 8 line display mode and the half page (zone) 

bit in 4 line display mode. See note for def. of interleave. 

is the underscore bit. When U = 1, any display character with a 

bit 6 will be underscored. 

is the disable CRT bit. 

is the 4/8 line mode select bit. If M = 0, the 8 line display mode 

is selected. 



TIMING: 4 Microseconds. 



EXAMPLE: 



174- 
174-020 
174-001 
174-021 



8 line normal mode - page 

8 line interlace mode - page 

4 line odd zone (zone 1) - (P00-200 thru 

4 line even zone (zone 0) -(P00-000 thru 



P00' 
P00. 



■377), 
■177). 



Note on Interleave : (8-line option only) 



In the normal display mode (not interleaved), a page will be displayed in 
continuous fashion, location 000 through 377, octal notation. 



Line 1 


Loc. 


180)9 Octal 


through 


Loc. 


037 Octal 


Line 2 


Loc. 


040 Octal 


through 


Loc. 


077 Octal 


Line 3 


Loc. 


100 Octal 


through 


Loc. 


137 Octal 


Line 4 


Loc. 


140 Octal 


through 


Loc. 


177 Octal 


Line 5 


Loc. 


200 Octal 


through 


Loc. 


237 Octal 


Line 6 


Loc. 


240 Octal 


through 


Loc. 


277 Octal 


Line 7 


Loc. 


300 Octal 


through 


Loc. 


337 Octal 


Line 8 


Loc. 


340 Octal 


through 


Loc. 


377 Octal 



99 



DISPLAY 
(cont.) 



The interleave mode will display this information in the following sequence: 

Loc. jD|D0 Octal through Loc. jZ)37 Octal 

Loc. 200 Octal through Loc. 237 Octal 

Loc. 040 Octal through Loc. 077 Octal 

Loc. 240 Octal through Loc. 277 Octal 

Loc. 100 Octal through Loc. 137 Octal 

Loc. 300 Octal through Loc. 337 Octal 

Loc. 140 Octal through Loc. 177 Octal 

Loc. 340 Octal through Loc. 377 Octal 

Display Page 09 (Octal Page 11) 

Comments 
4 lines from loc. 000 to 177, No Underscore. 

4 lines from loc. 200 to 377, With Underscore. 

8 lines from loc. 000 to 377. 

8 lines from loc. 000 to 377, With Underscore. 

8 lines Interleaved 

8 lines With Underscore and Interleaved. 



Li 


ne 


1 




Li 


ne 


5 




Li 


ne 


2 




Li 


ne 


6 




Li 


ne 


3 




Li 


ne 


7 




Li 


ne 


4 




Line 


8 




EXAMPLE: 


Dis 


IOC, 


C#4' 


,123. 


IOC, 


C#4' 


,113. 


IOC, 


C#4;102. 


IOC, 


C#4 


,112. 


IOC, 


C#4 


,122. 


K 


DC, 


C#4 


,132. 



100 





APPENDIX 




DPL-1 INSTRUCTION SET 


Class 1 


Branch and I/O Instructions 






Mnemonic 


BRU 
BRE 


Class 


Jump Instructions 




BRH 
BRL 


Mnemonic 


TLJ+ 








TLJ- 


Timing 


4 us Branch, 3 * us NO Branch 


Timing 


4 us Jump, 3* us NO Jump 


Description 


Branch Unconditional 
Branch on Equal 


Description 


Test Literal and Jump 




Branch on High 




Compare the instruction Literal to the Accumulator. 




Branch on Low 




On comparison equal jump +NNNN. On comparison 




On condition, branch directly to the 1 1 bit address 




not equal execute next instruction. 




carried in the instruction. Condition register 
previously set by a Jump or Compare instruction. The 


Binary Format 


7654321076543210 




11 bits of the direct address replace the least 
significant 1 1 bits of the current lAW. 


TLJ+ 


OOONNNNOLLLLLLLL 






TLJ- 


OOONNNNl LLLLLLLL 


Binary Format 


76543210 76543210 


Mnemonic 


TMJ+ 


BRU 


1 OOOAAA AAAAAAAO 




TMJ- 


BRE 


OlOOOAAA AAAAAAAl 






BRH 


OIOOIAAA AAAAAAAO 


Timing 


4 us Jump, 3* us NO Jump 


BRL 


OIOOIAAA AAAAAAAl 


Description 


Test Mask and Jump 


Notes 1. 


The least significant bit of the direct address is 




Compare the instruction Mask to the Accumulator. 




assumed to be zero and that bit in the instruction is 




On comparison equal jump +NNNN. On comparison 




used as part of the operation code. 




not equal execute next instruction. Mask logical ones 








are only bits compared. 






Binary Format 


76543210765 4 32 10 






TMJ+ 


00 1 NNNNOMMMMMMMM 






TMJ- 


00 1 NNNNl MMMMMMMM 


Class 1 


Branch and I/O Instructions 


Notes 


1 . Condition register set for +, -, = compare. 


Mnemonic 


SBU 




2. Jump past section boundary allowed. 




SBE 




3. N = Jump Count 




SBH 




L = Literal 




SBL 




M = Mask 










Timing 


4 us Branch, 3* us NO Branch 


Mnemonic 


TLX 








TMX 


Description 


Stack and Branch Unconditional 
Stack and Branch on Equal 


Timing 


4 us 




Stack and Branch on High 
Stack and Branch on Low 


Description 


Test Hteral and exit, test mask and exit. 




On condition, increment the stack pointer, store the 




Compare the instruction literal/instruction mask to 




1 1 bit direct address carried by the instruction into 




the accumulator. On comparison equal, exit. On 




the least significant 1 1 bits of the new IAS member 




comparison not equal, execute next instruction. Mask 




and branch to the resulting I AW. The condition 




logical ones are only bits compared. 




register is set by a previous Jump or Compare 
instruction. 


Binary Format 


7 6 543210 765432 10 










Binary Format 


76543210 76543210 


TLX 


00000000 LLLLLLLL 






TMX 


00100 00 MMMMMMMM 


SBU 


OIOIOAAA AAAAAAAO 






SBE 


OIOIOAAA AAAAAAAl 


Notes: 


1 . Condition register set for +, -, = compare. 


SBH 


0101 lAAA AAAAAAAO 




2. L = hteral 


SBL 


0101 lAAA AAAAAAAl 




M = mask 










Notes 1. 


The least significant bit of the direct address is 
assumed to be zero and that bit in the instruction is 
used as part of the operation code. 






2. 


A = Address 


♦If the instruction 


is located at the low order address of any page, 1 uSec is added 






to the instruction time to propagate the carry of the +2 add to the high order 






portion of the address. 







101 



Class 1 


Branch and I/O Instructions 


Class 1 


Branch and I/O Instructions 


Mnemonic 


EXU 


Mnemonic 


SMC 




EXB 




SSC 


Timing 


4 us 


Timing 


4 us 


Description 


Exit Unconditional 


Description 


Set memory control. 




Exit and Branch 




Set memory section and control. 




The exit instructions decrement the Stack Pointer 




When the U bit is set to 0, the address of the index 




and retum program control to the previous IAS 




registers is memory location 1-7 and direct addressing 




position. For EXU the lAW in that position is used. 




is only available in page of section 0. When the U 




For EXB the 1 1 least significant bits of the lAW in 




bit is set to 1 , the effective index register address is 




that position are replaced by the 1 1 bit direct address 




location 1-7 of the section where the indexed 




carried in the instruction. 




instruction is being executed. Likewise the effective 
direct address is page of the section where the 


Binary Format 


76543210 765-4 3210 




direct address instruction is being executed. 

When the V bit is set to 1 any branch, stack & 


EXU 


01100000 00000000 




branch, or exit & branch instructions given with page 


EXB 


OlllOAAA AAAAAAAO 




specified in the branch address will cause the 
branch to occur with the current section and page of 


Notes 1. 


The least significant bit of the direct address is 




the program. If any page other than is specified in 




assumed to be zero and that bit in the instruction is 




the branch address, the V bit control is inactive and a 




used as part of the operation code. 




normal branch will occur. 


2. 


A = Address 




Set memory section and control is a combination of 
set memory section and set memory control 
instructions. 






Binary Format 


76543210 76543210 






SMC 


01101001 UVO 00000 


Class 1 


Branch and I/O Instructions 


SSC 


01101010 UVSSSOOO 


Mnemonic 


SMS 






Timing 


4 us 






Description 


Set memory section 








Provides a means of transfering control from the 


Class 1 


Branch and I/O Instructions 




current section to an outside section. 










Mnemonic 


SAC 


Binary Format 


765 4 3210 76543210 










Timing 


4 us 


SMS 


01101000 OOSSSOOO 










Description 


Set arithmetic condition. 


Notes I. 


S is the section bits defining the section that control 




Arithmetical conditions of the processor will be 




will be transfered to. 




forced to a +, -, = condition dependent upon the 
state of Ace. bits 4 & 5. 00 sets -,01 sets +,10 sets 
=, and 1 1 is invalid. 






Binary Format 


76543210 76543210 






SAC 


01101011 00000000 






Ace. (force +) 


10 






Ace. (force -) 


00000000 






Ace. (force =) 


10 


*If the instruction 


is located at the low order address of any page, 1 uSec is added 






to the instruction time to propagate the carry of the +2 add to the high order 






portion of the address. 







102 



Class 1 


Branch and I/O Instructions 


Class 1 


Branch and I/O Instructions 


Mnemonic 


LSW 


Mnemonic 


LPS Load Processor Status 


Timing 


4 us 


Timing 


3* us 


Description 
Binary Format 


Load sense switches. 

The state of 8 toggle switches (located in the switch 

well under the CRT screen) to the accumulator. 

76543210 76543210 


Description 

Binary Format 
LPS 


Execution of this command transfers a hardware 
status word to the accumulators. 

76543210 7 6543210 
01101101 00000000 


LSW 
Class 1 

Mnemonic 

Timing 


0110110 00000000 

Branch and I/O Instructions 

DPI 
EPI 
CPI 

4 us 


ACC BIT 



1 
2 2 
3 
4 
5 
6 
7 


Stack Pointer Address Bit 2^ 
Stack Pointer Address Bit Ir 
Stack Pointer Address Bit 2^ 
Stack Pointer Address Bit 2^* 
Plus Condition 
Equal Condition 
Interrupt Overflow 
Program Interrupt Switch 


Description 


Disable processor interrupt. 

Enable processor interrupt. 

Clear processor interrupt. 

The automatic stack and branch that results from an 

interrupt is program enabled or disabled. The 

interrupt overflow indicator can be reset by the clear 

instruction. 






Binary Format 


76543210 76543210 






DPI 
EPI 
CPI 


110 1110 
01101110 00000001 
01101110 00000010 






Class 1 


Branch and I/O Instructions 






Mnemonic 


IOC 






Timing 


3* us 






Description 


Input/Output Control 

This instruction is used for all input and output 
operations. The IWL is used to designate the I/O 
sub-class and to pick the I/O device. The IWR 
designates the function to be performed. 






Binary Format 


76543210 76 543210 






IOC 


Ollllnnn yyxxxxxx 






Notes 1. 


n = Device designation 

y, X = Command micro-code 






2. 


Appendix C gives detailed listing of all IOC 
commands. 






♦If the instruction is located at the low order address of any page, 1 uSec is added 
to the instruction time to propagate the carry of the +2 add to the high order 
portion of the address. 







103 



Class 2 




Transfer and Arithmetic Instructions 


Class 2 




Transfer and Arithmetic Instructions 


Mnemonic 




L D X 
L D A 
S T A 


Mnemonic 




A D X 
ADA 
S U X 

SUA 


Timing 




4* us for Immediate Add. 












5 us for Direct Addressing 


Timing 




4* us for Immediate Addressing 






6 us for Indexed Addressing 






5 us for Direct Addressing 

6 us for Indexed Addressing 


Description 




Load Index register 












Load Accumulator 


Description 




Add to Index register 






Store Accumulator 






Add to Accumulator 






Specified index register is loaded with a literal carried 






Subtract from Accumulator 






in the instruction. The accumulator is loaded using 






Specified index register is operated on with the Hteral 






immediate, direct or indexed addressing modes. The 






carried in the instruction. The accumulator 






accumulator is stored in a direct or indexed address. 






operations specify the operand by immediate, direct 






In indexed addressing modes the specified index 






or indexed addressing. In indexed addressing the 






register may be automatically incremented or 






specified index register may be automatically 






decremented. 






incremented or decremented. 


Binary Format 


76543210 76543210 


Binary Format 


76543210 76543210 




L 


DX lOOOOXXX LLLLLLLL 




A 


DX lOlOOXXX LLLLLLLL 


(LA) 


L 


DA 10000000 LLLLLLLL 


(LA) 


ADA 10100000 LLLLLLLL | 


( DA) 


L 


DA 10001000 AAAAAAAA 


(DA) 


A 


DA 10101000 AAAAAAAA 


( I A) 


L 


DA lOOOlXXX AAAAAAYY 


( I A) 


A 


DA lOlOlXXX AAAAAAYY 


(DA) 


S 


TA 10011000 AAAAAAAA 




S 


UX lOllOXXX LLLLLLLL 


( I A) 


S 


TA 1001 IXXX AAAAAAYY 


(LA) 


S 


UA 10110000 LLLLLLLL 








(DA) 


S 


UA 10111000 AAAAAAAA 


Notes: 1. 




X = index register number 
L = literal 


( I A) 


S 


UA 10111 XXX AAAAAAYY 






A = address 


Notes 1. 




L = Uteral 






Y = index modifier 






A = address 

X = index register 


2. 




LA = Immediate Addressing 
DA = Direct Addressing 
lA = Indexed Addressing 






Y = index modifier 


3. 




Direct address 00000000 is invalid. 








Mnemonic 




LIA 








Timing 




4* us 








Description 




Load instruction address. 

This instruction will transfer the 8 least significant 
bits of the current instruction address to the specified 
index register. If the instruction literal is 000, then 
the section and page of the current instruction 
address is transfered to the accumulator. If the literal 
is not 000, then the Uteral is transfered to the 
accumulator. 








Binary Format 


76543210 76543210 








LIA 




lOOlOXXX LLLLLLLL 








Notes: 1. 




X = Index Register number 








2. 




L = Literal 








3. 




A = Address 








*If the instruction is located at the low order address of any page, 1 uSec is added 








to the instruction time to propagate the carry of the +2 add to the high order 








portion of the address. 









104 



Class 3 






Boolean and Compare Instructions 


Class 3 


Boolean and Compare Instructions 


Mnemonic 






ANA 
SAN 


Mnemonic 


C P A 
C P X 








ERA 
SER 
I R A 


Timing 


4* us Direct Address 
6 us Indexed Address 


Timing 
Description 






SIR 

4* us 

AND to Accumulator 

Shift and AND to Accumulator 

EXCLUSIVE OR to Accumulator 

Shift and EXCLUSIVE OR -to Accumulator 

INCLUSIVE OR to Accumulator 

Shift and INCLUSIVE OR to Accumulator 

Result 
OPERAND Accumulator AND FOR lOR 


Description 
Binary Format 


Compare Accumulator 
Compare Index Register 

The CPX instruction compares the contents of the 
specified index register to the Uteral carried in the 
instruction. The CPA instructions compare the 
contents of the Accumulator to a Uteral or to the 
contents of a direct or indexed address. In the 
indexed addressing mode the index register may be 
incremented or decremented. All comparison results 
are stored in the Condition Register as high, low or 
equal. 

76543210 76543210 










10 11 

1 11 
1 110 1 


C P 
(LA) C P 
(DA) C P 
( I A ) C P 


X 1110 XX X LLLLLLLL 
A 11100000 LLLLLLLL 
A IIIOIOOO AAAAAAAA 
A IIIOIXXX AAAAAAYY 








All shift instructions are right circular and literal 
addressing only. Remaining instructions use literal, 
direct or effective addressing. In indexed addressing 
mode, the specified index register may be 
incremented or decremented. Shifts take place prior 
to logical operation. 


Notes 1. 


L = literal 

X = index register 

A = address 

Y = index modifier 


Binary Format 




7654 3210 76543210 






(LA) 
(DA) 
( I A ) 

(LA) 
(DA) 
( I A ) 

(LA) 
(DA) 
( I A) 


ANA 11000000 LLLLLLLL 
ANA 11001000 AAAAAAAA 
ANA IIOOIXXX AAAAAAYY 
SAN llOOOSSS LLLLLLLL 
ERA 11010000 LLLLLLLL 
ERA 11011000 AAAAAAAA 
ERA IIOIIXXX AAAAAAYY 
SER IIOIOSSS LLLLLLLL 
IRA 11110000 LLLLLLLL 
IRA 11111000 AAAAAAAA 
IRA lllllXXX AAAAAAYY 
SIR llllOSSS LLLLLLLL 






Notes 1 . 






L = literal 

A = address 

X = index register 

Y = index modifier 

S = shift count 






2. 






Direct address of 00000000 is invalid. 






*If the instruction is located at the low order address of any page, 1 uSec is added 
to the instruction time to propagate the carry of the +2 add to the high order 
portion of the address. 







105 



IOC COMMANDS 




Class 1 


Branch and I/O Instructions 


Mnemonic 


IOC 


Timing 


3* us 


Description 


Input/Output Control 




This instruction is used for all input and output 




operations. The IWL is used to designate the I/O 




sub -class and to pick the I/O device. The IWR 




designates the function to be performed. 


Binary Format 


76543210 76543210 


IOC 


Ollllnnn yyxxxxxx 


Definition of nnn: 




nnn 


I/O sub-class 





current tape channel 


1 


tape channel 1 


2 


tape channel 2 


3 


keyboard 


4 


CRT 


5 


coaxial interface 


6 


communications interface 


Definition of yxx for the tape channel: 


yxx 


Function 


000 


start tape fwd, slow, erase 


001 


start tape fwd, slow 


002 


start tape fwd, fast 


003 


start tape rev, slow 


004 


start tape rev, fast 


005 


stop tape 


007 


transfer byte 


207 


transfer byte, skip next instruction if busy 


010 


write byte 


Oil 


read byte 


012 


rewind 


016 


read status 



106 



The Read Status instruction will transfer a status word to the 
accumulator. This is structured as follows: 



Ace bit 


Meaning 





keyboard error 


1 


tape error 


2 


I/O status 


3 


runaway 


4 


cartridge out 


5 


cHp out 


6 


end of tape 


7 


spare 



Definition of yxx for the keyboard channel: 

yxx Function 

007 transfer byte 

207 transfer byte, skip next instruction if busy 

013 keyboard beep 

Definition of yxx for the CRT channel: 

yxx for the CRT has the following structure : 

S S P I U D P M 

WHERE : S is the section bits of the page to be displayed 

P is the page bits of the page to be displayed 
I is the interleave bit in 8 line display mode and 

the half page (zone) bit in 4 line display mode. 
U is the underscore bit. When U = 1 , any display character 

with a bit 6 will be underscored. 
D is the disable CRT bit 
M is the 4/8 line mode select bit. If M = 0, the 

8 line mode is selected. 

If the character to be displayed has a 2q bit, this character 
position will be blanked. 

Definition of yxx for the coaxial interface: 



yxx 


Function 


000 


start transmit 


001 


receive byte 


201 


receive byte, skip next instruction if busy 


002 


transmit data byte 


003 


transmit control byte 


004 


stop transmit 


006 


inhibit line 


007 


set device address 


010 


set master mode 


Oil 


set slave mode 



Definition of yxx for the communications interface: 



yxx 


Function 


000 


transfer ace. to queue reg. 


001 


select comm. interface mode 


002 


transfer queue to reg. to ace. 


004 


present status 



107 



December 1972 



Manual No. S-100-2 



COGAR IIMFORMATIOINI SYSTEMS, IIMC. 



COSBY MANOR ROAD UTICA, NENA/ YORK 13502 C3153 737-5750