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DlMinM 



IM6103 CMOS Parallel 
Input-Output Port (PIO) 



FEATURES 

• 20 Programmable I/O Pins 

• TTL Compatible Inputs and Outputs 

• Compatible with I M 6 100 Microprocessor Family 

• Low Power Dissipation < 10 mW 

• Extended Temperature Range, -40° C to +85°C 

• Single Power Supply 



GENERAL DESCRIPTION 

The IM6103 is a Parallel Input-Output Port (PIO) device de- 
signed for use in IM6100 microcomputer systems. Its func- 
tion is to provide a general purpose parallel I/O component 
to interface peripheral equipment to the IM6100 system bus. 
The functional configuration of the IM6103 is programmed 
by the user software so that normally no external logic is 
necessary to interface a wide variety of peripheral devices 
such as displays, printers, keyboards, etc. to an IM6100 micro- 
computer system. 

A general purpose all-CMOS microcomputer system with 
64 x 12 RAM, Ik x 12 ROM and 20 I/O lines can be built 
with just four CMOS LSI devices - IM6100 microprocessor, 
IM6512 (64 x 12) RAM. IM6312 (1k x 12) ROM and 
IM6103PIO. 



FUNCTIONAL BLOCK DIAGRAM 



DXq-11 £ 



SEL6 - 
SEL7 - 



DEVSEL- 
LXMAR - 

C1 - 
SKP/INT - 



PIO 
SELECT 



c=> 



STATUS 
REG 



c=> 



PORT 

A 
HIGH 




PORT 

A 
LOW 



HAND- 
SHAKE 
CNTRL 



.PC8-11 
'PA4-7 




ORDERING INFORMATION 



PART NO. 


TEMPERATURE 
RANGE 


OPERATING 
VOLTAGE 
RANGE 


PACKAGE 


IM6103 AMDL 


-55°Cto+125°C 


4-11V 


40 Pin Ceramic 


IM6103 AIDL 


-40°C to +85°C 


r 4-11V 


40 Pin Ceramic 


IM6103 AIPL 


-40°C to +85°C 


4-1 1V 


40 Pin Plastic 


IM6103 IPL 


-40°C to +85°C 


4-7V 


40 Pin Plastic 


IM6103 CPL 


0°C to +70°C 


4-7V 


40 Pin Plastic 


IM6103MDL 


-55°C to+125°C 


4-7V 


40 Pin Ceramic 


IM6103 IDL 


-40°C to +85° C 


4-7V 


40 Pin Ceramic 



PIN CONFIGURATION 



vcc 


E 


W 


a 


PB11 


PA7/PC1 1 


E 




n 


PB10 


PA6/PC10 


n 




D 


PB9 


PA5/PC9 


E 




B 


PB 8 


PA4/PC8 


E 




n 


PB7 


SKP/INT 


E 




35] 


PB6 


PAs/IRS 


E 




B 


PB5 


PA9/IRE 


E 




u 


PB 4 


Ci 


E 




n 


PB3 


LXMAR 


E 


IM6103 


B 


PB 2 


PA10/ORS 


E 


PIO 




PB t 


DEVSEL 


E 




H 


PBo 


PAn/ORF 


E 




U 


DX11 


SEL6 


E 




13 


DX10 


SEL 7 


01 




u 


GND 


DXo 


E 




m 


OXg 


DX! 


E 




«1 


OX 8 


OX 2 


E 




m 


DX 7 


DX 3 


E 




u 


DX 6 


DX 4 


E 




ID 


DX 5 



PACKAGE DIMENSIONS 

ji 



_ 2.020 

MAX 




IM6103 



ABSOLUTE MAXIMUM RATINGS 

Operating Temperature 

Industrial IM61031 
Storage Temperature . 

Supply Voltage 

Voltage on Any Input or Output Pin With Respect to GND -0.3V to VfjC +0.3V 

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent 
device failure. These are stress ratings only and functional operation of the device at these or 
any other conditions above those indicated in the operational sections of this specification is 
not implied. Exposure to absolute maximum rating conditions for extended periods may cause 
device failures. 



. -40°Ctb+85°C 
-65°C to +150°C 
. ... . . . . +12V 



DC CHARACTERISTICS 

TEST CONDITIONS: VrjC = 5V ± 10%, Ta = Industrial 





SYMBOL 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


1 


V|H 


Logical "1" Input Voltage 




Vcc-17 






V 


2 


V|L 


Logical "0" Input Voltage 








0.8 


3 


IlL 


Input Leakage 


OV<V|N<V C C 


-1.0 




1.0 


juA 


4 


VOH 


Logical "1" Output Voltage 


'OUT = 0 except pins 6, 9 


V C C-1;0 






V 


5 


vol 


Logical "0" Output Voltage 


ldUT = 0 






. : 0.45 


6 


"0 


Output Leakage 


ov<v 0 <v C c 


-1.0 




1.0 


fiA 


7 


•cc 


Supply Current 


V C C = 5V 

CL=50pF;T A =25 o C 
FCLOCK = Operating Frequency 






2.5 


mA 


8 




Input Capacitance 






7.0 


8.0 




9 


c 0 


Output Capacitance 






8.0 


10.0 



AC CHARACTERISTICS 

TEST CONDITIONS: VqC = 5V ± 10%, Ta = -40° C to +85°C, Cl = 50pF, All times in ns. 





SYMBOL 


PARAMETER 




MIN 


MAX 


UNITS 


1 


t A DOS 


Address Set-Up Time 


DX-LXMARI 


110 






2 


tADDH 


Address Hold Time 


LXMARI-DX 


150 






3 


tDEN 


Output Enable Time 


DEVSELI-DX 




550 




4 


tDC 


Output Enable Time 


DEVSEL!-^ 




550 




5 


tDI 


Output Enable Time 


DEVSELI-SKP 




400 




6 


•tDS 


Data Set- Up Time 


DX-DEVSELt J 


200 






7 


t DH 


Data Hold Time 


DEVSELt-DX 


150 






8 


tps 


Data In Set-Up Time 


Port Data In-LXMARI 


200 




, ns 


9 


tPH 


Data In Hold Time 


LXMARl— Port Data In 


225 




10 


tDI 


Delay Time 


DEVSELt-Port Data Out 




550 




11 


tBS 


Data In Set-Up Time 


Port B In— 1 RS| 


200 






12 


tBH 


Data In Hold Time 


1 RS^-Port B In 


150 






13 


tD2 


Output Enable Time 


ORSt-Port B Out 




550 




14 


tD2 


Output Disable Time 


O RSI-Port B Out 




200 




15 


tD3 


Delay Time 


1RS|-IRE| 
ORSI-ORFI 
DEVSELt-IREt 
DEVSELt— ORFt 




550 





IM6103-1 



jMinEMlL 



ABSOLUTE MAXIMUM RATINGS 

Operating Temperature ... , . .. 

Industrial IMM6103I . . . . . ... ...... . . . . . . -40°C to +85°C 

Storage Temperature -65°C to +150°C 

Supply Voltage .". . . ... ; . +8V 

Voltage on. Any Input or Output Pin With Respect to GND ; . . . -0.3V to VfjC +0.3V 

NOTE: Stresses above' those listed under "Absolute Maximum Ratings" may cause permanent 
device failure. These are stress ratings only and functional operation of the device at these or 
any other conditions above those indicated in the operational sections of this specification is 
hot implied. Exposure to absolute maximum rating conditions for extended period 
device failures. , 



DC CHARACTERISTICS 

TEST CONDITIONS: Vcc = 5V ± 10%, T A = Industrial 





SYMBOL 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


1 


V| H 


Logical "1" Input Voltage 




VcC-1-7 






V 


2 


V|L 


Logical "0" Input Voltage 








0.8 


3 


1 1 1_ 


Input Leakage 


OV<V|M<VcC 


-1.0 




1.0 


M 


4 


VOH 


Logical "1" Output Voltage ' 


'OH = -0.2 mA except pins 6,9 


vcc-1.0 






V 


5 


Vol 


Logical "0" Output Voltage ■ 


IOL=2.0mA 






0.45 


6 


'o ; 


Output Leakage 


ov<v 0 <vcc 


-1.0 




1.0 


iuA 


7 


,'cc 


Supply Current 

' i ■ ! 


Vcc = 5.0V 

C L = 50pF;T A = 25 o C 
FCLOCK - Operating Frequency 






2.5 


mA 


8 




Input Capacitance 






7.0 


8.0 


pF 


. 9 


c 0 


Output Capacitance 






8.0 


10.0 



AC CHARACTERISTICS 

TEST CONDITIONS: Vqc = 5V ± 10%, Ta = -40°C to +85°C, Cl = 50pF, All times in ns. 





SYMBOL 


PARAMETER 




MIN 


MAX 


UNITS 


1 


tADDS 


Address Set-Up Time 


DX-LXMARl 


80 






2 


tADDH 


Address Hold Time 


LXMARl-DX 


100 






3 


tDEN 


Output Enable Time 


DEVSEL4-DX 




450 




4 


tDC 


Output Enable Time 


DEVSEL4— Ci 




450 




5 


tDI 


Output Enable Time 


devsel;-skp 




330 




6 


tDS 


Data Set- Up Time 


DX-DEVSELt 


150 






7 


tDH 


Data Hold Time 


DEVSELt-DX 


100 






8 


tps 1 


Data In Set-Up Time 


Port Data In-LXMARI 


150 






9 


tPH 


Data In Hold Time 


LXMARl— Port Data In 


175 




ns 


10 


tD1 


Delay Time 


DEVSE Lt-Port/Data Out 




450 




11 


tBS 


Data I h Set-Up Time 


Port B in— I HSl 


150 






12 


tBH 


Data In Hold Time 


I RSI-Port B In 


100 






13 


tD2 


putput Enable Time 


ORSt-Port B Out 




450 




14 


tD2 


Output Disable Time 


ORSI-Port B Out 




200 




15 


tD3 


Delay Time 


IRSj-IREl • 
ORSI-ORFI 
DEVSELt-IREt 
DEVSELt-ORFt 




450 





IM6103 



SEL 6 
SEL 7 



DEVSEL 
LXMAR 

Cl 
SKP/INT 



FIGURE 1: Functional Block Diagram. 



IM6103 FUNCTIONAL PIN DEFINITION 



PIN 
NUMBER 


SYMBOL 


INPUT/ 
OUTPUT 


DESCRIPTION 


1 


v cc 




Positive Power Supply 


2 


PA7 


I/O 


Port A I/O Line (4). Most Significant Bit 
of Port A in Mode 10. 




PC11 


I/O 


Port C I/O Line (8) in Mode 1 1/0 X-Most 
Significant Bit. 


3~5 


PA6~PA4 


I/O ; 


Port A5 ~A7 (Mode 10). 




PCi 0 ~PC 8 


I/O 


PortCg~Cii (Mode 11/OX). 


6 


SKP/INT 


0 


Time Multiplexed SKP and INTREQ lines to 
the IM6100 Microprocessor — Active Low. 


7 


PA8 


I/O 


Port A I/O Line in Mode 11/10 - Most 
Significant Bit of Port A in Mode 11. 




IRS 


0 


Input Register Strobe to clock data into 
Port B in Handshake Mode (Mode OX). 
Port B Latches in the data on the falling 
edge of IRS (I RSI). 


8 


PAg 


I/O 


Port Ag (Mode 11/10). ' 




IRE 


0 


Input Register Empty output goes high when 
Port B input buffer has been read by the 
IM6100 microprocessor. It goes low when 
Port B input buffers are strobed in by IRS|. 
(Mode OX). PIO may be programmed to 
generate an INTREQ on I RE|. 



°* CO 



PIO 
SELECT 



CONTROL C 



CO 



CO 



PORT . . 
A 

HIGH " 



v PORT 

) A 
' LOW 



a k, HAND- 

< > SHAKE 

N / CNTRL 



CO 



V PA 4-7 



PA8-11 
>IRS. IRE, 



IM6103 

IM6103 FUNCTIONAL PIN DEFINITION (Continued) 



PIN 
NUMBER 


SYMBOL 


INPUT/ 
OUTPUT 


DESCRIPTION 


9 


C1 


0 


C1 output goes low upon completion of PIO 
Port data transfer to the IM6100 Accumula- 
or (AC). This output is an open-drain out- 
put to be wire-OR'D with C-| Lines from 

1 f^thor 1 IV/I£% 1 00 narinhoKol PAntrAt tare 

oinci iivio iuu pcnpncidi coriiroiiers. 


10 


LXMAR 


..I . " 


Address Latch enable signal from the IM6100. 
PIO clocks in address and control informa- 
. tion from the IM6100 on the falling edge of 
LXMAR. (LXMARj). All Port inputs are 
sampled at LXMAR |. 


11 


PA10 
ORS 


I/O 
I 


Port A10 (Mode 11/10). 

Output Register Strobe input to enable Port B 
output buffers in Mode OX. Port B is tri- 
stated when ORS is low. 


12 


DEVSEL 


I 


Input-Output Device Select control line from 
the IM6100. It performs both the read and 
, write function. The first negative transition 
after LXMAR|, enables the DX output buf- 
fers of the selected PIO for a read operation. 
When DEVSEL returns high, the 'read' 
operation is terminated. The second negative- 
going pulse on DEVSEL serves as a 'write' 
pulse to the selected PIO and the IM6100 
AC data is written into the selected PIO re- 
gister or port on the rising edge. 


13 


PA11 


I/O I 


Port An (Mode 11/10)-Least Significant 
bit of Port A. 




ORF 


0 j 


Output Register Full output goes high when 
the IM6100 writes into Port B in a hand- 
shake mode. It goes low. when the peri- 

nhpral Hpv/irp rpaH<; Port R hv pnahlinn ORS 

high. The PIO may be programmed to gen- 
erate an INTREQ on ORF>|/(Mode OX). 


14 


SEL 6 


■ I 


A Chip Select Input. PIO has two chip 
selects, SEL6 and SEL7, thereby enabling 
up to four PIO chips in a system. 


15 


SELy 


I 


A Chip Select Input. 


16-25 


DX.07DX9 


I/O 


The IM6100 System bus (Data and Address). 


26 


GND 




Ground 


27~28 


DX^-DXn 


I/O 


I M6 100 System bus (Data and Address). 


29-40 


PBorPBn 


I/O 


I/O Port Pin. PBrj is the most significant 
bit, and PB1 1 is the least significant bit. 



I M 61 03 



IM6100 SYSTEM TIMING 

The tristate bidirectional 12-bit DX bus is used to transfer 
data arid control information (Figure 3) between the IM6103 
and the I M61 00 microprocessor. , The I M6 100 transmits the 
device address and control information on the DX bus 
during the 'execute' phase of an Input-Output Transfer 
(IOT) instruction. The IM6103 accepts this information on. 
the falling edge of the LXMAR (Address Latch Enable) 
Signal. 

The address bits (6-7) are compared with the chip select in- 
puts (SEI_6 and SEL7) to address 1 of 4 PIO's. The IOT ad- 
dress bits (3-5) are programmed internally to respond to the 
bit pattern 011. The SEl_6 and SEL7 inputs should be ex- 
ternally hard-wired to match the DX6 and DX7 chip select 
bits. As shown in Fig. 3, DEVSEL goes low, during the 
first half of an IOT execute machine cycle for a read operation 
and it goes low again in the second half for a write operation. 
The IM6103 responds to a 'read' instruction by putting data 



on the DX bus and C-| output (of IM6103) low when DEVSEL 
(from IM6100) input is low. C1 line goes low to indicate an in- 
put transfer cycle to the I M6 100. All PIO data transfers to the 
IM6100 Accumulator (AC) is an 'OR' transfer, (i.e., PIO data 
is OR'ed into the contents of the AC). i 1 

During the write operation into P|0, the PIO accepts data 
from the IM6100 Accumulator on the rising edge of the 
DEVSEL. During and after the PIO write, the contents of the 
accumulator are not cleared. 

SKP/INT line goes low during the 'read' DEVSEL if the 
IM6103 is responding to a 'skip' instruction, and the 'skip' 
conditio^ is met, therefore causing the IM6100 to skip the 
next sequential instruction. SKP/INT line reflects the inter- 
rupt request status of the IM6100 at all times except during 
the 'read' DEVSEL. The SKP/INT line goes low if an active 
interrupt request is pending. During read DEVSEL mode, 
the SKP/INT indicates the current skip condition. The bits 
are interpreted as shown below: 



DX 0 
0 



IOT _ 
CODE 



_ pio ' 

CODE 
FIGURE 2: 





• ' ■• 


' • 


• = 


• 


dxh 


6 


7 


8 


9 


10 


11 


SEL 6 


SEL7 


18 




■9 


ho 


in 


. 1of4 




PIO 







SELECT 

PIO instruction format. 



IM6100 
0SC OUT 



•firuiJTJir^^ 




1M6100 

LXMAR 



IM6100 
MEMSEL 



DX(o-„) A {jjjg|LJ INSTR 



INSTR U PIO DATA 



M. 



1M6100 

DEVSEL 



IM6103 
CI 



LOW FOR 
READ 



IOT INSTR SAMPLED BY PIO 

(i.e., All input data lines 
are sampled.) 



PIO OATA.CI.SKP SAMPLED 
BY IM6100 FOR READ 



IM6100ACtoPI0 
FOR WRITE 



FIGURE 3: 



TOT EXECUTE MACHINE CYCLE 
IM6103 system timing diagram. 



INTREQ SAMPLED 
BYIM6100 



OPERATION OF PORT BUFFERS 

The IM6103 has 20 I/O pins which can be individually pro- 
grammed in groups of 4, 8 or 12 bits in three different modes 
of operation. 

In Mode 11, the 20 I/O lines are divided into three ports: 
-Port A with 4 bits (PA8-PA1 1 ) 



-Port B with 12 bits (PBrj-PBn) 

-Port C with 4 bits (PCr-PCi 1 ) 

In Mode 10, the 20 I/O lines are grouped into 2 ports- 
-Port A with 8 bits (PA4-PA11) 1 
-Port B with 12 bits (PB0-PB11) 

-The four I/O lines associated with Port C in Mode 11 
(PCr-PCi 1 ) are allocated to Port A as PA4-PA7. 



IM6103 



In Mode OX, there are two ports— Port B with 12 bits and 
Port C with 4 bits and four lines, for handshake control 
logic. Four lines of Port A in Mode 1 1 (PAs-PAn) are re- 
assigned as handshake control lines. They are: 
-Input Register Strobe (IRS) 
-Input Register Empty (IRE) 
-Output Register Strobe (ORS) 
-Output Register Empty (ORE) 

The handshake logic controls the data transfer for the Port B. 
Port C operation remains the same as in Mode 11. 

For an 'input' transfer in OX Mode, the input register empty 
(IRE) output goes high to indicate to the peripheral device 
that the input register is empty (as shown in Fig. 4). The peri- 
pheral device may then strobe in the new data into Port B 
with Input Register Strobe (IRS). At this time, IRE goes 
low to indicate to the peripheral device that the input buffer 
is full, and remains low until Port B has been read by the 
IM6100 microprocessor. IRE then goes high after the IM6100 
executes a Read Port B (RPB) instruction to initiate an- 
other input sequence. The data into Port B should be valid 
only for a short duration before and after IRS makes the 1 to 
0 transition. 



The IM6100 monitors the status of ORF (Output Register 
Full). If it is low (i.e., output register is empty), IM6100 may 
load data into Port B output buffer with SPB/CPB/WPB in- 
struction. ORF goes high a delay time after the rising edge of 
the 'write' DEVSEL, signaling the peripheral device that out- 
put buffer has new data. During this time, Port B output buf- 
fers remain tristated. The peripheral device may then enable 
and read out Port B output latches by activating ORS (Out- 
put Register Strobe) high. The falling edge of ORS (from high 
to low) signajs the PIO that the peripheral device no longer 
needs the valid current information. Port B is tristated and 
ORF then goes low, thereafter* to indicate another output 
sequence. 

ORF should be set to 0 and IRE to 1 with a 'write' command 
in Mode OX, to initiate the handshaking sequence. 

The IM6100 microprocessor should not write into Port B until 
ORF is low for an 'output' transfer and should not read Port B 
until IRE is low for an 'input' transfer. The peripheral device 
reads Port B if ORF is high and writes into Port B if IRE is 
high. 



IM6100 DEVSEL 
(RPB INSTRUCTION) 

IRS 

(PERIPHERAL-* PIO) 
IRE 

(PIO -PERIPHERAL) 



PORT B DATA 
(PERIPHERAL -PIO) 




FIGURE 4: Input data transfer (peripheral device to PIO). 



For an 'output' transfer in OX mode, the IM6100 micropro- 
cessor writes the data into Port B and its timing is shown in 
Figure 5. ORF line from the PlO goes high, signaling 
the peripheral device that the output register is full. The peri- 
pheral device may then strobe in the new data from Port B 
with ORS. Port B stays in the high impedance mode until 
ORS is activated by the peripheral device. ORF line goes 
low and remains low until Port B has been written into by the 
IM6100 microprocessor. ORF then goes high, initiating an- 
other output sequence. 



IM6100 DEVSEL v 

(SPB/CPB/WPB) V_ 



ORF 

(PIP -PERIPHERAL) - 
ORS 

(PERIPHERAL-* PIP) - 

PORT B DATA 
(PIP -PERIPHERAL)" 



£71 



**-tQ2 



FIGURE 5: Output data transfer (PIO to peripheral device). 



The PIO may be programmed to generate an INTREQ (Inter- 
rupt Request) to the microprocessor when ORF or IRE goes 
low by setting the respective Interrupt enable bits, OREN 
and IREN. 

The IM6100 may poll the status of ORF or IRE by executing 
the respective skip instructions SKPOR and SKPIR, by reading 
the status register or by reading "Port A". 

In Mode 11 and 10, when handshaking control is not in effect, 
the execution of SKPOR and SKPIR Instructions depend on 
the state of the Port A lines PA-j -j and PAg, respectively. The 
Interrupt feature is available only in Mode OX. 

The mode of operation — 11, 10 or OX, is selected by pro- 
gramming the Status Register (SR). 

All ports are bidirectional. The execution of a 'write' in- 
struction caused a port to be automatically programmed to 
be an 'output'. The output data may be changed by using the 
'set', 'clear' or 'write' instructions. The output remains valid 
until the port bit lines are reset to be inputs. 

Execution of a 'read' instruction causes a port to be automati- 
cally set as an 'input' port — i.e., it presents a very high imped- 
ance to the I/O lines. Data appearing on the I/O lines will be 
sampled into the port input latch at every LXMAR pulse and 
may be read by the I M61 00 microprocessor by the 'read' 
instruction. 

In Mode OX, Port B acts as a tristate bidirectional buffer 
which is controlled by an external peripheral device. ORF 
and IRE lines are outputs and ORS and IRS lines are inputs. 

At power-on, all ports are defined to be input ports and the 
PIO is initialized to be in Mode 10. With 20 I/O lines 
partitioned into the 8/12 (i.e., Port A = 8 bits, Port B = 12 
bits) format. 



IM6103 

STATUS REGISTER 



The Status Register (SR) has 2 mode bits, W\q and Mg which 
can be modified by the WSR (Write Status Register) instruc- 
tion. These two bits define the mode of operation for the 
I M6 103 as shown in Figure 8. 



M 8 


Mg 


MODE 


PORT OPERATION 


0 


* 


Mode OX 


PBfj-1 1 . PCs-1 1 , 1 RS, I R E, ORS, OR F 


1 


0 


Mode 10 


PB0-11.PA4-H 


1 


1 


Mode 1 1 


PBo-11,PC8-11,PA 8 -11 




INTERRUPT OPERATION 

The IM6103 may be programmed to generate an interrupt re- 
quest input (INTREQ) when ORF or IRE goes low, by setting 
the corresponding interrupt enable bits, OR EN or I REN, to 1. 
If the IM6100 interrupt system has been previously enabled, 
the microprocessor will acknowledge the INTREQ input. If 
the IM6100 }iP does not see the higher priority INTREQ's, 
inputs from other peripheral controllers such as IM6102 
Memory Extender/Direct Memory Access/ Internal Timer Con- 
troller (MEDIC) or IM6101 Parallel Interface Elements (PIE) 
\n the system, the interrupt service routine should initiate a 
software poll of the PIO's in the system to identify the parti- 
cular PIO that generated the INTREQ. In Mode OX, the inter- 
rupt request status of ORF and IRE may be identified by 
reading the Status Register. OR INT or I R INT will be set to 0 
if ORF (being low) or IRE (being low) is generating an 
INTREQ. Note that IM6102 MEDIC and IM6101 PIE pro- 
vide an automatic priority vectoring. 

The interrupt feature of IM6103 is available only in Mode OX. 
An ORF INTREQ may be removed by one of the following 
methods: 

• executing a SPB/CPB/WPB Instruction (ORF goes high if 
Port B is written into), or 

• setting ORF to 1 with SPA/WPA Instruction, or 

• by resetting OR EN to 0 with a CPA/WPA Instruction, or 

• by changing to Mode 11/10. 

An IRE INTREQ may be removed by: 

• executing a RPB Instruction (IRE goes high after Port B is 
read), or 

• setting IRE to 1 with SPA/WPA Instructions, or 

• resetting I REN to 0 with a CPA/WPA Instruction, or 

• changing to Mode 11/10. 

PIO may be software programmed to generate an INTREQ 
to the IM6100 by resetting ORF or IRE to 0 with a CPA/WPA 
Instruction and by setting the corresponding enable bit, OR EN 
or I REN, with a SPA/WPA Instruction in Mode OX. 



FIGURE 8: Mode bit assignments. 

The Mode and Interrupt status bits, OR I NT (Output Register 
empty Interrupt) and IRINT (Input Register empty Interrupt), 
may be read with the RSR (Read Status Register) instruction. 
The interrupt status bits are set to 0 if the corresponding flag is 
requesting an interrupt. 

In Mode 11/10 the current value of PAi 1 and PAg can be in- 
terrogated. In this mode, Port A can be cither an input or an 
output. Ms and Mg are initialized to "1 1" at power-on. 



| DX8 | | DX 9 | DXiq | DX11 | DX BUS 

| Ms | | M 9 [PRINT I IRINT | SR MODE OX READ 

| Ms | [ Mg [ PAi 1 [ PAg "I . SR MODE 11/10 READ 

| Ms | | M 9 [ SR .MODE 11/10/OX WRITE 

FIGURE 9: Status register bit assignments. 



SKIP OPERATION 

The IM6100 may poll the status of ORF or IRE in Mode OX, 
by executing a skip instruction, SKPOR or SKPIR. The 
IM6103 will assert the SKP/INT line low if the corresponding 
status line (ORF or IRE) is low, causing the next sequential 
instruction to be skipped. During this cycle, ORF and IRE re- 
main unchanged. 

In Mode 11/10, SKPOR and SKPIR instruction executions de- 
pend on the state of PA-| -j and PAg, respectively. Port A may 
be an input or output port. 



If ORF is reset to 0 by executing a CLRPA or WP A instruction 
to initiate the handshaking sequence, the next SKPOR instruc- 
tion will cause the next sequential instruction to be skipped. 



IM6103 



PIO INSTRUCTION 

NOTE: Symbol Definition 



"•"-AND 
"+"-OR 

"=" - Is Replaced By 



PIO 
CONTROL 



0 0 0 0 



0 0 0 1 



0 0 10 



0 0 11 



0 10 0 



0 10 1 



0 110 



MNEMONICS 



SETPA 
(Set Port A) 



CLRPA 



WPA 



RPA 



SETPB 



CLRPB 



WPB 



DESCRIPTION 



Set PAj to 1 if ACj is 1. AC is not 
cleared. 

. Mode 1 1 : PA,=PA,+ACj, 8 < i< 1 1 
Mode 10: PAj=PAj+ACj, 4< i< 1 1 
Mode OX: I REN = IREN + ACs 
IRE = IRE + ACg 
OR EN = OR EN .+ AC10 
ORF = ORF + ACn 

Clear Port A. Clear PAj to 0 if ACj 
is 1. AC is not cleared. " ; 

Mode 11: PA,=PAj-ACj ( 8<i<11 

Mode 10; PAj=PAj'ACj, 4<i< 1 1 

Mode OX; I REN = IREN»ACjj / 
IRE = IRE 'ACg _^ 
OREN = ORE N'AC iQ 
: ORF = ORF«ACii 

Write Port A. Set PAj equal to AC,. ; ' 
AC is not cleared. 

Mode 11: PAj=ACj, 8<i<11 
Mode 10: PAj^ACj, 4<i< 1 1 

Mode OX: IREN = ACs ' 
.. > IRE = ACg 
OREN = AC10 
ORF. = ACn 

Read Port A. 'OR' transfer PA to AC. 

Mode 1 1 : ACj=AC,+PA (/ 8<i< 1 1 
AC,=ACj, 0<i<7 

Mode 10: ACj=ACj+PAj, 4<i< 1 1 
; ACj=ACj, 0<i<3 

ModeOX: AC8=AC8+ IRS 
ACg=ACg+IRE 
ACio=ACio+ORS 
AC|i=ACn+ORF 
ACj=ACj,0<i< 7 

Set Port B. Set PBj to 1 if ACj is 1. 
AC is not cleared. 

PBj=PBj+ACj, 0<i<11 

Clear Port B. Clear PBj to 0 if ACj 
is 1. AC is not cleared. 
PB,=PBj»ACj, 0<i<11 

Write Port B. Set PBj equal to ACj. 
AC is not cleared. 
PBj=ACj, 0<i<11 



PIO 
CONTROL 



0 111 



1 0 0 0 



10 0 1 



10 10 



10 11 



110 0 



110 1 



1 1 1 0 



1111 



MNEMONICS 



RPB 



SETPC 



CLRPC 



WPC 



RPC 



SKPOR 



SKPIR 



WSR 



RSR 



DESCRIPTION 



Read Port B. 'OR' transfer PB to AC. 
ACj=ACj+PBj,0<i<11 

Set Port C. Set PCj to 1 if ACj is 1. 
AC is not cleared. 

Mode 1 l and OX: PCj=PCj+ACj . 

8<i<11 
Mode 10: No operation 

Clear Port C. . Clear PCj to 0 if ACj 
is 1. AC is not cleared. 

Mode 11 and OX: PCj=PCj*ACj '. 

1 * 8< i< 1 1 
Mode 10: .No operation 

Write Port C. Set PCj equal to AC,; 
AC is not cleared. 

Mode 11 and OX: PCj=ACj 
8<i<11 
Mode 10: No operation 

Read Port C. 'OR' transfer PC to AC. 

Mode 1 T and OX: ACj=ACj+PCj 

8<i<11 
Mode 10: No operation 

Skip the next sequential instruction if 
PAi 1/ORF is low. 

Mode 1 1 and 10: Skip if PAi 1 is 
low. 

ModeOX: Skip if ORF is low. 

Skip the next sequential instruction if 
PAg/IRE is low. 

Mode 1 1 and 10: Skip if PAg is 

low. ' ' 

Mode OX: Skip if IRE is low. 

Write Status Register. AC is not 
cleared. 

M8 = ACs 

Mg = ACg . 

Read Status Register. 'OR' transfer 
Status register to AC. 

AC8 = AC8 + M8 
ACg = ACg + Mg 
\ACj = ACj,0<i<7 '.. 

Mode 1 1 and 1 0: ACi o= ACi o+PA 1 1 
ACi"i=ACn+PAg 
ModeOX: ACio=AC 10 +OR INT 
ACn=ACii+|RINT 



IM6103 



DXq DXi 



DX2 



DX 3 



DX4 



DX5 



DX 6 



DX7 



DX 8 



DXg 



DX10 



pxn 



SEL 6 | SEL7 I "l8~l I '9 I '10 \~} 



DXBUS 

PIO INSTRUCTION 



0 0 0 



ff 0 0 



0 0 0 



0 I PAs I I PA9 I PA10 | PAn I PORT A MODE 11 READ 



] I 0 I PA4 I PA 5 I J PA 6 1 PA7 I PAs 1 



PA4 



PA 5 



PA6 



PA 7 



PAg 



IRS 



IREN 



PAg 


PA10 


PA11 


PORTA MODE 11 WRITE 
PORTA MODE 10 READ 
PORTA MODE 10 WRITE 




PAg 


PA10 


PA11 




PAg 


PA10 


PA11 




PORTA MODE OX READ 


[ IRE 


ORS 


ORF 



IRE OREN ORF 



PORTA MODE OX WRITE 



PBq PB1 PB2 



PB3 PB4 PB5 



PB6 PB7 PB8 



PBg PB10 PB11 PORT B MODE 11/10/OX READ/WRITE 



0 | | 0 I 0 | PCs | I PCg | PCiQ I PCn I PORTC 



MODE11/OX READ 



| PCs | ["~PCg~ PC10 | PCn I PORT C MODE 11/OX WRITE 



Ms 



Ms 



Mg 



PAll 



PAg 



0 I Ms I I Mg I PRINT 



IRINT 



Mg 



STATUS REG MODE 11/10 READ 
SJATUS REG MODE OX READ 
STATUS REG MODE 11/10/OX WRITE 



FIGURE 6: IM6103 PIO register bit assignments. 



PINS 


I; 2 


3 4 5 | 


r 


■ 


11 


13 


29 


30 


31 


32 


33 


34 


35 


36 


37 


38 


39 


40 








































MODE 10 


|PA 7 


PA 6 PA 5 PA 4 | 


PA 8 


PAg 


PAlO 


PA11 | 


PBo 


PBi 


PB 2 


PB 3 


PB4 


PB5 


PB 6 


PB6 


PB 8 


PBg 


PB10 


PBll| 








































MODE 11 


|pch 


PC 10 PCg PC 8 | 


| PAS 


PAg 


PA10 


PA11 


PBo 


PB1 


PB2 


PB3 


PB4 


PB 5 


PB 6 


! PB 7 


PB 8 


PBg 


PBlO 


PB11 








































MODE OX 




PC 10 |PCg PC 8 | 


IRS 


IRE 


ORS 


ORF 


PBg 


PB1 


PB2 


PB3 


PB4 


PB 5 


PBg 


PB 7 


PB 8 


PBg 


PBlO 


PB11 



FIGURE 7: IM6103 PIO port pin assignments. 




IM6100 OEVSEL 
(RPB INSTRUCTION) 



IRS 

(PERIPHERAL -*PIO) 
IRE 

(PIO -^PERIPHERAL) 



PORT B DATA ^ 
(PERIPHERAL -PIO) 




tD3- 



FIGURE 11: Input data transfer (peripheral device to PIO). 



IM610Q DEVSEL V 

(SPB/CPB/WPB) \ 



ORF 

(PIP-PERIPHERAL) . 

ORS 

(PERIPHERAL -PIP) 

PORT B DATA 
(PIP -PERIPHERAL) 



tD3-^ 



Jr. 



4 


tD3-*" 













h 



FIGURE 12: 



Output data transfer (PIO to peripheral device). 



IM6103 

APPLICATION OF IM6103 

Figure 13 illustrates a microcomputer system block diagram using I M6 103 in a dual processor system 




IM6103 


PIO 




f 





IM6101 




PERIPHERAL 


PIE 




DEVICES 



2xL 



<2l 



SLAVE 
CPU 



IM6100 




LOCAL 
MEMORY 










FIGURE 13: Dual processor system with shared memory.