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MODELS 92200/93200 SERIES 

TIME-MULTIPLEXED 

COMMUNICATION CHANNELS 

(TMCC) 

Technical Manual 

SDS 900685C September 1 965 



Price: $6.25 



SCIENTIFIC DATA SYSTEMS/1649 Seventeenth Street/Santa Monica, California/UP 1-0960 



© 



1965 ScisnHfic Data Systems, Inc. Printed in U.S.A. 



September 1965 



SDS 900685C 



Contents 



TABLE OF CONTENTS 



Section 
I 



II 



GENERAL DESCRIPTION 

1 . 1 General , 

1 . 5 Purpose of Option 

1.7 Description and Leading Particulars 

1.10 Piiyslcal Description 

1.12 TMCC Models 922XX 

1.14 One Channel Configuration 

1.16 Two Channel Configuration 

1.18 Three Channel Configuration 

1.20 Four Channel Configuration 

1 . 22 TMCC Models 932XX 

1.24 One Channel Configuration 

1.26 Two Channel Configuration 

1.28 Three Channel Configuration 

1.30 Four Channel Configuration 

1.32 Semiconductor Complement 

1.34 Interlace Feature 

PROGRAMMING 

2. 1 Purpose 

2.3 General Operation 

2. 1 1 Direct Parallel Input/Output 

2. 13 Single-Bit Input/Output 

2.15 Primary Input/Output Instructions 

2. 16 Energize Output M (EOM) 

2.24 Skip If Signal Not Set (SKS) 

2.30 Communication Channel Input/Output 

2.31 General Information 

2.42 Communication Channel Description 

2.45 Time-Multiplexed Channel Registers 

2.51 Interlace Registers 

2.56 Communication Channel Programming 

2.58 Standard EOM Channel Instructions 

2.60 Alert Channel (ALC) 

2.62 Disconnect Channel (DSC) 

2.64 Alert to Store Address From Channel (ASC) 

2.68 Terminate Output of Channel (TOP) 

2.71 Compatible/Extended Input/Output Modes 

2.78 Input/Output Class EOM 

2.80 Terminal Functions; Extended Mode 

2.82 Input/Output of a Record and Disconnect (lORD) . 

2.83 Input 

2.85 Output 

2.89 Input/Output Until Signal Then Disconnect (lOSD) 

2.90 Input 

2.92 Output 

2.94 Input/Output of a Record and Proceed (lORP) . . . 

2.95 Input 

2.99 Output 

2. 105 Input/Output Until Signal Then Proceed (lOSP) . . 

2.106 Input 



Page 



1-1 
1-1 
1-1 
1-4 
1-4 
1-4 
1-5 
1-5 
1-5 
1-5 
1-5 
1-5 
1-5 
1-5 
1-5 
1-5 



2-1 
2-1 
2-1 
2-1 
2-1 

2-2 

2-3 

2-3 

2-3 

2-4 

2-4 

2-5 

2-5 

2-6 

2-6 

2-6 

2-6 

2-7 

2-7 

2-7 

2-8 

2-9 

2-9 

2-9 

2-9 

2-9 

2-9 

2-9 

2-9 

2-10 

2-10 

2-10 



Contents SDS 900685C September 1965 

TABLE OF CONTENTS (Continued) 

Section Page 

2. 109 Output 2-10 

2. 1 12 Channel and Device SKS 2-1 

2. 1 14 Channel Tests 2-1 

2. 1 15 Standard SKS Instructions 2-1 

2. 1 17 Channel Active Test (CAT) 2-1 

2. 121 Channel Error Test (CET) 2-1 

2. 125 Channel Zero Count Test (CZI). . 2-12 

2. 128 Channel Inter-Record Test (CIT) . 2-12 

2. 131 Device Tests 2-12 

2. 133 Single-Word Data Transfer Via Channels W (A) and Y 2-13 

2. 134 Instructions 2-13 

2. 137 Memory Into Channel W When Empty (MIW) 2-13 

2. 140 Channel W Into Memory When Full (WIM) 2-13 

2. 142 Memory Into Channel Y When Empty (MIY) 2-13 

2. 144 Channel Y Into Memory When Full (YIM) 2-13 

2. 146 Memory Into Channel A When Empty (MIA) 2-13 

2. 148 Channel A Into Memory When Full (AIM) 2-13 

2. 150 Single-Word Operations 2-13 

III THEORY OF OPERATION 

3. 1 General 3-1 

3.7 Character Buffer 3-1 

3. 9 Word Assembly Register 3-1 

3. 1 1 Unit Address Register 3-1 

3. 13 Word Counter 3-1 

3. 15 Address Counter 3-1 

3. 17 Input Process 3-3 

3. 23 Output Process 3-3 

3. 27 Parity 3-3 

3.29 TMCC and Interlace Configuration 3-3 

3.31 Detailed Description 3-3 

3. 34 Pulse Counter 3-3 

3.39 Input/Output Processing 3-4 

3. 43 W Register 3-6 

3.53 Input Process (W9 true) 3-9 

3.78 Output Process (W9 true) 3-24 

3. 91 SYS Gate . 3-31 

3.94 Skip Gate 3-36 

3. 102 Interlace, Compatible Mode (Time Share) 3-36 

3. 131 Interlace, Extended Mode (Time Share) 3-46 

3. 134 lORD - Iwg !wh T^i 3-48 

3. 135 Output 3-48 

3. 140 lOSD - Iwg !wPi Iwi 3-50 

3.141 Output . . . 2_^. - . 3-50 

3. 144 lORP - Iwg Iwh Iwi 3-50 

3. 145 Output 3-50 

3. 152 lOSP - Iwg Iwh Iwi 3-52 

3. 153 Output . . . ._^ 3-52 

3. 158 lORD - Iwg Iwh Iwi 3-53 

3. 159 Input. . ._^. 3-53 

3. 164 lOSD - Iwg Iwh Iwi 3-54 

3. 165 Input 3-54 



September 1965 



SDS 900685C 



Contents 



TABLE OF CONTENTS (Continued) 



Section 



Page 



3. 168 lORP - Iwg Iwh Iwi 3-55 

3. 169 Input 3-55 

3. 176 lOSP - Iwg Iwh Iwi 3-57 

3. 177 Input 3-57 

3. 1 80 Pin Address Counter 3-57 

3. 184 Glossary of Logic Terms 3-58 

3. 185 Logic Equations 3-61 

3. 186 Pulse Counter 3-61 

3. 187 Buc, loc, Sys, Etc 3-61 

3. 188 CPU Signals Received 3-61 

3. 189 Input/Output Signals Generated 3-62 

3. 190 CPU Signals Generated 3-62 

3. 191 TMCC Signals Received 3-64 

3. 192 Input/Output Signals Received 3-64 

3. 193 TMCC Signals Generated 3-64 

3. 194 Logic Equations For W Buffer 3-64 

3. 195 Unit Address Register 3-64 

3. 196 Input/Output 3-64 

3. 197 Clear and Set Signals 3-64 

3. 198 Clock Counter 3-64 

3. 199 Character Counter 3-64 

3.200 Character Counter Even 3-64 

3.201 Halt Interlock 3-64 

3.202 Computer Interlock 3-64 

3.203 End-of-Record Detector 3-65 

3.204 Halt Interlock 3-65 

3.205 Signal Complete 3-65 

3.206 Interrupt Signals 3-65 

3. 207 WIM + MIW Interlock = 3-65 

3. 208 Load Buffer From C . 3-65 

3.209 Time Share Request 3-65 

3.210 Time Share Select 3-65 

3. 21 1 Time Share Priority 3-65 

3. 212 W Register 3-65 

3.213 Character Buffer 3-66 

3.214 Character Buffer Extended to 12 Bits 3-66 

3.215 Character Buffer Extended to 24 Bits 3-66 

3.216 Parity Flip-Flop 3-67 

3.217 Error Detector 3-67 

3.218 Interlace Prepare 3-67 

3.219 Interlace Clear 3-67 

3. 220 Interlace Load 3-67 

3.221 Interlace Active 3-67 

3. 222 Zero Count 3-67 

3.223 Interlace Count Trigger 3-67 

3.224 Interlace Counter Clock Enables 3-67 

3. 225 Extend Operations 3-67 

3.226 Channel Command Interrupt Enables 3-68 

3.227 Channel Command Register 3-68 

3. 228 Word Counter 3-68 

3. 229 Address Counter 3-68 

3.230 PIN Address Counter 3-69 



Contents SDS 900685C September 1965 

TABLE OF CONTENTS (Continued) 

Section Page 

3. 231 Skip Gate 3-69 

3.232 Input/Output Signals Received 3-69 

3.233 Input/Output Signals Generated 3-69 

3.234 Logic Equations For Y Buffer 3-69 

3.235 Unit Address Register 3-69 

3.236 Input/Output 3-69 

3.237 Clear and Set Signals 3-70 

3.238 Clock Counter 3-70 

3. 239 Character Counter 3-70 

3. 240 Character Counter Even 3-70 

3. 241 Halt Interlock 3-70 

3.242 Computer Interlock 3-70 

3.243 End-of -Record Detector 3-70 

3.244 Halt Detector 3-71 

3.245 Signal Complete 3-71 

3.246 Interrupt Signals 3-71 

3.247 YIM + MIY Interlock = 3-71 

3. 248 Load Buffer From C 3-71 

3.249 Time Share Request 3-71 

3.250 Time Share Select 3-71 

3.251 Time Share Priority 3-71 

3.252 Y Register 3-71 

3.253 Character Buffer Extended to 12 Bits 3-71 

3.254 Character Buffer 3-71 

3.255 Character Buffer Extended to 24 Bits 3-71 

3.256 Parity Flip-Flop 3-72 

3.257 Error Detector 3-72 

3.258 Interlace Prepare 3-72 

3.259 Interlace Clear 3-73 

3.260 Interlace Load 3-73 

3.261 Interlace Active 3-73 

3.262 Zero Count 3-73 

3.263 Interlace Count Trigger 3-73 

3.264 Interlace Counter Clock Enables 3-73 

3.265 Extend Operations 3-74 

3.266 Channel Command Interrupt Enables 3-74 

3.267 Channel Command Register 3-74 

3. 268 Word Counter 3-74 

3.269 Address Counter 3-74 

3. 270 Pin Address Counter 3-74 

3. 271 Skip Gate 3-74 

3.272 Input/Output Signals Received 3-74 

3.273 Input/Output Signals Generated 3-75 

IV INSTALLATION AND MAINTENANCE 

4. 1 General 4-1 

4.3 Installation 4-1 

4.5 Intercabling 4-1 

4.9 925/930 Computer W Channel Test Program 4-1 

4. 1 1 9300 Computer A Channel Test Program 4-1 

4.13 Module Location 4-1 

4. 15 Maintenance 4-1 

iv 



September 1965 



SDS 900685C 



Contents 



TABLE OF CONTENTS (Continued) 



Section 



Page 



V 



VI 



4. 17 Periodic Inspection 

4. 19 Corrective Maintenance 

4.21 Input/Output Signals and Timing Relationships 

4. 24 (Q^ , (Q^ , and (O^ . 

4.26 (^Eom),(^Buc^,(Toc^ . 

4.31 rPU^,(W),(^),(^0 

4. 34 rpot J) , (^TS) ,CE), (Cj) 

4.37 (tkSS,(rtS' 

4. 40 Test Programs 

4. 42 Extended Mode I/O Test Program For 925/930 Computers 

4.45 Fill 

4. 47 Operation 

4. 51 Punching 

4.55 Reading 

4. 57 Test Program 

4. 59 Extended Mode I/O Test Program For 9300 Computer. . . , 

4.62 Fill 

4. 64 Operation 

4.68 Punching , 

4.72 Reading , 

4.74 Test Program , 

TROUBLESHOOTING 

5. 1 General , 

5, 4 Test Program Flow Chart , 

5.6 Flow Chart Example , 

5. 13 Troubleshooting Information , 

5. 16 Troubleshooting , 

DRAWINGS 

6. 1 General , 

6. 3 Scope of Section , 



4-1 
4-1 
4-1 

4-9 

4-9 

4-10 

4-n 

4-12 

4-13 
4-13 
4-13 
4-13 
4-14 
4-14 
4-14 
4-14 
4-14 
4-35 
4-35 
4-35 
4-36 



5-1 

5-1 

5-1 

5-15 

5-15 



6-1 
6-1 



LIST OF ILLUSTRATIONS 



Number Title Page 

1-1 TMCC Configuration, Models 922XX 1-2 

1-2 TMCC Configuration, Models 932XX 1-3 

3-1 Time Multiplexed Communication Channel With Interlace, Block Diagram 3-2 

3-2 TMCC Information Flow Diagram, Input/Output (6 Bit) 3-5 

3-3 Precession Loop and Input Parity Checking Logic 3-7 

3-4 Input Clock Timing Charts (Typical) 3-10 

3-5 Input Clock Timing Charts 3-1 1 

3-6 Input Timing Chart (Two Characters Per Word) 3-13 

3-7 Data Transfer From W Register to C Register 3-15 

3-8 Information Flow Diagram - Phototape 3-16 

3-9 Termination Timing A - Phototype Input 3-18 



Contents 



SDS 900685C 



September 1965 



LIST OF ILLUSTRATIONS (Continued) 



Number 



Page 



3-10 

3-11 

3-12 

3-13 

3-14 

3-15 

3-16 

3-17 

3-18 

3-19 

3-20 

3-21 

3-22 

3-23 

3-24 

3-25 

3-26 

3-27 

3-28 

3-29 

3-30 

4-1 

4-2 

4-3 

4-4 

4-5 

4-6 

4-7 

4-8 

4-9 

4-10 

4-11 

4-12 

4-13 

4-14 
5-1 



Termination Timing B - Phototype Input 

Information Flow Diagram - Magnetic Tape 

Input Timing - Magnetic Tape 

Input Termination Timing - Magnetic Tape 

Forward Scan Timing Chart - Magnetic Tape 

Reverse Scan Timing Chart - Magnetic Tape 

Output Information Flow Diagram 

Output Timing Chart 1 

Output Timing Chart 2 

Output Termination Timing (Except Magnetic Tape) 

Output Termination Timing - Magnetic Tape 

Output Timing Chart - Punch 

Output Timing Chart - Magnetic Tape 

Information Flow - Interlace Operation 

Interlace Word Counter - Typical Clock Input 

Relationship of Instruction Bits to Address and Word Counter Bits 

Interlace Register Loading Time Chart 

Interlace Word Transfer Timing Chart 

Interlace Input/Output Timing Chart 

Interlace Output Timing Chart 

Input Termination Timing Chart - Interlace (Compatible Mode) 

Model 93200 TMCC, Intercabling Diagram 

Model 93221 TMCC, Intercabling Diagram 

Power Distribution Diagram 

Module Location Diagram 

Input/Output Signal Location Diagrorriji,. 

930/9300 Timing Diagram, (Qqj) , (O^ , (Qq3). • • ■ 

ming Diagram, (Jom) , ^Buc) , (joc), (Sys) 

ming Diagram, (pin),^^^), (^3n),(Jtr) 

mIng Diagram, (pin),C§), Cc^,CRtD,CRt), Initially False . . . 
ming Diagram, C^m),QR£), (CdnJ),v^RH^ Effects of Time -Share .. 

ming Diagram, (Potj) , (P^^ '(Jt)' C^n) 

ming Diagram, (Potj) , (PoTl) ,(^), (^),(S)f Initially False . 

ming Diagram, (Pot I) , (Pot J) ,C_RtJ), CCrT)/ Effects of Time-Share 

ing Diagram, ('Skss"), CCn) , C^sgy 



930/9300 T 
930/9300 T 
930/9300 T 
930/9300 T 
930/9300 T 
930/9300 T 
930/9300 T 
930/9300 T 



Test Program Flow Chart 



3-19 

3-21 

3-22 

3-23 

3-25 

3-26 

3-27 

3-29 

3-30 

3-32 

3-33 

3-34 

3-35 

3-38 

3-39 

3-40 

3-41 

3-43 

3-44 

3-45 

3-47 

4-2 

4-3 

4-4 

4-5 

4-6 

4-9 

4-9 

4-10 

4-10 

4-11 

4-11 

4-11 

4-12 

4-12 
5-2 



LIST OF TABLES 



Table 

1-1 
T-2 
1-3 
1-4 
3-1 
3-2 



TMCC Models 

Applicable Publications 

Models 922XX Module Complement 
Models 923XX Module Complement 

Pulse Counter Truth Table 

Value of Parity Timing Signal Qwl. 



Poge 

1-1 
1-1 
1-4 
1-6 
3-4 
3-14 



VI 



September 1965 SDS 900685C Contents 

LIST OF TABLES (Continued) 

Toble Page 

3-3 Value of Qw2 Parity Timing Signal 3-28 

3-4 Interlace Extended - Mode Terminal Functions 3-49 

4-1 924/930 Computers, W Channel Sample Test Program 4-7 

4-2 9300 Computer, A Channel Sample Test Program 4-8 

4-3 925/930 Computers Breakpoint Switch Functions 4-13 

4-4 925/930 Computers, Extended Mode I/O Test Program 4-15 

4-5 9300 Computer Breakpoint Switch Functions 4-35 

4-6 9300 Computer, Extended Mode I/O Test Program 4-37 

5-1 lOSP Output Functions, W (A) Channel 5-15 

5-2 lORD Output Functions, W (A) Channel 5-16 

5-3 lOSD Output Functions, W (A) Channel 5-16 

5-4 lORD Output Functions, W (A) Channel 5-17 

5-5 lOSP Input Functions, W (A) Channel 5-17 

5-6 lORP Input Functions, W (A) Channel 5-18 

5-7 lOSD Input Functions, W (A) Channel 5-18 

5-8 lORD Input Functions, W (A) Channel 5-19 

5-9 Output Functions, Y Channel 5-19 

5-10 Input Functions, Y Channel 5-20 



September 1965 



SDS 900685C 



Paragraphs 1 . 1 to 1.8 



SECTION I 
GENERAL DESCRIPTION 



1.1 GENERAL 

1.2 This publication provides information relating 

to the Time-Multiplexed Communication Channel option 
manufactured by Scientific Data Systems, 1649 
Seventeenth Street, Santa Monica, California. 

1.3 In this publication, the Time-Multiplexed Com- 
munication Channel option is referred to as "TMCC". 
The models covered,with their description and the 
figure references,are listed in table 1-1. 





Table 1-1. TMCC Models 








Channel 




Model 


Description 


Used 


Figure 


92200 


6-bit characters with 
interlace 


W(A), C 


1-1 


92210 


6-bit characters with 
interlace 


Y(B), D 


1-1 


92201 


12-bit characters with 
interlace 


C 


1-1 


92211 


12-bIt characters with 
interlace 


D 


1-1 


92202 


24-bit characters with 
interlace 


C 


1-1 


92212 


24-bit characters with 
interlace 


D 


1-1 


93200 


6-bit characters without 
interlace, single channel 


W(A), C 


1-2 


91210 


Interlace option for Model 
93200 






93201 


12-bit character extension 
option for Model 93200 






93202 


24-bit character extension 
option for Model 93200 






93221 


6-bit characters without 


W + Y 


1-2 




interlace, two channels 


(A + B) 




91210 


Interlace option for either 
channel of Model 93221 






93201 


12-bit character extension 
option for Model 93221 






93202 


24-bit character extension 
option for Model 93221 







1.4 The information in this publication relates to the 
TMCC as utilized with the 925/930/9300 computers. 
Other publications containing information relating to 
the TMCC and input/output operation are listed in 
table 1-2. 

Table 1-2. Applicable Publications 



Title of Publication 


Publication No. 


SDS 925/930/9300 TMCC 
Input/Output Unit Logic 
Layouts, Current and History 


900557 


SDS 925 Computer Reference 
Manual 


900099 


Model 925 Computer, 
Technical Manual 


900633 


SDS 930 Computer Reference 
Manual 


900064 


Model 930 Computer, 
Technical Manual 


900066 


SDS 9300 Computer Reference 
Manual 


900050 


Model 9300 Computer, 
Technical Manual 


900570 



1.5 PURPOSE OF OPTION 

1.6 The TMCC Is a time-multiplexed input/output 
channel utilized for communication between peripheral 
devices and the 925/930/9300 computers. Its operation 
is designated "time-multiplexed" because it gains access 
to the computer memory through the same path utilized 
by the computer and must, therefore, momentarily inter- 
rupt computation to store or obtain a word of informa- 
tion. Up to fourTMCCs may be connected to one com- 
puter and all may be active simultaneously but since 
their operation is time-multiplexed, only one channel 

at a time communicates with the computer memory. 

1.7 DESCRIPTION AND LEADING PARTICULARS 

1.8 A computer may have from one to four TMCCs 
connected to it. These are designated by letter symbols 
In the order of their installation. When only one 



I-l 



SDS 900685C 



September 1965 



Channel 
W (or A) 



92200 



One Channel Configuration 



Channel 
W (or A) 



92200 



Hardwired 



Channel 
Y (or B) 



92210 
92211 
92212 



Two Channel Configuration 



Channel 
W (or A) 



92200 





Channel 
W (or A) 



92200 



Hardwired 



Channel 
Y (or B) 



92210 
92211 
92212 



Channel 
C 



92200 
92201 
92202 



~7y 

Hardwired 



Channel 
D 



92210 
92211 
92212 



Three Channel Configuration 



Four Channel Configuration 



Figure 1-1. TMCC Configuration, Models 922XX 



1-2 



September 1965 



SDS 900685 C 



Channel 
W (or A) 



93200 



One Channel Configuration 



Channels 
Wand Y 
(or A and B) 



93221* 



Two Channel Configuration 



Channels 

Wand Y 

(or A and B) 



93221* 



Channel 
C 



93200^ 



Channels 

W and Y 

(or A and B) 



93221* 



Channels 
C and D 



93221* 



Three Channel Configuration 



Four Channel Configuration 



■Note: The Interlace feature. Model 91210, is required on channels B, C and D, and is optional on W, 
A and Y. All channels ma/ have 93201 or 93202 options. 



Figure 1-2. TMCC Configuration, Models 932XX 



1-3 



Paragraphs 1 . 9 to 1. 15 



5DS 900685C 



September 1965 



channel is used it is specified as the W channel on the 
925 and 930 computers or as the A channel on the 9300 
computer. As additional channels are added they are 
designated. In order, Y (or B on the 9300 computer), 
C, and D. Because single-word Input/output instruc- 
tions (Memory Into W, Memory Into Y, Memory Into A, 
W Into Memory, Y Into Memory, and A Into Memory) 
are not available for all channels, the interlace feature 
is mandatory on channels B, C, and D. 

1.9 Primary differences between the models occur in 
the hardware layouts, connections between channels, 
and the options available. 

1-10 PHYSICAL DESCRIPTION 

1.11 The TMCC consists of plug-in modules contained 
In chassis consisting of four or six rows of modules. 



Each row contains 32 connectors thereby allowing the 
insertion of up to 32 modules in each row. Physical 
location of each module is given in Section 4 of this 
manual. 

1.12 TMCC Models 922XX 

1. 13 In TMCC Models 922XX, the character length is 
fixed for a particular model and the interlace feature Is 
included. One channel must be six bits to allow enter- 
ing a program into the computer. 

1. 14 One Channel Configuration 

1.15 A one channel configuration TMCC (Model 
92200) consists of a single chassis containing four rows 
of modules (C through F). The quantity and type of 
modules are listed In table 1-3. 







Table 1-3. Models < 


?22XX Module 


Complement 












Quantity 


92200 


92201 


92202 


92210 


92211 


92212 








6-BIt 


12-Bit 


24-BIt 


6-BIt 


12-Bit 


24-Bit 


Item 


Description 


Model 


"W" "A" or "C" 






"Y" "B" or "D" 


"Y" "B"or"D" 


"Y" "B"or"D" 


1 


Triple Flip-Flop 


FB52 


19 


21 


25 


18 


20 


24 


2 


NANDFlip-Flop 


FB54 


14 


14 


14 


13 


13 


13 


3 


Cable Driver No. 2 


AB55 


2 


2 


2 


1 






4 


NAND No. 2 


IB56 


5 


5 


5 


5 


5 


5 


5 


Band NAND 


IB57 


4 


4 


4 


4 


4 


4 


6 


NAND Module 


IB52 


2 


2 


2 








7 


Shift Register 


DB50 


3 


3 


3 


3 


3 


3 


8 


Receiver Inverter Buffer 


AB53 


2 


2 


2 








9 


Termination Module 


ZB52 


2 


2 


2 








10 


Interface +8 to +4 


NB50 


1 


2 


2 


1 


1 


1 


11 


Cable Driver 


AK53 


9 


10 


11 


3 


1 


2 


12 


Cable Driver 


NB52 


3 


3 


3 








13 


Termination Module +4 


ZB50 


7 


7 


7 


7 


7 


7 


14 


Termination Module 


ZB55 


1 






1 






15 


Receiver, Inverter 


AB52 


2 


2 


2 








16 


NAND No. 4 


IB59 


5 


5 


5 


4 


4 


4 


17 


Schmitt Trigger 


AK54 


1 


1 


1 








18 


Termination Module 


ZB56 




1 






2 




19 


Termination Module 


ZB57 






1 






2 



1-4 



September 1965 



SDS 900685C 



Paragraphs 1. 16 to 1.35 



1.16 Two Channel Configuration 

1.17 A two channel configuration TMCC consists of 
two chassis, one containing four rows of modules (C 
through F) and the other containing two rows of modules 
(A and B). These two chassis are physically bolted 
together and hardwired to allow mounting as a single 
unit. The two channel configuration consists of a 
Model 92200 for channel W (or A) and either o six bit 
option (92210), a twelve bit option (9221 1) or a twenty- 
four bit option (92212) for channel Y (B). The options 
selected determine the quantity and type of modules. 
Table 1-3 lists the modules required for each model. 

1.18 Three Channel Configuration 

1. 19 The three channel configuration consists of three 
chassis, two containing four rows of modules and the 
third containing two rows of modules. Channel W (or 
A), consists of a Model 92200; channel Y (or B) con- 
sists of six bit option (92210), a twelve bit option 
(9221 1), or a twenty-four bit option (92212); channel 
C consists of a six bit option (92200), a twelve bit 
option (92201), or a twenty-four bit option (92202). 
The quantity and types of modules for each option are 
listed in table 1-3. 

1.20 Four Channel Configuration 

1.21 The four channel configuration consists of four 
chassis, two containing four and two containing two 
rows of modules. The four channel configuration con- 
sists of a Model 92200 for channel W (A); a six bit 
option (92210), a twelve bit option (9221 1) or a twenty- 
four bit option (92212) for channel Y(B); a six bitoption 
(92200), a twelve bit option (92201), or twenty-four bit 
option (92202) for channel C; and a six bit option 
(92210), twelve bit option (92211), or a twenty-four bit 
option (92212) for channel D. The quantity and types 
of modules are listed in table 1-3. 

1.22 TMCC Models 932XX 

1.23 In TMCC Models 932XX, the interlace registers 
are optional equipment. Interlace options may be 
installed in any of the four TMCCs that a 925/930/9300 
computer may have. However, channels C and D (and 
B on the 9300 computer) must have interlace Installed 
since there are no computer instructions allowing use of 
these channels without It. 

1.24 One Channel Configuration 

1.25 A one channel configuration TMCC (Model 
93200) consists of a single chassis containing four rows 
of modules. The quantity and types of modules are 
listed in table 1-4. 



1.26 Two Channel Configuration 

1.27 The two channel configuration consists of a single 
chassis containing six rows of modules. For channels W 
and Y, a Model 93221 TMCC may be used. The Model 
93221 may be extended to twelve bit or twenty-four bit 
characters by addition of modules as listed in table 1-4. 
The Model 93221 must have the Model 91210 Interlace 
installed in either or both channels. The modules com- 
prising the Model 91210 Interlace are indicated In 
table 1-4. 



1.28 Three Channel Configuration 

1.29 A three channel configuration TMCC consists of 
a single chassis containing six rows of modules and 
another chassis of four rows of modules. Channels W 
and Y (or A and B) are as given in paragraph 1. 27. 
Channel C consists of a Model 93200 TMCC (with char- 
acter extension options) and must Include a Model 
91210 Interlace. 



1.30 Four Channel Configuration 

1.31 A four channel configuration TMCC consists of 
two chassis, each containing six rows of modules. Two 
Model 93221 TMCCs may be used with character exten- 
sion options if desired. Model 91210 Interlace options 
must be installed on at least channels C, and D (and B 
on the 9300). 

1.32 SEMICONDUCTOR COMPLEMENT 

1.33 The semiconductor complement may be derived 
from the Material Lists and Module Data Sheets con- 
tained in Section 6. The module complement for each 
model of TMCC Is contained in tables 1-3 and 1-4. 

1.34 INTERLACE FEATURE 

1.35 The purpose of the interlace feature is to provide 
the TMCC with a means of transferring blocks of words 
without requiring a separate instruction for each word. 
To do this, two counters are added to the TMCC. One 
counter is loaded with a count of the number of words in 
the block, and the other counter is loaded with the 
address of the memory position of the first word In the 
block. Then, as each input or output word is transferred 
to or from memory, the Word Counter and the Address 
Counter are incremented. The Word Counter holds the 
one's complement of the count; thus the count is 
decreased as the counter counts up. In addition to the 
two counters, the interlace logic also includes Channel 
Command Interrupt Enables, and all the necessary con- 
trol logic. 



1-5 



SDS 900685C 



September 1965 



Table 1-4. Models 923XX Module Complement 











Quantity 






93200 


93221 


93201 


93202 


91210 








6-Bit 


6-Bit 


12-Bit 


24- Bit 


Interlace 


Item 


Description 


Model 


"W" 


"W" & "Y" 


"W" or "Y" 


"W" or "Y" 


"W" or "Y" 


1 


Triple F lip-Flop 


FB52 


6 


n 


2 


6 


13 


2 


NAND Flip-Flop 


FB54 


13 


25 


- 


- 


1 


3 


Coble Driver No. 2* 


AB55 


3 


4 


- 


- 


- 


4 


NAND No. 2 


IB56 


4 


8 


- 


- 


1 


5 


Bond NAND 


IB57 


3 


7 


- 


- 


1 


6 


NAND Module 


IB52 


2 


2 


- 


- 


- 


7 


Shift Register 


DB50-2 


3 


6 


- 


- 


- 


8 


Receiver Inverter Buffer 


AB53 


2 


2 


- 


- 


- 


9 


Termination Module 


ZB52 


2 


2 


- 


- 


- 


10 


Interface +8 to +4 


NB50 


1 


2 


1 


1 


- 


11 


Cable Driver 


AK53 


9 


13 


1 


2 


- 


12 


Driver Cable Interface 


NB52 


1 


1 


- 


- 


2 


13 


Termination Module +4 


ZB50 


6 


10 








1 


14 


Priority Interrupt** 


SK61 


2 


2 


- 


- 


- 


15 


Receiver Inverter 


AB52 


2 


2 


- 


- 


- 


16 


NAND No. 4 


IB59 


3 


5 


- 


- 


3 


17 


Schmitt Trigger 


AK54 


1 


1 


- 


- 


- 



''SK61s are located in computer basic interrupt: 925/930 Reference Drawing 107352 

9300 Reference Drawing 107626 

'One AB55 is located in 5E (930 only) if I/O is used as a "C" or "C-D" channel. 



1-6 



September 1965 



SDS 900685 C 



Paragraphs 2.1 to 2.12 



SECTION II 
PROGRAMMING 



2.1 PURPOSE 

2. 2 The 925/930/9300 computers include as standard 
equipment one Time-Multiplexed Communication Chan- 
nel (TMCC), without interlacing capability, as well as 
provision for three additional channels. The interlace 
unit is available as an option. The W and Y channels 
are available with or without interlace; the C and D 
channels are available only with interlace. The W 
channel on the 925 and 930 computers is equivalent to 
the A channel on the 9300 computer and the Y channel 
on the 925 and 930 computers ie equivalent to the B 
channel on the 9300 computer. (The B channel on the 
9300 must also have the interlace feature). These 
channels are capable of automatically control ling the 
flow of data to and from memory at rates up to one word 
every 3.5 microseconds. These channels run independ- 
ently of the central processor and only communicate 
with it to transfer data to or from memory. 

2.3 GENERAL OPERATION 

2.4 Utilizing channels W and Y (or A), characters, 
and words can be transmitted between memory and 
peripheral devices under the direct control of single 
instructions. Each of these channels has associated with 
it two instructions to facilitate direct control operations. 
For channel W, W INTO MEMORY (WIM) (channel A, 
A INTO MEMORY (AIM)), causes a word from a periph- 
eral transmission to be taken from the channel W(A) 
buffer register and placed directly in the specified 
memory location without disturbing any internal regis- 
ters. MEMORY INTO W (MIW), (MEMORY INTO A 
(MIA)), causes a word to be taken from a specified 
memory location and placed in the channel W (A) buffer 
register to be read out to the currently operating periph- 
eral device connected to the channel. WIM (AIM) and 
MIW (MIA) are preceded by instructions from the EOM 
group that set up the input/output operation. YIM and 
MIY instructions function in an analogous manner for 
channel Y. The general test instruction, SKIP IF SIG- 
NAL NOT SET (SKS) provides the facility for testing 
error indications and/or for testing various peripheral 
device indicators. 

2.5 Additionally, using any channel including channels 
Wand Y (A and B) with interlace, data can be transmitted 
to and from core storage under channel control. Opera- 
tion of a channel is initiated by the execution of a 
sequence of instructions in the central processor. Once 
started, the channel operates independently of the 
central processor, automatically transferring each word 
at the correct time. 



2.6 Three instructions control the process of trans- 
mitting and receiving data between channel peripheral 
equipment and the central processor. These instructions 
are: 

EOM ENERGIZE OUTPUT M 

POT PARALLEL OUTPUT 

SKS SKIP IF SIGNAL NOT SET 

2.7 EOM instructions activate one of channels W(A), 
Y(B), C, or D, to select the peripheral device to be 
used, and to set up the initial conditions of the data 
transmission, including the peripheral operation to be 
performed. An EOM instruction also specifies terminal 
conditions for an operation. 

2.8 PARALLEL OUTPUT (POT) instruction sends out to 
the channel the number of words in the transmission and 
the address at which the output begins. 

2.9 SKIP IF SIGNAL NOT SET (SKS) instruction can 
test the Error indicators, End-of-Transmission indicators, 
and other Input/output control indicators, such as 
printer end-of-form or card hopper empty. 

2. 10 The general order of use of these instructions for 
interlaced operation is: 

Instruction Function 

EOM to address the channel, connect the 

peripheral device, specify various input/ 
output conditions, and alert the optional 
channel interlace (see Communication 
Channel Input/Output, paragraph 2.30). 

EOM to specify the terminal conditions and 

interrupts desired during the transmission 

POT to transmit to the channel a word con- 

taining the transmission starting address 
and block length 

Bits through 9 of this latter word contain the ten lower 
order bits of the word count; bits 10 through 23 contain 
the 14 bits of the starting address. The second EOM 
contains the high-order bits of the word count and 
starting address when needed. 

2. 1 1 DIRECT PARALLEL INPUT/OUTPUT 

2. 12 The direct parallel input/output (POT/PIN) facil- 
ity allows any word in core memory to be presented, in 



2-1 



Paragraphs 2.13 to 2.22 



SDS 900685C 



September 1965 



parallel, at any special system connector or applicable 
standard peripheral connector; or, conversely, allows 
signals sent to a connector to be stored in any core 
memory location. EOM and SKS instructions control 
parallel input/output operations in the same way as in 
channel operations. POT/PIN Instructions also gener- 
ate or check for correct parity with each word 
transmitted. 

2.13 SINGLE-BIT INPUT/OUTPUT 

2. 14 EOM and SKS instructions also perform single-bit 
input/output and testing for special or standard devices. 
The execution of an EOM transmits a single signal of 
approximately 1.4 microseconds duration to an external 
connector and also provides the connector with a 15- 
bit address for the destination of this signal. SKS tests 
whether a similar signal is present on an external con- 
nector and skips accordingly. 

2.15 PRIMARY INPUT/OUTPUT INSTRUCTIONS 

2.16 ENERGIZE OUTPUT M (EOM) 








02 

1 4: i 


1 \ \ 1 



12 3 
00 01 



8 9 
02 03 04 05 



06 



23 
07 



2. 17 The major instruction for preparing channel W (or 
Y, C, D) and an attached peripheral device to perform 
a data transmission or other peripheral activity is the 
multi-purpose Instruction, ENERGIZE OUTPUT M 
(EOM). This instruction operates in four distinct modes 
with many functional configurations. These modes are 
Buffer Control, Input/Output Control, Internal Control, 
and System Control. In the third and fourth modes, 
EOM controls and initiates non-communication channel 
operations such as special systems transmissions. Each 
of the frequently used EOM instruction configurations 
has a mnemonic tag used with standard SDS assemblers. 
The different modes of operation are program-selectable 
by thfe setting of two bits (10, 11 of octal position 3) 
within the EOM instruction format: 

Octal Bit Posi- Bit Posi- 

Value tion 10 tion 11 Area 









1 





2 


1 


3 


1 



Buffer Control 

1 Input/Output Control 

Internal Control 

1 System Control 

2. 18 A Buffer Control mode EOM operates essentially 
as a set-up or preparation facility for data transmissions 



or other peripheral activities using the channel. The 
channel to be used, the peripheral unit on that channel, 
the operation to be performed, and the type of charac- 
ter format to be used are all detailed within this EOM. 
It also details the use of BCD or binary data transmis- 
sion, the allowance or not of a leader (as in paper tape), 
and the direction of operation (as in forward direction 
for magnetic tape). Execution of such an EOM "con- 
nects" the specified peripheral unit to the channel. An 
EOM in this mode can also alert the interlace, which 
Is the optional, automatic buffer control for input/output. 

2. 19 An EOM In the Input/Output mode directs periph- 
eral devices to perform non-transmitting operations such 
as rewind magnetic tape and upspace the printer. This 
EOM selects certain channel operations such as inter- 
rupt response and input/output terminal function 
desired. It alerts peripheral devices that a PARALLEL 
INPUT (PIN) or PARALLEL OUTPUT (POT) instruction 
follows. It also can give an extension of the word 
count to 15-bits for the number of words to be trans- 
mitted and an extension of the address specification to 
15-bits. Without disturbing the associated channel, 
this EOM can also set up the interlace unit. It Is with 
the input/output mode EOM that the user selects his 
I/O operation as compatible or extended I/O modes. 

2.20 This coding sequence initiates such an interlaced 
channel operation (compatible mode): 



Instruction 

EOM (Input/Output 
Control Mode) 

POT 



EOM (Buffer 
Control Mode) 



Function 
Alert the interlace 

transmit starting address and 
block length to interlace 

address channel, connect 
peripheral device, specify 
various input/output condi- 
tions, start transmission 

2.21 Initiating an interlaced Input/output operation 
via this sequence of instructions facilitlates checkout by 
allowing the programmer to single-step through this por- 
tion of the program. The first two instructions, EOM 
(loc) and POT, set up the interlace with data address 
and block length. Therefore, single-stepping through 
the sequence allows the interlaced channel to complete 
the input/output operation. When a single EOM (Buf- 
fer Control mode) sets up the channel and interlace with 
a POT instruction following, the programmer cannot 
step through the sequence since the input/output opera- 
tion proceeds before the next stepped instruction (POT) 
places the address and block length in the interlace. 

2.22 An EOM in the Internal Control mode enables and 
disables the interrupt system. EOM in this mode also 



2-2 



September 1965 



SDS 900685C 



Paragraphs 2. 23 to 2.37 



can prepare the system for the selective arming and 
disarming of the system interrupt levels. This mode 
does not directly concern the input/output programmer. 

2.23 An EOM in the System Control mode is specific- 
ally coded for a given installation and system. Address 
capability is 15-bits or 32,768 combinations for these 
special system designations. 

NOTE 

If an interrupt occurs during the 
execution of an EOM in any mode, 
no acknowledgement occurs until 
the completion of the execution of 
the instruction following the EOM. 

2.24 SKIP IF SIGNAL NOT SET (SKS) 









40(20) 

' H ' 






\ \ \ 



12 3 
OO Ol 



8 9 



02 



10 11 12 
03 04 



05 



23 
06 07 



2.25 The principal instruction for testing the states and 
responses of data channels and their attached peripheral 
devices, as well as testing internal and external indi- 
cators, is the multi-purpose instruction, SKIP IF SIG- 
NAL NOT SET (SKS). SKS is a "skip class" instruction 
yielding a decision and transfer capability to all chan- 
nels, devices, indicators, and systems that require It. 
It operates in four distinct modes: Special Internal Test, 
Channel and Device Test, Internal Test, and Special 
System Test. In the second mode, SKS tests channel- 
oriented, input/output functions. Each of the fre- 
quently used SKS instruction configurations has a 
mnemonic tag, used with SDS assemblers. 

2. 26 These different modes of operation are program- 
selectable by the setting of two bits (10, 11 of octal 
position 3) within the SKS instruction format: 



Octal 


Bit Posi- 


Bit P 


osi- 




Value 


tion 


10 


tlon 


11 


Area 




1 










1 




Special Internal Test 
Channel and Device Test 


2 


1 









Internal Test 


3 


1 




1 




Special System Test 



2.27 In the Channel and Device Test mode, SKS tests 
a channel for channel Ready (not active), interlace 
Word Count Equal to Zero, and Error. This mode also 
tests peripheral devices directly. These include testing 



indicators in a magnetic tape unit such as Beginning-of- 
Tape, End-of-Tape, File-Protect Ring present, and 
End-of-FIIe. For example, an SKS instruction might 
address an indicator within the printer to determine 
whether the paper is at the End-of-Form. 

2.28 In the Internal Test mode, SKS tests whether the 
interrupt system is enabled or disabled, whether a break- 
point switch is set, and whether Overflow is set. 

2.29 In the Special Internal and Special System Test 
modes, SKS tests signals of special configuration as the 
specific system requires. 

2.30 COMMUNICATION CHANNEL INPUT/OUTPUT 

2.31 GENERAL INFORMATION 

2.32 SDS Communication Channels provide fully buf- 
fered, input/output control and transmission, multi- 
plexed or simultaneous with computation. Up to four 
data channels can connect to the central processor, all 
operating independently of each other. 

2.33 Each channel can control as many as 30 input/ 
output devices and automatically handles character, 
word assembly and disassembly, input/output parity 
detection and generation, data transmission to and from 
memory, and End-of-Transmission detection. 

2.34 All channels are bi-directional and can communi- 
cate with 6-bit character devices or word devices of up 
to 24-bits. In the case of character-oriented devices, 
the program specifies the number of characters to be 
contained in each word during the transmission. 

2.35 A channel buffer assembles and disassembles data 
words as they are transmitted between core memory and 
the peripheral equipment. The buffer maintains control 
of operations such as characters per word transmitted and 
direction of peripheral operation (as in magnetic tape 
forward/reverse). 

2.36 A Buffer Control mode EOM sets up the channel 
buffer for operation. The execution of this EOM sets 
the operation controls, places the unit address in the 
buffer, and initiates data assembly/disassembly. The 
presence of the unit address activates the buffer, caus- 
ing it to look for data coming from the peripheral device 
or from memory, as determined by the unit address. 

2.37 When in use, a channel Interlace controls the 
transfer of the data words going through the associated 
channel buffer. This interlace supplies the memory 
address of data coming from or going to memory and 
maintains the word count determining the number of 
words transferred. The terminal interrupts. 



2-3 



Paragraphs 2-38 to 3-48 



SDS 900685 C 



September 1965 



End-of- Record and Zero Word Count, come from the 
interlace and are under its control. The interlace con- 
trols input/output termination functions during inter- 
laced operation. 

2.38 Two EOM instructions and a POT instruction alert 
and set up a channel interlace. The first EOM alerts 
the interlace, that is activates the interlace and 
instructs it to expect a word count and starting address 
to be sent to it by the POT instruction. The second 
EOM is an Input/Output mode EOM that specifies the 
interrupt and the terminal function to be used. This 
EOM also can specify a 15th address bit and five more 
high-order word count bits expanding the word count 
from 10-bits to 15. This sequence is written: EOM 
(Alert), EOM (I/O), and POT. When the channel 
buffer is being set up at the same time, the buffer con- 
trol EOM can alert the interlace. When the buffer is 
already set up, during a continuing I/O operation, the 
programmer may use the I/O EOM, ALERT CHANNEL 
(00250000), to alert the interlace. 

2.39 When the programmer does not desire to program 
the Extended Mode with the input/output terminal 
functions, interrupts, and additional count or address, 
only the EOM (Alert) and the POT are necessary to set 
up the channel interlace (Compatible mode). 

2.40 In the Extended Mode, the four channels are 
programmed in the same way, 

2.41 The Time-Multiplexed Channels use the memory 
logic of the central processor to facilitate input and 
output of data words. The transfer of each word 
between a time-multiplexed channel buffer and memory 
requires two memory cycles. During this time, computa- 
tion stops in the central processor. Priority for the use 
of the word input/output logic is in the order: Channel 
D, C, Y(B), W(A). Any Time-Multiplexed Channel 
operating with interlace has priority over the central 
processor for memory access. 

2.42 COMMUNICATION CHANNEL DESCRIPTION 

2.43 Up to 30 peripheral devices may be connected to 
one channel. Each of these devices has a unique, two- 
digit, octal address by which it is selected for an input/ 
output operation. To select the peripheral device, the 
program loads the proper unit address into the 6-bIt 
Unit Address Register (UAR) in the channel buffer. This 
address selects both the device and, if appropriate, the 
function to be performed. Placing a non-zero unit 
address in the Unit Address Register "connects" the 
peripheral unit addressed to the channel and it becomes 
"active". When the UAR contains a zero address, or 
any time that a terminal or Initial condition clears the 
contents of UAR, the channel is "inactive. " The zero 



in UAR also means that it is not connected to a periph- 
eral unit. 

2.44 When the channel and the peripheral unit to be 
used have been connected, the channel must have 
information pertaining to the location in memory of the 
data to be transmitted or received and pertaining to the 
number of data words In the transfer. 

2.45 TIME-MULTIPLEXED CHANNEL REGISTERS 

2.46 In the Time-Multiplexed Channels W (A) through 
D, there are two registers important to the programmer, 
the Word Assembly Register (WAR) and the Single- 
Character Register (SCR). The WAR, a 24-bit, word- 
sized buffer, contains the word of data actively being 
received or transmitted during an input or output opera- 
tion. During input, 6-bit characters (plus parity) enter 
the Single-Character Register where the channel buffer 
assembles them, one at a time. Into the WAR, Then the 
completed word is placed in memory. Depending on the 
number of characters per word specified, the word 
assembled and placed in memory during input has the 
form: 

Word in Memory 

One character per word mode 



Unpredictable 



1st 



17 18 

Two characters per word mode 



23 



Unpredictable 



1st 



2nd 



11 12 17 18 

Three characters per word mode 



23 



Unpred 1st 



2nd 



3rd 



\ 

■ 5 6 11 12 17 18 

Four characters per word mode 



23 



1st 



2nd 



3rd 



4th 







5 6 11 12 



17 18 



23 



2.47 The unfilled character positions contain unpredict- 
able data. When assembled during a one-word opera- 
tion, a WIM (AIM) Instruction places the word Into 
memory. Under interlace control, the interlaced chan- 
nel automatically places the word in memory when 
assembled. 

2.48 When the end of an Information record is detected 
by a buffer, the buffer automatically disengages from 



2-4 



September 1965 



SDS 900685C 



Paragraphs 2.49 to 2.57 



the device and is then "ready" for another operation. 
The buffer logic is reset, except that the state of the 
error indicator is maintained and the last word of the 
input is still in the word register. If the number of 
characters in the input record was not a multiple of the 
number of characters assembled into each computer 
word, then zeros are automatically forced into the 
least significant positions of the last word. This last 
word can then be stored in memory by a BUFFER INTO 
M WHEN READY WIM (AIM) or YIM Instruction after 
the buffer has disengaged. If the number of characters 
in the input record was a multiple of the number of 
characters assembled into each computer word, then the 
word remaining in the W buffer is either the last group 
of characters from the input device, if they were not 
previously transferred to memory by a BUFFER INTO M 
WHEN READY WIM (AIM) or YIM, or zeros if the last 
group of characters had been transferred to memory. 
In either case, it is safe to issue one such instruction 
after the buffer has disengaged without "hanging up" 
the computer. 

2.49 During output, words come from memory into the 
WAR where the channel buffer disassembles them into 
the SCR one 6-blt character at a time. Depending on 
the characters per word mode specified, the 6-bit char- 
acters within the word are output as follows: 



Function 

Output one character 
from bits through 5 

Output two characters 
from bits through 5, 
6 through 1 1 

Output three characters 
from bits through 5, 6 
through 11, 12 through 17 

Output four characters 
from bits through 5, 6 
through 11, 12 through 
17, 18 through 23 



Mode 



One character per word 



Two characters per word 



Three characters per word 



Four characters per word 



2.50 As required, the characters are transferred info 
the One Character Register and output with generated 
parity. After each character transfer, the word In the 
WAR is shifted left six bits to be ready for the next 
transfer. Only those characters needed from each word 
are used; when required, a new word is brought to the 
WAR for the next character. For special applications 
a Time-Multiplexed Channel may be equipped with a 



12- or 24-bit One Character Register. The external 
device which has a character size greater than 6-bits 
specifies to the channel what its size is, 12- or 24-bits. 
Standard 6-bit devices are unaffected by the installa- 
tion of a wider SCR. 

2.51 Interlace Registers 

2.52 A channel interlace contains two working regis- 
ters, the Word Count Register (WCR) and the Memory 
Address Register (MAR). In the set-up sequence — 
EOM, EOM, POT — for an interlaced input/output 
operation, the POT instruction transmits to the interlace 
a data word made up of the word count (that is, length) 
and the starting address of the data block. The 15-bit 
Word Count Register (WCR) contains the data word 
count during a data transfer. The number of data words 
is decremented by one and the new count replaces the 
old one in the WCR for each word transmitted. 

2.53 The count is assembled into the WCR from two 
places: the least significant 10-bits is from the "POTed" 
word and the most significant 5-bits is from the "HI 
COUNT" field of the second EOM. The form of the 
"POTed" word is: 



Word Count 



Start Address 







9 10 



23 



2.54 When the word count is equal to zero, the trans- 
mission is complete. During output, this causes a termi- 
nation; during input, the interlace allows any further 
data to fill the channel buffer and generates the End-of- 
Word interrupt, if enabled. 

2.55 The Memory Address Register (MAR) contains the 
starting destination or source address in memory of the 
transmitted data. The memory locations to or from 
which data words are to be transmitted enter the MAR at 
the same time the word count does. During transmission 
of data, the interlace increments the contents of the 
MAR after each word as it decrements the contents of the 
WCR. These two registers provide the interlace control 
of block transmissions. The high-order 15th address bit 
comes from the second EOM, also. 

2.56 COMMUNICATION CHANNEL PROGRAMMING 

2.57 The ENERGIZE OUTPUT M (EOM) used in the 
Buffer Control mode addresses and connects the specified 
Channel W (A), Y (B), C, or D, and selects the desired 
unit address. The detailed Instruction format is: 



02 







f.k2 
R N B 



C 

W 



Unit 



12 3 89 10 11 12 13 1415 16 17 18 23 

OO Ol 02 03 04 05 06 07 



2-5 



Paragraphs 2.58 to 2.65 



SDS 900685C 



September 1965 



Bit Octal Octal 

Designation Position Value 



B1 



B2 



02 



I/N 



00 



F/R 



OO 



05 



01-2 02 



03 



03 



04 4 



L/N 



04 2 



D/B 



04 1 



CAN 



05 



UNIT 



06-7 



Function 

Bit positions 1 and 17 
specify the channel to 
be activated. 

Channel W (A) is num- 
bered 00, channel Y(B) 
is 01, channel C is 10, 
and channel D is 1 1. 

Bit positions 3 through 8 
contain 02, the instruc- 
tion code for EOM. 

A 1-bit In position9alerts 
the buffer Interlace. 

Bit positions 10 and 1 1 
contain the EOM mode 
indicator for the Buffer 
Control mode. 

Bit position 12 specifies 
the direction in which 
the peripheral device 
will operate. A "0" 
specifies the forward 
direction. A "1" specifies 
the reverse direction. 

Bit position 13 specifies 
whether the device 
should be started with 
a leader as in paper 
tape. A "0" specifies 
a start with leader. A 
"1 " specifies a start- 
without leader. 

Bit position 14 specifies 
the mode of character 
format. A "0" specifies 
BCD format. A "1" 
specifies Binary format. 

Bit positions 15 and 16 
specify the number of 
characters to be assem- 
bled into, or disassem- 
bled from, each trans- 
mitted word. One 
character per word is 
specified by 00, two by 
01, three by 10 and 
four by 1 1. 

Bit positions 18 through 
23 specify the unit and 
the function to be per- 
formed with that unit. 



2.58 STANDARD EOM CHANNEL INSTRUCTIONS 

2.59 Several EOM function configurations have stand- 
ard uses. These have standard, assembler-type mnemonics 
and are separate instructions. 

2.60 ALERT CHANNEL (ALC) 



X 



02 



50X00 



2 3 



8 9 



23 



2.61 ALC alerts the channel interlace. This instruction 
does not disturb the channel buffer in any way. ALC 
has no effect on W or Y Buffers without interlace. The 
channel Alerts are: 



Mnemonic 


Al 


ert Channel 


Instruction 


ALC 




W(A) 


02 50000 


ALCl 




Y(B) 


02 50100 


ALC 2 




C 


2 02 50000 


ALC 3 




D 


2 02 50100 



2.62 DISCONNECT CHANNEL (DSC) 



X 



02 



2 3 



8 9 



00X00 

-H h 



23 



2.63 DSC disconnects the channel. It unconditionally 
sets the Unit Address Register to 00 regardless of whether 
the channel is currently addressing a device. This 
instruction disconnects any device which may be con- 
nected to the channel. It also unconditionally makes 
the channel Ready (Inactive) and clears the Error 
indicator. 



Mnemonic 


D 


sconnect Channel 


Instruction 


DSC 




W(A) 


02 00000 


DSC 1 




Y(B) 


02 00100 


DSC 2 




C 


2 02 00000 


DSC 3 




D 


2 02 00100 



2.64 ALERTTO STORE ADDRESS FROMCHANNEL(ASC) 



X 



02 



12X00 



2 3 



8 9 



23 



2.65 ASC alerts an Interlaced channel so the PIN 
instruction that follows can store the contents of the 
Memory Address Register. This instruction does not 
affect the operation of the channel. 



2-6 



September 1965 



SD5 900685C 



Paragraphs 2.66 to 2.79 



2.66 ASC is always used in conjunction with PIN to 
determine the current status of a peripheral operation 
being performed by the selected channel. The two 
instructions are written together: 

ASC n 

PIN m, X 

2.67 When the program executes these two instructions, 
the contents of the effective memory location designated 
by the PIN instruction are: 



Bit Positions 




Contents 


through 8 


Zero 








9 through 23 


Contents 


of 


channel 's 




Memc 


>ry 


Add 


ress Register 


Mnemonic 


Channel 






Instruction 


ASC 


W (A) 






02 12000 


ASC 1 


Y(B) 






02 12100 


ASC 2 


C 






2 02 12000 


ASC 3 


D 






2 02 12100 



2.68 TERMINATE OUTPUT OF CHANNEL (TOP) 



X 


02 

1 + 1 


14X00 
L \ h— H \ -J 



2 3 



8 9 



23 



2.69 When the last word of a block enters the channel, 
TOP terminates channel output. After the execution of 
this instruction, the following occurs. When the chan- 
nel buffer delivers the last character to the peripheral 
device, the buffer disconnects. 

2.70 TOP always terminates a non-interlaced channel 
output operation. It may be used with all communica- 
tion channels if the particular function selected is ter- 
minal function 11 but no further data output is required. 





Terminate Output 




Mnemonic 


on Channel 


Instruction 


TOP 


W (A) 


02 14000 


TOP 1 


Y(B) 


02 14100 


TOP 2 


C 


2 02 14000 


TOP 3 


D 


2 02 14100 



2.71 COMPATIBLE/EXTENDED INPUT/OUTPUT 
MODES 

2.72 The termination of an I/O operation and the 
interrupts that may be associated with that termination 
fall into two classes: Compatible and Extended. The 
choice of one of these two "modes" of input/output 
operation determines how the system behaves when the 
termination of an I/O operation occurs. 

2.73 Interrupts occurring at the same level (e. g. , 
location 30, 31, etc.) can have difference names (e.g.. 
Count Equal Zero and End-of-Word). These names 
reflect the different I/O mode in operation when the 
interrupt occurs. The differences include the timing of 
interrupt occurrence relative to the I/O operation and 
type of interrupt requested. 

2.74 The Compatible mode of operation for channels 
W(A), Y(B), C, D is directly compatible with the SDS 
900 Computer series modes of I/O operation. The types 
of interrupts that can be requested are the End-of-Word 
and End-of-Transmission interrupts. 

2.75 The Extended mode for all channels expands the 
I/O capabilities to include the "terminal functions" 
discussed below. The types of interrupts that can be 
requested are the Count Equal Zero and End-of-Record 
interrupts. 

2.76 The I/O mode is selected in the Input/Output 
EOM via bit 12, the Interrupt Arm bit. A 0-bit makes 
the system operate in the Compatible mode; a 1-bIt sets 
the system in the Extended mode. 

2.77 In particular, the Interrupt Arm (lA) bit deter- 
mines whether any of the Extended functions operate; 
that is, a "0" in lA means that the other Extended mode 
controls, bits 13, 14, 15 and 16, have no effect. 

2.78 INPUT/OUTPUT CLASS EOM 

2.79 The Input/Output EOM selects the I/O operation 
mode. When the Extended mode is selected, this EOM 
also selects (arms) which interrupts are to be operational 
and selects the desired terminal function. This EOM 
applies to channels W (A), Y(B), C, and D. 






Bl 





02/06 

1 ] ' 








1 


I 

A 


E 

R 


Z 

c 


F C 


B2 


A 


HI Count 
1 ^ 1 



123 8910111213141516171819 23 

OO Ol 02 03 04 05 06 07 



2-7 



Paragraphs 2.80 to 2.81 



SDS 900685C 



September 1965 



Bit Octal Octal 

Designation Position Value 



Bl 
B2 

02/06 



01 



lA 



OO 2 

05 1 

01-02 02 



03 



04 4 



ER 



Function 

Bit positions and 2 are 
not used with this EOM. 

Bit positions 1 and 17 
specify the channel. 

Bit positions 3 through 8 
contain 02/06, the 
instruction code for EOM. 

Bit positions 10 and 1 1 
contain the EOM indica- 
tor for the Input/Output 
control mode. 

Bit position 12 selects the 
mode of I/O operation. 
A "0" specifies the Com- 
patible mode. The oper- 
ation of bits 13, 14, 15, 
and 16 are disallowed. 
Channels W (A), Y(B), 
C and D operate in this 
mode which is completely 
SDS 900 series compati- 
ble. If interrupts are 
required, the user 
enables the Interrupt 
System, thus enabling 
and arming the End-of- 
Word and End-of- 
Transmisslon interrupts. 

A "1" specifies the 
Extended mode. All 
channels can operate in 
this mode. This allows 
the use of bits 13, 14, 15, 
and 16. If interrupts are 
required, the user arms 
the associated ones by 
placing 1-bit In bits 13 
and/or 14. The "termi- 
nal function" to be used 
Is selected via bits 15 
and 16. 



Bit position 13 controls 
the arming of the End- 
of- Record interrupt. A 
1-bit arms the interrupt. 
A 0-bit disarms the 
interrupt. 



Bit Octal Octal 

Designation Position Value 

ZC 1 



FC 



05 



HI Count 



Function 

Bit position 14 controls 
the arming of the Zero 
Word Count interrupt. 
A 1-bit arms the Inter- 
rupt. A 0-bit disarms 
the interrupt. 

Bit positions 15 and 16 
specify the terminal con- 
dition function to be 
performed with the trans- 
mission. 

Bit position 18 is the 
high-order address bit. 

Bit positions 19 through 
23 contain the most 
significant four bits of 
the 15-bit word count. 
These positions specify a 
word count greater than 
1023. 



NOTE 

A 1-bit in 13 and/or 14 does the 
following: 

1. Arms that interrupt during this 
complete I/O operation; discon- 
necting this channel disarms the 
interrupt. 

2. Once armed by bits 13 and/or 14, 
the interrupt can be enabled or 
disabled by the Enable/Disable 
feature of the Interrupt System. 

If a channel generates an extended 
mode I/O interrupt while the sys- 
tem is disabled, the designated 
interrupt level goes to the Waiting 
state. When the program again 
enables the interrupt system, the 
interrupt goes to the Active state 
when its priority allows. 

2.80 TERMINAL FUNCTIONS; EXTENDED MODE 

2.81 A 2-bit function code In the Input/Output EOM 
controls the termination of input/output operation in 
the extended mode. These functions are described 
below with the letter C representing the specified word 
count of the transmission. 



2-8 



September 1965 



SDS 900685 C 



Paragraphs 2-82 to 2-97 



2.82 INPUT/CUTPUTOF A RECORD AND 
DISCONNECT (lORD) 

2.83 Input 

2.84 Read C words. If C equals zero before the End- 
of- Record is detected, the rest of the record Is ignored. 
At the End-of-R cord, the peripheral device is dis- 
connected and the channel becomes inactive. 

2.85 Output 

2.86 Write C words. When C equals zero, output is 
terminated (i.e., the device is signaled that the last 
characters have been transmitted). When the peripheral 
device has generated the end of record and, if neces- 
sary, checked the validity of the record, it sends an 
End-of-Record response to the channel buffer. When 
received by the buffer, the End-of-Record signal gen- 
erates an End-of-Record interrupt (if armed) and dis- 
connects the channel. 

2.87 The line printer generates the End-of-Record 
response when it completes the printing of a line. If 
the printer encounters any print errors or faults, it 
sends a signal to the channel that sets the channel error 
indicator; this can occur since the printer has not dis- 
connected from the channel. The lORD is useful when 
the program is to print several lines and the program is 
not otherwise to use the channel between lines. When 
the printer completes each line, it causes on End-of- 
Record interrupt (assumed to be armed), notifying the 
program that it can immediately transmit the next paper 
control instruction and the next line image. 

2.88 The unbuffered card punch operates similarly. 

It generates the End-of-Record response after punching 
each row. If any faults occur during the punching of 
the entire card, the card punch sends a signal to the 
channel that sets the channel error indicator; this occurs 
after punching the last row (row 9). 

NOTE 

A program should not use lORD with 
devices i lat do not hove End-of- 
Record conditions on input (e. g. , 
typewriter) or generate End-of-Record 
responses upon output termination, 
(e.g., devices such as the paper tape 
punch and typewriter). These devices 
do terminate output but give the pro- 
gram no indication when they receive 
the last characters. 



2.89 INPUT/OUTPUT UNTIL SIGNAL THEN 
DISCONNECT (lOSD) 

2.90 Input 

2.91 Read C words. When C equals zero or when the 
End-of-Record is encountered, the device is discon- 
nected and the channel becomes Inactive. If the chan- 
nel disconnects because of a zero count, an EOR Inter- 
rupt (if armed) will be generated in addition to the count 
equal zero interrupt. If both are armed, C = will 
occur first. 

2.92 Output 

2.93 Write C words. When C equals zero and when 
the last character has been transmitted, the channel 
disconnects the device and becomes inactive. If an 
End-of-Record signal is received before the count 
reaches zero, the channel will disconnect Immediately. 

NOTE 

The lOSD is designed for use on 
devices which are normally 
operated on the basis of the word 
count only. Typewriters and paper 
tape devices are of this type, as 
are the printer and card punch 
when the user does not wish to 
stay connected until the operation 
is complete. 

2.94 INPUT/OUTPUT OF A RECORD AND PROCEED 
(lORP) 

2.95 Input 

2.96 Read C words. If the channel counts C down to 
zero before the peripheral device encounters the End- 
of-Record (EOR), the channel ignores the rest of the 
record (to the End-of-Record). When the peripheral 
device sends the End-of-Record signal to the channel, 
the channel sets its End-of-Record Indicator; this signal 
sets the End-of-Record interrupt (If armed). The chan- 
nel does not disconnect. The channel is now in an 
"Inter-record" condition. 

2.97 When the peripheral device is magnetic tape, the 
tape continues to move when the tape handler encounters 
the End-of-Record. The End-of-Record occurs when the 
tape read-heads encounter tape gap; this also causes a 
Tape Gap signal to "come high". If the program 
executes a new read tape or scan tape EOM during the 
inter-gap time (approximately one millisecond while 

the Tape Gap signal is high), the tape remains in 
motion and proceeds to read or scan the next record. 



2-9 



Paragraphs 2.98 to 2. 1 11 



SDS 900685 C 



September 1965 



If the program executes no such EOM before the Tape 
Gap signal drops, the channel disconnects and the tape 
comes to a stop. No additional Interrupt occurs. This 
is the only condition that causes a channel to disconnect 
automatically. 

2.98 All other input devices remain connected until 
the program takes further action. The paper tape reader 
remains in motion; the program should issue a "dis- 
connect channel" instruction if the program is not read- 
ing any more tape. To proceed after the End-of- Record 
occurs, the program first executes a Buffer Control mode 
EOM to re-initialize the Channel Unit Address Register 
and then reloads the interlace portion of the channel 
(the program can alert the Interlace via the Buffer Con- 
trol EOM). Otherwise, the channel Immediately ter- 
minates any attempt to use its interlace portion since 
the channel is aware that it is still active and in the 
End-of-Record condition. When the program continues 
from an Inter-record condition, the program should use 
an extended mode terminal function. An lORP should 
not be used to read devices which do not have EOR 
signals (e. g. , the typewriter and paper tape punch). 

2.99 Output 

2. 100 Write C words. When the channel interlace 
counts C down to zero, the Interlace notifies the chan- 
nel buffer that it has received the lost word that is to 
be output; when the buffer outputs this last word, it 
sends a signal to the connected peripheral device indi- 
cating that the device has the last word now. When the 
peripheral device "receives, outputs and checks the 
validity of" this last word, it sends an End-of-Record 
response to the channel buffer. When received by the 
buffer, the End-of-Record signal generates an End-of- 
Record Interrupt (If armed) and sets the Inter- record 
Indicator; the channel does not disconnect. 

2. 101 When the peripheral device is magnetic tape, 
the tape continues to move after it signals End-of- 
Record. As in reading tape, the signal causes the Tape 
Gap signal to come high. If the program executes a 
new write tape or erase tape EOM during the inter-gap 
time (approximately one millisecond), the tape remains 
In motion and proceeds to write or erase a new record. 
If the program executes no such EOM before the Tape 
Gap signal drops, the channel disconnects and the tape 
comes to a stop. No interrupt occurs at this time. This 
Is the only condition which causes a channel to discon- 
nect automatically. 

2. 102 To proceed after the End-of-Record occurs, the 
program first executes a Buffer Control mode EOM to 
re-initialize the Channel Unit Address Register and 
then reloads the interlace portion of the channel (the 
program can alert the Interlace via the Buffer Control 



EOM). Otherwise, the channel immediately terminates 
any attempt to use Its interlace portion, since the chan- 
nel is aware that it Is still active and in the End-of- 
Record condition. When the program continues from an 
Inter-record condition, the program should use an 
extended mode terminal function. 

2. 103 A program should not use lORP with devices that 
do not generate End-of-Record responses upon output 
termination; such devices are paper tape and typewriter. 
These devices do terminate output but give the program 
no indication when they receive the last characters. 

2. 104 The lORP should also not be used with the printer 
and card punch since these devices expect the channel 
to disconnect after they send EOR, 

2. 105 INPUT/OUTPUT UNTIL SIGNAL THEN 
PROCEED (lOSP) 

2. 106 Input 

2. 107 Read C words. If the channel counts C down to 
zero before the peripheral device encounters the End- 
to-Record, the channel generates a Count Equals Zero 
interrupt (if armed). The program should reload the 
interlace portion of the channel to continue reading the 
record. As far as the peripheral device knows, nothing 
happens at this time. Failure to reload the Interlace 
before the peripheral device sends enough characters to 
overfill the channel buffer causes a rate error; this sets 
the channel error indicator. 



2. 108 When the peripheral device encounters the End- 
of-Record, lOSP operates Identically like the lORP 
command. 



2. 109 Output 

2. 1 10 Write C words. When the channel counts C down 
to zero, the channel generates a Count Equals Zero 
interrupt (if armed); the channel does not terminate out- 
put. The program should reload the interlace portion of 
the channel to continue writing in the same record. 
Failure to reload the Interlace before the buffer trans- 
mits all of the characters in its registers and before the 
peripheral device requests the next character from the 
buffer results In a rate error; this sets the channel error 
indicator. 

2. 1 1 1 If the program executes a TERMINATE OUTPUT 
(TOP) instruction after the channel has counted C down 
to zero, the channel terminates the output and operates 
identically like the lORP from this point on. 



2-10 



September 1965 



SDS 900685C 



Paragraphs 2.112 to 2.122 



2.112 CHANNEL AND DEVICE SKS 

2. 113 The Channel and Device Test mode SKIP IF 
SIGNAL NOT SET (SKS) tests the indicators in a chan- 
nel as well as devices attached to it. To test the chan- 
nel, use unit address 00. The instruction format is: 

2.114 CHANNEL TESTS 






C 
2 





40(20) 

' 1 ' 


C 

1 





1 


R 


C 


E 


I 





c 

3 


00 
' \ 1 



12 3 891011 1213 1415161718 23 

OO Ol 02 03 04 05 06 07 



Bit Octal Octal 

Designation Position Value 



Function 



01 



CI 
C2 
C3 



03 


4 


OO 


2 


05 


1 



40(20) 01-02 40(20) Bit positions 3 through 8 

contain 40(20), the SKS 
instruction code. 

03 1 Bit positions 10 and 11 

contain the mode 
selection. 

Bits C1,C2, C3 used as 
an octal address, specify 
the channel to be tested. 
ChannelW(A) is 0, chan- 
nel Y (B) is 1, and so on. 

R Test for ready. A 1-bit 

selects the test. Skip if 
Ready or Inactive. 

C 04 2 Test if indicator for 

Word Count Equal to 
Zero is set. A 1-bit 
selects the test. Skip if 
word count zero. 

E 1 Test for error indicator 

reset. A 1-bit selects 
the test. Skip if no error. 

I 05 4 Test for Inter-record 

condition. 

00 Bit positions 18 through 

23 are zero to specify a 
channel test. Each of 
these tests causes a skip 
when the test condition 
is true. 

2. 1 15 STANDARD SKS INSTRUCTIONS 

2. 116 Several SKS function configurations have 
standard uses. These have standard, assembler-type 
mnemonics and are always used as shown. 



2. 117 CHANNEL ACTIVE TEST (CAT) 



SKIP IF CHANNEL NOT ACTIVE 



X 



40(20) 



2 3 



14X000 



8 9 



H h 



23 



2. 1 18 If the channel is ready to accept a new input/ 
output instruction, the computer skips the next instruc- 
tion in sequence and executes the following instruction. 
If the channel is active, or in the process of disconnect- 
ing a peripheral unit, the computer executes the next 
instruction in sequence. 





Channel 




Mnemonic 


Active Test 


Instruction 


CATO 


W(A) 


40(20) 14000 


CAT 1 


Y(B) 


40(20) 14100 


CAT 2 


C 


2 40(20) 14000 


CAT 3 


D 


2 40(20) 14100 



2. 119 The following SDS 900 series compatible instruc- 
tions make the identical test as the above instructions on 
channels W and Y; 

BRTW 40 21000 W BUFFER READY TEST 



BRTY 



40 22000 



Y BUFFER READY TEST 



2. 120 The indicator that CAT tests is reset only by the 
next EOM that connects and alerts the same channel. 

2. 121 CHANNEL ERROR TEST (CET) 

SKIP IF NO ERROR ON CHANNEL 



X 



40(20) 



1 1X000 



2 3 



8 9 



23 



2. 122 CET tests the error indicator in the channel for 
being in the set condition. If the error indicator has 
not been set, the computer skips the next instruction in 
sequence and executes the following instruction. If the 
error indicator has been set, the computer executes the 
next instruction in sequence. 



Mnemonic 


Channel Error Test 


Instruction 


CETO 




W(A) 


40(20) nooo 


CET 1 




Y(B) 


40(20) 11100 


CET 2 




C 


2 40(20) 11000 


CET 3 




D 


2 40(20) 1 1 100 



2-11 



Paragraphs 2. 123 to 2. 132 



SDS 900685C 



2. 123 The folloy/lng SDS 900 series compatible instruc- 
tions make the identical test of channels W and Y: 

BETY 40 20020 Y BUFFER ERROR TEST 

BETW 40 200^0 W BUFFER ERROR TEST 



2. 124 The indicator that CET tests is reset only by the 
next EOM that connects and alerts the same channel. 



2. 125 CHANNEL ZERO COUNT TEST (CZT) 



SKIP IF CHANNEL WORD COUNT IS ZERO 



X 



40(20) 



2 3 



8 9 



12X00 
I k 



23 



2. 126 CZT tests whether the contents of the Word 
Count Register in the channel have been reduced to 
zero. If the contents of WCR are zero, the computer 
skips the next Instruction in sequence and executes the 
following instruction. If the contents of the WCR are 
non-zero, the computer executes the next instruction 
in sequence. 



Mnemonic 


Channel Zero 
Count Test 


Instruction 


CZT 




W(A) 


40(20) 12000 


CZT 1 




Y(B) 


40(20) 12100 


CZT 2 




C 


2 40(20) 12000 


CZT 3 




D 


2 40(20) 12100 



2. 127 The indicator that CZT tests is reset only by a 
POT instruction to set up the word count and data 
address in the same channel. 



2. 128 CHANNEL INTER-RECORD TEST (CIT) 
SKIP IF INTER-RECCRD INDICATOR IS SET 



X 



40(20) 



10X00 



2 3 



8 9 



23 



2. 129 CIT tests the Inter- record indicator in the 
selected channel. If the Inter-record indicator is set, 
the computer skips the next instruction in sequence and 
executes the following instruction. If the indicator is 
reset, the computer executes the next Instruction in 
sequence. 







September 1965 




Channel 




Mnemonic 


Active Test 


Instruction 


CITO 


W (A) 


40(20) 10400 


CIT 1 


Y(B) 


40(20) 10500 


CIT 2 


C 


2 40(20) 10400 


CIT 3 


D 


2 40(20) 10500 



2. 130 The Inter-record indicator is set only during 
extended mode operation when using a Proceed Function; 
the Indicator Is set for an inter-record or zero count 
condition. The Indicator is reset by the next alert and 
connect EOM, 

2.131 DEVICE TESTS 

2. 132 The SKIP IF SIGNAL NOT SET (SKS) below, 
used in the Channel and Device Test mode, tests the 
condition of the peripheral devices in the system directly. 
The peripheral device sections contain the individual 
instruction descriptions. 






c 

2 





40(20) 

1 1 


C 
1 





1 


Unit Tests 

1 \ 1 


C 

3 


Unit 

Address 
L-H- ' 



12 3 8 9 10 11 


12 


16 17 18 23 


OO Ol 02 


03 


04 


05 06 07 


Bit Octal 


Octal 






Designation Position 


Value 




Function 


CI 03 


4 


Bit 


positions 9, 1, and 






17 


are used as an octal 






dig 


it to specify the 






channel. 



C2 

C3 
40(20) 

01 



OO 

05 
01-02 

03 



Unit Tests 04-05 



Unit Address 06-07 



Channel W (A) Is 0, 
channel Y(B) Is 1, and 
so on. 



40(20) Bit positions 3 through 
8 contain the SKS 
instruction code. 

1 Bitpositions lOand 1 1 

contain the mode 
selection. 

Bit positions 12 through 
16 select the particular 
test and are system 
dependent. 

Bitpositions 18 through 23 
specify the unit address. 



2-12 



September 1965 



SDS 900685 C 



Paragraphs 2. 133 to 2. 152 



2.133 SINGLE-WORD DATA TRANSFER VIA 
CHANNELS W (A) ANDY 

2.134 INSTRUCTIONS 

2. 135 Channels W (A) and Y can be programmed as 
single-word input/output buffers. Data transfer is per- 
formed under direct program control or with the aid of 
the interrupt system. Interlace is not used with these 
instructions. 

2. 136 The following two instructions perform data 
transfer using channel W. 

2. 137 MEMORY INTO CHANNEL W WHEN EMPTY 
(MIW) 



R 



12 



M 



12 3 



8 9 10 



23 



2. 138 MIW transfers the contents of the effective 
memory location into the channel W word buffer. If 
necessary, the central processor "hangs up" until the 
buffer is empty and ready to accept the data word. 



2. 144 CHANNEL Y INTO MEMORY WHEN FULL 
(YIM) 



X 



30 



M 



12 3 



8 9 10 



23 



2. 145 YIM transfers the contents of the channel Y 
word buffer into the effective memory location. If 
necessary, the central processor hangs up" until the 
buffer is full and ready to deliver the data word. 

2. 146 MEMORY INTO CHANNEL A WHEN EMPTY 
(MIA) 



I 


X 


30 


M 

k: \ \ \ 1 zx^ 



12 3 



8 9 



23 



2. 147 The contents of the effective memory location 
are tronsferred into the channel A word buffer. The 
central processor "hangs up" until the buffer is empty 
and ready to accept the data word. 

2. 148 CHANNEL A INTO MEMORY WHEN FULL 
(AIM) 



2. 139 The W buffer must be connected to the desired 
peripheral device by a previous "connect" EOM instruc- 
tion that selects the buffer, the unit address, and all 
appropriate control functions. 

2. 140 CHANNEL W INTO MEMORY WHEN FULL 
(WIM) 



R 



X 



32 



M 



12 3 



8 9 10 



23 



2. 141 WIM transfers contents of the channel W word 
buffer into effective memory location. If necessary, 
the central processor "hangs up" until the buffer is full 
and reody to deliver the data word. 

2. 142 MEMORY INTO CHANNEL Y WHEN EMPTY 
(MIY) 



X 



10 



M 



12 3 



8 9 10 



23 



2. 143 MIY transfers the contents of the effective 
memory location into the channel Y word buffer. If 
necessary, the central processor "hangs up" until the 
buffer is empty and ready to accept the data word. 



X 



32 



M 



12 3 



8 9 



23 



2. 149 The contents of the channel A word buffer are 
transferred into the effective memory location. The 
central processor "hangs up" until the buffer is full and 
ready to deliver the data word. 

2.150 SINGLE-WORD OPERATIONS 

2. 151 The single-word buffer operations are used in 
two ways. Data words transfer between the channel and 
memory under direct program control. The "connect" 
EOM and the Input or output channel instruction are In 
sequence and the computer "hangs up" until the buffer 
is ready to perform the transfer. This delay is usually 
due to buffer tie-up while the buffer is actively trans- 
mitting or receiving the previously requested data word. 

2. 152 Use of the priority interrupt system eliminates the 
tie-up of the central processor. The Interrupt system 
allows the program to connect the device to be used In 
the transfer, to enable the interrupt, and then to con- 
tinue processing in the main program. When the buffer 
is ready to receive from, or transfer to, memory, the 
End-of-Word interrupt to the corresponding interrupt 
location notifies the program that the buffer is Ready. 
A service routine entered via a BRANCH AND MARK 
PLACE (BRM) instruction In the appropriate interrupt 



2-13 



Paragraphs 2. 153 to 2. 154 



SDS 900685 C 



September 1965 



location processes the Interrupt. This routine contains 
the instruction (MIW or WIM, for example) that can 
execute immediately without computer tie-up. 



2. 153 During single-word operations, a parity error or 
incorrect timing error sets the buffer error indication in 
the channel. The incorrect timing error occurs when 
characters enter the buffer during Input before the 
removal of the previous word; during output, buffer 
error indication occurs if characters are needed for out- 
put before the buffer receives the next word. The 
transmission does not terminate upon detection of any 
of these errors. 



2. 154 The interrupt system can detect an End-of-Record 
termination. During output, use of TERMINATE OUT- 
PUT (TOP) after the final MIW (MIY) causes an inter- 
rupt to the appropriate End-of-Transmission location 
when that final data word has been processed by the 
buffer. This interrupt takes the place of the End-of- 
Word interrupt; the End-of-Transmission condition 
Inhibits the End-of-Word interrupt. During input, the 
End-of-Transmission interrupt is sent to the End-of- 
Transmission location when the End-of-Record Is 
detected. During Input from devices which do not 
generate an End-of-Record, an EOM disconnects (DSC) 
the channel to terminate the transmission. This termina- 
tion generates no End-of-Transmission Interrupt. 



2-14 



September 1965 



SDS 900685 C 



Paragraphs 3-1 to 3. 16 



SECTION III 
THEORY OF OPERATION 



3.1 GENERAL 

3. 2 The TMCC communicates with an external system 
or device by means of a shift register utilizing 6, 12, 
or 24-bit characters plus a parity bit. The maximum 
character size depends on the optional registers that 
may be installed. In TMCC Models 922XX, the char- 
acter length is fixed at 6, 12, or 24 bits and can not 
be varied from one size to another. However, TMCC 
Models 932XX having the larger character length 
options may be switched from one size to another under 
control of the external system. The length is selected 
through activation of one of the character size control 
lines. External devices may activate these lines as 
necessary but if none are activated the TMCC assumes 
6-bit characters. The rate of information transfer is 
determined by a clock signal from the external device. 
For both Input and output, the TMCC slaves itself to 
the clock frequency of the device up to the TMM maxi- 
mum data rate of two machine cycles per character. 

3. 3 The TMCC communicates with the computer by 
means of a 24-bit shift register which transfers words, 
an octal group at a time, between the TMCC and the 
computer C Register. The TMCC thus has two registers 
for data storage. These provide the means to assemble 
input characters into words or disassemble words into 
output characters. The number of characters per word 
is under program control but is limited to a maximum of 
four 6-bit characters, two 12-bit characters, or one 
24-bit character. 

3.4 Information may be input or output by executing 
an instruction for each word (channels W (A), or Y, 
only). The instruction may be given in advance of the 
time it is needed, in which case the computer remains 
idle until the channel is ready. Or the computer inter- 
rupt system may be employed so that the channel can 
call for an instruction when It is ready to use it. This 
allows the computer to continue with other computa- 
tions when not actually engaged in the input/output 
(I/O) process. 

3.5 An optional interlace feature may be Installed In 
the TMCC to facilitate I/O operations with fewer in- 
structions. The Interlace logic allows a program to 
designate to the TMCC how many words ore to be trans- 
ferred and the memory location of the first word. Then, 
without further instructions, the TMCC can assemble 

or disassemble the number of words specified and time- 
share with the computer each time it Is ready to trans- 
fer a word to or from memory. The I/O process may 
thus be interlaced with computation or with similar 
I/O operations on other channels. 



3.6 Figure 3-1 is a block diagram of the TMCC. As 
indicated on the figure, the principal parts of the TMCC 
are the Character Buffer, Word Assembly Register, Unit 
Address Register, Word Counter, and Address Counter. 

3.7 CHARACTER BUFFER 

3.8 Depending on the option, the Character Buffer is 
a single character storage register of 6, 12, or 24 bits. 
It is implemented with S-R type flip-flops connected in 
a series-parallel manner so shifting takes place in octal 
groups (I.e. three bits In parallel). Transfer of data 
between the Character Buffer and an external system is 
entirely parallel for the whole character whether it be 
input or output. 

3. 9 WORD ASSEMBLY REGISTER 

3. 10 This register is also connected In series-parallel 
to allow shifting in octal groups. It is composed of 
three parallel registers of eleven flip-flops each. The 
register includes twenty-four flip-flops to store a com- 
plete word plus additional flip-flops on the ends of each 
series string to allow for timing considerations. The 
Word Assembly Register Is implemented with flip-flops 
connected in such a manner that continuous recircula- 
tion occurs. 

3.11 UNIT ADDRESS REGISTER 

3. 12 The 6-bIt address code to select a specific 
peripheral device is set-up In the Unit Address Register. 
The register is composed of five flip-flops whose outputs 
are sent to the peripheral unit for decoding. A sixth 
flip-flop, associated with the Unit Address Register, is 
also set-up at the same time to signal the external 
device whether an input or an output is to take place. 

3. 13 WORD COUNTER 

3. 14 The Word Counter Is part of the optional inter- 
lace equipment. It is a fifteen stage flip-flop counter 
used to store the number of words to be transferred dur- 
ing an interlaced I/O operation. With each word 
transfer, the counter Is decremented by "one". (Actu- 
ally, the complement of the count Is incremented. ) 

3. 15 ADDRESS COUNTER 

3. 16 This counter is also part of the optional interlace 
feature. Its purpose Is to store the address of the d 
memory location currently being accessed. Each time 
a word Is taken from or sent to memory, the Address 



3-1 



I 

fO 



6 Bit 

Character ^ 
+ Parity Bit 



Unit 

Address 

Code 



Device 
Control 



Channel W or A 



Parity 



Unit 
Address 
Register 



I 



Char. 
Buffer 



L_ 



I 



_J 



_J 



7^ 



^ 



1 



Word 

Assembly 

Register 



Interlace 
(Optional) 



Word 
Counter 



Data 
(Out) 



Data 



(In) 



Address 
Counter 



I 



Control Logic 



< ^ 




> To CPU 



Memory 
Address 
Lines 



J 



Request and 

Interrupt 

Signals 



a 

</> 

^0 
O 
O 

O^ 
00 
Cn 

n 



CO 

■D 

-t- 

a> 

3 

D- 
fD 



Figure 3-1. Time Multiplexed Communication Channel With Interlace, Block Diagram 



""O 
On 



September 1965 



SDS 9000685C 



Paragraphs 3. 17 to 3.35 



Counter Is Incremented by "one" to prepare for loca- 
ting the next word. 

3. 17 INPUT PROCESS 

3. 18 A brief outline of a non-interlaced input process 
follows. The TMCC is initialized by an EOM instruc- 
tion to set-up the address code of the peripheral de- 
vice, to designate Input or output, and specify the 
number of characters per word. When the address is 
decoded by a peripheral device, the device is activ- 
ated and begins sending clock signals and data to the 
channel. 

3. 19 Input clocks are synchronized with TMCC timing 
by clock counter flip-flops which detect the peripheral 
device clock, transfer the input data to the Character 
Buffer and cause the Word Assembly Register to circu- 
late through the Character Buffer. Ordinarily the 
Word Assembly Register recirculates on itself but as 
each new input character is ready it circulates through 
the Character Buffer for one machine cycle to pick up 
the new character. A machine cycle Is defined as 
eleven computer clock pulse periods. 

3.20 As each character Is clocked in, the character 
counter (W7 W8) is decremented until the count reaches 
zero, signaling that a complete word has been formed. 
Depending on the particular channel (TMCC W (A) or 
Y) a WIM, AIM, or YIM instruction may be used to 
transfer the word from the TMCC to memory. When the 
Instruction Is executed, a word Is shifted In octal groups 
from the Word Assembly Register to the computer C 
Register and then stored in the memory location speci- 
fied by the effective address of the WIM, AIM, or YIM 
instruction. 

3.21 To prepare for the next word, the Character 
Counter Is reset to its original count which was de- 
signated by the initializing EOM instruction. Storage 
of the original count is accomplished by utilizing ex- 
cess positions of the Word Assembly Register. 

3.22 The input process may be terminated by another 
EOM instruction or by detection of an externally 
applied halt condition. 

3.23 OUTPUT PROCESS 

3.24 A non-interlaced output process is started In the 
same way that an input operation is initialized. A MIW 
(MIY or MIA) instruction can then be used to transfer 
words from memory to the Word Assembly Register via 
the computer C Register. 

3. 25 Each time the external device sends a clock sig- 
nal to the TMCC, it is detected by the Clock Counter. 



At a certain point in the counter sequence, the device 
extracts information from the Character Buffer. At the 
end of the counter sequence, the Word Assembly Re- 
gister recirculates through the buffer for one machine 
cycle. At the conclusion of the cycle, a new character 
is available in the Character Buffer awaiting the next 
clock. The Clock Counter also decrements the Char- 
acter Counter. When it is decremented to zero, the 
last character of a word is In the buffer. By this time 
another MIW (MIY or MIA) instruction should be exe- 
cuted; or the instruction may be called for through the 
interrupt system. As with input, the Character Counter 
is reloaded between words from the Word Assembly 
Register. 

3. 26 The output operation Is concluded by a Terminate 
Output EOM Instruction. 

3.27 Parity 

3.28 During input, a parity flip-flop accepts the Input 
parity bit and checks the character for odd parity. The 
same flip-flop Is also used to generate the parity bit for 
output characters. 

3.29 TMCC AND INTERLACE CONFIGURATION 

3. 30 The theory of operation contained in this manual 
is applicable to all models of the Time-Multiplexed 
Communication Channels for the 925/930/9300 Com- 
puters. The operation is for the most part Identical for 
all models. Those differences that do exist, however, 
are covered in the explanation where appropriate. 

3.31 DETAILED DESCRIPTION 



3. 32 Many portions of the TMCC logic are common to 
both Input and output operations. Other portions of the 
logic are specifically related to Input only, output only, 
or Interlace only. The following logic description 
begins with the common logic functions. 

3. 33 Subsequent to the logic descriptions are the 
Glossary of Logic Term and the Logic Equations. 

3.34 PULSE COUNTER 

3.35 The pulse counter consists of flip-flops Qrl, Qr2, 
Qr3, and Qr4. These flip-flops perform the same func- 
tion for the TMCC that the pulse counter, Ql through 
Q6, does for the central processor (CPU). The counter 
Is included In the TMCC In addition to the counter In 
the CPU In order to avoid excessive delays and loading 
that would occur If all timing signals were obtained 
directly from the CPU. The Pulse Counter defines the 
pulse times, T8, T7, T6, T5, T4, T3, T2, Tl TO, Tr, 
and Tp needed for timing of all processes within the 
unit. Refer to table 3-1 for the Pulse Counter Truth 
Table. 



3-3 



Paragraphs 3. 36 t-o 3. 40 



SDS 900685C 



September 1965 



Table 3-1. Pulse Counter Truth Table 



X 





Qrl 


Qr2 


Qr3 


Qr4 


Tp 














T8 


1 











T7 


1 








1 


T6 


■....1} 


1 




1 


T5 





1 




1 


T4 










1 


T3 













T2 


1 










Tl 


1 


1 







TO 





1 







Tr 














Tp 















3.36 It is logically impossible to set Qr2, Qr3, and 
Qr4 unless Qrl has been previously set. Therefore, 
without the additional set signal provided by Tpc, the 
counter would soon reach the reset state of time Tr + 
Tp and then stop counting. However, Tpc, the Tp 
signal from the CPU, is used to advance the TMCC 
pulse counter from Tp to T8. Thus, both counters ad- 
vance to T8 at the same time and both remain in syn- 
chronism. An examination of the logic also indicates 
that the two pulse counters will synchronize regardless 
of the turn-on state. 

sQrl = Tpc + Qr2 Qr3 QTa 
rQrl = Qr2 

sQr2 = Qrl M Qr4 (Qr4 + TO) + Qrl Qr3 
rQr2 = QH 

sQr3 = Qrl Qr4 

rQr3 = Qr3 QTA {Qr4 + TO) 

sQr4 = Qrl Ol^ 
rQr4 = QH Oi^ 

Only those pulse times or combinations of pulse times 
that are need for timing in the TMCC are decoded. 
For example: 



3. 37 In examining the pulse counter and the TO decod- 
ing logic, it appears that the term (Qr4 + TO), as used 
on the inputs of Qr2 and Qr3, contains redundant logic. 
This is a result of logic mechanization and the redun- 
dant terms are not significant to the counter operation. 

3. 38 A TMCC pulse counter is associated with each W 
and C channel. The Y and D channels share the same 
pulse counters as the W and C channels, respectively. 
Other logic is shared in a similar manner by two chan- 
nels and will be noted as each case arises. 

3.39 INPUT/OUTPUT PROCESSING 

3.40 When an EOM instruction of the form, EOM- 
OXXXX or EOM4XXXX, is executed to start an input or 
output process, a Buffer Control Signal, Buc, produces 
a clear signal, Wc, and a set signal, Ws. These two 
signals, Wc and Ws, permit initialization for the input/ 
output operation. The Unit Address and the Character 
Count are set up from the C-Register. The registers are 
first cleared by Wc and then set by Ws. Refer to 
figure 3-2. 

Buc = Eom CTO CTl CT* 

Wc = Buc CTZ (T6 + T5) + St + . . . 

Ws = Buc 07 (T3 - TO) 

*C1 is used in place of C I for Channels C and D. 

Similarly, C17 and C17 distinguish between the W and 
Y channels, or between the C and D channels. 

(T6 + T5) and (T3 - TO) are decoded timing signals from 
the pulse counter. Frequent use is made of such pulse 
times thr ough out the manual without further explanation. 
The term C17 distinguishes enabling of the W channel 
rather than the Y channel. The combination of terms 
which make up the input of Buc indicate that the com- 
puter is in phase (0) 5 of the execution of an EOM 
Buffer Control instruction. The term, St, is produced 
by the start switch which may also be used to reset the 
TMCC. The register logic involved in the clear and set 
sequencing is: 



sW14 = Ws C23 
rW14 = Wc 



sWll 
rWll 



I 
I 

Ws C20 

Wc 



TO 
T6-T0 



Qrl Qr2 Qr4 
Qr3 



sWlO = Ws C19 + 



rWlO = Wc 



Unit Address Register 

5-bits provide 31 address- 
ing codes and a discon- 
nect code. 



3-4 



MIW 
Data 




C Register in CPU 



Full I 
or Empty, C15 C16 



C18 C19 



C23 



1 



Wf 



'00' 



Char. 



W7 W8 



Store/Load Count 
Precess 






Parity 
Flip-Flop 



' Counter ' ' ' ' Register ' ' 



W9 



Decrement 
Count by 
One 



W4 

T 



Clock 



Detector 



W5 



W6 



P 1 2 3 4 



5 6 



Input or Output Characters 



Unit 
Address 



WIG 



W14 



Clock Input ^ 

or 



V 

Unit 

Output Address Code 

(5 Bits) 



00 

(D 

-a 

(D 

3 
o- 

(D 



>o 



vO 

o 
o 

00 
Cn 

o 



CO 

I 

Cn 



Figure 3-2. TMCC Information Flow Diagram, Input/Output (6 bit) 



Paragraphs 3.41 to 3.46 



SDS 900685C 



September 1965 



sW9 = Ws C18 
rW9 = Wc 

sW8 = WsC16 + . 
rWB = Wc + . . . 

sW7 = WsC15 + . 
rW7 = Wc + . . . 



"^ 



W9 = 1 for output 
W9 = for input 

Character Counter 





W7 


W8 


Characters/Word 


1 


1 


4 


1 





3 





1 


2 








1 



3.41 At the end of the Buc type instruction and during 
the last pulse time (TO) that Ws Is on, the flip-flop, W4, 
Is set on for three pulse times. 

sW4 = Ws TO + . . . 
rW4 = W4 T8 + . . . 

During this time, W4 allows the contents of the char- 
acter counter to be copied into the W-Register. The 
bit In W7 goes into Wwl and the bit in W8 goes Into 
Ww2. 



Wwl 



W4 W7 (T7 - TO) + . . . 



Ww2 = W4 W8 (T7 - TO) + . . . 

During this period, W4 or timing singals Inhibit the 
other inputs to the W-Reglster. 

3.42 This process provides a means for the TMCC to 
remember the initial character count while using flip- 
flops W7 and W8 to perform the actual count-down of 
the characters as each word is assembled on input or dis- 
assembled on output. As a word Is processed, the 
original count is reloaded into the counter to get ready 
for the next word. 



sW8 = Wxx Wn2 (T7 - TO) W4 

sW7 = Wxx Wn 1 (T7 - TO) W4 

The term Wxx Is true during the transmission of a word 
being processed. Thus, in addition to its normal word 
handling functions, the W-Register provides storage of 
the character count for W7 and W8. 

3.43 W-Register 

3.44 The W-Reglster Is a one word recirculating flip- 
flop register with additional flip-flops at the read and 
write ends. The Write input signals to the first flip- 
flops of the register are designated Ww-, the Inter- 
mediate Read flip-flops are designated Wr- and these 
drive the last flip-flops which are designated Wn-. The 
n represents now. 



3.45 During normal recirculation, the outputs of the 
n flip-flops are fed to the w inputs, which, in turn, 
feed the remaining serial shift circuits. There are a 
total of eleven stages in a recirculating loop, one for 
each pulse time of a machine cycle. Three recircula- 
ting loops are required to hold a 24-bit word. The first 
recirculating loop holds only the most significant bits 
of each of the eight octal digits in a word. The second 
recirculating loop holds the middle bits of the eight 
octals. The third recirculating loop holds the least 
significant bits of each of the eight octals. If the octal 
word 07030407 (000 111 000 01 1 000 100 000 1 1 1) 
were being held in the register, its bits at pulse time 
Tp would appear as follows: 



C 



H 



COIOOOIOICC 
L^C 1 1 000 1 c c^ 



C = Character 
Count 

X = Irrelevant 



C 



XOIOIOOOIXX 



D 



At the next pulse time, T8, all bits would be moved one 
bit position to the right and for succeeding pulse times 
as the register recirculates. At the least significant 
pulse time, T7, the bits of the least significant octal 
digit are in their respective now flip-flops, Wnl, Wn2, 
and Wn3. At succeeding pulse times the now flip-flops 
present the corresponding octal digits. The additional 
positions beyond the eight octals of the register act as 
fill-in bits to satisfy logic timing requirements (so that 
a word is back in Its original position after one machine 
cycle of 1 1 clock pulses) and are also used to store the 
character count. Normal recirculation is allowed by 
the following logic: 



Wwl = W4 Wnl Wxx + 



Ww2 = W4 Wn2 Wxx + 



Ww3 = W4 Wn3 Wxx + 



W4 Wxx indicates the 
W-Register is not par- 
ticipating in some other 
operation. 



3.46 The Character Register is composed of six, twelve, 
or twenty-four R-S type flip-flops. When shifting an 
input character from the Character Register into the W- 
Register or an output character from the W- Register to 
the Character Register, W4 is set for the period (T7-T0) 
of one machine cycle. This enables the gating of one 
character precession in the W-Reglster by causing the 
data In the W-Reglster to recirculate through the Char- 
acter Register. Refer to figure 3-3. 

Wwl = W4 Wbl (T7- T0) + . . . 
Ww2 = W4 Wb2 (T7 - TO) + . . . 



3-6 



W Register 



Character Buffer 



Wbl 



Error 
Signal 



We 



Wwl 



Wrl 



Wnl 



11 Bit Delay 



Rwl 



Rw4 






_H 



Wbl e wb2ewb3 

True 

for 1 or 3 
■ones" 



Rwp 



Inhibit 
Parity 



Parity 

Bit 

From 

Input 

Character 





Wx24 



Ww2 



Wr2 



Wn2 



11 Bit Delay 



Rw2 




(r7-T0)Qw1 



Rw5 

T 



•-ITI 



Wxl2 
Wx24 



Rw23 



€ — QZ 



Wxl2 



d 



Wx24 



Ww3 



11 Bit Delay 



NOTE: 

1 , Gating is as shown for Models 93200 and 93221 . 
For 922XX Models, gating is replaced by plug cards wired as follows: 

Wbl, 2, 3 equal Rw4, 5, 6 respectively for 92200 (92210 For Y Channel) 
Wbl, 2, 3 equal RwlO, 11, 12 respectively for 92201 (92211 for Y Channel) 
Wbl, 2, 3 equal Rw22, 23, 24 respectively for 92201 (92212 for Y Channel) 

2. Wx12 and Wx24 are signals derived from the peripheral device to sele ct the I/O 
charac ter size. If the device does not designate a character size then Wx12 and 
Wx24 are true and Wx12 and Wx24 are false. 




Wx24 



t/1 

CO 

^o 
o 
o 
o 

00 
Cn 

n 



C/1 

-a 

3 ■ 



CO 



Figure 3-3. Precession Loop and Input Parity Checking Logic 



vO 



Paragraphs 3. 47 to 3. 52 



SDS 900685C 



September 1965 



Ww3 = W4 Wb3 + . . . 

sRwl = W4 W^ (T7 - TO) Wnl + . . . 
rRwl = W4 Vh^WT] +. . . 

sRw2 = W4 W^ (T7 - TO) Wn2 + . . . 
rRw2 = W4 W^ W^ + . . . 

sRw3 = W4 W^ (T7 - TO) Wn3 + . . . 



rRw3 = W4 Wxx Wn3 + . . . 

Wxx Is a signal denoting that an MIW, WIM or Time 
Share operation is occurring. 

Wxx = Rx Pwy + . . . * 
Pwy = 05 ** 

*Rx is always false for the C-channel. Another term, 
not shown allows Wxx to function in that channel 
only on an interlaced basis. 

**In Model 92200. See 05, Pw5 in the Glossary of 
terms. 

3.47 The Time Share Operation Is discussed beginning 
with paragraph 3. 102. Since there are no WIM/MIW 
type instructions for TMCC-B, C, or D, Rx is always 
false for these channels. 

3.48 The timing signals (T7 - TO) on the Inputs of Wwl 
and Ww2 are necessary to prevent Interference with the 
storage of the character count which was previously 
described. The character count does not precess but 
recirculates. This recirculation Is allowed by: 



Wwl = W4 Wnl (T7- TO) + 



Ww2 = W4 Wn2 (T7 - TO) + . . . . 

3.49 During the Input or output precession, the shift 
logic for the character register is as shown below. De- 
pending on the 12- or 24-bit character option, all bits 
may not be installed. 

sRw4 = W4 Rw4 Rwl + . . . 
rRw4 = W4 Rw4 Rwl + . . . 



sRw5 

rRw5 
I 
I 
I 
I 
sRw23 

rRw23 



= W4 Rw5 Rw2 + . 

= W4 Rw5 R^ + . 

I 



sRw24 = W4 Rw24 Rw21 + . . . 
rRw24 = W4 Rw24 R^ +. . . 

The shift inputs for Rwl, Rw2, and Rw3 ore given In 
paragraph 3. 46. The precession of characters Is con- 
trolled by W4. When a WIM or MIW instruction is 
executed, Wf Is set. Wf remains set until the count in 
W7 and W8 is 00. 

sWf = Rx TO Twy 

rWf = W7 W8 W4 (T6 + T5) 

Rx Pwy = Wxx which Indicates a WIM or MIW instruc- 
tion is occurring. Wf is later used to indicate to the 
computer when the W-Register is full on input or empty 
on output. 

3.50 Two other flip-flops, W5 and W6, detect external 
device clocks (which may occur either before or after 
Wf is set). The clock Ecw is first detected by W6 as 
follows: 



sW6 = W5 Ecw T8 WIO Wl 1 W12 W13 W14 
rW6 = W4 TO + Wc 

At the next TO pulse after the device clock goes false, 
W5 sets allowing W6 to reset again. Setting of W5 in- 
hibits further clock detection until the current clock Is 
processed. 



= W4 Rw23 Rw20 + 



= W4 Rw23 Rw20 + 



sW5 = W5 W6 Ecw TO + . . . 
rW5 = W4 TO + . . . 

Setting of W4 is interlocked with W5 and Wf to allow 
one precession of the W Register to take place after 
each external clock signal. 

sW4 = W5 Wf T8 Wi + . . . 
rW4 = W4T0 + . . . 

The term, Wg, explained In detail In paragraphs 3-66 
and 3-150) Is assumed to be true at this time. 

3.51 The equation for Wf contains W7 W8, indicating 
that precession is complete when the character count 
reaches 00. The count down Is enabled by W4 and is 
accomplished by: 

sW8 = W7 W8 W4 TO + . . . 
rWS = W8 W4 TO + . . . 
rW7 = W7 W8 W4 TO + . . . 

3.52 The foregoing discussion was limited to processes 
common to input and output operations. The interrupt 



3-8 



Sepl-ember 1965 



SDS 900685 C 



Paragraphs 3. 53 to 3. 59 



function, which allows the TMCC to signal the computer 
when It is ready to transfer a word to or from memory, 
was omitted. In subsequent paragraphs, features pecul- 
iar to input or output operation are discussed separately. 
Details concerning interrupt operation are included. 

3.53 INPUT PROCESS (W9 true) 

3.54 The characteristics of a typical input clock signal 
and its relationship to the Input data and Clock Counter 
flip-flops are illustrated in figure 3-4. Examination of 
figu re 3 -4 indicates that if the data is to be sampled by 
W6 W5 it has to be on by the time the clock, Ecw, re- 
turns to zero volts. Also, in order not to be read by 
the previous or next clock, the data may not come on 
until at least one machine cycle after the previous 
clock and must go off before the next clock appears. 

3.55 Two detailed examples of the clock signal, Ecw, 
are illustrated In figure 3-5. To be assured of a timing 
pulse occurring during the on period (to set W6) and 
the off period (to set W5) of Ecw, each of these periods 
must be at least one machine cycle in length. This 
prescribes an Input clock cycle of no less than two 
machine cycles. The clock rate must be somewhat 
slower than this for proper operation of W6, W5, and 
W4. Figure 3-5a illustrates two input clocks with tim- 
ing such that the second clock is missed. Any clock 
rate slower than that illustrated in figure 3-5a would be 
satisfactory, however, a safety margin must be provided 
to compensate for noise and variations in waveshape and 
frequency. 

3.56 The input frequency may be Increased as illus- 
trated In figure 3- 5b If the clocks are interlocked with- 
in the peripheral device with W5 and W6 from the 
TMCC such that 



Jew) = (Device Clock) W5 W6 



In this case, only two machine cycles per input clock 
are needed. Some of the peripheral device couplers 
Include this interlocking feature. 

3.57 When a Buc type EOM instruction is executed to 
activate the TMCC for an input operation, the halt 
detector, Wh, is reset and the computer interlock flip- 
flop, Wf, is set by the clearing signal, Wc. 

Wc = Buc CTZ (T6 + T5) + 

sWf = Wc Wh" + . . . 

rWh = Wc (T6 + T5) + . . . 

This prepares the Character Register to precess the first 
input character into the W- Register enabling W4 which 
gates Wwl, Ww2 and Ww3. 



3.58 The Character Register and parity flip-flop are 
cleared originally and again between each input char- 
acter by W^W6 W3W^. After processing the Buc type 
EOM instruction, the Character Register is ready to re- 
ceive an input character and clock even though a WIM 
instruction is not immediately given. The input bits, 
Zwl through Zw24 and the parity bit Zwp, are gated 
into th e Ch aracter Register and the Parity Flip-Flop by 
W9 W6 W5. W9 signifies an input operation and W6 
W5 Indicate on input clock has been detected from the 
peripheral device. 



sRwl 


= W9W6W5Zwl 


rRwl 
1 
1 


= W9 W6 W5 W4 

1 
1 


1 

1 

sRw24 


1 
1 

= W9W6W5Zw24 


rRw24 


= W9W6W5W4 



sRwp - W9W6W5Zwp 
rRwp = W9W6W5W4 

3.59 Precession then takes place as described earlier 
and another input character can be read into the Char- 
acter Register. This read-precess cycle is repeated for 
each input character until the Character Counter Is 
decremented to 00 causing Wf to reset. Resetting of Wf 
Inhibits further precessions and indicates to the computer 
that the W- Register is full and ready to transfer a word 
into memory. The program should now provide a WIM 
instruction to enable the transfer. One more character 
may still be stored in the Character Register before re- 
ceiving the WIM Instruction. Further input characters 
are blocked because W4 is inhibited while Wf is reset. 
This prevents W5 from resetting, which In turn disables 
clock detection by W6. When a WIM instruction does 
occur late, The Error Detection Flip-Flop, We, Is set. 
This condition can be tested by an 5KS Instruction. The 
error detection flip-flop is reset by Wc which occurs 
with an EOM-Buc instruction. 

sWe = WO W6 W5 Ecw T8 + . . . 
rWe = Wc Wh 

This equation signifies that a WIM instruction is late if 
the clock signal, Ecw, is received before the previous 
character has been precessed out of the Character Re- 
gister. The WO, Halt Interlock, and Wh, Halt Detec- 
tor, signals appearing here are discussed in detail In 
paragraphs 3.65 and 3.66. When the interlock feature 
of figure 3-5 is employed, the condition W6 W5 Ecw 
cannot occur to set We. Under such circumstances, the 
peripheral device (or coupler) must be capable of de- 
tecting Its own rotgerrors and reporting them via the 
Error Signal line, (Wep . 



3-9 



SDS 900685 C 



September 1965 



TO 



Jl_Jl_JLJLJl_JLJLJl_fl_JLJl_J_JI_Jl 



VV 



Ecw 



W6 



W5 



W4 



Wf 



WIM 



Time 



(^Ecw)o- 




O Ecw 
o Ecw 



TO 
Ecw 






Input Data / 



7\ 



Figure 3-4. Input Clock Timing Charts (Typical) 



3-10 



September 1965 



SDS 900685C 



TO 



_R 



n 



n 



T8 Missed 



Ecw 



W6 



J 



25 Pulse Times 



W5 



W4 



Time 



-^ 



a. Input Clocks too Fast 



TO 



_R 



n 



n 



n 



n 



Ecw 



J 



W6 



L 



W5 



L 



W4 



Time 



■^»- 



L 



b. Input Clocks Interlocked With W5 W6 



Figure 3-5. Input Clock Timing Charts 



3-11 



Paragraphs 3.60 to 3.63 



SDS 900685C 



September 1965 



sWe = Wes + . . . 

3.60 The Input Timing Chart, figure 3-6, indicates the 
flow of the basic input process. The first WIM instruc- 
tion is shown occurring late to illustrate how the Char- 
acter Register accepts one more character after the W- 
Register is full. 

3.61 The error detector flip-flop may also be set if the 
input character has even parity. 

sWe = W9 W6 W5 W4 Rwp W^ Npw I^ + . . . 

In t his equation, W9 indicates an input process, W6 
W5 W4 indicates that the received character has 
already been precessed into the W-Register when We is 
set. The term Npw is a signal received from the periph- 
eral device to disable parity checking when a parity 
bit is not supplied. Wg and Iwg are End-of- Record and 
Extended Mode signals. These are discussed in para- 
graph 3-131 dealing with Interlace. Rwp is the Parity 
Flip-Flop which is toggled while the character is pre- 
cessing out of the Character Register. During input, 
the operation of Rwp takes place as follows. Initially 
and again betwe en each character precession, Rwp is 
reset by W9 W6 W5 W4. If the parity bit of the input 
character is a one, Rwp is set by W9 W6 W5. 

sRwp = W9W6W5Zwp+. . . 
rRwp = W9W6W5W4 + Wc + . . . 

Since W6 is set at pulse time T8 in the above equations 
Rwp may be set (if Zwp = 1) at the next pulse time, T7. 
At the next TO, W5 is set and the state of Rwp is re- 
versed at T8, three pulse times later. 

sRwp = Wf W5 T8 R^ + . . . 
rRwp = Wf W5 T8 W9 Rwp + . . . 

As a result of this reversal, Rwp is set if the input parity 
bit was a zero and reset if the bit was a one. The parity 
of the 6-, 12- or 24-data bits of the input character is 
now examined. This takes place while the character is 
being precessed into the W-Register. While precession 
occurs, the three bits of each octal group appearing as 
the output of the Character Register are tested by (Wbl 
© Wb2 Wb3). This parity logic term is true when- 
ever there Is an odd number of one's in a three bit 
group. It is used to reverse the state of Rwp for each 
such octal group containing an odd number of ones. 

sRwp = W9 W4 R^ (Wbl Wb2 Wb3) 
(T7- TO) Qwl +. . . 



rRwp = W9 W4 Rwp (Wbl Wb2 © Wb3) 
(T7- TO) Qwl +. . . 

The proper state of Rwp is thereby achieved, establish- 
ing whether the incoming character had a parity error. 
For example, if the following twelve bit character were 
received, 

1 101 101 111 001 

\ 

^ — (parity bit) 

its parity bit would cause Rwp to start off by setting 
then being reversed to the reset state. Of the four 
octal groups, two of them have an odd number of ones. 
This would cause Rwp to change state twice as preces- 
sion took place thus returning to the reset condition. 
With Rwp reset, no parity error would be reported by We. 

3. 62 The number of octal groups that must be checked 
for each character precession and which outputs of the 
Character Register to be monitored for 6-, 12-, and 24- 
bit characters must also be determined. The number of 
octal groups to check is solved by (T7 - TO) Qwl, which 
is true for 2, 4, or 8 pulse times in accordance with the 
character length. Table 3-2 lists the values of signal 
Qwl. The character length may be determined by hard- 
wired logic or by gating of Wxl2 and Wx24 signals 
(depending on the model). Which outputs to monitor is 
solved by using the same gating signals, Wxl2 and Wx24, 
or by hardwiring to select the proper outputs. Whether 
gating or hardwiring is employed depends on the equip- 
ment model number. The variations in models are 
detailed in table 3-2. 

3.63 The characters have now been read into the Char- 
acter Register, precessed into the W-Register, and par- 
ity has been checked. The contents of the W-Register 
must now be transferred to the C-Register In the Central 
Processor Unit (CPU). Each time a WIM (AIM) instruc- 
tion is executed, the contents of the W (A) and C- 
Registers are interchanged. At this time (04 of the WIM 
instruction execution) precession is blocked by W4 and 
recirculation is blocked by Wxx. The condition Wf W9 
is used to signal the computer that the exchange can 
take place. 



Wxx = Rx Pwy + 



(Pwy = 05 In Model 92200) 



Rx indicates that a WIM or MIW Instruction is being 
processed. It Is always false for the C and D channels, 
since no WIM or MIW type instructions exist for those 
channels. 

Wwl =W4C21r (T7- TO) Wxx 



3-12 



September 1965 



SDS 900685C 



Start Signal, 
Eom 



n 



Clock Signal, 
Ecw 



Clock Detector, 
W6 



1_ 



P recess Detector, 
W5 



n n_ 



P recess W, 
W4 



I m [ I ] m [i i n 



Clear Char. Reg., 
W W6 W5 W4 



r 



Set Ch ar. R eg., 
W9 W6 W5 



Char. Counter, 
W8 



¥ 



L 



WIM Interlock, 
Wf 



Interrupt Signal, 



Store W, 
Rx 



n 



Halt Interlock, 
WO 



Time 



Figure 3-6. Input Timing Chart (Two Characters Per Word) 



3-13 



Paragraphs 3.64 to 3.65 



SDS 900685 C 



September 1965 



Table 3-2. Value of Parity Timing Signal Qwl 



TMCC 








Time When {17 - TO) 


Model No. 




Value of Qwl 




Qwl is true 


92200 


Qwl 


= Qrl Qr4* 




17, T6 


92201 


Qwl 


= Qr4* 




17, 16, 15, T4 


92202 
93200/93221 


Qwl 
Qwl 


= 1 (Qwl is deleted)* 




17 through TO 
17, T6 


= Wxl2 Qr4 + Wxl2 Wx24 Qrl 


Qr4 










if Wx 12 and Wx24 are off. 










17 through T4 










if Wxl2 is on. 










17 through TO 










if Wx24 is on. 



'Qwl is replaced by the signal shown. 



Ww2 = W4 C22r {17 - TO) Wxx 

Ww3 = W4 C23r {17 - TO) Wxx 

The terms C21r, C22r, and C23r are logically equiv- 
alent to the outputs of the C-Register, C21, C22, and 
C23, respectively, but are implemented through special 
drivers for this transfer function in order to minimize 
the delay. The three parallel portions of the C-Register 
behave in a manner similar to one another, therefore 
only one is listed below (all three are illustrated in 
figure 3-7). 

sCO = Cr3 (Rx Rnl +. . .) 

rCO = Cr3 (Rx Rn 1 + . . . ) 

sRnl = Rwyl Ts7 + . . . 



-Rnl 



Rwyl Tsr + 



3. 64 The data transfer takes place during one machine 
cycle of the WIM instruction (Rx) and when completed, 
the computer Interlock Flip-Flop, Wf, is set to prepare 
the TMCC to accept the next input word. 

sWf = Rx TO Twy + . . . 

Terminating an input operation can take place in one 
of several ways. The more sophisticated methods are 



discussed in paragraph 3. 131 dealing with the interlace. 
The simplest procedure is to program an EOM instruction 
to disconnect the peripheral unit after a sufficient 
number of WIM instructions have been processed. Other 
methods will now be discussed and illustrated as they 
apply to specific devices. Use will be made of the 
interlock and interrupt signals while considering these 
devices. These features are applicable to other I/O 
units as well. 

3. 65 A photoreader input process (refer to figure 3-8) 
can be terminated by detecting tape gap following a 
block of input data. The tape gap consists of one or 
more tape frames where only the sprocket hole Is 
punched. However, the photoreader must be able to 
initially read through a tape gap or leader without ter- 
minating at every tope frame. This is accomplished by 
the Halt Interlock Flip-Flop, WO, which detects the 
start of a block of data and is used by the peripheral 
device coupler to inhibit sprocket clocks until the first 
(or second) character is sent to the TMCC. Clocks for 
these first characters are derived from the characters 
themselves. The equation for WO is given below, but 
to fully understand its action, the equation for a typical 
photoreader clock signal is also shown. 

sWO = W9 W6 W8 Ecw + . . . 
rWO = Wc + . . . 



3-U 



September 1965 



SDS 900685 C 



C Register 



CPU 
TMCC 









C21 




CO 


Rnl 


























C22 




CI 


Rn2 
































C23 




C2 


Rn3 














































I 


1 














J 






Wwl 




Wrl 


Wnl 






































J 








Ww2 




Wr2 


Wn2 








































i 






L* 


Ww3 




Wr3 


Wn3 








W Register 











Y(B) Channel 
Data Lines 



Figure 3-7. Data Transfer from W Register to C Register 



3-15 






WIM 
Data 



Interrupts 
Full Terminate 



Wwl 



Ww2 



Ww3 



I 



We 



Wnl 



Wn2 



H 



1 



Rwl 



Rw4 



^ 



" Rw2 Rw5 




Precess 



W4 



W6 W5 



Detector 



W7 



W8 



Character Counter 




D 

CO 

>o 
o 
o 
o- 
oo 

Oi 

n 



CO 

-r 

3 

D- 



Figure 3-8. Information Flow Diagram - Phototape 



vO 

o 



September 1965 



SDS 900685C 



Paragraphs 3. 66 to 3. 70 



Ecw = (Zwl + Zw2 + Zw3 + Zw4 + Zw5 
+ Zw6 + Zwp + WO) Sp Re 

In the latter equation, Zwl through Zw6 are the char- 
acter reader signals, Zwp is the parity bit signal, Sp is 
the sprocket hole signal, and Re is a photoreader en- 
able level. The result of this combination is that while 
WO is reset, the clocks are derived from the character 
bits. After setting WO, the term In parentheses is 
always true so Ecw varies with Sp only. When the first 
character is read following leader, a clock is produced 
which sets W6. W6 allows WO to be set. The term 
W8 on the input of WO prevents setting of WO until the 
second character appears (in the four character per word 
mode). Waiting until the second character is desirable 
when reading from magnetic tape so a single noise 
character within a gap does not set WO. It is also 
important during a reverse scan of magnetic tape to 
avoid setting WO on the longitudinal parity character. 

3. 66 After WO has been set to enable the clocks to 
read in data, the End-of-Record Detector, Wg, is used 
to detect the first all -zeros, or gap, character (all 
zeros Including the parity bit). Wg then enables the 
Halt Detector Flip-Flop, Wh. 



sWg = W9 WIO Wll W12 W13 

("Rw 1 Rw2 Rw3 Rw4 Rw5 Rw6 Rwp) W5 



(T7 - TO) (WIO Wl 1 W12 W13 W14) 

rWg = Wc 

sWh = Wg iw^ T8 

The combination, W9 WTo WTf W12 WIS, at the Input 
of Wg decodes the fact that paper tape reader n umbe r 1 
or number 2 is being used for input. The terms (WIO 
WTl W12 W13 WR are redundant and are due to the 
logic mechanization. 

3. 67 After Wg sets, parity errors no longer set the 
Error Detector Flip-Flop, We. 

sWe = W9 W6 W5 W4 Rwp W^ Npw h^ + . . . 

Disabling We avoids parity testing for the next few 
machine cycles. During this time a complete word is 
processed into the W-Reglster if the input did not supply 
sufficient characters to finish the last word. In the 
case where Wh sets but the W-Register Is not yet full, 
W4 is set for successive cycles until the character 
counter reads 00. This process is termed "flushing". 
When W7 W8 read 00, Wf Is reset and a Wc signal is 
generated to disconnect the TMCC. 

sW4 = Wh Wf T8 + . . . 



rW4 = W4 TO + . . . 

sWf = Wc WR + . . . 

rWf = W7 W8W4 (T6 + T5) + . . . 

Wc = Wh Wf (T3 -T0) + . . . 

The clear signal, Wc, disconnects the tape reader and 
clears the character counter, End-of-Record Detector, 
and Halt Interlock. 



rWO = Wc 
rWg = Wc 

The Halt Detector Is then reset at the next T8 pulse 
time. 

rWh = Wh Wf T8 

3. 68 By allowing the character counter to count down 
to 00 before resetting, the final input word is filled-in 
with zero characters. The Phototape Termination Tim- 
ing Charts illustrate the flow of this termination precess. 
Figure 3-9 illustrates the case where the last input word 
does not contain a full complement of characters. 
Figure 3-10 illustrates the timing for the case where the 
last word does have all characters filled before an all 
zeros character is detected. 

3. 69 If the interrupt system Is enabled during the ter- 
mination process, the Wf Wh condition generates an 
interrupt signal to call for a final WIM instruction from 
the computer. 



I2w = (En +(En)) Iwg 



Wh Wf 



The signals En and(En)are programmable and manual 
enable signals for the Interrupt system. The final WIM 
Instruction, as provided by a halt subroutine, stores the 
lost word even though it may not have originally con- 
tained a sufficient number of characters. The final 
WIM instruction may be executed before or after the 
channel Is disconnected. However, additional WIM 
instructions after that cause the computer to lock-up 
because It would be waiting for another input word. 

3. 70 When operating with devices other than punched 
paper tape, the input process Is very similar to that just 
described, although the method used to derive the 
clock signals may vary somewhat from one device to 
another. Also, the gap (End-of-Record) signal, when 
required, is normally supplied by the external device 
rather than developed within the TMCC as is done for 
paper tape. 



3-17 



SDS 900685C 



Sepfember 1965 



Clock Signal, 
Ecw 



m m m m r ?n 



Clock Detector, 
W6 



Precess Detector, 
W5 



Precess W, 
W4 

Cle ar Char, Reg ., 

WvJZWW 



R 



J — L_i — L_r 



n n n n n. 



n Fi Fi K 



n 



Set Ch ar. R eg., 
WW6W5 



Character Counter, 
W7, W8 



n r 



J~L 



r 



r 



WIM Interlock, 
Wf 



Interrupt Signal, 



Store W, 
Rx 

Halt Interlock, 
WO 



n 



n 



y-Wc 



End of Record Detect., 
Wg 



Halt Detect, 
Wh 



Halt Interrupt, 



n 



Time 



4 Charocters/Word 



Figure 3-9. Termination Timing A. Phototape Input 



3-18 



September 1965 



Clock Signal, 
Ecw 



SDS 900685C 

\T ] loT 



Clock Detector, 
W6 



_r 



Precess Detect, 
W5 



n 



Precess W Register, 
W4 



R___RRRR 



Clear Char. Re g . , 



~L 



Ml 



Set Ch ar. R eg., 
W7W6W5 



_rL 



Character Counter, 
W7 W8 



nxL 



WIM Interlock, 
Wf 



Interrupt SigrKil, 



Store W, 
Wxx 



Halt Interlock, 
WO 



n 



1__ 



n 



End of Record Detect, 
Wg 



Halt Detect, 
Wh 



Halt Interrupt, 



Time' 



n 



4 Characters/Word 



Figure 3-10. Termination Timing B - Phototope Input 



3-19 



Paragraphs 3.71 to 3.76 



SDS 900685C 



September 1965 



3.71 An information flow diagram for magnetic tape 
input is illustrated in figure 3-11. The input timing 
for magnetic tape using the two character per word 
mode is illustrated in figure 3-12. When terminating, 
the magnetic tape unit generates a halt signal with a 
time delay triggered by the tape gap and WO. The halt 
detector is then triggered by the delayed signal. 



sWg = Whs (T7 - TO) WTO WTT WT2 W13 W14 

rWg = Wc 

sWh = Wg h;^ T8 

Whs is a halt signal from the peripheral device. In 
this case, it is the delayed signal from the magnetic 
tape unit. The delay allows time for the tape reader 
to check the longitudinal parity character following 
the block of data. Refer to figure 3-11. When a 
longitudinal par ity e rror occurs, the tape reader sends 
an e rror si gnal (Wes) and the Error Detector is set. 
The (Wep signoTTriay also result from a rate error. 



sWe 



Wes + . 



Other devices may also supply error inputs via the 
(Wes) line. Unless inhibited by Npw, character 
parity Is checked by Rwp when precession takes place. 

3. 72 Input termination timing for magnetic tape Is 
illustrated in figure 3-13. The figure illustrates the 
case in which the input furnishes only three characters 
for the last four character word and the remaining 
character is filled with zeros. Also illustrated in 
figure 3-13 are the Halt Interrupt, calling for one more 
WIM instruction, and the final WIM Instruction, itself. 

3. 73 Another type of input operation in which the 
TMCC participates is the scanning of magnetic tape. 
The process is similar to the usual magnetic tape read- 
ing process except that the character counter is pre- 
vented from reaching 00 again after WO Is set. The 
counter flip-flop, W8, is held in the "one" or set state 
by: 

sWB = W7 W WIO Wl 1 Wh + . . . 

In this equation, W9 WIO Wl 1 Indicates a scan process 
has been programmed. A forward scan can be Initiated 
by an EOM 0363X instruction. It may also be pro- 
grammed by modifying a read process. While magnetic 
tape is being read, if an EOM14000 instruction isgiven, 
the flip-flop, WIO, is set to convert directly from 
reading to scanning of the same tape. 

sWlO = (loc C12Cl7CT9C20Cri Cr2C23) 
W9WT0 + . . . 



With W8 of the character counter held in a set state,the 
Buffer Full Signal, W9 Wf, and the normal interrupt 
signals are prevented by keeping Wf from being reset. 

rWf = W7 W8 W4 (T6 + T5) + . . . 

Ilw = Wf WOWh(En +(^)h/b^U^ + . . . 

I2w = (En +(3^) Wi Wh Wf +. . . 

This allows each Input character to be precessed Into 
the W-Reglster without requiring WIM instructions to 
set Wf. However, when the end of a data block Is 
reached, Wf Is reset by a gap signal from the tape 
reader. 

rWf = W9 WIO Wl 1 WO Mtgw"W7 (T6 + T5) Wh 

And an interrupt is generated. 

Ilw = Wf WOWh (. . .) 

This interrupt calls on the computer to enter a sub- 
routine to execute a WIM instruction. The WIM instruc- 
tion stores the last four characters read from the tape 
and which were precessed into the W-Register. The 
WIM instruction sets W7 and Wf In preparation for 
scanning another record. 

sW7 = Wxx Wnl (T7 - TO) W4 + . . . 

sWf = Tx TO Pwy + . . . (Pwy = 05 for 92200) 

3. 74 Based on a block counting program or an examina- 
tion of the last four characters, the computer may reset 
WO with another EOM0363X instruction, to cause the 
scan process to continue without a pause through the 
gap and into the next record. If^O Is not reset, the 
scan process is terminated by a (Whs) signal from the 
tape unit in a manner similar to that previously des- 
cribed for normal input termination. When the scan 
process does terminate, a halt Interrupt signal is 
generated. 



I2w = (En +(^2)) Iwg 



Wh Wf 



3. 75 During the scan process the character parity is 
checked by the Rwp flip-flop and the longitudinal parity 
is checked by the tape unit (only If WO is reset after 
the longitudinal parity character). Any error during the 
scan process sets the Error Detector flip-flop. We. 

3.76 A reverse scan of magnetic tape is started by an 
EOM 0563X Instruction. The process is similar to a 
forward scan, except that the WIM instruction at the 
end of a data block scan stores the first four characters 
of the block In reverse order. The longitudinal parity 
is not properly checked, with the result that We may be 
erroneously set. 



3-20 



"WIM" 



Character 
Counter 




Precess 



Clock Detector 



W5 



W6 



Not Part of TMCC 



Gap 
Detector 



Time 
Delay 



Whs 




Wh 



Halt 



I 

Enable Halt 



Interrupt 
Computer 




Error 



Parity 
(even) 



Lateral Parity (odd) 



(D 

-a 

-+ 

0) 

3 

cr 

o 



o 



D 

CO 

S3 
O 
O 
O^ 
00 
Oi 

O 






Figure 3-11. Information Flow Diagram - Magnetic Tape 



SDS 900685C 



September 1965 



Start Signal, 
Eom 



Jl 



Clock Signal, 
Ecw 



R_R_n__Fl_Fl_J^ 



Clock Detect, 
W6 



Precess Detect, 

W5 



Jl n n__n__n__n. 



Precess W 

Register, 
W4 

Clear Char. 
Register, 

Set Char, 
Register, 

W\N6W 

Character 
Counter, 

vys 

WIM Interlock, 
Wf 



J 



J 



n' rp n' n^ n' n ^ 



rL_n_rL_n_n_ii 



uii 



_r 



Holt Interrupt, 



Store W, 
Wxx 

Halt 

Interlock, 

WO 

Gap Signal, 
(Mtgw) 



J 



End of Record 
Detect, 

Wg 

Halt Signal, 

Whs 



Jl 



Jl 



Jl 



Jl 



Wc 



-Time Delay-^-JI 



Halt Detector, 
Wh 



Time 



2 Characters/Word 



Figure 3-12. Input Timing - Magnetic Tope 



3-22 



Sepfember 1965 



SDS 900685C 



Clock Signal, 
Ecw 



_Pl 



Clock Detector, 
W6 



_n 



Precess Detector, 
W5 



Jl 



Precess W Register, r|3 

W4 IL. 



H 



Clear Char . Reg., — I r 

WWmW I 1 



¥ 



Set Char, Reg., r~| 

W9W6W5 —I L 



Char. Counter, 
W7, W8 



r 



r 



WIM Interlock, 
Wf 



r 



Halt Interrupt, 

Store W, 
Wxx 

Halt Interlock, 
WO 



Jl 



Wc 



\ 



H 



Gap Signal, 
(Mtgw) 



End of Record Detect, 
Wg 



Halt Signal, 
Whs 



n 



— Time Delays — ^A I 



Halt Detector, 
Wh 



Time 



n 



4 Characters/Word 



Figure 3-13. Input Termination Timing - Magnetic Tape 



3-23 



Paragraphs 3. 71 \o 3. 82 



SDS 900685C 



September 1965 



3.77 In the Magnetic Tape Forward Scan Timing Chart 
(refer to figure 3-14) and Reverse Scon Timing Chart 
(refer to figure 3-15), when the first interrupt Informs 
the computer that the gap has been reached, a WIM 
instruction stores the last four characters read. An- 
other EOM instruction then resets WO to continue the 
scan process through the next block 

rWO = (loc C12CT7CT9C20C2T C23) 
W9T0 + . . . 

Dotted lines indicate the reaction if the process were 
terminated. In case of termination, WO allows the Tape 
Reader Holt Signal, Whs, to come through. 



sWg = Whs T7-T0W10 Wll W12WT3 WTT+. . . 
sWh = Wg i^ T8 + . . . 

Whs sets Wg, which in turn sets Wh. After Wh Is set, 
the Character Counter Fllp-Flop, W8, is no longer 
held on and a count-down begins. 

sW8 = W7 W9 WIO Wl 1 Wh + . . . 
rW8 = W8W4T0+WC 

This process Is very similar to that described for termin- 
ating a normal read operation and Wf is reset as soon as 
the count-down reaches a point where W7 and W8 are 
both reset. 

rWf = W7 W8 W4 (T6 + T5) 

A clear signal, Wc, then resets the TMCC after the four 
precessions. 

Wc = Wh WT (T3 - TO) + . . . 

3.78 OUTPUT PROCESS (W9 true) 

3. 79 When an EOMOXXXX or EOM4XXXX Instruction 
is executed to start on output process, an interlock 
signal, Wf (WO + . . . ) is Immediately sent to the com- 
puter. And, if enabled, an interrupt calls for the com- 
puter to load the W-Reglster with the first output word. 
If the interrupt is disabled, the program should supply 
the MIW loading instruction before it is needed (I.e. 
before a clock signal Is received from the peripheral 
unit). 

rWf - Ws C18 + . . . (denotes W register Is empty) 
sWO = Ws C18 W9 + . . . 

(iiw)= Wf WO wh"(En+(;^) ^rB^i;^ + . . . 



3.80 Each MIW instruction, or time-share operation 
If interlace is being used (Wxx), exchanges the W- 
Register and the C-Register. Refer to figure 3-16. 

Wwl = W4 C21r (T7 - TO) Wxx + . . . 
Ww2 = W4 C22r (T7 - TO) Wxx + . . . 



Ww3 

sCO 

rCO 

sRnl 
rRnl 



W? C23r Wxx + . . . 

Cr3 |TTsr + Rx) Rnl +. . T] 

Cr3 Rjsr + Rx) Rnl + . . 7| 
similarly for CI and C2 

Rwyl TTr + Rrl Tsr 



Rwyl Tsr + Rrl Tsr 
similarly for Rn2 and Rn3 



Wxx = Rx Pwy + 



(Pwy = 05 for 92200, 
Rx Is always false for 
TMCC-C) 



3.81 As with the Input process, Wxx blocks recircu- 
lation and with W4 false precession is blocked at this 
time also. When precession does take place, as enabled 
by W4, an output character is shifted from the W- 
Register to the Character Register and Rwp is used to 
generate an odd parity bit. During the output operation 
the parity flip-flop operates in a manner similar to Its 
action during Input. 

3.82 Rwp is initially set by Wf W5 T8. Then, when 
precession occurs, each octal group coming from the 
W-Register is examined for an odd or even number of 
ones. This checking Is done by (Wnl ©Wn2©Wn3) 
which is true whenever there are one or three ones in 
Wnl, Wn2, and Wn3. Each time this term is true dur- 
ing the checking period, Rwp is switched to its opposite 
state. 



sRwp 



rRwp 



W9 W4 R^ W^ (Wnl © Wn2 
© Wn3) Qw2 (T7 -TO) 
+ Wf W5 T8 R;;^ + . . . 



W9 W4 Rwp Wxx (Wn 1 © Wn2 

© Wn3) Qw2 (T7 - TO) + . . . 
Qw2 is a term similar to the Qwl used during the Input 
process. Qw2 with (T7 - TO) establishes the pulse times 
during which the parity checking Is done. It may either 
be hardwired or function with the gating signals Wxl2 
and Wx24 depending on the equipment model number. 
Refer to table 3-3. 



3-24 



September 1965 



SDS 900685C 



Start Signal, 
Eom 



Jl 



Jl 



Clock Signal, 

Ecw 



RJ^U^UOUl 



Clock Detector, 
W6 



nnnnon 



Precess Detector, 
W5 



JULiUULJl 



Precess W Register, 

W4 



J TLUliJliJliJLni 



JUSH 



Character Counter, 
W7, W8 



I i 



I I I 

LJ L 



WIM Interlock, 

Wf 



Interrupt Signal, 



Halt Interlock, 
WO 



Reset by EOM 0363X 



Gap Signal, 
(Mtgw) 



Halt Signal, 
Whs 



_r 



— Time Deiay- 



I 1 

1 I 

-I u 



End of Record Detect, 
Wg 



I 1 

I I 

I I 



Halt Detect, 

Wh 



Halt Interrupt, 
Cl2w) 



Store W, 
Wxx 



Jl 



Time. 



Figure 3-14. Forward Scan Timing Chart - Magnetic Tape 



3-25 



SDS 900685C 



September 1965 



Start Signal, 
Eom 

Clock Signal, 
Ecw 

Clock Detect, 
W6 

Precess Detect, 
W5 

Precess W, 
W4 



Jl 



ni:£ n_fi_Fi_R_fi_ni 



R 



ruinnn_R 



JUUUUUl 



I nup. 2 ni n4 ns n2 n 



Jl 



nnnn 
I II II II I 
I II 11 11 I 



Char. Counter, 
W7, W8 



_r 



_r 



m: 



inm 



WIM Interlock, 
Wf 



_r 



Interrupt Signal 

(® 

Holt Interlock, 
WO 



Gap Signal, 
(Mtgw) 

Halt Signal, 
Whs 



_r 



i_ 



Time Delay 



I T 

•i i 
J L 



End of Record Detect, 
Wg 

Halt Detect, 
Wh 



r— ~n 
I I 

J L 



r 1 

1 L 



Halt Interrupt, 
12^ 



Store W, 
Wxx 



Time 



n 
II 

■X4. 



hftiH 



Figure 3-15. Reverse Scan Timing Chart - Magnetic Tape 



3-26 



"MIW" 



Data from C Reg. 






o 

3 



o* 



CO 







(Tiw) 



Interrupt 



y 

Computer 



Pre cess 



Ecw 



Clock 
Generation 



T 1 



V^ 



W Register 



Char. Register 




Data to Output Device 



Figure 3-16. Output Information Flow Diagram 



Rwp 



W4 



00 

oo 
S3 

o 

O 

o> 

00 
Ol 



Paragraphs 3. 83 to 3. 86 



SDS 900685C 



September 1965 



Table 3-3. Value of Qw2 Parity Timing Signal 



TMCC 






Pulse Times When {17 - TO) 


Model No 




Value of Qw2 


Qw2 is True 


92200 


Qw2 


= Qr2 J^ * 


TO, Tl 


92201 


Qw2 


= Qr4 * 


T3 through TO 


92202 
93200/93221 


Qw2 
Qw2 


= 1 (Qw2 is deleted) 


T7 through TO 

TO and Tl, if Wx 12 and Wx24 


= Wxl2 Qr4 + Wxl2 Wx24 Qr2 Qr4 








are both off. 








T3 through TO, If Wxl2 is on 








T7 through TO, if Wx24 is on 



^Qw2 is replaced by the signal shown above for Models 92200/201/202. 



3. 83 As an example of output parity generation, con- 
sider the twelve-bit character 111 010 101 001. Rwp 
would start in the set condition and would then switch 
states three times, once for each of the octals contain- 
ing an odd number of ones. Thus, Rwp would conclude 
its switching operation in the reset state to produce a 
zero parity bit for an odd parity output character. 

3.84 The basic flow of the output process is illustrated 
in figure 3-17. The execution of the second MIW in- 
struction is shown occurring late to depict how the 
Character Register is cleared when a new output char- 
acter is not available. If another output character is 
still not available when the next clock signal, Ecw 
appears, the error detector (We) is set as is done during 
an input process. 

sWe = WO W6 W5 Ecw T8 + . . . 

rWe = Wc Wh 

3. 85 In the output processes (as in the input processes), 
the Character Register is initially cleared by W9 W6 
W5 W4. The first output character to be read is, there- 
fore, all zeros. This is appropriate for a leader or gap 
in paper tape punching. However, for some forms of 
output, such as typing or leaderless punching, and 
magnetic tape writing (the tape unit automatically gen- 
erates leader), the first output character should be in 
the Character Register before the first clock signal. For 
this type of output, an EOM2XXXX instruction with a 
"one" bit in CI 3 is used. This code bit is used to set 
W5 which then causes the first loading of the W- 
Reglster to be followed directly by precession of the 
first output character into the Character Register. In 
this case the sequence of operations again starts by 



resetting Wf and setting WO with the resulting interrupt 
Ilw. However, now W5 is also set by the Ws signal. 
Then, as usual, when the MIW instruction is executed 
and Rx goes true, Wf is set. With W5 on, W4 can be 
set at pulse time T8 just after the data transfer takes 
place. Figure 3-18, Output Timing Chart 2, illustrates 
the flow of this process. 



sWf = Rx TO Pwy + 
rWf = Ws C18 + . . 



(Pwy = 05 for 92200) 



sW5 = WsC13 C18 WIO Wll W12W13 W14 + .. 
rW5 = W4 TO + Wc 

sW4 = WrWf T8Wi+. . . 
rW4 = W4 TO + . . . 

3.86 To terminate an output process, the MIW instruc- 
tion which loads the last output word Into the W- 
Register is followed by an EOM14000 instruction to 
reset WO. An EOM14100 Instruction is used to termin- 
ate the Y channel. 



rWO = (loc C12C17C19C20C21 C22 C23) 

W9 TO + . . . 
loc = loci CT ErQr3 
loci = Eom CTO Cn 

Er is a signal inhibiting Eom and loc when the Interlace 
Prepare flip-flop (to be discussed later) has been set. 
The CI bit, which appears on loc, indicates a W or 
Y channel instruction. CI is used with the C and D 
channels. 



3-28 



September 1965 

Start Signal, 
Eom 

Clock Signal, 
Ecw 

Clock Detect, 


n 


SDS 900685C 






r 


T\ rr 


2 


rr rr 










W6 






Precess Detect, 


-^ 


r 






W5 




n 



Precess W, 
W4 



I^ R 



i^l Fl HL 



r Char. Req. 1 L 



Cle ar Char. Reg 
W^W6W5 W? 



Output Code, 
W9 



Char, Counter, 
W8 



1_ 



MIW Interlock, 
Wf 



Interrupt Signal 

(nw) 



Load W, 
Wxx 



n 



Halt Interlock, 
WO 



~ir 



Time 



2 Char./Word starting with Gap or Leader 
Figure 3-17. Output Timing Chart 1 



3-29 



SDS 900685C 



September 1965 



Start Signal, 
Eom 



_rL 



Clock Signal, 
Ecw 



Clock Detect, 
W6 



Precess Detect, 
W5 



n 



n Ti 



Precess W Reg., 
W4 



ji n 1^^ n f^i R 



Clear Char. Reg., 
W9 W6 W5 W? 



Output Code, 
W9 



Char. Counter, 
W8 



MIW Interlock, 
Wf 



_[l 



Interrupt Signal, 
(Ilw) 



Load W Register, 
Wxx 



n 



n 



Halt Interlock, 
WO 



Time 



2 Char./Word Starting with Leaderless Punching or Typing 
Figure 3-18. Output Timing Chart 2 



3-30 



September 1965 



SDS 900685C 



Paragraphs 3. 87 to 3. 93 



3.87 Resetting of WO results in the following: Further 
normal interrupt signals are blocked. 

Iwl = Wf wowiTC . .) 

Further late-load error signals are blocked. 

sWe = WO W6 W5 Ecw T8 + . . . 

The WIM/MIW Interlock Signal Wf WO is blocked. As 
a result of inhibiting the interlock and interrupt signals, 
no further MIW instructions are processed and, there- 
fore, Wf is not set again after the last character is pre- 
cessed into the Character Register. 

sWf = Rx TO Pwy + . . . (Pwy = 05 for 92200) 
rWf = W7 W8 W4 (T6 + T5) + . . . 

With Wf reset, W4 is prevented from setting after the 
last output character is precessed. This results in the 
state, WO W4 W5 W6, following the precession. 

sW4 = W5 Wf T8 W^ + . . . 
rW4 = W4 TO + W4 T8 



Then Wh is reset, as well as the rest of the TMCC. 



sW6 = W5 EcwTSWlOWIl W12 W13 W14+, 
rW6 = W5 WO + Wc 



sW5 = W5 W6 Ecw TO + . . . 
sW5 = W4 TO + Wc 

The state, WO W5 W6, is used to s et th e halt detector 
unless magnetic tape is being used (Wll indicates not 
magnetic tape). 



sWh = W9 Wl 1 WO W5 W6 (Iwg + 



) T8 + . . 



Wh en the output is to a magnetic tape unit, the state 
WO W5 W6 is sent to that unit and after a suitable 
delay (while the tape unit generates a longitudinal 
parity character) a Whs halt signal is received back to 
set Wh. 



5Wh 



Whs Wll T8 + 



Regardless of the method of setting Wh to terminate an 
output process, the Halt Interrupt Signal, Q2w) , is 
generated in the cycle in which Wh is set. 

I2w = (En +(1n^) W^ Wh Wf + . . . 

Ana a clear signal is generated. 

Wc = Wh WT (T3 - TO) + . . . 



rWh 



Wh Wf T8 + Wc (T6 + T5) 



The Output Termination Timing Charts indicate the flow 
of these output termination processes for devices other 
than magnetic tape (refer to figure 3-19) and for 
magnetic tape (refer to figure 3-20). 

3.88 Two additional timing charts are included to 
illustrate the output sequences for specific devices. The 
flow of the complete output process for a paper tape 
punch operation is illustrated in figure 3-21. The 
EOM0XX4X start Instruction causes tope leader to be 
punched while the device inhibits clock signals. An 
all zeros character is also punched for the first output 
clock signal. After the last output character is proc- 
essed, a halt interrupt signal is generated. 

3. 89 The flow of an output process using magnetic tape 
is illustrated in figure 3-22. A time delay triggered by 
the EOM02X5X start instruction causes a tape gap to be 
recorded first while inhibiting output clock signals. 
WO W5 W6 signals the tape unit to count three clocks 
and record the longitudinal parity character, and 
triggers a second time delay to cause a gap to be re- 
corded after the data block. When the gap is completed, 
the tape unit generates a (WRp signal to halt the out- 
put process. Each character parity and the longitudinal 
parity of the characters reproduced at the read head are 
checked by the tape unit and an error signal, (Wep , 
Is generated to set We for any detected errors. Several 
other error conditions are also checked, such as slew, 
amplitude, and rate error. 

sWe = Wes + . . . 

3. 90 A special case of a magnetic tape output opera- 
tion is the erase function. The tape erase is started by 
an EOM01X7X instruction. The erase procedure is 
performed In the same way as any other output to mag- 
netic tape but the WIO bit is used by the tape unit to 
cause writing of all zero data regardless of what may be 
appearing at the character register outputs. 

3.91 SYS GATE 

3.92 The system control EOM instruction has little 
effect on the TMCC. It Is included here only because 
the Sys signal Is gated through the TMCC channel. 

3.93 When an EOM instruction, containing "ones" in 
bits 10 and 11, is executed, an Sys signal is generated 
as an output from the TMCC on the Sys line. 

Sys = Eom CIO Cll C9 



3-31 



SDS 900685C 



September 1965 



Clock Signal, 
Ecw 



"I 



Clock Detect, 
W6 



Precess Detect, 
W5 



_n R 



n 



Precess W Register, I ^ I I ^L 

W4 



n Fi 



Clear C har. Register, 
W^ W6 W5 W3 

Output Code, 
W9 



Char. Counter, 
W8 



MiW Interlock, 
Wf 



Interrupt Signal, 



Load W Register, 
Wxx 

Halt Interlock, 
WO 



n 



Reset by EOM 14000 



Halt Interrupt, 



Halt Detector, 
Wh 



n 



n 



Clear, 
Wc 



Time 



2 Characters/Word 



Figure 3-19. Output Termination Timing (Except Magnetic Tape) 



3-32 



September 1965 



SDS 900685C 



Clock Signal, l 



Ecw 



Clock Detect 
W6 



~LJ — i_r 



Precess Detect, T 

W5 — * 



n 



Precess W Register, [71 fTI 



W4 



Clea r Char. Reg., 
W9 W6W5 W4 



Output Code, 
W9 



Char. Counter, T 

W8 — ' 



MIW Interlock, 
Wf 



I nter rupt Signal, 

(nw) 



Load W Register, | I 

Wxx — I L 



Halt Interlock, 
WO 



EOM 14000 



Halt Interrupt, 



n 



Halt Signal, 
Whs 



WO W6 W5 



Time Delay 



Halt Detector, 
Wh 



Time 



V 



Wc 



2 Characters/Word 



Figure 3-20. Output Termination Timing - Magnetic Tape 



3-33 



SDS 900685C 



September 1965 



Start Signal, 
Eom 



_Jin 



Time Delay 



^ 



Clock Source, 
Clock 



Clock Signal, 
Ecw 



TJiJiJTJ|iJTJi_rLrLrL_ri_rLJ 

I 

ki n m n m m m 



Clock Detect, 
W6 



rLTLrLrLrLTLR 



Precess Detect, 

W5 



JL_ii_n_n_n_n_Ji 



Precess W Reg., 

W4 



JLJlUlLJliJLJk 



Clear Char. Reg., 
W9W6W5W4 



Output Code, 

W9 



Char. Counter, 

W8 



MIW Interlock, 

Wf 



u u 



Interrupt Signal, 
(Hw) 



Load W Register, 
Wxx 



Jl 



J1 TL 



Jl 



n 



Halt Interlock, 
WO 



Halt Detect, 

Wh 



Halt Interrupt, 
1^ 



EOM 14000 



Figure 3-21. Output Timing Chart - Punch 



Jl 



Time 1^- 2 Characters/Word 



^ 



Wc 



3-34 



September 1965 



SDS 900685C 



Start Signal, 
Eom 



Clock Signal, 
Ecw 

Clock Detect, 
W6 



jm 



Time 
Delay 



RJlJLilJiIL[]_[]_[lLL 



Finn 



Time I 
Delay*^ 



Precess Detect, 
W5 



Precess W Register, 
W4 

Clear Char, Reg,, 
W9W6W5 W4 



1 



JULOJI 
JlLfkJM^ 



Output Code, 
W9 



J 



Character Counter, 
W8 



J 



MIW Interlock, 
Wf 



Interrupt Signal, 
Halt Interrupt, 



Load W Register, 
Wxx 



u 



_Jl 



U 

n 



R 



R 



Halt Interlock, 
WO 



Halt Signal, 
Whs 



Halt Detector, 
Wh 



J 



Time 



EOM 14000 



WO W6W5-w-^Time Delay 



m 



ji 



2 Characters/Word 



V_ 



Wc 



Figure 3-22. Output Timing Chart - Magnetic Tape 



3-35 



Paragraphs 3.94 to 3. 103 



SDS 900685C 



September 1965 



(g) = Sys (T5 - Tl) Tsr Pwy 
(delete Pwy for 92200 and 92210) 

The (^yw signal may be used in conjuncfion with fhe 
C-Regisl-er output lines Q^O) through (C24) to select 
and control special system devices. One OyO line 
is provided on each TMCC W (A) channel or each 
W(A) + Y(B) channel pair. One more (jys) line is 
provided on the C or C + D channels (for a maximum 
of two lines). 

3.94 SKIP GATE 

3.95 The Skip Gate, Skr, and its associated line 
driver, /Skrz/, provide interrogation response signals 
for use with SK5 instructions. 

The equation for the line driver is: 

Al^ = SlTr (ClO Cll Ssc) 



(Cf C9 CIO Cll Sio) . . .* 

*Cl becomes CI for TMCC-C and TMCC-D 

This signal is inverted in the CPU and sampled during 
execution of an SKS instruction to determine if a 
response has been received. At times other than when 
being tested, the signal is changing levels and has no 
meaning. The inverse of /Skrz/ is: 

Skrz = Skr + CIO Cll Sec 

+ Cl C9 CTO Cll Sio + . . . 

3. 96 The dashed lines indicate that other response 
signals may be connected to satisfy special system re- 
quirements. Sio is a response from the addressed 
peripheral I/O unit. The addressing is performed using 
SKS instruction bits 18 through 23 and the same address 
codes as assigned for EOM instructions. The output lines 
C^O]!)through (C2^ provide the necessary addressing 
and control connections to the peripheral units. As 
seen above, Sio is used in conjunction with Cl C9 CIO 
Cll, Bits 1 and 9 (along with bit 17 decoded by the 
peripheral device) select one channel out of four TMCC 
and four DACC channels. Bits 10 and 11 determine the 
type of the SKS instruction. 

3. 97 Ssc is an interrogation response from external system 
equipment. This type of interrogation is selected by on 
SKS instruction with "ones" in bits 10 and 11. The con- 
trol and address bits may be assigned as required. Again 
theQCO)- (C24) lines provide the necessary connections. 

3. 98 The remaining term in Skrz is Skr, the output of 
the Skip-Gate in the TMCC. The use of Skr is similar 



to that of Sio just described except the SKS instruction 
address bits (19-23) are "zeros". This causes the instruc- 
tion to address the I/O channel itself rather than 
peripheral devices. 

Skr = CT CT7C9CT0CllCT9C20C2TC22C23C15Wsc 
+ a CT7 C9 CfoC 1 1 CT9 C2b C2l C22 C23 C 1 2 

wTo wTi wT2 WT3 wT4 

+ cl CT7 C9 ClO C 1 1 CT9 C20 C21 C22 C23 C 1 3 Iwf 
+ CI 07 C9 CTo C 1 1 CT9 C20 C2T C22 C23 C 1 4 Wi 

3.99 In these equations, bits 1, 9, and 17 select one 
of eight channels (TMCCs and DACCs). Bits 10 and 11 
determine the type of SKS instruction. "Zeros" in bits 19 
through 23 address the channel rather than a peripheral 
unit. Bits 12, 13, 14, and 15 select the particular test 
function. A "one" in bit 15 tests the Signal-Complete 
flip-flop. Similarly, o "one" in bits 12, 13, or 14 
tests the Unit Address Register, the Interlace Address 
Register, or the Error Flip-Flop, respectively. 

3. 100 Two additional TMCC channel tests, similar to 
two of those just described, are provided by the Skr 
gate. These also test the Unit Address Register and the 
Error Flip-Flop but with a different type of SKS instruc- 
tion. This is done to provide program compatibility 
with the SDS 910/920 Computers. 



Skr = ClOCll C14 WIO Wll W12 W13 W14C1 
+ C10 CTl C20 We CT + . . . 

3. 101 The equations shown in this discussion are speci- 
fically applicable to the W(A) channel TMCC. To 
select the other channels Cl must replace Cl for chan- 
nels C and D. To distinguish between W and Y or 
between C and D, C17 is switched (except in the lost 
two equations where C14 and C20 are used for W and 
are changed to C13 and C19 for the Y channel). 

3. 102 INTERLACE, COMPATIBLE MODE (Time Share) 

3. 103 The Interlace register is enabled by a "one" in 
bit position 9 of either BUC or IOC type of EOM in- 
struction. These produce Buc or loc signals which are 
derived from EOMOXXXX and EOMIXXXX instructions, 
respectively. Therefore, the interlace register can be 
enabled by the some instruction that sets up the other 
TMCC registers, (i. e., by Buc), or it can be enabled 
without disturbing the rest of the TMCC, (i.e., by loc). 
Either of the EOM instructions clears the entire inter- 
lace register then sets the Enable Flip-Flop, Ew. 

Interlace Clear: Iwc = Eom C9 000 07 (T3 - TO) 
O Becomes O for TMCC-C 



3-36 



September 1965 



SDS 900685C 



Paragraphs 3. 104 to 3. 107 



Interlace Prepare: sEw = Iwc Ew (T3 - TO) 
rEw = Wc TO + . . . 

3. 104 For a Buc instruction, Ew Is first reset by Wcat 
pulse time TO then reset during the next pulse time. 
The above equation for Iwc is specifically related to 
the W(A) channel. To select any of the other three 
TMCC channels, different combinations of CI and C17 
are used. 



Channel 


CI 


C17 


W(A) 








Y(B) 





1 


C 


1 





D 


1 


1 



With Ew set, the computer can preset the interlace reg- 
ister with the starting memory address and the word 
count for an I/O process. Refer to figure 3-23. The 
loading of these counts is accomplished by a POT in- 
struction. The POT instruction, which produces a Potl 
signal, is ordinarily used to parallel transfer data from 
the C-Register to an external device. Potl, then, 
produces the loading signal, 

Iwp = Potl (T6 + T5) Ew 

then resets Ew, 

rEw = Pot 1 (T3 - TO) Ew + . . . 

3. 105 The Word Counter, WcO through Wcl4, is 
initially cleared by Iwc which sets all stages of the 
counter. The one's complement of the count is then 
produced by resetting the counter flip-flops for corre- 
sponding "ones" in the C-Register during Iwp. Actu- 
ally, this applies to only the ten least significant bits 
of the counter. If a word count greater than 1023 is 
needed, the five most significant bits of the counter 
must be preset by a second EOM instruction. This in- 
struction must be executed after the Interlace is enabled 
and before the POT instruction is executed. An loc 
instruction, without bit 9, is given for this purpose and 
it generates an Iwe load signal. 

Iwe = loci (T6 + T5) Ew 

Iwe then resets the most significant bits of the Word 
Counter to complete the storage of the one's complement 
count. 



sWcM = Iwc + 



rWcl4 

1 


= Iwp C9 + . 

1 


1 

sWc5 


1 

1 

= Iwc + . . . 


rWc5 


= Iwp CO + . 


sWc4 


= Iwc + . . 


rWc4 
1 


= Iwe C23 + 
1 


1 

sWcO 


1 
= Iwc + . . 


rWcO 


= IweC19 + 



3. 106 Using the one's complement, the Word Counter 
can count up rather than down and produce a termina- 
tion signal when it contains "ones" In all of its stages. 
The counting is performed by triggering each stage of 
the counter on the falling edge of a previous stage. For 
example: 



sWcl3 = Ew Wcl3 WcMJw 

rWcl3 = E^Wcl3 Wcl4 E^ 

where the underlined term represents the clock or trig- 
gering level. This method of counting conserves gating 
but produces a propagation delay through the counter. Th is 
delay is minimized too satisfactory level with some increase 
in the number of gates by arranging the fifteen counter 
stages into five octal groups. The first stage of each 
group is connected to only the last stage of the previous 
group. An example of one octal group is: 



sWclO 


= Ec WclOWcll Ew 


rWclO 


= E7 WclOWcll E^ 


sWc9 


= EwWc9 WclOWcll Ew 


rWc9 


= EwWc9 WclOWcll Ew 


sWc8 


= Ew Wc8 Wc9 Wc 10 Wc 1 ] Ew 


rWc8 


- E^ Wc8 Wc9 WclOWcll E^ 



Here it is seen that for this octal group, a common clock 
term Wc 1 1 Ew is used for all three stages. 

3. 107 This reduces the propagation delay for each 
group to the delay that would be expected for a single 
flip-flop. The delay for the entire fifteen stage counter 
is therefore equivalent to that of five flip-flop stages. 
The double appearance of Ew is due to the clocking 
arrangement and the flip-flop module layout. During 
the loading operations, Ew issettoallowthe clock pulses 
to appear as the Gc4 clock for use by the flip-flop. 
After Ew Is reset and the counting is to take place, 
Gc4 is held off while Ew Wcl4 performs the triggering. 
Refer to figure 3-24. 



3-37 



CO 

I 

CO 
00 



a 



Interlace Buffer 



Word 
Counter 




Count = 



Address 
Counter 



Time- 
Share 
Address 
Lines 



\zy 



Tsm 



Ew 



POT 



EOM 



Computer 



WO 


Wn 



r 



^ 







l-^ 



-I 



C Register 



W Register 



Char. Reg. 



Y 

I/O Unit 



CO 

u> 

o 
o 
o 
o- 

00 

o 



CO 

n 

-<■ 
(t 

3 

n 



Figure 3-23. Information Flow - Interlace Operation 



vO 

o>- 



September 1965 



SDS 900685C 



Paragraphs 3. 108 to 3. 112 



Clock 
Pulses 




O 



Gc4 



Ew Iw 



D=^ 



D» 



n 



i> 



\> 



(Wcl3) 



Iwc" 



sWcl3 



Wcia 



-WclS 



Ew Wcl4 



Figure 3-24, Interlace Word Counter - Typical Clock Input 



3. 108 The Address Counter is set up in much the same 
way as the Word Counter. Again the counter counts 
up, but in this case the one's complement is not used. 
With the Address Counter, the actual address of the 
first memory location to be used is placed in the reg- 
ister. As with the Word Counter, Iwc clears the 
counter then Iwp or Iwe sets up each stage with data 
from the C-Register. For some stages of the counter, 
the flip-flops are reset by Iwc then set with the data. 
For other stages, the flip-flops are set by Iwc then re- 
set with the complement of the data. Either way, the 
same thing is accomplished. It was a matter of con- 
venience in wiring for one method or the other to have 
been used. 

3. 109 The counting of the Address Counter is handled 
in the same way as the Word Counter. The least signi- 
ficant stages of both counters are triggered by Iwa Ew . 



Iwa 



Rxw Tsr 



Rwx is the Time Share Select Flip-Flop and is covered 
in detail In paragraph 3. 113. Tsm is a signal from the 
CPU indicating that counter information for each word 
has been received by the CPU. 

3.110 In the Instruction sequence, EOM, EOM, POT, 
used to set up and start the interlace operation, the 
second EOM may be omitted if the most significant bits 
of the Word and Address Counters are "zeros". Refer 
to figure 3-25 for the relationship between the instruc- 



tion bits stored In the C-Register and their respective 
positions in the counters. 

3. 1 1 1 The POT instruction which resets the Interlace 
Prepare Flip-Flop, Ew, also sets the Interlace Active 
Flip-Flop, Iw. 

slw = Pot 1 (T3 - TO) Ew Iw 

Ew furnishes the ready signal required for the POT in- 
struction. Both the Ew and Iw flip-flops Inhibit W- 
channel interrupts. 



Ilw = Wf WOWh (En +Qn» 
Iw Ew Iwg 

3. 1 12 Refer to figure 3-26 for the timing for the inter- 
lace loading process. The Interlace Active Flip-Flop, 
Iw, allows the buffer to issue a time share request 
(Trqw) to the CPU whenever the channel needs access 
to memory. 

Trqw = Wf WO Wh Iw Wf 

Trqw is combined with similar signals from the other chan- 
nels to produce a common request term for all TMCC's. 



Trqx = Trq(c) + Trq(d) 
Trq = Trqx + Trqw + Trqy 



3-39 



Paragraphs 3. 1 13 to 3. 1 16 



SDS 900685C 



Sepf-ember 1965 



Word 
Counter 

C Register 





2nd 


EOM 














POT 












WcO 


Wcl 


Wc2 


Wc3 


Wc4 


Wc5 


Wc6 


Wc7 


Wc8 


Wc9 


WclO 


Well 


Wcl2 


Wcl3 


Wcl4 


C19 


C20 


C21 


C22 


C23 


CO 


CI 


C2 


C3 


C4 


C5 


C6 


C7 


C8 


C9 



J 



r 



Address 
Counter 

C Register 



WaO 


Wal 


Wa2 


Wa3 


Wa4 


Wa5 


Wa6 


Wa7 


WaS 


Wa9 


WalO 


Wall 


Wal2 


Wal3 


Wal4 


CIS 


Cll 


C12 


C13 


C14 


C15 


C16 


C17 


CIS 


C19 


C20 


C21 


C22 


C23 


C24 

































Figure 3-25. Relationship of Instruction Bits to Address and Word Counter Bits 



3. 1 13 When two or more TMCC's make a time share 
request at the same time or when one channel makes a 
request while another Is already performing a time 
share operation, the TMCC priority logic determines 
which channel is allowed to access memory first. For 
this purpose, each channel has its own Time Share 
Select flip-flop. No more than one of these flip-flops 
may be set at any time. The priority established by the 
flip-flops for the four TMCC channels Is D, C, Y, and 
W in descending order. However, once a channel has 
been selected, it is allowed to complete the processing 
of Its word without being disturbed by other channels. 
Using the Time Share Request signals mentioned pre- 
viously, the priority logic to select the channel is: 



Channel W; sRwx 

rRwx 
Channel Y; sRyx 

rRyx 



Tsm Trqw Trqy Trqx (T7 - TO) 
fsm TO 



Tsm Trqy Trqx (T7 - TO) 
Tsm TO 



3. 114 The TMCC's for the C and D channels are 
identical to those for the W and Y channels and so use 
the same logic nomenclature as above. But a request 
signal, Trqx, is not brought into the C and D units from 
other higher priority TMCC's. Then, for simplicity the 
C and D channel equations may be written: 



Channel C, sRcx 
rRcx 

Channel D, sRdx 
rRdx 



Tsm Trq (c) Trq (d) (T7 - TO) 
Tsm TO 

Tsm Trq (d) 
fsm" TO 



The terms Rex and Rdx are used here for clarity but do 
not actually appear in the logic equations for the 
equipment. 

3. 115 If a TMCC channel makes a time share request 
and has the h ighe st priority of those making such a re- 
quest, and if Tsm is true, the n the channel can set its 
Time Share Select flip-flop. Tsm indicates that the 
CPU is not already engaged in a time share operation. 
Confining the discussion to the W channel, Rwx would 
set at pulse time Tr - T8. 

3. 116 The Interlace Prepare flip-flop (Ew) also pro- 
duces Er which prevents output signals, Eom and loc, 
from reaching external devices while initializing the 
Interlace. 

Er = Ew Ey . . . 

loc = loc 1 CTErQr3 
Eom^ = Eom Er 



3-40 



Sepf ember 1965 



SDS 900685C 



Tpp"i-- n n n n n n 

Tp 



Jl_ 



EOM Instructions, r~~ I r~ 

Eom -J 0^ Bug U 05 Io( 



POT Instructions, 
Pot 



[— - 00 



02 



06 -^ 



Clear Interlace, 
Iwc 



Interlace Prepare, 

Ew 



Interlace Load, 
Iwp 



n 



Interlace Load, 
Iwe 



Interlace Active, 
Iw 



Clear TMCC, F] 
Wc 1 L 



Time 



''Second EOM may be eliminated if not needed to set count in most signif- 
icant bits of Address and Word Counters or to set up the extended mode. 



Figure 3-26. Interlace Register Loading Timing Chart 



3-41 



Paragraphs 3. 117 to 3. 123 



SDS 900685C 



September 1965 



The CPU then answers the request with a Tsr signal 
which remains on for two machine cycles. Tsr enables 
Wxx to permit a data transfer between W and C reg- 
isters. While Tsr is true, the CPU sets Tsm to incre- 
ment the Word and Address Counters. 

Iwa = Rwx Tsm = count trigger 
Wxx = Rwx Tsr Iw = load buffer from C 

3. 1 17 Refer to figure 3-27 for the timing of the signals 
involved in the data transfer between the W and C Registers. 
Figure 3-27, indicates that Wxx remains on for two 
machine cycles. This allows the data exchange to take 
place twice. The two cycles are used as follows. 

a. Input Operation. The first cycle exchanges 
the Input word and any word currently in the C-Register. 
Then between cycles, the input word is copied from the 
C-Register into memory (in parallel). During the 
second exchange cycle, the word temporarily stored in 
the W-Register is returned to the C-Register where it 
can continue in whatever function It may have been 
participating. 

b. Output Operation. The first cycle shifts any 
information which was being operated on in the C- 
Register to the W-Reglster for temporary storage. The 
word requested by the TMCC Interlace Address Counter 
Is then parallel transferred from memory to the C- 
Register (between cycles). The second exchange cycle 
then returns the word from the W-Register back to the 
C-Register and brings the word out of memory from the 
C to the W-Register. 

3. 1 18 The double exchange cycle thus provides the 
TMCC with a means of: 

a. moving a word from the W-Register through 
the C-Register to memory or vice versa, and 

b. preserving the contents of the C-Register 
while the transfer takes place. This is important If the 
CPU is engaged In some form of computation when the 
time share takes place. Figure 3-28 Is an illustration 
of the timing Involved for a typical interlaced I/O 
process. 

3. 1 19 Another Important aspect of the W and C- 
Register data exchange during an interlaced output 
concerns the path taken by the output word In getting 
to the W-Reglster. If a clock has read the last word 
out of the Character Register when the exchange takes 
place, the next word is precessed simultaneously with 
its transfer to the W-Register. This occurs as follows. 
During both of the exchange cycles, Wxx is on because 
of Rxw and Tsr. 



Wxx = Rwx Tsr Iw + . . . 

3. 120 If at this time a clock has already been detected 
(to read the last character of the previous word) so that 
W5 is set, W4 is set at pulse time T8 in the beginning of 
the second exchange cycle. 

sW4 = W5 Wf T8 W^ 

3. 121 Thus, during the second cycle, Wxx and W4 are 
both true. The output word may then be shifted directly 
from the C-Register to the Character Register and on 
through to the W-Register. A one cycle precession Is 
thereby automatically accomplished and the character 
may be read by the next clock without waiting for 
another precession to take place. 



iRwl 



W4 Wxx C21r + . 



rRwl = W4 Wxx C21r + . 



sRw2 = W4 Wxx C22r + 



rRw2 = W4 Wxx C22r + . 

sRw3 = W4 Wxx C23r + . 
rRw3 = W4 Wxx C23r + . 

Wwl = W4Wbl (T7-T0) + , 
Ww2 = W4 Wb2 (T7-T0) + , 
Ww3 = W4 Wb3 +. . . 



Refer to figure 
3-3 for Wbl, 
Wb2, and Wb3. 



3. 122 This same path for loading the W-Register 
through the Character Register is also followed when 
the Interlace is Initially set up and the first word Is 
called for. If the EOM Instruction calls for starting 
without leader. In this case W5 is first set by Ws C13 
instead of a clock signal from the peripheral unit. 



sW5 =Ws C13 C18 WIO Wn W12 W13 W14 

Figure 3-29 Illustrates the use of this feature In loading 
the first word. 

3. 123 When transferring data directly from the C to 
the Character Register, the parity bit Is generated as 
previously described except that Cpr Is used in place of 
(Wnl © Wn2 © Wn3). Cpr performs a similar func- 
tion but originates in the CPU and monitors the parity 
of the octal groups coming from the C-Register rather 
than from the W-Reglster. 

sRwp = W9 W4 R^ Wxx Cpr Qw2 (T7-T0)+ . . . 
rRwp = W9 W4 Rwp Wxx Cpr Qw2 (T7 -T0) + . . . 

Refer to figure 3-4 for Qw2. 



3-42 



September 1965 

TO _n 



SDS 900685C 



n 



Wf 



Trq 



Tsr 



L. 



Rwx 



Wxx 



Iwa 



Time 



CPU SIGNALS: sTsm 
rTsm 
sTsr 
rTsr 



= Tsm Tsr T4 



Tsm (Ts Tsr) T4 

[Mit (Trq + Tsm)] Tr 

[Mit (Trq + Tsm)] Tr 



Figure 3-27. Interlace Word Transfer Timing Chart 



3-43 









SDS 900685C 








September ]965 


Tn Pulses, 














1 1 


Tp 
















Clock Signals, , . 

Ecw 


2 _ 


1 


2 1 2 


1 


2 


1 


2 1 


Clock Detector, 
W6 




■ 


J U I 


■ 


■ 


■ 


J L 


Pr(3r*»« Hpfrprtrtr^ 




' 


1_ " 


— 1 






J 


W5 






Prprf><;<; W 


J 


. 1 


_r 


— 


n r 


— 




Register, 
W4 






rhnrnrtpr , 
















Counter, 






1 








1 1 


W8 
















<~r»mpiit«»r 












p 




Interlock, 






1 






Wf 













Time Share 

Request, 

Trqw 



Time Share 

Select, 

Rwx 



r 



Load Buffer 

Signal, 

Wxx 



Time 



2 Characters/Word 



r 



Figure 3-28. Interlace Input/Output Timing Chart 



3-44 



September 1965 



SDS 900685 C 



Output without Leader 



Tp Pulses, 
Tp 

EOM 

Instruction, 

Eom 

POT 

Instruction, 

Pot 

Clock Signal 
Ecw 

Clock 

Detector, 

W6 

Precess 

Detector, 

W5 

Precess W 

Register, 

W4 

Character 

Counter, 

W8 

Computer 

Interlock, 

Wf 



Jl 



_r 



_r 



Wc 



Time Share 

Request, 

Trqw 

Load W 
Register, Wxx 

Word 

Count = 0, 
Iwf 

Interlace 

Prepare, 

Ew 

Interlace 

Active, 

Iw 

Halt 

Interlock, 

WO 

Halt 
Detector, 

Wh 



_r 



I2w 



Time 



2 Characters/Word 



Figure 3-29. Interlace Output Timing Chart 



3-45 



Paragraphs 3. 124 to 3. 132 



SDS 900685C 



September 1965 



3. 124 As each I/O word is processed, the Word and 
Address Counters ore incremented by Iwa. Iwa also sets 
Wf again after it has issued the time share request via 
Trqw. 

Iwa = Rwx Tsm 
sWf = Iwa Mi7 TO 

The term Mit, when false, denotes that a direct access 
I/O channel (DACC) is accessing the memory. Since 
the DACC may requ ire access during an I/O operation 
by the TMCC, Mit is used to momentarily stop the 
TMCC's action . Memory access by the DACC, 
although producing Tsm, thus cannot set Wf. 

3. 125 When the Word Counter reaches the all "ones" 
condition, the count Is decoded by Iwf. 

Iwf = WcO Wcl Wc2 Wc3 Wc4 Wc5 Wc6 Wc7 

Wc8 Wc9 WclO Well Wc 12 Wcl 3 Wcl4 E^ 

Iwf inhibits further time share request signals and resets 
the Interlace Active flip-flop. 

Trqw = Wf WO Wh Iw Iwf = time share request 
rlw = Iwf T8 = Interlace Active 

3. 126 If the Interlace is controlling an input process, 
the next word loaded into the W-Register after Iw is 
reset, generates a Word Ready Interrupt, Ilw. 



II' 



Wf WO Wh (En +C|n^) Iw Ew Iwg 



At this time the program can reload the Interlace if 
reading is to continue. On channel W (or Y) the con- 
tents of the buffer can be stored with a WIM (or YIM) 
instruction. 

3, 127 During the input process, if on End-of-Record 
is encountered before the word count is completed, 
termination takes place as described earlier for the non- 
interlaced input. Wg detects the gap and sets Wh. 

sWh = Wgl^TS 

An interrupt is generated and the TMCC is cleared in 
the usual manner. 

I2w = (En +Cgn^) Wj Wh Wf + . . . 

3. 128 If the Interlace is controlling an output process, 
Iwf resets the Halt Interlock flip-flop, WO, and blocks 
Ilw and Trqw. 



Ilw = Wf WO Wh (En +(Jn^) Iw Ew Iwg 
Trqw = Wf WO WF! IwT^ 
Thus, Rwx is not set again and Iwa cannot be turned on. 



sRwx = Tsm Trqw Trqy Trqx (T7 - TO) 
Iwa = Rwx Tsm 

Then when the last word is precessed out of the W- 
Register, Wf is not set again. 

sWf - Iwa TAh TO 

This results in a situation similar to that for the non- 
interlaced output. The condition, WO W4 W5 W6, 
exists following the precession of the last character. 
The state, WD W5 "WS, then sets Wh. Or, if magnetic 
tape is being used, WO W5 W6 is detected by the tape 
unit and after a delay, Whs is generated to set Wh. 

sWh = W9 WTT WO W5 W6 (T^ + . . . ) 
T8 + Whs Wll T8 + . . . 

Then, halt interrupt and clear signals are generated and 
the TMCC, including Wh, is reset. 

I2w = (En +C|n^) M Wh W+ . . . 
Wc = WhW(T3 -T0) + . . . 
rWh = Wh Wf T8 + . . . 

3. 129 The termination timing for a typical interlaced 
input process is illustrated in figure 3-30. In general, 
termination of a Compatible Mode I/O process is much 
the same as that for a non-interlaced I/O operation, 
but figure 3-30 illustrates the relationship of the addi- 
tional interlace signals involved with those shown in 
earlier figures. 

3. 130 As with other forms of I/O operation, a dis- 
connect EOM (address 00) can also terminate on inter- 
laced operation. This is done by resetting the Interlace 
Active Flip-Flop and the Extend Operations Flip-Flop 
through Ws and Wsc. (Refer to the paragraphs on Ex- 
tended Mode beginning with 3-100 for explanation of 
Iwg. ) 

rlw = Ws CT9 C20 cTl C22 C23 (T3 - TO) Iw + . . . 



rWO = W9 Iw Iwf (Iwg + . . . ) (T7 - TO) 
3-46 



rlwg = Wsc T8 WIO Wll W12 W13 W14 Iwg + . . . 

sWsc = Ws CT9 C20 C2l C22 C23 + . . . 

3.131 INTERLACE, EXTENDED MODE (Time Share) 

3. 132 TheWordCounterandAddressCounterset-up pro- 
cedures are similarforboth the Compatible and Extended 



September 1965 



SDS 900685C 



Tp Pulses, 
Tp 



u. 



Clock Signal, [" 

Ecw J 



1 



LJ" 



Clock Detector, T 

W6 -• 



Precess Detector, 
W5 



1^ U f 



n 



1^ — ^ 






Precess W Register, 

W4 



m_r^i_R 



FL 



Clear C har. Re g., ""! fl (1 [1 

W9 W6 W5 W4 I 11 11 IL 



n n n r 



Set Char. Reg., 
"W9W6Wr 



J 



1_J 



Char. Counter, 
W7 W8 



Computer Interlock, 

Wf 



1_ 



Time Share Request, 
Trqw — 



Time Share Select, 
Rwx 



Ts Memory Control , 
Tsm 



Word Count=0, 
Iwf 



Interlace Active, 
Iw 



Interrupt Signal, 
liw 



r 



Time 



4 Characters/Word 



Figure 3-30. Input Termination Timing Chart - Interlace (Compatible Mode) 



3-47 



Paragraphs 3. 133 to 3.139 



SDS 900685C 



September 1965 



Modes. That is, the same sequence of instructions is 
used, (EOM-EOM-POT). However, to select the 
Extended Mode of operation. It is necessary to place a 
"one" in bit 12 of the second EOM (loc) instruction. 
When this instruction is processed, the Iwe loading sig- 
nal sets bit 12 into the Extended Operations F lip-Flop, 
Iwg. 

Iwe = loc 1 (T6 + 15) Ew 
slwg = Iwe C12 

Prior to this, Iwg was cleared by the first EOM instruc- 
tion as was the rest of the Interlace logic. 

Iwe = Eom C9 CTO Cl ClT (T3 - TO) CT becomes CI 

forTMCC-C 

rlwg = Iwe + . . . 

3. 133 To use the Extended Mode, four additional flip- 
flops are loaded by the loc Instruction. Two of these, 
Iwh and Iwi, comprise the Channel Command Register 
which selects the type of termination. The remaining 
two flip-flops, Iwj and Iwk, are employed to arm the 
I2w and Ilw interrupts on a selective basis. 

slwj = Iwe C 13 
rlwj = Iwe + . . . 

slwk = Iwe C14 
rlwk = Iwe + . . . 

slwh = Iwe C15 
rlwh = Iwe 

siwi = Iwe C16 
riwi = Iwe 

By decoding Iwj and Iwk, the Extended Mode can per- 
form the four different terminal functions listed In 
table 3-4, Each function can be used to control either 
an Input or an output operation. In the following 
paragraphs, each of the four functions is discussed in 
detail. In each case, it is assumed that the interlace 
registers have already been loaded by the EOM-EOM- 
POT instructions and that the Interlaced I/O operation 
is proceeding normally. 

3. 134 lORD - Iwg Iwh l"^ 

3.135 Output 

3. 136 Write C words. When C equals zero, output Is 
terminated (I.e. the device Is signaled that the last 
characters have been transmitted). When the peripheral 
device has generated the End-of -Record and, if 



necessary, checked the validity of the record, It sends 
an End-of-Record response to the channel buffer. When 
received by the buffer, the End-of-Record signal gen- 
erates an End-of-Record interrupt (if armed) and discon- 
nects the channel. 

3. 137 The line printer generates the End-of-Record 
response when it completes the printing of a line. If 
the printer encounters any print errors or faults, it sends 
a signal to the channel that sets the channel error In- 
dicator. This can occur since the printer has not dis- 
connected from the channel. The lORD is useful when 
the program is to print several lines and the program is 
not otherwise to use the channel between lines. When 
the printer completes each line, it causes an End-of- 
Record interrupt (assumed to be armed), notifying the 
program that it can immediately transmit the next paper 
control instruction and the next line image. 

3. 138 The unbuffered card punch operates similarly. 
It generates the End-of-Record response after punching 
each row. If any faults occur during the punching of 
the entire card, the card punch sends a signal to the 
channel that sets the channel error Indicator; this occurs 
after punching the last row (row 9). 

NOTE 

A program should not use lORD with 
devices that do not have End-of-Record 
conditions on output (e.g., devices 
such as the paper tape punch and type- 
writer). These devices to terminate 
output but give the program no indica- 
tion when they receive the last 
characters. 

After the last word is accessed from memory, zero word 
count Is established. 

3. 139 The interlace is counted by the Interlace Count 
Trigger, Iwa. 

Iwo = Rwx Tsm 

Zero Word Count, Iwf, occurs and the Interlace Active 
flip-flop, I\v Is reset. 



Iwf = WcO Wcl 
rlw = Iwf T8 



. Wcl3 Wcl4 Ew 



The Halt Interlock, WO, Is reset. 



rWO = W9 Iw Iwf (Iwg + Iwh + Iwi) (T7 - TO) + . . . 

If the End-of-TransmissIon Interrupt Enable, Iwk, has 
been previously aimed, an Ilw interrupt occurs and Iwk 
is reset. 

Ilw = Iwg Iw Iwf Iwk + . . . 



3-48 



September 1965 



SDS 900685 C 



Table 3-4. Interlace Extended - Mode Terminal Functions 



Terminal Function 


Iwg 


Iwh 


Iwi 


Summary of Operation 


lORD 


1 








The I/O operation proceeds until the word count equals zero 


Input/Output of 
record then 
disconnect. 








then terminates. On input, the channel disconnects when the 
End-of-Record is encountered. On output, the channel signals 
the device that the lost character has been transmitted then 
disconnects after the device provides an End-of-Record 
response. 


lOSD 


1 





1 


The channel disconnects when the word count equals zero or 


Input/Output 








at the end of a record. 


until signal 










then disconnect. 










lORP 


1 


1 





The I/O operation proceeds until the word count equals zero 


Input/Output of 
a record then 
proceed. 








but does not terminate. On input, the channel sets the inter- 
record indicator when the end of a record is encountered. On 
output, the channel signals the device that the last character 








has been transmitted then sets the inter-record indicator after 










the device provides an End-of-Record response. The channel 










does not disconnect (except for magnetic tape). 


lOSP 


1 


1 


1 


When the word count equals zero, the program should either 


Input/Output 
until signal 
then proceed. 








reload the interlace to continue, or terminate the operation 
before the next clock is received; otherwise a rate error will 
occur. 



rlwk = IlwIwkT8+. . . 

When the last character of the lost word has been pre- 
cessed Into the Character Register, Wf is reset. 

rWf = W7 W8 W4 (T6 + T5) + . . . 

Because the Halt Interlock, WO, and Interlace Active, 
Iw, have been reset, a Time Share Request, Trqw, can 
not be made. 

Trqw = WfWO Wh IwK^ 

Any further clocking, Ecw, of the buffer generates a 
Halt Interlock Signal condition. 



sW6 = W5 Ecw T8 WIO Wl 1 W12 W13 W14 



sW5 = W5 W6 Ecw TO + . . . 
rW6 = W5 TO + . . . 

Halt Interlock Signal (decoded by the peripheral device) 
= W5 W6 WO 



If the Halt Signal, Whs, Is received the Halt Detector 
Wh, is set and a disconnect occurs. 

sWh = W9hj7T8 Whs+ . . . 
Wc = Wh Wf (T3 - TO) + . . . 
rW9 = Wc 



rWlO 
etc. 



Wc 



The Signal Complete flip-flop, Wsc, is set. 

sWsc = Wh W T8 + . . . 

If the End-of-Record Interrupt Enable, Iwj, has been 
previously armed, an I2w Interrupt occurs and Iwj is 
reset. 

I2w = Wsc Iwj Iwg + . . . 
rlwf = I2w Iwj T8 + . . . 

The Extend Operations flip-flop, Iwg, and the Signal 
Complete flip-flop, Wsc are then reset. 



3-49 



Paragraphs 3. 140 to 3. 146 



SDS 900685C 



September 1965 



rlwg = Wsc T8 W10 Wl 1 W12 W13 W14 Iwg + . . . 

rWsc = Wsc Iwg T8 

3. 140 lOSD - Iwg Iwh Iwi 

3. 141 Output 

3. 142 Write C words. When C equals zero and when 
the last character has been transmitted, the channel 
disconnects the device and becomes inactive. If an 
End-of-Record signal is received before the count 
reaches zero, the channel disconnects immediately. 

NOTE 

The lOSD is designed for use on devices 
which are normally operated on the basis 
of the word count only. Typewriters and 
paper tape devices are of this type, as 
are the printer and card punch when the 
user does not wish to stay connected 
until the operation is complete. 

3. 143 The interlace is counted by the Interlace Count 
Trigger, Iwa. 

Iwa = Rwx Tsm 

Zero Word Count, Iwf, occurs and the Interlace Active 
flip-flop, Iw, is reset. 



Iwf = WcO Wcl 
rlw = Iwf T8 + 



Wcl3 WcU Ew 



The Halt Interlock, WO, is reset. 

rWO = W9 Iw (Iwg + Wh + M (T7 - TO) + . . . 

If the End-of-Transmission Interrupt Enable, Iwk, has 
been previously armed, an Ilw interrupt occurs and Iwk 
is reset. 

Ilw = Iwg Iw Iwk Iwk + . . . 
rlwk = Ilw Iwk T8 + . . . 

When the last character of the last word has been pre- 
cessed into the Character Register, Wf is reset. 



rWf 



W7 W8 W4 (T6 + T5) 



Because the Halt Interlock, WO, has been reset, a Time 
Share Request, Trqw, cannot be made. 

Trqw = Wf WO Wh Iw Iwf 



Any further clocking, Ecw, of the buffer generates a 
Halt Interlock Signal condition. 



sW6 = W5 Ecw T8 WIO Wn W12 W13 W14 
sW5 = W5 W6 E^ TO + . . . 
rW6 = W5 TO + . . . 

Halt Interlock Signal 

= W5 W6 WO 

For devices other than magnetic tape, the Halt De- 
tector, Wh, sets upon reaching zero Word Count, Iwf, 
and after the last character has been clocked from the 
buffer. 



sWh = W9 wn WO W5 W6 (Iwh Iwi + 



T8 + 



The Halt Detector, Wh, also sets upon the occurrence 
of a Halt Signal, Whs, from the magnetic tape unit. 

sWh = W9 ]^ Whs T8 + . . . 

The setting of the Halt Detector, Wh, initiates a buffer 
disconnect sequence. 



Wc = Wh Wf (T3 - 


- TO) + . 


rW9 = Wc 




rW10= Wc 




etc. 





The Signal Complete flip-flop, Wsc, is set. 

sWsc = WhWfT8 

If the End-of-Record Interrupt Enable, Iwj, has been 
previously armed, an I2w interrupt occurs and Iwj is 
reset. 

I2w = Wsc Iwj Iwg + . . . 
rlwj = I2w Iwj T8 + . . . 

The Extend Operations flip-flop, Iwg, and the Signal 
Complete flip-flop, Wsc, are then reset. 



rlwg = Wsc T8 WIO Wl 1 W12 W13 W14 Iwg + . . . 

rWsc = Wsc iw^ T8 

3. 144 lORP - Iwg Iwh h?i 

3. 145 Output 

3. 146 Write C words. When the channel interlace 
counts C down to zero, the interlace notifies the channel 
buffer that it has received the last word that is to be 



3-50 



r^' 



September 1965 



SDS 900685C 



Paragraphs 3. 147 fo 3. 150 



output; when the buffer outputs this lost word, it sends 
a signal to the connected peripheral device indicating 
that the device has the last word. When the peripheral 
device receives, outputs and checks the validity of 
this last word, it sends an End-of-Record response to 
the channel buffer. When received by the buffer, the 
End-of-Record signal generates an End-of-Record inter- 
rupt (if armed) and sets the Inter-Record indicator; the 
channel does not disconnect. 

3. 147 When the peripheral device is magnetic tape, 
the tape continues to move after it signals End-of- 
Record. As in reading tape, the signal causes the Tape 
Gap signal to come high. If the program executes a 
new write tape or erase tape EOM during the inter-gap 
time (approximately one millisecond), the tape remains 
in motion and proceeds to write or erase a new record. 
If the program executes no such EOM before the Tape 
Gap signal drops, the channel disconnects and tape 
comes to a stop. No interrupt occurs at this time. This 
is the only condition which causes a channel to dis- 
connect automatically for an lORP. 

3. 148 To proceed after the End-of-Record occurs, the 
program first executes a Buffer Control mode EOM to re- 
initialize the Channel Unit Address Register and then 
reloads the interlace portion of the channel (the pro- 
gram can alert the Interlace via the Buffer Control 
EOM). Otherwise, the channel immediately terminates 
any attempt to use its interlace portion, since the 
channel is still active and in the End-of-Record con- 
dition. When the program continues from an Inter- 
Record condition, the program should use an extended 
mode terminal function. 

NOTE 

A program should not use lORP with 
devices that do not generate End-of- 
Record responses upon output termin- 
ation; such devices are paper tape and 
typewriter. These devices do termin- 
ate output but give the program no 
indication when they receive the last 
characters. The lORP should also not 
be used with the printer and card 
punch since these devices expect the 
channel to disconnect after they send 
EOR. 

3. 149 After the last word is accessed from memory, the 
Interlace is counted and zero word count is established. 
The Interlace is counted by the Interlace Count Trigger, 
Iwa. 

Iwa = Rwx Tsm 

Zero Word Count, Iwf, occurs and the Interlace Active 
flip-flop, Iw, is reset. 



Iwf = WcOWcl . . . Wcl3Wcl4Ew 
rlw = Iwf T8 + . . . 
The Halt Interlock, WO, is reset. 

rWO = W9 Iwf (h^ + Iwh" + h^) 



(T7 - TO) + . . . 

If the End-of-Transmission Interrupt Enable, Iwk, has 
been previously armed, an Ilw interrupt occurs and Iwk 
is reset. 

Ilw = Iwg Iw Iwf Iwk + . . . 
rlwk = Ilw Iwk T8 + . . . 

When the last character of the last word has been pre- 
cessed into the Character Register, Wf is reset. 

rWf = W7 W8" W4 (T6 + T5) + . . . 

Because the Halt Interlock, WO, and Interlace Active, 
Iw, have been reset, a Time Share Request, Trqw, 
cannot be made. 

Trqw = Wf WO Wh"lw ^J 

Any further clocking, Ecw, of the buffer generates a 
Halt Interlock Signal condition. 



sW6 = W5 Ecw T8 WIO Wll W12 W13 W14 
sW5 = W5 W6"E^T0 + . . . 

rW6 = W5 TO + . . . 

Halt Interlock Signal 

= W5 W6 WO 

3. 150 For non-magnetic tape devices, the buffer 
awaits the receipt of a Halt Signal, Whs, from the de- 
vice. The End-of-Record Detector, Wg, is set. 



sWg = Whs (T7- TO) WIO Wll W12 W13 W14 + . . 

The Signal Complete Detector, Wsc, sets and if the 
End-of-Record Interrupt Enable, Iwj, has been pre- 
viously armed, an I2w interrupt Is generated and Iwj is 
reset. 



sWsc = Wg Iwg Iwh T8 (Iwf + ...)+.. 

I2w = Wsc Iwj Iwg + . . . 
rlwj = I2w Iwj T8 + . . . 



3-51 



Paragraphs 3. 151 fo 3. 157 



SDS 900685 C 



Sepfember 1965 



The device does not disconnect because Wh is not per- 
mitted to set. 

3. 151 For magnetic tape, the buffer awaits the re- 
ceipt of a gap signal, Mtgw. The End-of-Record 
Detector, Wg, is set. 

sWg = Mtgw TO Iwg Wll (WO W5W6 W9 + . ..)+.. . 

The Signal Complete Detector, Wsc, sets and if the 
End-of-Record Interrupt Enable, Iwj, has been pre- 
viously armed, an I2w interrupt is generated and Iwj 
is reset. 

sWsc = Wg Iwg Iwh T8 (Iwf + ...) + . . . 
I2w = Wsc Iwj Iwg 

rlwj = I2w Iwj T8 + . . . 

The magnetic tape system can continue if the interrupt 
sub-routine executes an EOM to the tape within 
approximately one millisecond from the occurrence of 
the interrupt. If no EOM is executed, the tape 
generates a Halt Signal, Whs, and the Halt Detector, 
Wh, sets. The magnetic tape Is disconnected and the 
buffer is cleared. 



sWh 


= Whs Wl 1 T8 + . . . 


Wc 


= Wh Wf (T3 - TO) + . . . 


rW9 


= Wc 


rWlO 


= Wc 


etc. 




rlwg 


= Wsc T8 WIO Wll W12 W13 W14 




Iwg + . . . 


rWsc 


= Wsc T8 Iwg 


rWh 


= Wh Wf T8 + . . . 



the buffer results in a rate error; this sets the Channel 
Error Indicator. 

3. 155 If the program executes a TERMINATE OUTPUT 
(TOP) instruction after the channel has counted C 
down to zero, the channel terminates the output and 
operates identically like the lORP from this point on. 

3. 156 After the last word is accessed from memory, 
the Interlace is counted and zero word count is 
established. 

The Interlace is counted by the Interlace Count Trigger, 
Iwa. 

Iwa = Rwx Tsm 

Zero Word Count, Iwf, occurs and the Interlace Active 
flip-flop, Iw, Is reset. 

Iwf = WcOWcl . . .Wcl3Wcl4E^ 

rlw = Iwf T8 + . . . 

If the End-of-Transmlssion Interrupt Enable, Iwk, has 
been previously armed, an Ilw interrupt occurs and 
Iwk is reset. 

Ilw = Iwg Iw Iwf Iwk + . . . 

rlwk = Ilw Iwk T8 + . . . 

The program, upon receipt of an Ilw interrupt, should 
reload the Interlace to permit the transmission to con- 
tinue with a new set of parameters (I. e. , word count, 
address, terminal functions, etc.). The loading of the 
Interlace with a zero word count could permit conver- 
sion of the current lOSP to some other terminal function, 
for example to an lORD, thereby effecting a disconnect. 

3. 157 Execution of a TERMINATE OUTPUT (TOP) 
Instruction, e.g., EOM14000, would convert the lOSP 
to an lORP. The TOP instruction resets the Halt Inter- 
lock flip-flop, WO. 



3. 152 lOSP - Iwg Iwh Iwi 

3. 153 Output 

3. 154 Write C words. When the channel counts C 
down to zero, the channel generates a Count Equals 
Zero interrupt (if armed); the channel does not termin- 
ate output. The program should reload the interlace 
portion of the channel to continue writing in the same 
record. Failure to reload the Interlace before the buffer 
transmits all of the characters in its registers and before 
the peripheral device requests the next character from 



rWO = loc C12 C17 C19 C20 C21 C22 C23 W9 

T0 + . . . 

Any further clocking of the channel by Ecw generates 
a Halt Interlock Signal condition when the last charac- 
ter has been clocked from the buffer. 



sW6 = W5 Ecw T8 WIO Wll W12 W13 W14 
sW5 = W5 W6 E^TO + . . . 
rW6 = W5 TO + . . . 



3-52 



September 1965 



SDS 900685C 



Paragraphs 3. 158 to 3. 161 



rW5 = W4 TO + . . . 

Halt Interlock Signal 

= W5 W6 WO 

The Halt Interlock Signal is representative of the buffer 
status had the lOSP been an lORP. 

3. 158 lORD - Iwg iwh iwT 

3. 159 Input 

3. 160 Read C words. If C equals zero before the 
End-of- Record is detected, the rest of the record is 
ignored. At the End-of- Record, the peripheral device 
is disconnected and the channel becomes inactive. 

3. 161 When the W-Register acquires the specified num- 
ber of characters, a Time Share Request, Trqw, is 
generated. 

Trqw = W? WO Wh Iw I^ 

When memory is accessed, the interlace registers are 
counted by the Interlace Count Trigger, Iwa. 

Iwa = Rwx Tsm 

Zero Word Count, Iv*/f, may occur and the Interlace 
Active flip-flop, Iw, is reset. 

Iwf = WcOWcl . . . Wcl3Wcl4Ew 

rlw = Iwf T8 + . . . 

If the Zero Word Count Interrupt Enable, Iwk, has been 
previously armed, then an Ilv»/ interrupt occurs. 

Ilw = Iwg Iw Iwf Iwk + . . . 

rlwk = Ilw Iwk T8 + . . . 

Additional characters entering the channel after Zero 
Word Count has been reached are precessed into the 
W-Register. 



sW6 = W5 Ecw T8 WIO Wl 1 W12 W13 W14 
rW6 = W5 TO + . . . 



sW5 = W5 W6 Ecw TO + . . . 

rW5 = W4 TO + . . . 

sW4 = W5 Wf T8 W^ + 

+ Iwg W9 iwrW5 Iwf T8 + . 
sW4 = Wr TO + . . . 

Wwl = W4 Wbl {17 - T0) + . . . 



Ww2 = W4 Wb2 (T7 - TO) + . . . 
Ww3 = W4 Wb3 + . . . 

However, Time Share Request, Trqw, is inhibited. 

Trqw = Wf WO Wh Iw "i^ 

Parity errors cannot occur after Zero Word Count. 

sWe = W9 W6 W5 W4 Rwp W^ Npw 
(Iwg + Iwi + Iwf) + . . . 

Rate errors cannot set We while W4 is enabled by Iwg 
W9 Iwi Iw. 

sWe = WO W6 W5 Ecw T8 + . . . 

After Zero Word Count Is established, detection of a 
Halt Signal or Photoreader Gap sets the End-of-Record 
Detector, Wg. 



sWg = Whs (T7-T0) WlOWll W12 W13 W14 
+ W9 wTb WTI W12 W13 



(Rwl Rw2 Rw3 Rw4 Rw5 Rw6 Rwp) 



W5 (T7-T0) WlOWll W12 W13 W14+. 
The Halt Detector, Wh, sets. 



sWh = Whs Wn T8 + Wg W9 Wl 1 Iwh Iwg T8 
(Iwf + ...) + ... 

The buffer is flushed (i.e., allowed to precess without 
receiving input clocks until the Character Count equals 
zero) until it is assured that Wf is reset. 

sW4 = Wh Wf T8 + . . . 

rWf = W7 W8 W4 (T6 + T5) + . . . 

The buffer Is cleared and the peripheral device 
disconnected. 

Wc = Wh Wf (T3 - TO) + . . . 

If the End-of-Record Interrupt Enable, Iwj, has been 
previously armed, and End-of-Record Interrupt, Iw2, 
occurs. 

sWsc = Wh Wf T8 + . . . 

rWsc = Wsc T8 Iwg 

I2w = Wsc Iwj Iwg + . . . 

rlwj = I2w Iwj TO + . . . 



3-53 



Paragraphs 3. 162 to 3. 166 



SDS 900685 C 



September 1965 



rlwg = Wsc Iwg WIO Wl 1 W12 W13 W14 T8 + . . . 

Should an End-of- Record occur before Zero Word Count 
is established, the End-of-Record Detector is set. 

sWg = Mtgw TO Iwg Wn {WO W9 + . . .) 



+ Whs {17 - TO) WIO Wl 1 W12 W13 W14 



+ W9W10Wn W12W13 



(Rw 1 Rw2 Rw3 Rw4 Rw5 Rw6 Rwp) W5 



(T7 - TO) WIO Wl 1 W12 W13 W14 

Any character remaining in the W-Register are flushed 
by W4 and a Time Share Request, Trqw, is generated. 



sW4 = Iwg Wg Wf WO Wev Iw T8 W7 W9 WIO 



wn Wh + 



where: 



Wev = W8 Wn2 W7 Wnl + W8 Wn2 W7 Wn 1 



rWf 
Trqw 



+ W8 Wn2 W7 Wnl + W8 Wn2 W7 Wnl 

W7W8 W4 (T6 + T5) +. . . 
Wf WO Wh Iw Wf 



and W7 W9 WIO Wl 1 Wh indicates that a scan opera- 
tion is not taking place. 

3. 162 As a result of one Time Share operation, Wf is 
set. 



sWf 



Iwa Mit TO + . 



The Character Counter is reloaded with its original 
count, making Wev true and the flush operation ceases. 

3. 163 The Halt Detector, Wh, is now permitted to set. 
For Magnetic Tape operation tjiis occurs upon receipt 
of a Halt Signal, Whs. 



sWh = Whs Wl 1 T8 + Wg W9 Wl 1 Iwh 
(Iwf + Wev Wf) T8 Iwg + . . . 

Before the buffer is cleared, the buffer is again flushed 
but a Time Share Request, Trqw, is inhibited. 

sW4 = Wh Wf T8 + . . . 

rWf = W7 W8 W4 (T6 + T5) + . . . 

Trqw = Wf WOWh Iw'Wf 

The buffer is then cleared. 

Wc = Wh Wf (T3 - TO) + . . . 



If the End-of-Record Interrupt Enable, Iwj, has been 
previously armed, an End-of-Record Interrupt, I2w, 
occurs. 



sWsc 
rWsc 
I2w 
rlwj 



Wh Wf T8 + . 
Wsc T8 Iwg 
Wsc Iwj Iwg 
I2w Iwj T8 + 



rlwg = Wsc Iwg WIO Wll W12 
WT3WT4T8 + . . . 

3. 164 lOSD - Iwg Iwh Iwi 

3. 165 Input 

3. 166 Read C words. When C equals zero or when the 
End-of-Record is encountered, the device is disconnec- 
ted and the channel becomes inactive. If the channel 
disconnects because of a zero count, an EOR interrupt 
(if armed) is generated in addition to the count-equal - 
zero interrupt. If both are armed, the count-equal- 
zero interrupt occurs first. 

When the W-Register acquires the specified number of 
characters, a Time Share Request, Trqw, is generated. 

Trqw = Wf WO Wh Iw Iwf 

When memory is accessed, the interlace registers are 
counted by the Interlace Count Trigger, Iwa. 



Iwa 



Rwx Tsr 



Zero Word Count, Iwf, may occur and the Interlace 
Active flip-flop, Iw, is reset. 

Iwf = WcOWcl . . .Wcl3Wcl4E^ 
rlw = Iwf T8 + . . . 

If the zero Word Count Interrupt Enable, Iwk, has been 
previously armed, then an Ilw interrupt occurs. 

Ilw = Iwg Iw Iwf Iwk + . . . 
rlwk = Ilw Iwk TO + . . . 
The Halt Detector is set. 



sWh = W9 Wll Iwg Iwh Iwi Iwf T8 WO + . . . 

The buffer is flushed, but no Time Share Request, Trqw, 
may be initiated. 

sW4 = Wh Wf T8 + . . . 

rW4 = W4 TO + . . . 



3-54 



September 1965 



SDS 900685C 



Paragraphs 3. 167 to 3. 170 



rWf = W7 W8 T8 + . . . 
Trqw = Wf WO Wh Iw I^ 

The channel Is cleared and the peripheral device dis- 
connected. 

Wc = Wh Wf (T3 - TO) + . . . 

If the End-of-Record Interrupt Enable, Iwj, has been 
previously armed, and End-of-Record Interrupt, I2w, 
occurs. 

sWsc = Wh Wf TB + . . . 

rWsc = Wsc Iwg TB 

I2w = Wsc Iwj Iwg + . . . 

rlwj = I2w Iwj T8 = . . . 



rlwg = Wsc Iwg WIO Wn W12W13W14 
T8 + . . . 

Should an End-of-Record occur before Zero Word Count 
is established, the End-of-Record Detector Is set. 

sWg = Mtgw TO Iwg Wl 1 (WO W9 + . . . ) 



+ Whs (T7-T0) WIO Wl 1 W12 W13 W14 



+ W9 WIO Wll W12 W13 



(Rwl Rw2 Rw3 Rw4 Rw5 Rw6 Rwp) 



W5 (T7-T0) W10W11 W12 W13W14 

Any characters remaining in the W-Reglster are flushed 
and a Time Share Request, Trqw, Is generated. 



sW4 = Iwg Wg Wf WO Wev Iw W7 W9 WIO Wl 1 
Wh TB + . . . 

^here: 



Wev = WB Wn2 W7 Wnl + WB Wn2 W7 Wnl 



+ W8 Wn2 W7 Wnl + W8 Wn2 W7 Wnl 

rWf = W7 W8 W4 (T6 + T5) + . . . 
Trqw = Wf WOWh Iwi^ 

As a result of the Time Share operation, Wf, Is set. 

sWf = Iwa Mit TO 

When the term Wev Is true the flush and store operation 
ceases. The Halt Detector, Wh, Is permitted to set 

sWh = Whs Wl 1 TB + Wg W9 WTI I^ 
(Iwf + Wev Wf ) T8 Iwg + . . . 



Before the buffer Is cleared, the buffer is again flushed 
but a Time Share Request, Trqw, Is Inhibited. 

sW4 = Wh Wf T8 + . . . 
rWf = W7 WB W4 (T6 + T5) + . . . 
Trqw = M WO Wh Iw iwf" 

The buffer is then cleared. 

Wc = Wh Wf (T3 - TO) + . . . 

If the End-of-Record Interrupt Enable, Iwj, has been 
previously armed, an End-of-Record Interrupt, I2w, 
occurs. 



sWsc 


= Wh Wf TB + . . . 


rWsc 


= Wsc Iwg TB 


I2w 


= Wsc Iwj Iwg + . . . 


rlwk 


= I2w Iwk TB + . . . 


rlwg 


= Wsc Iwg WIO Wl 1 W12 W13 W14 




TB + . . . 



3. 167 Should an lOSD mode be used on Input with 
magnetic tape devices, no disconnect will occur at Iwf. 
Should additional characters enter the buffer after Iwf, 
a rate error may occur. 

sWe = WO W6 W5 Ecw T8 + . . . 

Disconnect occurs upon receipt of a Halt Signal, Whs, 
from the magnetic tape system. 

sWh = Whs Wll TB + . . . 

sW4 = Wh Wf TB + . . . 

rW4 = W4 TO + . . . 

rWf = W7 WB W4 (T6 + T5) + . . . 

Wc = Wh Wf (T3 - TO) + . . . 

3. 16B lORP - Iwg Iwh Iwl 

3. 169 Input 

3. 170 Read C words. If the channel counts C down to 
zero before the peripheral device encounters the End- 
of-Record (EOR), the channel Ignores the rest of the 
record (to the End-of-Record). When the peripheral 
device sends the End-of-Record signal to the channel, 
the channel sets Its End-of-Record Indicator; this signal 
sets the End-of-Record interrupt (if armed). The chan- 
nel does not disconnect. The channel Is now in an 
"Inter- Record" condition. 



3-55 



Paragraphs 3. 171 to 3. 174 



SDS 900685C 



September 1965 



3. 171 When the peripheral device is magnetic tape, the 
tape continues to move when the tape handler encoun- 
ters the End-of-Record. The End-of-Record occurs when 
the tape read-heads encounter tape gap; this also causes 
a Tape Gap signal to come high. If the program exe- 
cutes a new read tape or scan tape EOM during the 
inter-gap time (approximately one millisecond while 
the Tape Gap signal is high), the tape remains in motion 
and proceeds to read or scan the next record. If the 
program executes no such EOM before the Tape Gap 
signal drops, the channel disconnects and the tope comes 
to a stop. No additional interrupt occurs. This is the 
only condition that causes a channel to disconnect auto- 
matically in an lORP. 

3. 172 All other input devices remain connected until 
the program takes further action. The paper tape reader 
remains in motion; the program should issue a "discon- 
nect channel" instruction if the program is not reading 
any more tape. To proceed after the End-of-Record 
occurs, the program first executes a Buffer Control mode 
EOM to re-initialize the Channel Unit Address Register 
and then reloads the interlace portion of the channel 
(the program can alert the Interlace via the Buffer Con- 
trol EOM). Otherwise, the channel immediately termi- 
nates any attempt to use its interlace portion since the 
channel is aware that it is still active and in the End- 
of-Record condition. When the program continues from 
an Inter-Record condition, the program should use an 
extended mode terminal function. An lORP should not 
be used to read with devices that do not have EOR sig- 
nals (e.g., the typewriter). 

3. 173 When the W-Register acquires the specified 
number of characters, a Time-Share Request, TRQW, is 
generated. 

Trqw = Wf WO Wh Iwl^ 

When memory Is accessed, the interlace registers ore 
counted by Interlace Count Trigger, Iwa. 

Iwa = Rwx Tsm 

Zero Word Count, Iwf, may occur and the Interlace 
Active flip-flop, Iw, is reset. 



Iwf = WcOWcl 



rlw = Iwf T8 + 



Wcl3 Wcl4 Ew 



If the Zero Word Count Interrupt Enable, Iwk, has been 
previously armed, then an Ilw interrupt occurs. 

Ilw = Iwg Iw Iwf Iwk + . . . 

rlwk= Ilw Iwk T8 + . . . 



3. 174 Additional characters entering the channel after 
Zero Word Count has been reached are precessed into 
the W-Register. 



sW6 = W5 EcwTBWlOWll W12W13W14 

rW6 = W5 TO + . . . 

sW5 = W5W6 E^TO + . . . 

rW5 = W4 TO + . . . 

sW4 = W5 Wf T8 W^ + Iwg W9 i^W5 Iwf T8 + . . . 

rW4 = W4 TO + . . . 

Wwl = W4 Wbl (T7 - TO) + . . . 

Ww2 = W4 Wb2 (T7 - TO) + . . . 

Ww3 = W4 Wb3 + . . . 

However, Time Share Requests, Trqw, are inhibited. 

Trqw = WfWOWh Iwl^ 

Parity and rate errors cannot occur after Zero Word 
Count. 



sWe = W9 W6 W5 W4 Rwp Wg Npw (Iwg 

+ Iwi +1^) +W0W5W6 EcwT8 + . . . 

Detection of magnetic tape gap, photoreader gap or a 
halt signal sets the End-of-Record Detector. 

sWg = MtgwTOIwgWll (W0W9 + . . .) 



+ Whs (T7-T0) WlOWll W12W13 W14 



+ W9W10WllW12W13(RwlRw2Rw3Rw4Rw5 



Rw6 Rwp) W5 (T7-T0)W10W11 W12W13 W14 

If the End-of-Record Detector is set before Zero Word 
Count has occurred, then the buffer is flushed and the 
completed word is stored in memory. 



sW4= IwgWg Wf WOWev IwW7W9 WlOWll WhT8+. 



rW4 = W4 TO + 
where: 



Wev = W8 Wn2 W7 Wnl + W8Wn2W7 Wnl 



+ W8Wn2W7Wnl +W8Wn2W7Wnl 
Wf is reset and Time Share Request is inhibited. 



3-56 



September 1965 



SDS 900685C 



Paragraphs 3. 175 to 3. 183 



rWf = W7 W8 W4 (T6 + T5) + . . . 

Trqw = WfWOWh Iw I^ 

sWf = Iwa Mlt TO + . . . 

If Wg is set, Wsc is set after the buffer is flushed or 
immediately if Zero Word Count exists. 

sWsc = Wg Iwg Iwh (Wev Wf + Iwf) T8 + . . . 

rWsc = Wsc Iwg T8 

If the End-of-Record Interrupt Enable, Iwj, has been 
previously armed, an I2w interrupt occurs. 

I2w = Wsc Iwj Iwg + . . . 

rlwj = I2w Iwg T8 + . . . 

3. 175 In general, the buffer does not disconnect, as 
the Halt Detector has not been set. For magnetic tape 
operation, a new EOM may be given within 0.75 milli- 
second from the occurrence of I2w to permit the magne- 
tic tape system to proceed to a new record. In the case 
of magnetic tape, failure to give an EOM results in the 
tape stopping and the buffer disconnecting. 

sWh = WhsWll T8 + . . . 

The buffer is flushed but not stored as Trqw Is inhibited. 

sW4 = Wh Wf T8 + . . . 

rW4 = W4 TO + . . . 

rWf = W7W8 W4(T6 + T5) 

Trqw = WfWOV/hlwT^ 
The buffer is cleared. 

Wc = WhWf (T3-T0) + . . . 

3. 176 lOSP - Iwg Iwh Iwi 

3. 177 Input 

3. 178 Read C words. If the channel counts C down to 
zero before the peripheral device encounters the End-of- 
Record, the channel generates a Count Equals Zero 
interrupt (if armed). The program should reload the 
interlace portion of the channel to continue reading the 
record. As far as the peripheral device knows, nothing 
happens at this time. Failure to reload the Interlace 
before the peripheral device sends enough characters to 
overfill the channel buffer causes a rate error; this sets 
the channel ernpr indicator. 



3. 179 When the peripheral device encounters the End- 
of-Record, lOSP operates identically like the lORP 
command. An lOSP is identical to an lORP in operation 
except that when Zero Word Count occurs it is antici- 
pated that the interlace will be reloaded. Failure to 
reload the interlace in time results in rate errors. Parity 
error detection is not inhibited after Zero Word Count. 

sWe = V^W6W5W4 RwpW^Npw(Iwi + . . .) 

+ W0W6W5 EcwT8 + . . . 

3. 180 PIN ADDRESS COUNTER 

3. 181 The PIN Address Counter flip-flop allows a PIN 
instruction to interrogate the Interlace Address Counter. 
The flip-flop is set by an I/O Unit Control instruction 
EOM (loc) in which the address bits are "zeros" and bit 
13 is a "one". Bit 17 of the instruction selects either 
the W or Y channel TMCC. 



sWpa =IocC17C13C19C20C21 C22C23 TO 

The loc signal indicates that an I/O control instruction 
is being processed and also distinguishes between the 
W - Y channels and the C - D channels. 



loc = loc 1 CI Er Qr3 
loc 1 = EomCToCll 



CI becomes C 1 
for TMCC-C & D 



3. 182 After Wpa is turned on, the Interlace Merrxiry 
Address Counter flip-flops are gated to the CPU via the 
parallel input lines (CdO) - (Cd2^ . For this purpose, 
only fifteen of the lines are required. 

(Cd^ = (WaO Wpa) (YaO Ypa) + . . . 



^d^ = (Wal4 Wpa) (Yal4 Ypa) + . . . 

The dotted lines indicate other parallel signals may be 
connected to the same lines. 

3. 183 When a PIN instruction is executed, Wpa is re 
reset and the interrogation is complete. 

rWpa = Pin TO + St 



3-57 



Paragraph 3. 184 



SDS 900685 C 



September 1965 



3. 184 GLOSSARY OF LOGIC TERMS 



Buc A control signal derived from the 

EOM instruction used to activate the 
TMCC and peripheral devices. 

CO - C23 The 24 signals received from the C 

register in the CPU. 

Clx A signal from the CI flip-flop in the 

C register in the CPU. Clx is uti- 
lized to distinguish between TMCC 
W or Y and TMCC C or D. CU 
becomes Clx for TMCC C or D. 

C21r - C23r Signals from the C register in the 

CPU used when serial transfers occur 
from the C register to the W register. 

Cc^- (^d2^ Input data lines that are read by the 
C register in the CPU during a PIN 
instruction. 



I2w 



/CiO/-/Ci23/ 



Cpr 



Ecw 



En+(En) 



Eom 



Er 



Ew 



Ilw 



The 24 signals derived from the C 
register In the CPU and transmitted 
on the interconnecting cable 

A signal from the CPU Indicating the 
parity of C21r - C23r from the C 
register as information is serially 
transmitted to the TMCC. 

The clocking signal from external 
devices used in clocking of infor- 
mation into or out of the TMCC. 

A signal from the CPU denoting that 
interrupt system Is enabled. 

A signal from the CPU occurring 
during an EOM instruction. 

A signal which inhibits Eom and loc 
to external devices when an Inter- 
lace Prepare flip-flop has been set. 

A flip-flop which when set prepares 
the interlace to be loaded. 

An interrupt signal Indicating In the 
compatible mode that a WIM or MIW 
instruction should either empty or 
load the TMCC and in the extended 
mode indicating that the interlace 
word count Is zero. 



loc 



/Ir0/-/Irl4/ 
Iw 

Iwa 
Iwc 

Iwe 



Iwf 

Iwg 
Iwh, Iwi 

Iwj 
Iwk 



Iwp 



An interrupt signal indicating in the 
compatible mode that the input or out- 
put process has been terminated and 
the external device has been discon- 
nected and in the extended mode 
indicating that an End-of-Record 
condition has been detected. 

An Input/output control signal 
derived from Eom. 

Interlace address signals transmitted 
to the CPU. 

A flip-flop which when set denotes 
that the Interlace system is active. 

A signal which counts the interlace 
word and address counters when a 
memory access is performed. 

A signal occurring during the inter- 
lace loading sequence which clears 
the Interlace registers. 

A signal occurring during the EOM 
Instruction of an interlace loading 
sequence which sets the high order 
bits of the interlace counters and set 
several flip-flops used in the ex- 
tended mode. 

A signal denoting that the Interlace 
Word Count Register has reached zero 
word count. 

A flip-flop which when set denotes 
extended mode operation. 

Two flip-flops comprising the Channel 
Command Register used in the ex- 
tended mode to control terminal 
functions of the TMCC. 

The Channel Command Interrupt 
Enable flip-flop used in the extended 
mode to permit selective arming of 
the I2w interrupt signal. 

The Channel Command Interrupt Enable 
flip-flop used in the extended mode to 
permit selective arming of the Ilw 
Interrupt signal. 

A signal occurring during the POT in- 
struction of an Interlace loading 
sequence which sets Initial word count 
and memory address information into 
the Interlace Word and Address Counters. 



3-58 



September 1965 



SDS 900685 C 



/Kcc0/-/Kcc2/ 



/Kcclx/ 



MIt 

Mtgw 
Npw 

05, Pwy 

Pin 
Pot 
Qrl -Qr4 

(Qqi) 

Qw2 



Switch controlled signals from the 
Control Console used to select a 
particular TMCC or DACC for Unit 
Address and Error display on the 
Control Console. 

A switch controlled signal used to 
distinguish between TMCC W or Y 
a nd TMC C C or D. /Keel/ becomes 
/Kcclx/ for TMCC C or D. 

A signal decoded from /KccO/- 
/Kcc2/ such that when true enables 
displaying the TMCC-W Unit Address 
and Error status. 

A signal derived from memory indi- 
cating the DACC is in process of 
accessing the memory. 

The magnetic tape gap signal gener- 
ated by the magnetic tape system. 

A signal from external devices used 
to inhibit parity checking by the 
TMCC. When Npw is low, parity 
checking is inhibited. 

A signal from the CPU Operation 
Code Register, of the SDS 925 and 
930. "05" is always true from the 
9300. 

A signal from the CPU derived from a 
PIN instruction. 

A signal from the CPU derived from a 
POT instruction. 

The four flip-flops in the TMCC 
comprising the pulse counter. 

Timing signal sent to external devices 
which is true from T5 through TO. 

Timing signal sent to external devices 
which is true from T6 through T3. 

Timing signal sent to external devices 
which is true from T7 through T4. 

Timing signal which varies when a 
TMCC character length is expanded. 

A signal transmitted from the TMCC to 
the CPU def i ning whether the TMCC 
memory access operation isa load or store. 



/RaO/-/Ra3/ Signals from the TMCC to the CPU 
denoting which particular TMCC's 
are active. These signals are displayed 
on the SDS 9300 Control Console and 
not used on the SDS 930. 



/Rd9/-/Rdl4/ 



/Rde/ 



/ReO/-/Re3/ 



/RFT/-/Rr3/ 



Rti 



Rwl-Rw24 



Rwp 



Rwx 



Signals from the TMCC to the CPU 
denoting Unit Address Register con- 
tents for the particular TMCC selected 
for displays. These signals are dis- 
played on the Control Console. 

A signal from the TMCC to the CPU 
denoting the status of the Error 
Detector for the particular TMCC 
selected for display. This signal is 
displayed on the Control Console. 

Signals from the TMCC to the CPU 
denoting the Error Detector status for 
each particular TMCC. These signals 
are displayed on the SDS 9300 Con- 
trol Console and not used on the 
SDS 930. 

Serial data signals transmitted from 
the TMCC to the CPU during time 
share operations. 

A ready signal from the TMCC on ex- 
ternal devices used to release PIN or 
POT instructions from 02. 

A signal from the CPU to external 
devices indicating that a PIN instruc- 
tion has terminated. 

Twenty four flip-flops comprising the 
character buffer. Rwl through Rw6 
are basic. Rw7 through Rwl 2 are 
optionally added to expand the char- 
acter buffer to 12 bits. Rw7 through 
Rw24 are optionally added to expand 
the character buffer to 24 bits. TMCC 
Y, C, D are the only buffers which 
may be expanded. 

The parity flip-flop in the TMCC. An 
"odd" parity system Is used. 

A flip-flop in each TMCC which is 
set if a Time Share Request for the 
particular TMCC can occur. 



/Rwyl/-/Rwy3/ Serial data signals transmitted from 
the TMCC to the CPU during WIM 
instructions. 



3-59 



SDS 900685C 



September 1965 



Rx 



Sio 



A signal from f-he CPU denoting that W4 

a WIM or MIW instruction is 

occurring. 

A response signal from peripheral 

devices interrogated by an SKS W5 

instructions. 



A flip-flop in the TMCC which con- 
trols the precessing of data between 
the Character Buffer and the W 
register. 

A flip-flop which detects that a pre- 
cess should occur. 



Skss 



/ST^/ 



Ssc 



St 



Sys 



A signal generated in the CPU during 
SKS instructions and sent to external 
equipment to be used as a strobe. 

A signal generated by TMCC's or 
DACC's which is sent to the CPU for 
interrogation during SKS instructions. 

A response signal from external sys- 
tems equipment interrogated by SKS 
instructions. 

A signal from the CPU derived from 
the manual start button. 

A control signal for systems commu- 
nication derived from EOM. 



T8, T7-T0, Timing pulses used in the TMCC de- 

T6 + T5, T6-T0, coded from the Pulse Counter, Qrl 
T4-T0, T3-T0, TO through Qr4. 



Tpc 



A timing pulse from the CPU used to 
synchronize the Pulse Counter, Qrl 
through Qr4 in the TMCC with the 
Pulse Counter, Ql through Q6, in 
the CPU. 



W6 A flip-flop which detects that an 

external clock is present. 

W7, W8 Two flip-flops comprising the 

Character Counter. 

W9 A flip-flop which is part of the Unit 

Address Register defining whether a 
process is Input or output. 

W10-W14 The Unit Address Register which des- 

ignates to the TMCC and peripheral 
devices which device Is activated. 

Wa0-Wal4 Fifteen flip-flops comprising the 

Interlace Address Register. 

Wbl-Wb3 Inputs to the W register from the 

Character Register which will vary 
depending on whether the TMCC Is 
expanded. 

Wc The signal which resets the TMCC and 

prepares It for a new operation. 

Wc0-Wcl4 Fifteen flip-flops comprising the 

Interlace Word Counter. 



Trq 



Trqx 



Trqw 



Tsm 



Tsr 



A signal transmitted from the TMCC We 

to the CPU indicating that a TMCC 

requests a Time Share operation. Wes 

A signal transmitted from TMCC C 

and D indicating to TMCC W and Y Wev 

that TMCC C and D are requesting a 

Time Share operation. 

A signal generated by TMCC-W in- 
dicating that TMCC-W is requesting Wf 
a Time Share operation. 

A signal from the CPU indicating that 
the interlace address counter Infor- 
mation has been received by the CPU. 9 

A signal from the CPU indicating 

that a Time Share operation is In Wh 

process. 



The Error Detector flip-flop. 

An error signal from peripheral 
devices. 

A signal which when true indicates 
that the Character Counter Is set to 
the same character count as It was 
when Initially set up by the EOM. 

A flip-flop which when reset denotes 
on input that the W register Is full 
and on output that the W register is 
empty. 

A flip-flop used to detect End-of- 
Record conditions. 

The Halt Detector flip-flop. 



3-60 



September 1965 



SDS 900685 C 



Paragraphs 3. 185 to 3. 188 



Whs 

Wnl-Wn3 

WO 



Wpa 

Wrl-Wr3 
Ws 

Wsc 
Wwl-Ww3 

Wxx 

Zwl-Zw24 
Zwp 



A halt signal from peripheral devices. 

The "now" flip-flops of the W register. 

The Halt Interlock flip-flop used on out- 
put to enable the Halt Detector after out- 
put has been termi noted and used on i nput 
to denote that the input process has pro- 
ceeded to process characters. 

The PIN Address Counter flip-flop 
which when set allows a PIN instruc- 
tion to interrogate the Interlace 
Address Counter. 

The "read" flip-flops of the W register. 

The signal derived from an EOM in- 
struction which initially sets up the 
TMCC. 

The Signal Complete flip-flop. 

The signals which permit "writing" 
into the W register. 

A signal which denotes that an MIW, 
WIM or Time Share operation is 
occurring. 

The twenty four inputs to the Charac- 
ter Register from peripheral devices. 

The input to the Parity flip-flop from 
peripheral devices. 



3.185 LOGIC EQUATIONS 

3.186 Pulse Counter 

sQrl = Tpc + Qr2 Qr3 Qr4 
rQrl = Qr2 

sQr2 = Qrl Q^ Qr4 

(Qr4 + T0)+Qrl Qr3 
rQr2 = QrT 

sQr3 = Qrl Qr4 

rQr3 = Qr3Qr4(Qr4+T0) 

sQr4 = Qrl Qr3 

rQr4 = QrT Qr2 





Qrl 


Qr2 


Qr3 


Qr4 


Tp 














T8 


1 











17 


1 








1 


T6 


1 


1 




1 


T5 





1 




1 


T4 










1 


T3 













T2 


1 










Tl 


1 


1 







TO 





1 







Tr 














Tp 















T8 

T6 + T5 
T7 -T4 
T7 -TO 
T6 -TO 
T6 -T3 
T3 -TO 
TO 

T5 -Tl 
T5 -TO 



Qrl Qr3 Qr4 

Qr2 Qr4 

Qr4 

Qr3 + Qr4 

Qr3 

(Qr4 + on Q^) Qr3 

Qr3 Qr4 

QrT Qr2 Qr4 



= Qr3 Qrl Qr4 TO 



= Qr3 Qrl Qr4 



3.187 Buc, loc, Sys, etc. 

Buc = Eom CTO CTT cT* 

loci = Eom CTOCII 

loc = loci cT E7Qr3* 

Sys = Eom ClOCll C9 

*CT becomes CI for TMCC-C and TMCC-D 

3. 188 CPU Signals Received 



CO 

CI 

C2 

C3 

C4 

C5 

C6 

C7 

C8 

C9 

CIO 

Cll 

C12 

C13 

C14 

C15 

C16 

C17 



= /CiO/ 



/CiT7/ 



3-61 



Paragraphs 3. 189 to 3. 190 



SDS 900685 C 



September 1965 



CIS 
C19 
C20 
C21 
C22 
C23 

Tpc 
Eom 
Pot 1 
Pin 

W\ 
Cpr 

C21r 

C22r 

C23r 

Rx 

Tsm 
Tsr 
Clx 

Pwy 

Mft 

En+ dn) 

St 

Skss 

Kccw 



= /ens/ 



= /Ci23/ 

= Ap^/ 

= /W 
= /Ph^/ 

= /W_ 
= /c^/ 



= /C21r/ 



= /C22r/ 



= /C23r/ 

= /W 
= /Ti^ 

= /W_ 

= /CbT/ *ForTMCC-CanclTMCC-D: 
— Clx = /CT^/ 

= /Pwy/ (Pwy = 05 for 92200 
and 92210) 

= /MIt/ 



= /En+ Qn) / 

= /W 
= /Sl^/ 

= /KccO/ + /Kcc 1/ + /Kcc2/* 



= /Kcc2/ 



Kcc2 

Kccy = /KccO/ + /Kcc 1/+/KS/* 

*For TMCC-C and TMCC-D, /Keel/ becomes /K^/ 
3. 189 Input/Output Signals Generated 



(cD 
(2) 
(3) 

(3) 



= CO 
= CI 
= C2 
= C3 
= C4 
= C5 
= C6 





= C7 
= C8 
= C9 
= CIO 
= Cll 
= C12 
= C13 
= C14 
= C15 
= C16 
= C17 
= C18 
= C19 
= C20 
= C21 
= C22 
= C23 
= C17 
= Cpr 



(93200 and 92331 only) 



= Qr3 (Qrl Qr4) = T5 - TO 

= (T7 - T3) Qr3 = T6 - T3 

= Qr4 = T7 - T4 Replaces Mtgw on POT 
connectors at 23F & 24F 

= Buc 

= loc 



= Eom Er 

= Sys (T5 - Tl) Tsr Pwy (delete Pwy for 

92200and 92210) 

= St 

= Pin 

= Pot 1 

= Pot 1 (T5 - Tl) Tsr Pwy (delete Pwy for 

92200and92210) 

= Rfi 

= Skss 



3.190 CPU Signals Generated 



/Rd9/ = W9 Kccw Y9 Kccy 



/RdTO/ = WIO Kccw YIO Kccy . . . 



3-62 



September 1965 



SDS 900685C 



/Rdll/ 



= Wll Kccw Yll Kccy 



/RdT2/ 



= W12 KccwY12 Kccy . . . 



/Rdia/ 



= W13 Kccw Y13 Kccy . . 



/Rdl4/ 
/Rdi/ 

/R^V 



= W14 Kccw Y14 Kccy 



= We Kccw Ye Kccy . . 



= WlOWll W12 W13 W14 
/R^/forTMCC-C 



= YlOYll Y12 Y13 Y14 

/R^/forTMCC-D 



/ReO/ 




= We 


/Re2/forTMCC-C 


Ael/ 




= Ye 


/Re3/forTMCC-D 


/Wf(WO 


4-W9)/ 


= Wf (WC 


) + W9) 


/Yf(Y04 


Y9)/ 


= Yf (YO 


+ Y9) 


Arc/ 


= Trqw Trqy Trqx 


/Ilw/ 




= Ilw 


/lie/ for TMCC-C 


/I2w/ 




= I2w 


/I2c/ for TMCC-C 


/iiy/ 




= Ih 


/Ild/for TMCC-D 


/I2y/ 




= I2y 

= Skr 


/I2d/forTMCC-D 


/STrz/ 


ClOCn Ssc CI C9 




ciocn sio . . .* 


1 becomes CI fo 


' TMCC-C 


and TMCC-D 



/Rrl/ 
/M/ 



= Wrl Rwx Yrl Ryx 



= Wr2 Rwx Yr2 Ryx . 
= Wr3 Rwx Yr3 Ryx . 



/Rwyl/ 



= Wrl Pwy Yrl Pwy 

(Pwy = 05 for 92200 and 92210) 



/Rwy2/ 



/Rwy3/ 




Wr2 Pwy Yr2 Pwy 

(Pwy = 05 for 92200 and 92210) 

Wr3 Pwy Yr3 Pwy 

(Pwy = 05 for 92200 and 92210) 

=(cS^ 











(W) 



/W 

m/ 
/w 

/li^/ 

/i^/ 

/w 
/w 

/IFTO/ 
/IH"1/ 
/i7T2/ 
/Fl3/ 
/WU/ 

m/ 




Ya9 Ypa . 



= (Cd 1 9)Wa 1 Wpa Ya 1 Ypa 



= (Cd20)Wa 1 1 Wpa Ya 1 1 Ypa . 



;^d2i;Wal2 Wpa Yal2 Ypa . 
= (^^Wal3Wpa Yal3Ypa . 



= ^^d2^Wal4Wpa YaUYpa . 

=CS)Wap + Ew Yap + Ey . . . 

=(^^ (93200 and 93221 
only) 



Bt) (93200 and 93221 only) 



= WaO Rwx YaO Ryx . 
= Wa 1 Rwx Ya 1 Ryx . 
= Wa2 Rwx Ya2 Ryx . 
= Wa3 Rwx Ya3 Ryx . 
= Wa4 Rwx Ya4 Ryx . 



= Wa5 Rwx Ya5 Ryx 
= Wa6 Rwx Ya6 Ryx 



= Wa7 Rwx Ya7 Ryx . 



= Wa8 Rwx Ya8 Ryx . 



= Wa9 Rwx Ya9 Ryx . 



= WalO Rwx YalORyx 



= Wall RwxYall Ryx 



= Wo 12 RwxYal2 Ryx 



Wal3 Rwx Yal3 Ryx 



Wal4 Rwx Ya 14 Ryx 
W9 Rwx Y9 Ryx . . . 



3-63 



Paragraphs 3. 191 fo 3.202 



SDS 900685 C 



September 1965 



3.191 TMCC Signals Received 

Er = /Txl 

Trqx = /Trqx/ 

3. 192 Input/Output Signals Received 



sW5 = W5 W6 Ecw TO + Ws C13 C18 TO WIO Wl 1 



Sio 
Ssc 



= QSio^ 
= CSsc. 



3. 193 TMCC Signals Generated 

/eT/ = B^Ef. . . 
/TF^/= Ti^ T>^ 

3. 194 LOGIC EQUATIONS FOR W BUFFER 

3.195 Unit Address Register 
sWU = Ws C23 
rW14 = Wc 

sW13 = WsC22 

rW13 = Wc 

sW12 = WsC21 

rW12 = Wc 

sWll = WsC20 

rWll = Wc 

sWlO = WsC19 + (Ioc C12CI7CT9 
C20 C2T C22 C23) W9"wTo 

rWlO = Wc 

3.196 Input/Output 

sW9 = Ws CIS 
rW9 = Wc 

3.197 Clear and Set Signals 

Wc = Buc CT7 (T6 + T5) + Wh Wf (T3 -TO) + St 
Ws = Buc CTZ (T3 - TO) 

3. 198 Clock Counter 







W12 W13W14 


rW5 


= 


W4 TO + Wc 


sW4 


= 


W5 Wf TB W5 




+ 


WsTO 




+ 


Wh Wf T8 




+ 


Iwg W9 Iwi W5 Iwf T8 




+ 


Iwg Wg Wf WO Wev I\a 
Wll Wh 


rW4 


= 


W4 TO + W4 T8 


3.199 


Character Counter 


sW8 


= 


WsC16 




+ 
+ 


W7 W8 W4 TO 




Wxx Wn2 (T7 - TO) W4 




+ 


W7 W9 WIO Wll Wfi 


rW8 


= 


W8 W4 TO + Wc 



sW7 = WsC15 



+ Wxx Wnl (T7 -TO) W4 
rW7 = Wc 

+ W7W8W4T0 

3.200 Character Counter Even 



sW6 = W5 EcwT8W10 Wll W12 W13 W14 
rW6 = W5T0 + WC 



Wev = W8 Wn2 W7 Wnl + W8 Wn2 W7 Wnl 
+ W8 Wn2 W7 Wnl + W8 Wn2 W7 Wnl 

3.201 Halt Interlock 

sWO = W9W6W8ECW 
+ WsC18W9 

rWO = Wc 

+ (loc C12CT7Cl9C20C2l C22C23)W9T0 
+ W9 Iw Iwf (Iwg + 1^ + I^) T7 - TO 

3.202 Computer Interlock 
sWf = WcWh 

+ Iwo Mit TO 

+ Rx TO Pwy *(Pwy = 05 for 92200) 

*Rx is always false for TMCC-C 



3-64 



September 1965 



SDS 900685 C 



Paragraphs 3.203 to 3.212 



rWf = W7 W8 W4 (T6 + T5) 
+ Ws C18 
+ W9W10Wn WOMtgw W7 (T6 + T5)Wh 

3.203 End -of -Record Detector 



3.208 Load Buffer from C 



sWg = MtgwT0IwgWll(W0W9+W0W5W6W9) 
+ Whs T7 - TO WTO WTl WT2 WT3 WU 



rWg 



+ W9 WToWn W12 WT3 (R^l R^ R^ 
Rw4 Rw5 Rw6 Rw^) W5 17 - TO 

wTowTTwT2 wTs wll 

= Wc 

+ Wg i^ Wl 1 TO 



3.204 Halt Detector 



sWh 



= Wg Iwg T8 
+ Whs Wll T8 



rWh 



+ Wg W9 WTl h^ (Iwf + Wev Wf) T8 Iwg 
+ W9 Wl 1 WO W5 W6 (i^ + Iwi I^) T8 
+ W9 WTl Iwg I^ Iwl Iwf T8 WO 
+ W9 i^ T8 Whs 
= Wc (T6 + T5) 
+ Wh WfT8 



3.205 Signal Complete 

sWsc = Wg Iwg Iwh (Wev Wf + Iwf) T8 
+ WhWfT8 + St 
+ Ws 09 C20 C2i C22 C23 

rWsc = Wsc T8 iwg 

3.206 Interrupt Signals 

Ilw = Wf WO Wh (En + (g)) Iw Ew Iw^ 

+ Iwg Iw Iwf Iwk 

I2w = (En +Cln) ) I^ Wh Wf 

+ Wsc Iw| Iwg 

3.207 WIM + MIW Interlock = 

Wf (W0+W9J 



Wxx 



Rx Pwy + Rwx Tsr Iw* 

(Pwy = 05 and Iw deleted from 92200) 



*Rx is always false for TMCC-C 

3.209 Time Share Request 
Trqw = Wf WO Wh Iw I^ 

3.210 Time Share Select 



sRwx = Tsm Trqw Trqy Trqx (T7 - TO) 
rRwx = Tsm TO 

3.211 Time Share Priority 

Trqx = Priority signal from TMCC-C and TMCC-D 

Trqx = Trq(c) + Trq(d) 

Trq = Trqx + Trqw + Trqy 

3.212 W Register 



Wwl 



= W4 W7 (T7 - TO) 



+ W4Wnl (T7 -TO) 
+ W4Wnl W^ 
+ W4Wbl (T7 -TO) * 
+ W4C21r (T7 -TO) Wxx 



Ww2 



= W4 W8 (T7 - TO) 



+ W4 Wn2 (T7 - TO) 
+ W4 Wn2 W^ 
+ W4Wb2 (T7 -TO)* 
+ W4 C22r (T7 - TO) Wxx 

sWrl, 2, 3 = Wwl, 2, 3 Delayed by 9 pulse times 
sWnl, 2, 3 = Wrl, 2, 3 respectively 



Wbl =Wxl2 Wx24Rw4 + Wxl2 RwlO 
+ Wx24 Rw22 



Wb2 = Wxl2 Wx24 Rw5 + Wxl2 Rwl 1 
+ Wx24Rw23 



for 93200 
^and 93221 



3-65 



Paragraphs 3.213 to 3.215 



SDS 900685,C 



September 1965 



Ww3 = W4Wn3Wxx 
+ W4 Wb3 * 
+ W? C23r Wxx 



3.214 Chorocter Buffer Extended to 12 Bits 



* Wb3 = Wxl2 Wx24 Rw6 + Wxl2 Rwl2 for 93200 
+ Wx24Rw24 and 93221 

Wbl, 1, 3 equals Rw4, 5, 6 respectively for 92200 
Wbl, 2, 3 equals RwlO, 1 1, 12 respectively for 92201 
Wbl, 1, 3equalsRw22,23,24 respectively for 92202 

3.213 Character Buffer * 

sRwl = W4 W^ (T7 - TO) Wnl + W9 W6W5Zwl + 

W4WxxC21r 
rRwl = W4W^ VWTi + W9 WTWS W4 + 

W4 Wxx C2T7 

sRw2 = W4 W^ (T7 - TO) Wn2 + W9 W6 W5 Zw2+ 

W4 Wxx C22r 
rRw2 = W4W^ Wi^ + W9 W6 W5 W4 + 



W4 Wxx C22r 

sRw3 = W4 W^ (T7 - TO) Wn3 + W9 W6 W5 

Zw3 + W4 Wxx C23r 

rRw3 = W4 W^ Wn3 + W9 W6 W5 W4+ 

W4 Wxx C237 

sRw4 = W4 R^ Rwl + W9 W6 W5 Zw4 
rRw4 = W4Rw4RVi +W9 W6W5 W4 

sRw5 = W4 Rw5 Rw2 + W9 W6 W5 Zw5 
rRw5 = W4 Rw5 R^ + W9 W6 W5 W4 

sRw6 = W4 R^ Rw3 + W9 W6 W5 Zw6 
rRw6 = W4 Rw6 Rw3 + W9 W6 W5 W4 

*For 12-bit extension, add Rw7 through Rwl2 
For 24-bit extension, add Rw7 through Rw24 



Character Size 

12 bit character = Wxl2 
24 bit character = Wx24 



(93200 and 93221 only) 
(93200 and 93221 only) 



sRw7 


= W4 Rw7 Rw4 + W9 W6 W5 Zw7 


rRw7 


= W4 Rw7 Rw4 + W9 W6 W5 W4 


sRw8 


= W4 Rw8 Rw5 + W9 W6 W5 Zw8 


rRw8 


= W4 Rw8 Rw5 + W9 W6 W5 W4 


sRw9 


= W4 Rw9 Rw6 + W9 W6 W5 Zw9 


rRw9 


= W4 Rw9 Rw6 + W9 W6 W5 W4 


sRwlO 


= W4 RwlO Rw7 + W9 W6 W5 ZwlO 


rRwlO 


= W4 RwlO Rw7 + W9 W6 W5 W4 


sRwll 


= W4 Rwl 1 Rw8 + W9 W6 W5 Zwl 1 


rRwll 


= W4 Rwl 1 Rw8 + W9 W6 W5 W4 


sRwl2 


= W4 Rwl2 Rw9 + W9 W6 W5 Zwl2 


rRwl 2 


= W4 Rwl2 Rw9 + W9 W6 W5 W4 


.215 Character Buffer Extended to 24 Bits 


sRwl3 


= W4 Rwl3 RwlO + W9 W6 W5 Zwl3 


rRwl 3 


= W4 Rwl3 RwlO + W9 W6 W5 W4 


sRwU 


= W4Rwl4Rwll + W9 W6 W5Zwl4 


rRwl 4 


= W4Rwl4Rwn +W9 W6 W5 W4 


sRwl5 


= W4 Rwl5 Rwl2 + W9 W6 W5 Zw15 


rRwl 5 


= W4 Rwl5 Rwl2 + W9 W6 W5 W4 


sRwl6 


= W4 Rwl6 Rwl3 + W9 W6 W5 Zwl6 


rRwl 6 


= W4 Rwl6 Rwl3 + W9 W6 W5 W4 


sRwl7 


= W4 Rwl7 Rwl4 + W9 W6 W5 Zwl7 


rRwl 7 


= W4 Rwl7 Rwl4 + W9 W6 W5 W4 


sRwlS 


= W4 Rwl8 Rwl5 + W9 W6 W5 Zwl8 


rRwl 8 


= W4 Rwl 8 Rwl5 + W9 W6 W5 W4 


sRwl9 


= W4 Rwl 9 Rwl6 + W9 W6 W5 Zwl9 


rRwl 9 


= W4 Rwl9 Rwl6 + W9 W6 W5 W4 


sRw20 


= W4 Rw20 Rwl7 + W9 W6 W5 Zw20 


rRw20 


= W4Rw20Rwl7 + W9 W6W5 W4 


sRw21 


= W4 Rw21 Rwl8 + W9 W6 W5 Zw21 


rRw21 


= W4 Rw21 Rwl8 + W9 W6 W5 W4 


sRw22 


= W4 Rw22 Rwl9 + W9 W6 W5 Zw22 


rRw22 


= W4 Rw22 Rwl9 + W9 W6 W5 W4 



3-66 



September 1965 



SDS 9008650 



Paragraphs 3.216 fo 3.225 



sRw23 
rRw23 

sRw24 
rRw24 



= W4 Rw23 Rw20 + W9 W6 W5 Zw23 



rWe 



= Wc Wh 



= W4 Rw23 Rw20 + W9 W6 W5 W4 



= W4 Rw24Rw21 + W9 W6 W5 Zw24 



= W4 Rw24 Rw21 + W9 W6 W5 W4 



3.216 Parity Flip-Flop 

sRwp = W9 W4R^ (Wbl © Wb2 © Wb3) 

(T7 - TO) Qwl * 
+ W9W4"R^ W^(Wnl@Wn2©Wn3) 

Qw2 (T7 - TO) * 
+ W9 W4 R^ Wxx Cpr Qw2 {17 - TO) * 
+ W9 W6 W5 Zwp 

+ wf W5 T8 r;;;;^ 

rRwp = W9 W4 Rwp (Wbl©Wb2©Wb3) 

(T7 - TO) Qwl * 
+ W9 W4 Rwp W^ (Wnl0Wn20Wn3) 

Qw2 (T7 - TO) * 
+ W9 W4 Rwp Wxx Cpr Qw2 (T7 - TO) ■" 
+ W9 W6 W5 W4 
+ Wf W5 T8 W9 Rwp 
+ Wc 



* Qwl = Wxl2 Qr4 + Wxl2 Wx24 Qrl Qr4 
(for 93200 and 93221) 



Qw2 = Wxl2 Qr4 + Wxl2 Wx24 Qr2 Qr4 

(for 93200 and 93221) 
Qwl= Qrl Qr4 for 92200 
Qwl= Qr4 for 92201 

Qwl is deleted for 92202 
Qw2= Qr2 Q?3 for 92200 
Qw2= QF4 for 92201 
Qw2 is deleted for 92202 

3.217 Error Detector 



sWe = W9 W6 W5 W4 Rwp Wg Npw 
(Iwg + Iwi + Iwf) 
+ W0W6 W5 Ecw T8 
+ Wes 



3.218 Interlace Prepare 

sEw = Iwc Ew (T3 - TO) 

rEw = Wc TO 

+ Pot 1 (T3 -TO) Ew 

3.219 Interlace Clear 
Iwc 



Eom C9 CIO CI C17 (T3 -TO) 



* Cl becomes CI for TMCC-C 

3.220 Interlace Load 

Iwp = Pot 1 (T6 - T5) Ew 

Iwe = loc 1 (T6 + T5) Ew 

3.221 Interlace Active 



slw 



Pot 1 (T3 - TO) Ew Iw 



rlw = Iwf T8 (T7 - TO) 

+ (Wc + Iwc + Ws CT9 C20 C21 C22 C23) 
(T3 - TO) Iw 

3.222 Zero Count 

Iwf = WcO Wcl Wc2 Wc3 Wc4 Wc5 Wc6 Wc7 

Wc8 Wc9 WclOWcll Wcl2 Wcl3 Wcl4 
Ew 

3.223 Interlace Count Trigger 
Iwa = Rwx Tsm 

3.224 Interlace Counter Clock Enables 

Computer Clock Enable: Ew Iw 

Counter Clock Enable: Ew 

3.225 Extend Operations 
slwg = Iwe C12 



rlwg = Iwc+WscT8W10WllW12 W13W14Iwg 

3-67 



Paragraph; 


5 3.226 to 3. 229 

□nnel Command Interrupt Enables 


SDS 900685, C 

sWc4 




September 1965 


3.226 Ch( 


Iwc + Ew Wc4 Wc5 Ew 


slwj 


= 


IweC13 


(Eor) 


rWc4 


= 


Iwe C23 + Ew Wc4 Wc5 Ew 


rlwj 


= 


Iwc + I2w T8 Iwj 




sWc3 


= 


Iwc + Ew Wc3 Wc4 Wc5 Ew 


slwk 


= 


Iwe C14 


(Iwf) 


rWc3 


= 


Iwe C22 + Ew Wc3 Wc4 Wc5 Ew 


rlwk 


= 


Iwc +Ilw T8 Iwk 




sWc2 
rWc2 


=: 


Iwc +EwWc2 Wc3Wc4.Vyc51w 
Iwe C21 + Ew Wc2 Wc3 Wc4 Wc5 Ew 


3.227 Chi 


annel Command Register 


















sWcl 


= 


Iwc +EwWclWc2Ew 


slwh 


= 


Iwe C 15 




rWcl 


= 


Iwe C20 + EW Wcl Wc2 Ew 


rlwh 


— 


Iwc 




sWcO 


_ 


Iwc +Ew WcOWcl Wc2 Ew 


siwi 


= 


Iwe C16 




rWcO 


= 


Iwe C19 


rlwi 


= 


Iwc 


















3.229 Adc 


Iress Counter 


3.228 Wo 


rd Counter 




sWaM 


_ 






Iwc + Ew Wal4 Iwa Ew 


sWcl4 


= 


Iwc + Ew Wcl4 Iwa Ew 




rWal4 


= 


Iwp C23 + Ew Wal4 Iwa Ew 


rWcU 


= 


Iwp C9 + Ew Wc 1 4 Iwa Ew 




sWal3 
rWal3 


= 






Iwc + Ew Wal3 Wal4 Iwa Ew 


sWcl3 


Iwc ' +EwWcl3 Wcl4Ew 


Iwp C22 + Ew Wal3 Wal4 Iwa Ew 


rWc13 


= 


IwpC8 + Ew Wcl3 Wcl4Ew 




sWal2 


_ 






Iwc + Ew Wal2 Wal3 Ew 


sWcl2 


= 


Iwc +Ew Wcl2 Wcl3Wcl4Ew 




rWal2 


= 


Iwp C21 +EwWal2 Wal3 Ew 


rWcl2 


= 


Iwp C7 + Ew Wcl2 Wcl3 Wcl4 Ew 




sWall 


_ 






Iwc + Ew Wall Wal2WaJJLEw 


sWcll 


= 


Iwc + Ew Well Wcl2 Wcl3 WcUEw 


rWall 


= 


Iwp C20 + Ew Wal 1 Wal2 Wal3 Ew 


rWcll 


= 


Iwp C6 + Ew Well Wcl2Wcl3Wcl4Ew 


sWalO 


_ 






Iwc +Ew WalOWall Wal2WflIILEiiL 


sWclO 


= 


Iwc + Ew WclO Well Ew 




rWalO 


= 


Iwp C19 + Ew WalO Wall Wal2 Wal3 Ew 


rWclO 


= 


Iwp C5 + Ew WclO Well Ew 




sWa9 
rWa9 


= 






Iwp C18 + Ew Wa9 WalO Ew 


sWc9 


Iwc + EwWc9 WclO Well Ew 


Iwc +EwWa9WalOEw 


rWc9 


= 


Iwp C4 + Ew Wc9 WclO Wcl 1 Ew 


















sWa8 


= 


Iwp C17 + Ew Wa8 Wa9 WalO Ew 


sWc8 


= 


Iwc + Ew Wc8 Wc9 Wc 1 Well Ew 


rWa8 


= 


Iwc +E^Wa8Wa9WalOE^ 


rWcS 


= 


IwpC3 + EwWc8Wc9 WclO Well 1 


Ew 








sWc7 


= 


Iwc + Ew Wc7 Wc8 Ew 




sWa7 
rWa7 




Iwp C16 + Ew Wa7 Wa8 Wa9 WalO Ew 
Iwc + Ew Wa7 Wa8 Wa9 Wa 1 Ew 


rWc7 


_ 


Iwp C2 + Ew Wc7 Wc8 Ew 
Iwc + Ew Wc6 Wc7 Wc8 Ew 




sWa6 


= 




sWc6 


Iwp C15 + Ew Wa6 Wa7 Ew 


rWc6 


= 


Iwp CI + Ew Wc6 Wc7 Wc8 Ew 




rWa6 


= 


Iwc + Ew Wa6 Wa7 Ew 


sWc5 


= 


Iwc + Ew Wc5 Wc6 Wc7 Wc8 Ew 




sWa5 


= 


Iwp C14 + Ew Wa5 Wa6 Wa7 Ew 


rWc5 


= 


Iwp CO + Ew Wc5 Wc6 Wc7 Wc8 Ew 




rWa5 


= 


Iwc + Ew Wa5 Wa6 Wa7 Ew 



3-68 



September 1965 



SDS 900685. C 



Paragraphs 3. 230 t-o 3. 233 



sWa4 
rWa4 

sWa3 
rWa3 

sWa2 
rWa2 

sWal 
rWal 

sWaO 
rWoO 



= Iwp C13 + Ew Wa4 Wa5 Wa6 Wa7 Ew 
= Iwc + E^ Wa4 Wa5 Wa6 WoTJw 

= Iwp C12 + E^ W^ Wa4E^ 
= Iwc + Ew Wa3 Wa4 Ew 

= Iwp Cn + E^ WS Wa3 Wa4B^ 



= Iwc 



+ Ew Wa2 Wa3 Wa4 Ew 



= Iwp CIO + Ew Wal Wa2 Wa3 Wa4 Ew 
= Iwc +E^ Wal Wa2 Wa3Wa4|w 

= Iwe C18 +Ew Wab Wallw 
= Iwc 



3.230 PIN Address Counter 



sWpa = loc C17 C13C19 C20C21 C22C23T0 
rWpa = Pin TO + St 

3. 231 Skip Gate: 



Skr 



= CI C17 C9 ClOCll C19 C20C21 C22 
C23 C15 Wsc* 



+ CI C17 C9 ClOCll C19 C20C21 C22 



C23 C12 WIO Wl 1 W12 W13 W14* 
+ cl Ci7C9 CTOCII CT9C20C21 C22 
C23 C13 Iwf* 



+ Cl C17C9 ClOCll C19 C20C21 C22 
C23 CUW^* 



+ CIO Cll C14W10 Wn W12 W13 W14C1* 
+ ClOCTT C20WeCl* 

+ 

*C1 becomes Cl for TMCC-C 

3.232 Input/Output Signals Received 

Zwp = (Zwp) 

Zwl =(Z^ 

Zw2 =(Z^ 

Zw3 =(Z^ 

Zw4 

Zw5 

Zw6 







(93200 and 93221 only) 
(93200 and 93221 only) 



3.233 Input/Output Signals Generated 




.RwlO = RwlO 
.RwlP = Rwll 



3.69 



Paragraphs 3. 234 to 3. 240 



SDS 900685C 



September 1965 



3.236 Input/Output 









3.234 LOGIC EQUATIONS FOR Y BUFFER 

3.235 Unit Address Register 

sY14 = Ys C23 
rY14 = Yc 

sY13 = Ys C22 
rY13 = Yc 

sY12 = Ys C21 
rY12 = Yc 

sYll = YsC20 
rYll = Yc 

sYlO = Ys C19 +(Ioc C12 C17 09 020 C21 C22 

C23) Y9 yTO 
rYlO = Yc 



sY9 


= YsC18 


rY9 


= Yc 


3.237 


Clear and Set Signals 


Yc 


= Buc C17 (T6 + 15) + Yh Yf (T3 - TO) + St 


Ys 


= BucC17(T3 -TO) 


3.238 


Clock Counter 


sY6 


= Y5 Ecy TSYIOYH Y12Y13 Y14 


rY6 


= YSTO + Yc 


sY5 


= Y5Y6 Ecy T0+YsC13C18T0 




YlOYll Y12Y13Y14 


rY5 


= Y4T0 + YC 


sY4 


= Y5 Yf T8 Yg 




+ YsTO 




+ YhYfTS 




+ lyg Y9 lyi Y5 lyf T8 




+ lyg Yg Yf YOYevIyTS "Y7Y9 YlOYll Yh 


rY4 


= Y4T0 + Y4T8 


3.239 


Character Counter 


sY8 


= YsC16 




+ Y7Y8Y4T0 




+ Yxx Yn2 (T7 - TO) Y4 




+ Y7Y9 YlOYll Yh 


rY8 


= Yc 




+ Y8Y4T0 


sY7 


= YsC15 




+ YxxYnl (T7 - TO) Y4 


rY7 


= Yc 




+ Y7Y8Y4T0 


3.240 


Character Counter Even 



Yev = Y8 Yn2 Y7 Ynl + Y8 Yn2 Y7 Ynl 

+ Y8 Y>^ Y7Wl +Y8 Yn2 Y7 Yivi 



3-70 



September 1965 



SDS 900685C 



Paragraphs 3. 241 to 3. 252 



3.241 Halt Interlock 



sYO = Y9 Y6 Y8 Ecy 

+ YsC18Y9 
rYO = Yc 

+ (loc C12 C17 CT9 C20 C2T C22 C23) 
Y9T0 



+ Y9 ly lyf (lyg + lyh + lyi) 17 - TO 

3.242 Computer Interlock 

sYf = Yc Yh 

+ lya Mit TO 

+ RxTOPw^ * (Pw^ = 05 for 92210) 
rYf = Y7Y8Y4(T6 + T5) 

+ YsClB 

+ Y9 YlOYll YOMtgy Y7 (T6 + T5) Yh 

*Rx is always false for TMCC-D 

3.243 End -of -Record Detector 

sYg = Mtgy TO lyg Y 1 1 (YO Y9 + YO Y5 Y6 Y9) 



rYg 



+ YhsT7 -TO YlOYll Y12Y13Y14 
+ Y9 yTo yTi Y12 yTs ( r7i Ry2 Ry3 M 

R^ R^' r^) Y5 17 -TO yTo yTi YT2 

yT3yT4 
= Yc 
+ Yg l7g Yll TO 



3.244 Halt Detector 
sYh 



= Yg lyg T8 

+ YhsYll T8 

+ Yg Y9 yTI i^i (lyf + Yev Yf) T8 lyg 

+ Y9 yTI YO Y5 Y6 (I^ + lyi lyh) T8 



rYh 



+ Y9 Yll lyg lyh lyi lyf T8 YO 
+ Y9 I^Yhs T8 

= Yc (T6 + T5) 
+ Yh Yf T8 



3.245 Signal Complete 

sYsc = Yg lyg lyh (Yev Yf + lyf) T8 

+ Yh Yf T8 + St 

+ Ys 09 C20 C2T C22 C23 
rYsc = Ysc TO lyg 

3.246 Interrupt Signals 

Ily = Yf YO Yh (En + (Jn) ) b' Ey lyg 

+ lyg ly lyf lyk 

I2y = (En+d^) I^^YhYf 

+ Ysc lyj lyg 

3.247 YIM + MIY Interlock = 

Yf (Y0 + Y9) 

3.248 Load Buffer from C 

Yxx = Rx Pwy + Ryx Tsr ly * (Pwy = 05 and ly 

deleted for 922 10) 

*Rx is always false for TMCC-D 

3.249 Time Share Request 
Trqy = Yf YO Yh ly I^ 

3.250 Time Share Select 



sRyx = Tsm Trqy Trqx (T7 - TO) 

rRyx = Tsm TO 

3.251 Time Share Priority 

Trqx = Priority Signal from TMCC-C and TMCC-D 

Trqx = Trq(c) + Trq(d) 

Trq = Trqx + Trqw + Trqy 

3.252 Y Register 



Ywl = Y4Y7(T7 -TO) 



+ Y4Ynl (T7 -TO) 
+ Y4Ynl Y^ 



3-7? 



Paragraphs 3. 253 to 3. 255 



SDS 900685.C 



September 1965 



+ Y4Ybl {17 -TO) * 
+ Y4C21r(T7 -TO) Yxx 



Yw2 = Y4Y8(T7 -TO) 



Yw3 



+ Y4Yn2(T7 -TO) 
+ Y4Yn2 Y^ 
+ Y4Yb2 (T7 -TO) * 
+ Y4 C23r (T7 - TO) Yxx 

= Y4Yn3 "VV^ 
+ Y4 Yb3 * 
+ Y4 C23r Yxx 



sYrl,2, 3 = Ywl, 2, 3 delayed by 9 pulse times 
sYnl,2,3 = Yrl, 2, 3 respectively 



Ybl = Yxl2 Yx24 Ry4 + Yxl2 RylO 
+ Yx24 Ry22 



\ 



Yb2=Yxl2Yx24Ry5+Yxl2 Ryll 
+ Yx24 Ry23 



} for 93221 



/ 



Yb3=Yxl2 Yx24Ry6+Yxl2 Ryl2 
+ Yx24 Ry24 

Ybl, 2, 3 equals Ry4,5,6 respectively for 92210 
Ybl, 2, 3 equals RylO, 11, 12 respectively for 92211 
Ybl, 2, 3 equals Ry22, 23, 24 respectively for 92212 

3.253 Character Buffer Extended to 12 Bits 



sRy7 
rRy7 

sRy8 
rRyS 

sRy9 
rRy9 

sRylO 
rRylO 

sRyll 
rRyll 



= Y4 Ry7 Ry4 + Y9 Y6 Y5 Zy7 
= Y4 Ry7 R^ + Y9 Y6 Y5 Y4 

= Y4 R^ Ry5 + Y9 Y6 Y5 Zy8 
= Y4Ry8R^+Y9 Y6 Y5 Y4 

= Y4 R^ Ry6 + Y9 Y6 Y5 Zy9 
= Y4Ry9 R^+Y9 Y6 Y5 Y4 



= Y4 RylO Ry7 + Y9 Y6 Y5 ZylO 
= Y4RylOR^ + Y9 Y6 Y5Y4 

= Y4r7Ti Ry8 + Y9 Y6 Y5Zyll 
= Y4Ryll r5^ + Y9 Y6 Y5Y4 



sRyl2 = Y4 Ryl2 Ry9 + Y9 Y6 Y5 Zyl2 
rRyl2 = Y4Ryl2 R^ + Y9 Y6Y5 Y4 



3.254 Character Buffer * 


sRyl 


= Y4 Yxx (T7 -TO) Ynl + Y9 Y6 Y5 




Zyl +Y4Yxx C21r 


rRyl 


= Y4 Yxx Ynl + Y9 Y6 Y5 Y4 + Y4 




Yxx C21r 


sRy2 


= Y4 Yxx (T7 - TO) Yn2 + Y9 Y6 Y5 




Zy2 + Y4 Yxx C22r 


rRy2 


= Y4 Yxx Yn2 + Y9 Y6 Y5 Y4 + Y4 




Yxx C22r 


sRy3 


= Y4 Yxx (T7 - TO) Yn3 + Y9 Y6 Y5 




Zy3 + Y4 Yxx C23r 


rRy3 


= Y4 Yxx Yn3 + Y9 Y6 Y5 Y4 + Y4 




Yxx C23r 


sRy4 


= Y4Ry4Ryl + Y9 Y6 Y5 Zy4 


rRy4 


= Y4Ry4Ryl + Y9 Y6 Y5 Y4 


sRy5 


= Y4 Ry5 Ry2 + Y9 Y6 Y5 Zy5 


rRy5 


= Y4 Ry5 Ry2 + Y9 Y6 Y5 Y4 


sRy6 


= Y4 Ry6 Ry3 + Y9 Y6 Y5 Zy6 


rRy6 


= Y4 Ry6 Ry3 + Y9 Y6 Y5 Y4 



* For 12-bit extension, add Ry7 through Ryl2 
For 24-bit extension, add Ry7 through Ry24 

Character Size 

12 bit character = Yxl2 (93221 only) 

24 bit character = Yx24 (93221 only) 

3. 255 Character Buffer Extended to 24 bits 



sRyl3 
rRyl 3 

sRyl4 
rRyl 4 



Y4 Ryl3 RylO + Y9 Y6 Y5 Zy13 



Y4 Ryl3 RylO + Y9 Y6 Y5 Y4 



Y4 Ryl4 Ryl 1 + Y9 Y6 Y5 Zyl4 



Y4Ryl4Ryll + Y9 Y6 Y5 Y4 



3-72 



September 


1965 


sRyl5 


= Y4 Ryl5 Ryl2 + Y9 Y6 Y5 Zyl5 


rRyl5 


= Y4 Ryl5 Ryl2 + Y9 Y6 Y5 Y4 


sRyl6 


= Y4 Ryl6 Ryl3 + Y9 Y6 Y5 Zyl6 


rRyl6 


= Y4Ryl6Ryl3+Y9Y6Y5Y4 


sRyl7 


= Y4 Ryl7 Ryl4 + Y9 Y6 Y5 Zyl7 


rRyl7 


= Y4 Ryl7 Ryl4 + Y9 Y6 Y5 Y4 


sRylS 


= Y4Ryl8Ryl5+Y9 Y6 Y5Zyl8 


rRyl8 


= Y4 RylB Ryl5 + Y9 Y6 Y5 Y4 


sRyl9 


= Y4 Ryl9 Ryl6 + Y9 Y6 Y5 Zyl9 


rRyl9 


= Y4 Ryl9 Ryl6 + Y9 Y6 Y5 Y4 


sRy20 


= Y4 Ry20 Ryl7 + Y9 Y6 Y5 Zy20 


rRy20 


= Y4 Ry20 Ryl7 + Y9 Y6 Y5 Y4 


sRy21 


= Y4 Ry21 Ryl8 + Y9 Y6 Y5 Zy21 


rRy21 


= Y4 Ry21 Ryia + Y9 Y6 Y5 Y4 


sRy22 


= Y4 Ry22 Ryl9 + Y9 Y6 Y5 Zy22 


rRy22 


= Y4 Ry22 Ryl9 + Y9 Y6 Y5 Y4 


sRy23 


= Y4 Ry23 Ry20 + Y9 Y6 Y5 Zy23 


rRy23 


= Y4 Ry23 Ry20 + Y9 Y6 Y5 Y4 


sRy24 


= Y4 Ry24 Ry21 + Y9 Y6 Y5 Zy24 


rRy24 


= Y4Ry24Ry21 + Y9 Y6 Y5 Y4 


3.256 Par 


ity Flip-Flop 



SDS 900685:0 



Paragraphs 3. 256 fo 3. 261 



sRyp = Y9 Y4R^(Ybl0Yb2©Yb3) (T7-T0) Qyl 
+ Y9Y4R^Y^(Ynl0Yn20Yn3)Qy2 

(T7 - TO) * 
+ Y9 Y4 R^ Yxx Cpr Qy2 (T7 - TO)* 
+ Y9 Y6 Y5 Zyp 
+ Yf Y5 T8 R^p 

rRyp = Y9 Y4 Ryp (Yb l©Yb2©Yb3) (T7 - TO) 

Qyl * 
+ Y9 Y4 Ryp Y^ (Ynl0Yn2© Yn3) 

Qy2(T7-T0)* 
+ Y9 Y4 Ryp Yxx Cpr Qy2 (T7 - TO)* 
+ Y9 Y6Y5Y4 



+ Yf Y5 T8 Y9 Ryp 
+ Yc 



Qyl = Yxl2 Qr4 + Yxl2Yx24Qrl Qr4 for 93221 



Qy2 = Yxl2 Qr4 + Yxl2Yx24Qr2Qr4 for 93221 

Qyl = Qrl Qr4 for 92210 

Qyl = Qr4for922n 

Qrl is deleted for 92212 

Qy2 = Qr2 Qr4 for 92210 

Qy2 = Oi^ for 922 11 

Qy2 is deleted for 92212 



3. 


257 


Error Detector 










sYe 


= Y9 Y6 Y5 Y4 Ryp Yg Npy (lyg + Iyi 


+Iy0 






+ YO Y6 Y5 Ecy T8 










+ Yes 










rYe 


= YcYh 








3 


258 


Interlace Prepare 










sEy 


= lyc e7 (T3 


-TO) 








rEy 


= Yc TO 

+ Pot 1 (T3 - 


- TO) Ey 






3 


259 


Interlace Clear 









lyc = Eom C9 CIO CI C17 (T3 - TO) 

*CT becomes CI for TMCC-D 

3.260 Interlace Load 

lyp = Pot 1 (T6 + T5) Ey 

lye = loc 1 Ey (T6 + T5) 

3.261 Interlace Active 



sly 


= Pot 1 (T3 - TO) Ey 1^ 


riy 


= lyfTS 




+ (Yc + lyc + Ys C19 C20 C21 C22 C23) 




(T3 - TO) ly 



3-73 



Paragraphs 3. 262 to 3. 269 



SDS 900685 C 



September 1965 



3.262 Zero Count 

lyf = YcO Yd Yc2 Yc3 Yc4 Yc5 Yc6 Yc7 

Yc8 Yc9 YclO Yell Ycl2 Ycl3 Ycl4 E^ 

3.263 Interlace Count Trigger 
lya = Ryx Tsm 

3.264 Interlace Counter Clock Enables 

Computer Clock Enable: Ey ly 
Counter Clock Enable: Ey 

3.265 Extend Operations 

slyg = lye C12 

riyg = lyc + Ysc T8 YIO yTT yT2 YT3 YU lyg 

3 . 266 Channel Command Interrupt Enables 

slyj = lye C13 

rlyj = lyc + I2y T8 lyj 

slyk = lye CI 4 

rlyk = lyc +ny T8 lyk 

3.267 Channel Command Register 

slyh = lye C15 
rlyh = lyc 

siyi = lye C16 

riyi = lyc 

3.268 Word Counter 



sYcl4 = lyc + Ey Yd 4 lya Ey 

rYcU = IypC9 + E^Yd4Iya E7 

sYcl3 = lyc +E^Yd3Yd4E7 

rYcl3 = IypC8 + E^Yd3 Yd4E7 



sYcl2 = lyc +Ey Yd2 Yd3 Yd4Ey 
rYd2 = lyp C7 + E^ Yc12 Yd3 YcU E^ 



sYclO = 
rYclO = 

sYc9 
rYc9 

sYc8 
rYc8 

sYc7 
rYc7 

sYc6 
rYc6 

sYc5 
rYc5 

sYc4 
rYc4 

sYc3 
rYc3 

sYc2 
rYc2 

sYcl 
rYcl 

sYcO 
rYcO 

3.269 Address 



sYcll = lyc +Ey Ydl Yd2 Yd3 Ycl4Ey 
rYcll = IypC6 + E^ Ydl Yd2 Yd3 Yd4E7 



sYaU 
rYaU 

sYal3 
rYal3 

sYal2 
rYal2 

sYall 

rYall 

sYalO 
rYalO 



yc +EyYdOYcnEy 




ypCS + E^YdOYcll E7 




yc +EyYc9 YclO Yell Ey 




yp C4 + 17 Yc9 YclO Yell E^ 




yc +EyYc8Yc9 YclO Yell 


Ey 


yp C3 + E^ Yc8 Yc9 YclO Yd 1 


e7 



yc + Ey Yc7 Ye8 Ey 
yp C2 + E^ Ye7 Yc8 E^ 



yc + Ey Yc6 Yc7 Ye8 Ey 
yp CI + E^ Yc6 Yc7 Yc8_g_ 

yc + E^ S^ Yc6 Yc7 Yc8 17 
yp CO + E^ Yc5 Yc6 Yc7 Yc8j£ 



yc + Ey Yc4 Yc5 Ey 

ye C23 + 17 Yc4 Yc5 E^ 

yc +e7 Y^ Yc4Yc5 17 

ye C22 + E^ Yc3 Yc4 Yc5 E^" 



yc + Ey Yc2 Yc3 Yc4 Yc5 Ey 

ye C21 + e7 Yc2 Yc3 Yc4 Yc5 E^ 

yc + 17 VVi Yc2 17 

ye C20 + 17 Yd Yc2 1^ 



ye + Ey YcO Yd Yc2 Ey 

ye C19 



Counter 



yc + Ey Yal4 lya Ey 

yp C23 + 17 Yal4lya 17 



yc +Ey Yal3 YaUlya Ey 

yp C22 + 17 Yal3 YaMIyaJy 



yc + Ey Ya12 Yal3 Ey 

yp C2T + E7Ya12 Yal3 17 



yc + Ey Yall Yal2 Yal3 Ey 

ypC20 + E7"Yan Yal2 Yal3 E7 



yc +E^Yal0Yan Yal2 Yal3 Ey 

ypC19 + Ey YalO Yall Yal2 Yal3 Ey 



3-74 



Sepf ember 1965 



SDS 900685C 



Paragraphs 3. 270 to 3. 272 



sYa9 
rYa9 

sYa8 
rYaS 

sYa7 
rYa7 

sYa6 
rYa6 

sYa5 
rYa5 

sYa4 
rYa4 

sYoS 
rYaS 

sYa2 
rYa2 

sYal 
rYal 

sYaO 
rYaO 



= lyp C18 + Ey Ya9 YalO Ey 
= lyc + Ey Ya9 YalO Ey 



= lyp C 17 + Ey Ya8 Ya9 YclO Ey 
= lyc +E^Ya8Ya9 Ya10E7 



= lyp C16 + Ey Ya7 Ya8 Ya9 YalO Ey 

= lyc +E7Ya7Ya8Ya9 Ya10E7 

= lyp C15 + e7Y^ Ya7 E^ 

= lyc +E^Ya6Ya7j£ 



= lyp C14 + Ey Ya5 Ya6 Ya7 Ey 
= lyc + E^ Ya5 Ya6 YoTj^ 



= lyp C 1 3 + Ey Ya4 Ya5 Ya6 Ya7 Ey 
= lyc +E^Ya4Ya5Ya6 Ya7 e7 



= IypC12 + Ey Ya3 Ya4Ey 
= lyc +E7Ya3 Ya4E7 

= lypCn +e9y^ Ya3 Ya4E7 



= lyc + Ey Ya2 Ya3 Ya4 Ey 



= lyp CIO + Ey Yal Ya2 Ya3 Ya4 Ey 
= lyc +E^Yal Ya2 Ya3Ya4|£ 



lye Cl8 + Ey YaO Yal Ey 
lyc 



3.270 Pin Address Counter 

sYpa = loc C17C13a9C20Cr[C22C23T0 
rYpa = Pin TO + St 

3.271 Skip Gate 

Skr = CT C17 C9 CTOCn 09 C20C21 C22 
C23 C15 Ysc* 
+ CTC17C9CT0C11 CT9C20C2TC22 
C23 C12 YToSTI yT2 YT3 YM* 



+ CTC17 C9CT0C11 C19 C20 C2T C22 

C23 C13 lyf* 
+ CTC17C9CT0C11C19C20C21C22 

C23C14Yi* 



= ^ 

= rz^ 



+ ClOCll C19 Ye CI* 

+ 

*CT becomes CI for TMCC-D 

3.272 Input/Output Signals Received 
Zyp 
Zyl 
Zy2 
Zy3 
Zy4 
Zy5 
Zy6 
Zy7 
Zy8 
Zy9 
ZylO 
Zyll 



= (ZyS) 






= (j-y9) 



Zyll 
Zyl2 =(^3) 
Zyl3 = (Z7l3) 



Zyi4 = Cjy3/ 

Zyl5 = (Zyl5^ 



Zyl6 = (Z^]6) 

Zyl7 = ( ^) 

Zyl8 = (^^ 
Zyl9 



Zy20 = (^^ 
Zy21 = (^) 
Zy22 = (^) 



+ ClOCll C13Y10Yn Y12Y13Y14 CI* 



Zy23 



3-75 



Paragraph 


2.273 




Yhs 


-^ 




Yes 


= (Yes) 




Mtgy 


= (Mtgy) 




Npy 


= (Npy) 




Ecy 


-Qz) 




Yxl2 


= (YxJ2) 


(93221 only) 


Yx24 


= (Yx24) 


(93221 only) 


3.273 Inp 


lUt/Output Signal 


s Generated 


(Ryg) 


= Ryp 




©) 


= Ryl 




(R^ 


= Ry2 




(RyS) 


= Ry3 




(R^ 


= Ry4 




Cr/D 


= Ry5 




eg) 


= Ry6 




(R) 


= Ry7 




(Ry8) 


= Ry8 




(R^ 


= Ry9 




(Ryld) 


= RylO 




(Rylj) 


= Ryll 




(Ryli) 


= Ryl2 




(Ryl3) 


= Ry13 





900685 C 




(Ryl^ 


= Ryl4 


(Ryl5) 


= Ryl5 


(Ryl6) 


= Ryl6 


(Ryl^ 


= Ryl7 


(Ryl 8) 


= Ryl 8 


(Ryl9) 


= Ryl9 


(Ryi^ 


= Ry20 


(Ry2j) 


= Ry21 


(@) 


= Ry22 


(Ry2^ 


= Ry23 


(Ry24) 


= Ry24 


(Y9) 


= Y9 


Cyio) 


= YIO 


CyiD 


= Yll 


Cy12) 


= Y12 


Cy13) 


= Y13 


CY14) 


= Y14 


Cyo^ 


= YO 


(yi) 


= Y5 


Cy6) 


= Y6 


CiD 


= ly 



September 1965 



3-76 



September 1965 



SDS 900685C 



Paragraphs 4. 1 to 4. 22 



SECTION IV 
INSTALLATION AND MAINTENANCE 



4.1 GENERAL 

4.2 This section contains information relating to the 
installation and maintenance of Model 932XX series 
TMCCs. As the Model 922XX series TMCCs are no 
longer being installed, only the Model 932XX series is 
covered in this section. 

4.3 INSTALLATION 

4.4 The basic 925/930/9300 computers are shipped 
with the TMCC physically installed. After installation 
of the computer, the intercabling of the TMCCs must be 
performed. 

4.5 INTERCABLING 

4.6 Figure 4-1 illustrates typical intercabling of the 
Model 93200 TMCC for the 925/930/9300 computers. 
Figure 4-2 illustrates the intercabling of the Model 
93221 TMCC. Power distribution for the various chassis 
is illustrated in figure 4-3. 

4.7 Intercabling of the input/output devices to the 

W (or A) channel may be found in the applicable input/ 
output device technical manual. 

4.8 After intercabling the TMCCs and the input/ 
output devices, a program should be run to ensure 
proper operation of the W (or A) channel. Any diagnos- 
tic program utilizing the input/output device may be 
run. 

4.9 925/930 COMPUTERW CHANNEL TEST PROGRAM 

4. 10 Table 4-1 lists a sample program which may be 
run to check out the W channel for proper operation. 
This test program causes the message ASSEMBLY DONE 
ENTER NEW PROGRAM to be typed out under program 
control. The computer stores the internal codes for 
these characters in memory beginning In location 2000. 
The routine inserts the carriage return code, 52, and 
the space code, 12, where needed and requests End-of- 
Record interrupt. It is written as a closed subroutine 
using interrupts, channel W and Typewriter Number One. 
The internal code for the output message is as follows: 



2000 



A S S E 
21 62 62 25 


M B L Y 
44 22 43 71 


Sp D O N 
12 24 46 45 


E C/R E N 
25 52 25 45 


T E R Sp 
62 25 51 12 


N E W Sp 
45 25 66 12 


PROG 
47 51 46 27 


R A M Sp 
51 21 44 12 



2004 



4. 1 1 9300 COMPUTER A CHANNEL TEST PROGRAM 

4. 12 Table 4-2 lists a sample program which may be 
run to check out the A channel for proper operation. 
This test program causes the message ASSEMBLY DONE 
ENTER NEW PROGRAM to be typed out under program 
control. The computer Internal codes for these charac- 
ters are stored beginning in location 02000. The car- 
riage return code, 052, and the space code, 012, are 
inserted where needed. The End-of-Record interrupt is 
requested. The routine is written as a closed subroutine 
which uses interrupts, channel A, and Typewriter Num- 
ber One. The internal code for the output message is 
the same as given in paragraph 4. 10. 

4.13 MODULE LOCATION 

4. 14 Figure 4-4 illustrates the location of all modules 
for the various models of TMCCs. 

4.15 MAINTENANCE 

4. 16 The following information is presented as an aid 
in maintaining the Models 932XX TMCCs. Presented 
herein are descriptions and timing diagrams of the sig- 
nals available on the various Input/output connectors 
and the diagnostic test programs for maintenance of the 
TMCC. 

4.17 PERIODIC INSPECTION 

4. 18 No periodic inspection is required for the TMCC 
other than that required for the computer as a whole. 
No attempt should be made to periodically check for 
loose wires, poor solder connections, or bent pins 
because of the packaging density of the wiring and com- 
ponents and the possibility of causing malfunctions. 
Wiring layout and length is critical in some areas and 
should not be touched except for correcting a malfunction. 

4. 19 CORRECTIVE MAINTENANCE 

4.20 If it should become necessary to replace a com- 
ponent on a module, the physical location of the com- 
ponent, quantity, type, and part number are indicated 
on the module drawings contained in Section 6. 

4.21 INPUT/OUTPUT SIGNALS AND TIMING 
RELATIONSHIPS 

4.22 The signals described are available on the input/ 
output connectors as illustrated in figure 4-5. The sig- 
nals are theoretical and do not take into consideration 
circuit and transmission delays which tend to add 200 to 
400 nanoseconds of delay. 



4-1 



I 

lO 



925 
29F 



| P^*^| — 



9300 TMCC 



2aC 271 

As 






|P9i? f - ^P9il I 
|P9I0 ) - ^P9G9| 
|P9'< |- Hp9i7] 
|P9I6 [ -^ ^P9T| 
|p91i |— S-lp9|7| 2f If 




|P9fC | -^ Hp909| 




44N 1195441- 


4iN^ 


1 


pbiobitV 

INT 


1 


WIRED 


L 



-|p9a9 I 



■f^ 



11F 


I4F 




4i 


?4r 


?'f 


4. 





30E 29t 

4i 






I5E 14E 




[p;iO j-fcl |p909| 



7B le 



re ee 



6 |PSI0 I - 



REF CABLE PLUG SCHEMATICS: 

P909-P9I0 K>720l 

P9II-P9I2 107303 

P9I5-P9I4 107300 

P9IS'P9I6 107201 

P9I7-P9I6 107303 

P939-P940 I0B600 

P94I-P942 107201 

P95I-P952 K3720I 

P953-P9S4 II3Z4I 

P955-P956 113242 

P957-P95« 113243 



- )F955 I 



|PS52[ -2 ^P95I I 



Eiirp^^iri 



D&CI 



2B 3B 



P9S7 
P957 



|P952 f ^ ^P95l I 



I3« 12B 
6B TB 



29B 30B 



25 B 26 a 

4i 




4i 



2eiA25A 
^ 



^ IN LIEU Of CABLE PLUC. MODULE F^^ BEFtKtNCED LOCATiaMS INiEt,T 2B52 TEBMIN4TI0N MCDULt. 
A APDniONAL ^BlOOlTV INI. CDuKLtt.S 9J260 INSEt<T INTO REF t HENCE D LOCATIONS. 
^ T'EP«iNA°TVN':ODutr """'' ^"^ ''^^"""D LOCATIONS INSERT 2B73 



(-0 

oi 

o 
o 
o 
o^ 

00 
en 

O 



CD 
T3 

-*■ 
(D 

3 



Figure 4-1. Model 93200 TMCC, Intercabling Diagram 



^o 
o 



—f 

a 

3 
cr 



,9f5 
i9F 



|P942| — 



|P9I0 | -^-- (pq09| 




f 2Sr |P9*gj-iil)p9«l I 24F ;5F |P94g P ^P94I | |5E |4£ |P9I0 | -fe^-|P909] 



iOt 29E 

4\ 



26t lit 




79 lee |p9io I - 



r6 8B 



REF CABLE PLUG SCHEMATICS: 

P909-P9I0 I0720I 

P9II-P9I2 107303 

P9IS-P9I4 IC7300 

P9I5-P9I6 107201 

P9I7-P9IB 107305 

P939-P940 100600 

P94I-P942 IO720I 

P95I-P952 107201 

P9S3-P954 II324I 

P95S-P956 113242 

P957-P95* 113245 



^jT}- 



2SA 2*A 

26* 27* 



|P952) - ^P95I I 



|P952 f ^^^ >9>l I 



DSC n DSC I 

|p9i8]^P9S7| 

|P95» IALJP957 I 



2S 3B 



|P952 [ ^ ^P95l I 



39 121 

61 7a 



29B 50B 



- |P9I3 I 
- |P909| 



|P9I0 ^^l-)p9oc| 



I5A I6A 



26* 2S* 
A 



A m LIEU OF CABLE PLU6 MOOULt FOB BtFlHtNCED LOC*TIONS INSEPT ItiZ .TEAMINATION MOOOLE. 
A APOITIONAL PBIOBITY INT. COUPLERS 93260 INSERT INTO REFEBENCtO LOCATIONS. 
^ T*'ERMIN*no" M^ODULE^ MODULE FOR REFERENCED LOC*TIONS INSERT IB73 



o 



o 

S3 

o 
o 

00 

Ol 

n 



I 

CO 



Figure 4-2. Model 93221 TMCC, Intercabling Diagram 



SDS 900685C 



September 1965 




♦«-25*8 CV**0 

II ?M? I 

I I/O CA8INCT 

REF SCHEMATIC I 
!__! 11590 I 



I, 93200 INCLUDES C,0^ I F CHASSIS. 
93221 INCLUDES A^,C,D,t4F CHASSIS. 

[7] FOR INSTALLATION OF CABLE PLUGS IN 
ASSOCIATED COMPUTER SEE PACES 9$I0. 
3. REF CABLE PLUG SCHEMATICS! 
107201 (P909-P9I0)(P«S-P9(*) 
I073O0 (P^IJ-P^M) 
I0T3OJ (P9ll-P9l2)(P9l7-H9ia) 



Figure 4-3. Power Distribution Diagram 



4-4 



Sepfember 1965 



SDS 900685,C 





1 


7 


^ 


4 


1 «i 


R 


7 


A 


9 


10 


II 


12 


13 


14 


»5 


16 


\7 


Ifi 


19 


L^O 


21 


rh 


2.3, 


?/u 


2.5, 


26, 


2L 


^ 


29 


5.Q., 


31 


32 


- 




it-94 


'aiz 


■92 

•1-34 


Ft54 


»*7 
S044 


Fb54 
J2-3I 


FBST 
52 -3( 


FB54 
52-38 


1-854 
32-S« 


ri54 

92 -3( 


ri54 

92-31 


2850 

l^40 


2850 
12^ 


1856 
12-X 


1857 
5044 


iBsr 

1044 


IB5b 
52-M 


FBb;; 

28-34 


?834 


>8-J4 


?8-34J29 34 28-3428-34 !8-54 »8-34J28-34e8-34 26-34 28-34 


t2-4{ 


A 






























03 




S3 




m 


























s 




V 

Nsac 


V 
ilSO 

12-40 


V 
1157 
9044 


FIS2 

88-34 


_JL. 

FS52 
28-34 








T 




V 


y 


T 


1 


T 


T 


» 


Y 


Y 


Y 


» . 


, « 


Y 


1 


Y 


Y 


Y 


Y 


Y 


Y 


Y 


Y 


' 


'^■52 
28^ 


F8&2 
M-34 


FbSZ 
»-34 


fBSZ 
28-34 


raS2 

28-34 


rii54 
a-it 


Fl(54 
52-3« 


Fbb4 
5**1 


IS96 
52-3« 


'BS4 

J2-SI 


1856 


IB59 

4»4« 


DB50 
5»44 


DBSO 
92-44 


obso 

12 44 


FB52 

>a-34 


tfl54 
?2 3« 


IBS'* 

«24e 


rB54 

52V 


IB96 
52-36 


2B51 

I2-4C 






EB%0IB59 IBS9IBS9 
I2-4C 12-46 4246 «24( 


B 
















































Eia 












S 


m 


US 




Y-12 










r-74 


I'M 


»-l2 
Y-^4 


r- 12 


V 


Y 


Y 


Y 


Y 


Y 


y 


Y 


y 


i 


Y 


Y 


Y 


Y 


Y 


Y 


Y 






Y 


Y 


Y 


Y 




2kS0 


ran 

2t-34 


FB52 
21-34 


FB52 
28-34 


•154 

J2-3f 


30 4< 


FBS4 

3^3« 


=^B54 

^^3t 


FB54 
32-36 


rB94 
J2-M 


FB54 
52-38 


FB54 
92-38 


2950 
l?40 


W50 
12-40 


1856 
U-3C 


1857 
5044 


IB57 
1044 


IB56 
52-36 


FB52 
?fl 34 


FB52 
?9i4 


FBiZ 
!854 


JB-34 


FB52 FB32 FB52 FB52 FB52 ftSZ 
!;8-54 26-34 28-54 ?B-34 ?fl-34 28-34 


28-54 sa-34!8-54l24C 

1 


C 



































03 




m 


























m 












w 


w 


w 


w 


w 


w 


w 


w 


LJ 


LJ 


vr 


w 


Y» 


tt 


t 


ia_ 


W 


* 


w 


..ff 


-^ 


w 


Y» 


wJ 


M^ 


w 


w 


« 




Muse 


2KS0 

l^4c 


K>44 


FISl 
28-34 


fBS2 
28-34 


FB52 
28-34 


FB52 


FBS2 
W-34 




•B52 

»e-34 


•BS4 
>2-3( 


=BS4 
52-38 


^BS4 
52-38 


I8S6 
52-3C 


FBS4 
12 38 


I8SS 
92-3* 


IB 59 
4246 


DBSO 
52-44 


BhSO 
52-44 


DB50 
52-44 


FB52 
28-54 


rB54 
52-38 


1859 
*2-4« 


FB54 
52-38 


BS6 
32-36 


2B5C 

12 -4C 






285011859 IB5'*IIB5'» 

I2-4CM2^ 42-4<|4248 

1 


D 
















































S 












a 


s 


s 




M-12 




W 






M-24 


W-24 


w-12 
w-U 




w 


w 


W 


w 


w 


<M 


W 




w 


W 


W 


w 




VY 


W 


w 


W 






A 


«v 


w 


w 




AK5J 
^4C 


>M(53 


AK53 

34-4C 


«KS3 
S4-4C 


AK5S 
34-4C 


AKS3 

34-40 


*K53 
34 -4C 


AK53 
M-4C 


Fe52 

28-34 


FB94 
12-36 


IB52 
12-32 


IB52 
12 -3J 


1839 
4iM 


3-4 7 


P9I3 
3-47 


NBSd 
i84C| 


NISO 
!84G 




At>55 
924f 


AB55 
5246 


*B5i 
92-46 


2852 
50-38 


3038 


18-22 2044|l8-22J309e 


30-S8Jao-44b4-3t S4^ J4-SI 


E 




























P9I4 
















P9l6 










P9I0 






s 


s 










W-13 




W 






W 


W 


w 


f 




v 


(!? 


W 


1 


w 




f 


» 


V* 


m 


W 


..« 


w 


W 


El 


w 


w 


'*f 


aU 


w 




5-47 


P9I7 
3-47 


AK53 
34-40 


AK 53 
J4-40 


^K 5! 
M-4C 


« 52 
t4-40 


AK54 

S-JI 


MOT 
4-24 


WRO* 
4 24 


WRW 
4 24 


tmm 

4-24 


6-28 


DSCY 
6 26 


auxY 
b-26 


Auxy 
6-26 


AUKY 
b-26 


MAC* 

fc-2B 


DSCW 


AUXW 
6-26 


AOX» 
6-26 


AUXW 
6-26 


POT 
6-20 


HOT 
6-20 


POT 

b-^o 


AKii 
J4-40 


>4-40iM-4C54-4Q3 47 


3-47 


PlM 
6 -lb 


PIN 
6-16 


F 




W 


V-12 


x. 


Y 


.1- 


joJ 




































1« 


1 


-IL- 


03 









W-Modul«*ntquir«dFor 6 lit w Buffai 
Wl2- Modultfl Addfd To Convert 6 Bit w 

•ufttrTol2Bit W Buffer. 
W24-Modultt Added To Convert 6BitW 

Buffer To 24 lit W Buffer. 
Y « ModuKs Regolred For 6 Bit Y Buffer 

Requires AllW Modulef 
Yl2<l«odulet Added To Convert 6 'lit v 

Bufrcr Tol2 Bit Y Buffer. 
Y24*Modulec Added To Convert 6 Bit T 

Buffer 1o24Dirr Buffer. 



H TbeieModulei Deleted When y-TMCC 

*^ Buffer Used with W-TMCif Buffer 

(71 AddP9tO.P9i2..P9l4,P9i6.P9ie When C«ndO 

'-' Bur/crtAre Added 

fail Th«»e Mo4ul»i UiKi Only Wilti Th» Intiilict Option. 

Q] Us* 28 52,Wh>i« initiciltil.Whtn C <ni) 
Buffirs 4rc Not *iiit»i- 



Figure 4-4. Module Local- ton Diagram 



4-5 



SDS 900685C 



September 1965 



PIN 
NO. 



INPUT/OUTPUT SIGNAL LOCATION 



WROY WRDir WROW WROW MAGV OISCV *UXV AUXV *U«r M*GW DISCW AUKW AUXW AUKW POTA POTB P0T8 PIN PIN 

J(»n J(9r) J(IOr) J(llf) J(I2F) J(ISF) J(l4f) JdSF) J06FI J(I7F) JOSf) Jfl9F) J(20f) JgiF) J&ZF) J(2JF) JC4F) JC3lf) J(320 



Cni»> o(^^4)° °CO^ 

CSj)" o<@^3> oCS^ 



(^^^> o(^^^ °C^>- 

(^iipo o(g^oi>> oCS>- 



<g^l2>> 0(^^5)0 oC|ut>>- 









-oC^)"- 



-oCPon)o- 

-oCIoc>- 
-oTEoniV- 
-o(Pjn )o- 



^CP^ 



y(t^y- 



-oC^r>>- 






-oC^> o o- 



-o(^> o o- 



(g^i^o 0(^^9)0 o(;yo)»- 



-o(,Wo 



(g^J)o 0(^15)0 '>Clo£)°- 

Cr^^>> o(g^> oCS>- 

000 o(5j^^)o- 

000 oCJix)^ 



'CvyT>- 



'Cwi>- 

'C^/io>>- 



— oC|^^° °- 

— oCU> c>- 

— oC|S)=' ^ 

-^Cri> ^ 

-^cil> — o- 
-oCir> — ^ 

— o(C 21)0 o- 



^C&>>- 






^ij^o o 

'C^ o 



-<=CCaL>- 




J(BF) J®FJ J(IOF) J(IIF) JdiFl J03F) J(I4F1 J(I5F) J(I6F) MTf\ J(I8FI J(|9FJ J(20F) .)(2lFI ,«2F> J^JF) J(i4FI J.3IF) J(J2F) 

wnoy wRov wrdw wrdw magv disc* au*v aukv auxv maow oiscw auxw auxw auxw pota poi b potb pin pin 



Figure 4-5. Input/Output Signal Location Diagram 



4-6 



September 1965 



SDS 900685 C 



Table 4-1. 925/930 Computers, W Channel Sample Test Program 



Location 


Instruction 


Address 


Comments 


1000 


PZE 




This instruction is an assembler instruction, used as 
convenient way to reserve the entry location for 
subroutine use. 




CLR 




Clears the A and B Registers. 




STA 


SWICH 


Clears the location called SWICH. SWICH later 
indicates to the main program that output is 
complete. 




TYP 


*0, 1, 4 


Connects Typewriter Number One to channel W for 
output, specifies four characters per word mode, 
and alerts channel W interlace. The instruction is 
an EOM with octal configuration, 02 40641. 




EXU 


WRITE 


Causes the Input/Output EOM in location WRITE 
to be executed. 




POT 


WRITE + 1 


Sends the word count and starting address in 
WRITE + 1 to the channel. 




BRR 


1000 


Branches back to the main program. 


WRITE 


EOM 00403720 


16200 


Specifies output function code 00 and the End-of- 
Record interrupt. The word in WRITE + 1 specifies 
that eight words will output from memory beginning 
in location 2000. According to output function 00, 
when the word count equals zero during the trans- 
mission, the output terminates, and when the last 
character is out, the device disconnects and the 
interrupt occurs. 


33 


BRM 


OKAY 


Branches and marks to location OKAY elsewhere 
in memory. 


OKAY 


PZE 




Saves the entry location 




MIN 


SWICH 


Increments location SWICH as an Indicator for the 
main program. 




BRU 


*OKAY 


Branches to the main program and clears the 
active interrupt. 



4-7 



SDS 900685C 



September 1965 



Table 4-2. 9300 Compul-er, A Channel Sample Test Program 



Location 


Instruction 


Address 


Comments 


01000 


PZE 




This instruction is an a^iembler instruction used as 
a convenient way to reserve the entry location for 
subroutine use. 




STZ 


SWICH 


Clears the location called SWICH. SWICH is later 
used to indicate to the main program that output is 
complete. 




TYP 


*0, 1, 4 


Connects Typewriter Number One to channel A for 
output, specifies four characters per word mode, 
and alerts channel A interlace. The instruction is 
an EOM with octal configuration, 02 42641. 




EXU 


WRITE 


Causes the Input/Output Control EOM in location 
WRITE to be executed. 




POT 


WRITE + 1 


Sends the word count and starting address in 
WRITE + 1 to the channel. 




BRR 


01000 


Branches back to the main program. 


WRITE 


EOM 00403720 


016200 


Specifies output function code 01 (lOSD) and the 
End-of-Record interrupt. The word in WRITE + 1 
specifies that eight words will be output from 
memory beginning in location 03720. According 
to output function 01 (lOSD) when the word count 
equals zero during the transmission, the device is 
disconnected when the last character is out and the 
interrupt then occurs. 


Oil 


BRM 


OKAY 


Branches and marks to location OKAY elsewhere in 
memory. 


OKAY 


PZE 




Saves the entry location. 




MPO 


SWICH 


Increments location SWICH as an indicator for the 
main program. 




BRC 


*OKAY 


Branches to the main program and clears the active 
interrupt, level Oil. 



4-8 



September 1965 



SDS 900685,C 



Paragraphs 4. 23 to 4. 29 



4.23 The logic terms for signals generated in the main 
frame referred to in these paragraphs represent the 930 
computer logic equations. Although the 925 and 9300 
computer implementation may differ somewhat from the 
930 computer, the functions achieved are similar. 

4. 24 (Q^, (gq2), and(Q^ (See figure 4-6) 

4.25 (Qq]^# (Qq2), and(Qq3)are clocking signals 
provided to external devices. They are functionally 
similar to the Ql and Q2 signals provided to external 
equipment on the 910 and 920 computers. Signals 
(Qql\ (Qq2), and(Qq3)are derived from the Pulse 
Counter, Qrl through Qr4, in the TMCC. 

(Q^ = Ts - TO 

T5 - TO = Qr3 oTl q74 

(Q^ = T6 - T3 

T6 - T3 = Qr3 Qr4 + Qr3 Oi^ OTT 

(Q^ = T7 - T4 

T7-T4 = Qr4 



TP \l_ 



il 



[*1.75|JS'^ 

J^ Jl 



Jl 



r 



@)_n 
@)_r 



r 



n 



Figure 4-6. 930/9300 Timing Diagram, 
(5^,(^2), (S5) 

4.26 (^Eony,^Bu(r),rioc), QSys") (See figure 4-7) 

4.27 (Eom)is the execution signal for the EOM 
instruction. 



Eom) = Ec 



The term Er inhibits(Eom)during the interlace loading 
sequence. rEorn) is derived from the CPU and trans- 
mitted to the TMCC. (Eonyis true from T7 through Tr. 

(1^ = Q5 Ol 04 05 Ti (Q2 + Q5) + . . . 

Q2+Q5 = T7-Tr 



During FILL operations, a pseudo Eom is generated. 

(^^^= Ix G^ Ht(K^(A2 + Q5) + . . . 
The term Ts inhi bits QEony during all time share operations. 

4.28 rBuc)is a control signal derived from the EOM 
instruction and is used to activate the TMCC and 
peripheral devices. ("Buc^is true from T7 through Tr. 

(b^= EomcTocTTcT 

For TMCC channels C and D, 

(b^= EomcTocnci 

Peripheral devices must use C17 and C17 to distinguish 
between channels W and Y and similarly, between 
channels C and D. 

4.29 Qjoc^is an input/output control signal derived 
from the EOM instruction. (loc)is true from T6 
through TO. 

(^c)= EomCToCn Cl El^Qr3 

Qr3 = T6 - TO 

For channels C and D, 

(j^ = Eom CTO C n C 1 li^ Qr3 



The term Er is used to inhibit(Ioc)during the interlace 
loading sequence. Peripheral devices must use C17 and 
C17 to distinguish between channels W and Y, or 
similarly, between channels C and D. 



Tp 



(l 



il \[ 



(@> _r~ 
(^ _r 



Figure 4r^ 930/9300 Timing Diagram, 
(Eony , QB uc^,r loc), rSys) 



4-9 



Paragraph 4. 30 to 4. 32 



SDS 900685C 



September 1965 



4.30 r Sys)ls a control signal for systems communica- 
tion derived from an EOM instruction. T Sys^is true 
from T5 through Tl . 

(Sys)= EomClOCn C91V(T5 -Ti) 



Systems devices must use C]7 and C17 to distinguish 
between channels W and Y, or similarly^ between 
channels C and D. The term Tsr inhibits Sys during 
time-share operations with the TMCC. 

4.31 Cpin),(^^,(^^, (^) 
(See figures 4-8, 4-9, and 4-10) 

4.32 The PIN instruction permits direct parallel entry 
of up to 24-bits of data to memory via the C register. 
A "Ready for Input" signal,(Pin), is provided by the 
TMCC to external equipment. 

(J]n)= Pin 

Pin = fT F2F3 02 06 tIQI 

Ql = T7- TO 

While the Pin signal is true, the C register is first reset 
and then the external data, (Cdn^, is strobed. 



rCn = Cxi Q2 

Cxi = fT F2 F3 02 06 tIqI 

Q2 = T7- T3 

sCn = Cxi Cdn 



Cdn = vCdn 

The process of resetting the C register and then strobing 
the data repeats until the external device provides a 
"Ready" indication by making ( ^Rt^ false. The data 
lines, (Cdn^, must be In a stable condition prior to the 
time(^W^goes false and should remain stable for the 
duration of the(Pin)signal. Unti I Q^Rty goes false, the 
PIN instruction was locked In phase 02, but is now per- 
mitted togiroceed to phase 04. A "PIN Complete" 
signal, (^Rti"^, is generated and sent to the external 
device. 

sRf = 06 F2 F3 Q2 Rt + . . . 

Rt =(^^ 

sF 1 = n F3 Oi 03 04 T^ Rf Tp + . . . 



rF2 = Fl F3 01 03 04 1a Rf Tp + . . . 

Rti = 0'4 OT 04 06 Ti (Q2 + Q5) 

(Q2 + Q5) = T7-Tr 

(^)= Rt7 

IfQR];^is always held false during the PIN instruction, 
the PIN instruction remains in phase 02 for only one 
cycle. 



Tp fl 



A 



il 



A 



(T) - 



Cdn 
RH 



Data lines stable 



Cxi _f 

Cxi Q2 -f 
Rf 



Figure 4-8. 930/9300 Timing Diagram, 



Tp n n \ [ 



ji 






Xdn 

- — — 

Itl 



-*-^ Data lines stable 



Cxi _J 
CxiQ2-r 
Rf — I 



Figure 4-9. 930/9300 Timing Diagram, Q^n^, 
(E)r (§), C^^/C^^InitiallyFalse 



4-10 



September 1965 



SDS 900685C 



Paragraphs 4. 33 to 4. 35 



Tp 



a 



(T)- 



Cdn 

Iti 



Cxi J" 
Cxi 02.1 



Rf 
Ts 



A 



J^ \l 



Jl 



n n n n 



-*-l Data lines stable 



Figure 4-10. 930/9300 Timing Diagram, (Jin^,(^Rt^,(^),CRt?), 

Effects of Time-Share 



4.33 Should a time-share operation occur during phase 
02 of the PIN instruction, theQPirOsignal is inhibited. 
At the completion of the time-share operation, depend- 
ing on the condition of(Rt ),at least one more cycle of 
the(Pin)signal occurs. Should a time-share operation 
occur during phase 04, the "Pin Complete" signal is 
inhibited until the time-share operation(s) is/are 
completed. 

4.34 (P^ , (P^ ,C^,Cc^ 
(See figures 4-11, 4-12, and 4-13) 

4.35 The POT instruction permits direct parallel output 
of up to 24-bits of data to external devices from memory 
via the C register. The CPotO signal denotes to 
external devices that the computer is in the process of 
executing a POT instruction. 



Pot 1 



Pot 1 = Fl F2 F3 02 06 

The CPot2) signal denotes to external devices that the 
contents of the C register may be strobed. 

(^^tj) = Pot 1 (T5-T1) TV 

The (Potj) signal stays true and the (Pot 2) signal 
repeats as long as the computer is locked in phase 02. 



Tp a 



(©) J 



^potj; 



Rf 



il 



Jl 



A 



Figure 4-11. 930A300 Timing Diagram, 

(^n) , (M2) .C^rT), (^C^ 



Tp 



fl 



il a 



& J 
& - 



(sE)J 



Rf _J 



Figure 4-12. 930/9300 Timing Diagram, (PoTj) , 
(P^72) ,(j^,rC^,(Rt)lnitially False 

^-^ 4-11 



Paragraphs 4. 36 to 4. 38 



SDS 900685,C 



September 1965 



Tp 



a 






Rf _ 



Ts 



il 



il 



Jl 



il 



JL 



I 



r 



Figure 4-13. 930/9300 Timing Diagram, (PoTT) , (^tj) ,(^^Rr),(^^^Cn) Effects of Time-Share 



When the Ready signal,(^Rt^, from the external device 
goes false (low), the POT instruction proceeds to 
phase 06. (Pot l) and (Pot 2) are then inhibited. 

sRf = 06 F2F3 Q2 Rt 

Rt =(^^ 

sFl = Ff F3 01 03 04 I^ Tp Rf 

IfC^Rt^is always held false during the POT instruction, 
the POT instruction remains in phase 02 for only one 
cycle. 

4.36 Should a time-share operation occur during the 
phase 02, the (Pot j) signal remains true but (Pot2) 
is inhibited. At the completion of the time-share opera- 
tion, depending on the condition of(Rt), at least one 
more cycle of ( Pot j ) and (Pot 2) occurs. It is neces- 
sary thatC.__RtJ) be held at ground until the computer 
acknowledges receipt of the Ready signal by making 
(PoM) go false. 



(See figure 4-14) 



4.37 CSkss 



4.38 On instructions for external system devices, an 
Sks strobe pulse, Qkss) , Is provided from the TMCC. 

(Skss) = Skss 

Skss = 05 01 04 fl (AOO (Q3 + Q5) + C9) 
Q3 +Q5 = T6 - Tr 

The SKS instruction remains in phase 05 for two cycles 
to permit the C register outputs, CCnj, to attain a 

4-12 



stable configuration at the external system device. The 
signal (SkssJ) is generated during the second cycle if 
C9 is true. ^SksT) is true for approximately two cycles 
if C9 is true. The response from external system devices, 
(^sc _), (false for a skip condition) is received by the 
TMCC and is sent to the computer as Skrz. If a skip is 
to occur, the Sk flip-flop Is set at Tr time during the 
second cycle of phase 0^5. 

sSk = 05 01 04 AOO Tr Sks + . . . 

Sks = Skrz + . . . 

If a time-share operation occurs during the SKS Instruc- 
tion, phase 05 is repeated for two cycles, thereby per- 
mitting the C register outputs, (Cn^, to attain a stable 
configuration prior to the generation of the (Skss^ probe 
pulse. 



Tp 



a 



Jl 



Jl 



Jl 



(sbr)ifC9. 

sSk 

Ssc 



C Reg. stable 



il 



(sbr)ifC9j' 



Figure 4-14. 930/9300 Timing Diagram, 
(SbT), (Cn^, (^) 



September 1965 



SDS 9006850 



Paragraphs 4. 39 to 4. 49 



4.39 If C9 is true, the (Skssy signal may occur for 
only one cycle if a time-share operation occurs during 
the SKS instruction. At the c omp letion of the time- 
share, however, a two cycle (^ksT) signal occurs. If 
C9 is true and time-share operation occurs, the (Skssy 
signal occurs only once, during the last of the two phase 
05 cycles. 

4.40 TEST PROGRAMS 



4.41 Proper operation of the TMCC can be checked by 
performance of the applicable test program. Operation 
in the compatible mode of the TMCC can be checked by 
performing the test program for the input/output device 
connected to the TMCC, The sample test programs 
given in tables 4-1 and 4-2 may be performed. Test 
programs for the extended modes are given in the fol- 
lowing paragraphs. 

4.42 EXTENDED MODE I/O TEST PROGRAM FOR 
925/930 COMPUTERS 

4. 43 This program tests as many of the extended I/O 
operations as possible with paper tape. Any 925/930 
computer with a typewriter attached to the W channel 
and a paper-tape punch and reader on any interlaced 
communication channel may be utilized. The W chan- 
nel need not be interlaced for the typewriter. 

4.44 The program occupies 838]o locations from 0177 
to 1714 octal. It is supplied on paper tape with a self- 
loading bootstrap. To load, insert tape in tape reader 
and perform fill procedure. 



4.45 FiM_ 

4.46 The fill procedure is as follows: 

a. Set up selected input device with the input 
program. Initial portion of the program contains the 
"bootstrap" program. 

b. Set RUN-IDLE-STEP switch to the IDLE position. 

c. Press START switch. 

d. Press PAPER TAPE FILL switch. This causes a 
WIM 2 (03200002) instruction to be inserted into the 
instruction register and loads the Index Register with 
7777777], The FILL switch also prepares the channel 
to operate in the forward, binary, four characters per 
word mode. 

4.47 Operation 

4.48 To select the reader and punch units to be used 
enter: 

"CU" P to select punch 

"CU" R to select reader 

The letter C is the channel number and may be any 
digit 0-7, and the letter U is the unit, either one or 
two. The reader and punch need not be on the same 
channel. 

4.49 The test is started by entering the letter "S". 
Control of the test operation is then a function of the 
Breakpoint Switches. Table 4-3 summarizes the switch 
functions. 



Table 4-3. 925/930 Computers Breakpoint Switch Functions 



Breakpoint 
Switch 


Reset 


Set 


1 


Run in the normal mode as determined 
by the other switches 


Stop and return to keyboard 
control at the end of the 
current pass (punch or read) 


2 


Continue to run test selected by 
switch 3 


Cycle test runs from punch to 
read to punch and so on 


3* 


Selects punch mode 


Selects read mode 


4 


Stop and type diagnostic messages 
whenever an error occurs 


Do not stop and type on errors 
but continue to run. 



'Used when switch 2 is reset or when starting test 



4-13 



Paragraphs 4.50 to 4,63 



SDS 900685C 



September 1965 



4.50 When running cyclic tests from puch to read, the 
tape from the punch should be inserted into the reader. 

4.51 Punching 

4. 52 The program punches ^our blocks of 64 characters 
each in one pass. The chan cters form a counting 
sequence from 00 to 778- The first block is started with 
leader and output with an lOSP. All punching is done 
in the one character per word mode. When the word 
count reaches zero, an lOSD Is loaded to punch a 
second block of 64 characters. No leader is punched 
between the first and second blocks. This results in 
one physical block 128 characters long. Starting with 
leader, two additional blocks of 64 characters are then 
punched with an lOSD. 

4.53 At the conclusion of each output operation, the 
channel address register is stored and compared with the 
expected value. If they do not agree, the program 
types the expected and actual values. 

4.54 The program tests the channel during the output 
operation to see if the channel should erroneously dis- 
connect before the word count reaches zero. 

4. 55 Reading 

4. 56 Each of the four blocks is read with a different 
set of commands and counts so as to test as many opera- 
tions as possible. After reading a block, a general 
subroutine checks for input parity errors, channel end 
address for agreement with the expected address, and 
the data read character by character. Error messages 
with block numbers are typed in the event of any one 
of these tests failing. If a test fails, reference should 
then be made to the test program flow diagram and 
troubleshooting Information in Section 5 of this manual. 
The handling of each block Is as follows: 

a. Block 1. The first block Is one-half of a 128 
character physical block. Reading one character per 
word, an lOSD with a count of 64 is used to read this 
block. The program checks to see if the count reaches 
zero and the channel becomes inactive at the same time. 

b. Block 2. This is the second half of the first 
physical block and is read with an lOSP with a count 
of 65. The read should terminate because of the end of 
record. The program checks to see that the word count 
does not reach zero and the channel remains active 
after the CIT (inter-record test) instruction skips. The 
tape is finally stopped with a disconnect before the 
data is checked. 

c. Block 3. Block 3 is a 64-character physical 
block. It is read with two channel commands. The 



first is an lOSP with a count of 32. If the count goes to 
zero before the channel disconnects, an lORP with «. 
count of 33 is loaded. This should cause the inter- 
record indicator to be turned on at the end of the record. 
The count should not reach zero and the channel should 
remain active. The tape is again stopped with a dis- 
connect before the data is checked. 

d. Block 4. This is the third physical block of 
64-characters and is read with an lORD with a count of 
56. The program waits for the channel to be inactive 
then checks to see if the channel ignored the last eight 
characters. If the tape was erroneously stopped after 
the 56th character it will show up as a failure on the 
first block of the next read pass. 

4. 57 Test Program 

4.58 Table 4-4 gives the test program for the 925/930 
computers I/O extended mode. 

4.59 EXTENDED MODE I/O TEST PROGRAM FOR 
9300 COMPUTER 

4.60 This program tests as many of the extended I/O 
operations as possible with paper tape. Any 9300 com- 
puter with a typewriter attached to the W channel and 
a paper-tape punch and reader on any interlaced com- 
munication channel may be utilized. The W channel 
need not be interlaced for the typewriter. 

4.61 The program occupies 838]o locations from 0177 
to 17143. It is supplied on paper tape with a self- 
loading bootstrap. To load, insert tape in tape reader 
and perform fill procedure. 

4.62 Fill_ 

4.63 The fill procedure is as follows: 

a. Press POWER switch on. When power is on, 
the switch is lighted. 

b. Press IDLE switch. 

c. With computer in IDLE, press RESET switch. 
This clears the D register and the program counter. 

d. Press RUN switch. The computer now executes 
the instruction in the D register (which is a HALT 
instruction). The program counter advances to 00001. 

e. Press PAPER TAPE LOAD switch. This switch 
causes an AIM 2 (0 32 00002) Instruction to be inserted 
into the D register and clears the HALT instruction. 
Index 1 Is loaded with 001 7777^. The LOAD switch 
also prepares the channel to operate In the forward, 
binary, four character per word mode. 



4-14 



00001642 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 1 of 20) 

1 TYPE EQU 930 MACHINE DEFINITION: 930/925 

2 * 

3 ♦ 

4 • EXTENDED MODE I/O TEST PROGRAfl. (925/930/9300 ALL CHANNELS) 

5 • 

6 * A.U. ENGLAND^ SDS 

7 * 

8 * 

9 • THIS PROGRAM USES THE PAPER TAPE READER AND PUNCH TO CHECK THE 
10 * OPERATION OF THE I/O CHANNELS IN THE EXTENDED INTERLACE MODE OF 

U * OPERATION. THE READER AND PUNCH MAY BE CONNECTED TO ANY INTERLACED 

12 * TMCC OR DACC. THEY NEED NOT BE ATTACHED TO THE SAME CHANNEL. THE 

13 * PROGRAM ADDRESSES THE KEYBOARD FOR INFORMATION ABOUT UNIT AND CHANNEL 

14 * SELECTION. 

15 * 

16 * 

17 * 

18 * 

19 * 

20 ♦ 



TO SELECT PUNCH TYPE: 'CU'P 
TO SELECT READER TYPE: 'CU'R 



UHERE 'C* REPRESENTS CHANi><EL NO. AND MAY HAVE THE VALUES 0-7; 

21 * AND 'U* REPRESENTS UNIT NO. AND MAY HAVE THE VALUE 1-2. THE LETTER 

22 * P OR R CAUSE THE SELECTION TO BE MADE WITH THE TWO PREVIOUS DIGITS. 

23 * SPACES SHOULD NOT BE TYPED BETWEEN DIGITS OR CONTROL CHARACTER. 

24 ♦ 

25 * TO START THE TEST TYPE: i> 

26 PAGE 

27 * 

28 * 

29 * 

30 * 

31 * 

32 * 

33 * 

34 ♦ 

35 * 

36 * 



BREAKPOINTS OR SENSE SWITCHES CONTROL THE RUNNING OF THE PROGRAM: 
RESET 



SUITCM 



BP i 
SW 1 



~^r^ 



R LI N TN~ TH E"' NO RH A LT MO D E 
AS DETERMINED BY THE 
OTHER SWITCHES. 



^TOP AT"THE^^NT)'^OT^~THE CUR^RTW 
PASS AND RETURN TO KEY BOARD 
CONTROL 



i 



37 ♦ 

38 * 
39* 

40 * 

41 * 
4 2 J 

43 * 

44 * 

45 * 

46 * 

47 * 

48 * 



BP 2 
'Sir2" 



CONTINUE TO RUN THE 
TrST"ffOTJE SELECTFir^ 
SWITCH 3. 



CYCLE TEST RUNS FROM READ TO 
INCH TO READ, ETC. 



BP 3 
SW 3 



SELECTS PUNCH MODE SELECTS READ MODE. 

(USED WHEN SWITCH 2 IS RESET OR WHEN STARTING THE TEST) 



BP 4 STOP AND TYPE DIAtiNOSTIC DO NOT STOP OR TYPE ON ERRORS. 



CO 

(B 

-t- 
(D 

3 

D- 



vO 
Cn 



t/1 

t/> 

S3 
O 
O 
Ox 
00 
Oi 

o 



■1^ 
I 





Table 4-4. 


925/9: 


30 Computers, Extended Mode I/O Test Program (Sheet 2 of 20) 




49 * 

50 * 

51 * 


SU 4 


MESSAGES WHENEVER AN CONTINUE RUNNING REGARDLESS. 
ERROR OCCURS. 




52 • 

53 * NOTE 

54 * 


: TO RUN CONTINOUS FROM READ TO PUNCH THE OUTPUT OF THE PUNCH 
SHOULD BE FED INTO THE READER. A LOOP SHOULD BE USED TO RUN 




55 • 
56 
57 * 


CONTI 

PAGE 

F8LLC 
OR A 
HINE T 

PROC 
NAME 
FORM 
PROC 
NAME 

"NATTE" 
NAME 
INST 

"END 
PROC 
NAME 


NOUS ON THE READER. 




58 * THE 

59 * SET 

60 * MACI 


tWING SECTION OF CODE DEFINES EITHER A 925/930 INSTRUCriON 
9300 INSTRUCTION SET. THIS IS DONE ON THE BASIS OF THE 
YPE STATEMENT AT THE BEGINNING OF THE DECK. 




oi » 

62 * 

63 * 

64 * 
65 

66 DF9300 










67 SINST 

68 P 

69 $LDX 


3*6.15 

1 DEFINE INDEX OP'S TO IMPLY XI. 
017 




70 $STX 

71 $BRX 
72 


077 
057 
<P(*1 >*/2)++l»P(0>*P<l) 




73 

74 P 

75 $XAB 

76 $A3C 

77 $BAC 

78 $CLR 


1 

037733 DEFINE COMPATIBLE REGISfER OP'S 




NAME 

NAME 

NAME 

INST 

END 

PROC 

NAME 

NAME 

NAME 

NAM""E 

NAME 

FORM 

SHFT 

END 

PROC 

NAME 

NAME 

NAME 

INST 

END 


037731 
037713 
037711 




79 
80 

81 P 

82 $R§H 

83 SRCY 

84 SLSH 

85 SLGY 

86 $N9D 

87 SSHFT 
88 

69 
90 P 


G#040.P(0) 

1 


■• 


000 DEFINE COMPATIBLE SHIFTS 

002 

004 




006 
044 

3*6.6.9 




P(2)*a60*P(a)*P(l )**0777 

1 DEFINE MISC. COMPATIBLE OP'S. 




91 SHIN 

92 $MIB 

93 $BIM 
94 

95 
96 * 


071 
030 
032 
(P(*l )*/2)+ + P(2),r'(0)*P( 1 ) 



D 
c/> 

o 
o 
o^ 

00 
Cn 
O 



c/i 



0^ 
Oi 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 3 of 20) ^ 



cr 



>o 



■^ 143 P PRec 1 



97 $X EQU 1 DE^^'INE INDEX TAS'X* FOR Xi 

98 * E9D CSNSTANT 

99 A0RG 0177 

100 $E9DC DATA 04000000 EOD C8NSTANT ^ 

101 * 

102 SSWTFRM FORM 3#6»3#12 

103 Q PRec 1 

104 SBPT NAMt 040000 

105 »eVT NAME 014040 

106 $R8V NAME 04000 

107 $SOV NAME 00040 

105 SWTFRii 0*022.0(0 )*/( -12 )**7,d(0)** 07 7 77 ♦♦(Qt l)>0)*/(6-Q(n) 

109 END 

110 END 

111 * 

112 PR9C 

113 DF930 NAME 

114 * 

115 * IF NOT A 9300 THEN D9 THE FOLLOWING OPERATIONS 

116 * ^ 

117 P PROC 1 DEFINE I/O INSTRUCTIONS O 
lid $MIB NAME 012 '^ 

119 $BIM NAME 032 g 

120 INST FORM 3.6,1,14 §^ 

121 INST P(2),P(0)*P(*1 ),P( 1 » ^ 

122 END 

123 * 

124 $X EQU 2 DEFINE INDEX US 'X' FOrf 2 ON 930 

125 * 

126 * 

127 AOR», 0177 

126 $E3DC DATA 0400000 EOD CONSTaM 

129 * 

130 * 

131 K PROC 1 Scl PVFRFLtJU 

132 $50V NAMl 

133' BRR $V4 ^ ^ ^ 

134 END 

135 * 

136 M PROC 1 " "BRANCH AND CLE AR "INTERRUPT 

137 $BRC NAME 

136 DO _"i*ii*L*2_ 

139 ^RLT MTi ) ~~ 

140 8RU *$+l 

i^^_ „ ^^^ M( 1 ) 

14 2^ "■ "^ """"END ■ "^" ^" 

143 P PRO! 

144 $DSC NAME 



4>- 
00 



Table 4-4. 925/930 Computers, Extended Mode l/O Test Program (Sheet 4 of 20) 



00177 00400000 



00200 










00200 





76 





00233 


00201 





35 





OOODl 


00202 





35 





00032 


00203 





01 





00234 


00204 





23 





01241 


00205 





23 





01231 


00206 





46 


30003 


00207 





35 





01444 


00210 





02 





02031 


00211 





32 





01445 


00212 





76 





01445 


00213 





75 





01636 


00214 





70 





01637 


00215 





01 





00217 


00216 





01 





00233 


00217 





70 





01640 


00220 





01 





00222 


00221 





01 





00266 


00222 





70 





01641 


00223 





01 





00225 


00224 





43 





00317 


00225 





72 





01642 


00226 





01 





00236 


00227 





75 





01444 



145 
146 
147 
148 
149 

151 
152 
153 
154 
155 

J^56 
157 
158 

J 59^ 
160 
161 
162 



$ALC 
$ASC 

siap 
I 



p 

SCAT 
$CET 
$C I T 
$CZT 
I 



NAM 
NAM 
NAM 
F9R 
I 

END 
~PR9 
NAM 
NAM 
NAM 
NAM 
FBR 
I 

END 
END 



050000 
012000 
014000 



3#6,15 



P(l )**2* (P(l >**4)*/3^*2*P(0 )+•»•(?( 1 )•*! )*/6 



014000 
OllOOO 



010400 
012000 
3*6*15 



•J r \J m X ■J 

Pm**2*040*P(0) + +(P( 1 )**4)*/12**(P( 1 )**1 >*/6 



De 

DF9 
DO 



300 



TYPE-9300 
TYPE<9300 



163 
164 
165 
166 
167 
168 
169 
170 
171 
172 
173 
174 
175 
176 
177 
178 
179 
180 
181 
182 
183 
184 
185 
186 
187 
188 
189 
190 
191 
192 



DF9 
PAG 



30 

E 



* THE START OF THE PROGRAM 



BEGIN 



BRUG9 
KYBD 

662 



GOl 



A8R6 

LDA 

STA 

STA 

BRU 

EXU 

EXU 

CLR 

STA 

RKB 

BIM 

LDA 

LD8 

SKM 

BRU 

BRU 

SKH 

BRU 

BRU 

SKM 

BRU 

BRM 

SKA 

BRU 

LDB 



0200 

BRUG8 

1 

032 

KYBD 

RDIS 

PDIS 

Tl 

0*1.1 
Tl*l 
Tl + 1 

«077 

_* p. 

$ + 2 

PO 

= • R- 

$♦2 

RO 

= • S' 

%*2 

SO 

= 070 

692 

Tl 



INITIALIZE RECOVERY LOCATIONS 



O 

GO 

>o 

8 

Ov 
00 

n 



READ CHARACTER 



CHECK FOR CONTROL CHAR. 



CHECK FOR DIGIT 
IF NOT CONTROL OR DIGIT CLEAR 



T3 

3 



O 
O^ 

en 



Table 4-4. 925 '930 Computers, Extended Mode I/O Test Program (Sheet 5 of 20) 



-D 



00230 36 01446 

00231 35 .01444 

00232 01 00211 



00233 
002 34" 
00235 
00236 

0023 7" 
00240 

0024 1_ 
002 42 
00243 
00244 
0024 5 
00246 
0024 7 
002 50" 
00251 
00252 
00253 
00254 
00255 
00 2"56 
00257 
00260 
00261 
00262 
00263 
00264 
00265 





2 

"O" 16 



43 00323 
71 01 643 
76 01234 
14 01644 
01446 
35 1 00235 








3 











2 



















16 01651 

35 01227 

01 OO204 



41 00235 
71 0164 5 
76 01227 
14 01646 
16 01447 
35 1 00243 
41 00243 
7ro 01643 
76 01212 
14 01647 
16 01450 
1 00251 



35 
41 
4 1 



00256 

0" 00251 



76 01230 

14 01650 

16 01444 

35 01230 



I 



o 



00266 





43 





00323 


00267 





71 





01643 


00270 


2 


76 






01244 


00271 





14 


01644 


00272 





16 





01446 


00273 





35 


1 


00270 


00274 





41 





00270 


00275 





71 





01643 


00276 


2 


76 





01240 


00277 





14 





01646 



PO 



193 
194 
195 

196 
197 
198 
199 

200 
201 
202 
203 

204"" ' 

205 
206 
20 7 
203 
209 
210 
211 
212 
213 
214 
215 
216 
217 
2i6 

219 

220 

221 

222 

223 

224 

22^5^ 

226 

227 * 

22 8 * 

229 * 

230 * 
2 3T~R 
232 
2^3 

234 ~ 
235 
236 
237 
238 
239 
240 



ST8 
STA 
BRU 

PAGt 



Tl+2 
Tl 

G9I 



SAVE CHANNEL NUMBER IN i i +2 
SAVE UNIT NUMBER IN U 



cr 



S3 



PUNCH CHANNEL" SET UP ROUTINE 



BRM ^Ai^ECH 

L D X = - 4 * * 1777 7 7 

LDA PALC+1*X 

ETR =050277677 

MRG Tl+2 

STA *$-3 

BRX %'A 

LDX =^**01 77 777" 

LDA PCET+1,X 

ETR =057737677 

HRG Ti+3 

STA *$-3 

BRX $-4 

LDX =-4V«oi7777T 

LDA Pi;;SD + 2*x 

ETR =0^:0277777 

MRG" " Tl+4 

STA *$-3 

BRX $+1 

BRX j_5~" 

LDA PTL 

ETR =-2 

MRG "^ Tl 

STA PTL 

MR^ =0200 

S:Ta PPT 

BRU KYBD 



GET CHANNEL NO. BUILT. 
UPDA IE EeM/E0D'S 



SAVED IN Tl+2 



I NSER T CHANNEL "DE3 I 5 N AT i 9N 



UPDATE SKS'S 



UHUA I C. CHANNLL COiiMAriDS 



O 

CO 

O 
O 
O 
00 

Oi 

o 



UPDA IE UNIT N8 



MAKE N3 L , DcH £3M 



RE A D E R C H A N N E L S ET U P rj 9 U T I N c 



"BRM 
LDX 
LDA 
ETR 
MRG 
STA 
BRX 
LDX 
LDA 
ETR 



"MAKECH 
=-4**0177777 
RALC+1*X 



GET CHANNEL Me 3UILT 
UPDAIE tPM/E9D'5 



=050277677 

Tl+2 

*$-3 

$-4 

=-4**0177777 

RCIT+l.X 

=057737677 



dUlLD SKS'S 



Table 4-4. 925/930 Computers, Exf ended Mode I/O Test Program (Sheet 6 of 20) 



ro 
o 










00300 





16 





01447 


00301 





35 


1 


00276 


00302 





41 





00276 


00303 





71 





01652 


00304 


9 


76 





012?4 


00305 





14 





01653 


00306 





16 





01450 


00307 





35 


1 


00334 


00310 





41 





00311 


00311 





41 





00334 


00312 





76 





01240 


00313 





14 





01650 


00314 





16 





01444 


00315 





35 





01240 


00316 





01 





00234 



00317 02 00000 

00320 40 20100 

00321 01 00640 

00322 01 00356 



00323 

00324 

00325 

00326 

00327 

00330 

0033^1 

00332 

00333 

00^334^ 

00335" 

00336 

00337 

00340^ 

00341 

00342 

00343 

00344 

0J)3j45 

b0346 

00347 



00^ 
4 6 
76 
72 
75 
36 
J 4 
35 
71 
76 
16 
35 
46 



72 
75 
46 
2 16 
35 
^76^ 
14 
17 



00^30 

"30003 

01446 
01654 
00177 
01450 
01655 
01 4 46 

01446 
01450 
00352" 
01446 

10012 

"00177 

01656 

0^014 

003 52 

01447 

^14 44 

01657" 

01657 



241 

342 

943 

244 

245 

246 

247 

24S 

249 

250 

251 

252 

253 

254 

255 

256 

257 

258 

259 

260 

261 

262 

263 

264 

265 

266 

267 

268 

269 

270 

27^ 

27 2 

273 

27 4 

275" 

276 

27 7 

278 

279 

280 



HftG 


Tl^3 


STA 


*$-3 


BRX 


f-4 


LDX 


•-10**0I77777 


LDA 


RISRD«2.X 


ETR 


-070277777 


nRii 


Tl*4 


STA 


*$-3 


BRX 


S*l 


BRX 


5-5 


LDA 


RPT 


ETR 


»-2 


HR6 


Tl 


STA 


RPT 


BRU 


KYBD 



BUILD CHANNEL COHHANO C0t«/EOO*S 



BUILD RPT WITH UNIT NO. 



* 
* 
* 
* 
SO 



START TEST RUNNING 



DSC 
BPT 

BRU 
BRU 

PAGE 




3 

IN 
OUT 



DISCONNECT 
START READ 
READ 
PUNCH 



OR PUNCH? 



8UILD CHANNEL NO. SUBROUTINE 



281 
282 
283 
284 
285 
^86 
287 
288 



MAK^ECH^J^ZE 

■ " CLR 
LDA 
SKA_ 
""LDB" 
STB 

ETR_ 

STA 
LDX 
__LDA 
MRG 
STA 

BAC_ 

SK"A 
LD8 

XAB^ 

MRG 
STA 

LDA 

ETR" 
E8R 



Tl + 2 

= 4 _ 

TO DC"" " 
Tl + 4 
= 3 

Tl^2 
Tl + 2 
Tl + 4 

MAKETB/X 
Tl+2 



GET CH. NO. 
EOD REQUIRE D 
"YES 

NO, SAVE EOD BIT, 



"B U I L D E~0 M / E^D SE L E C TTWhi 
SAVE EOM 
BUILD SKS SELECTION 



E9DC 
=040000 



MAKETB»X 
Tl+3 

Jl 

= f 

= 1 



SAVE SKS 

BUILD UNIT NO. BIT 



D 
i/> 

8 

00 
Cn 

n 



CO. 

CD 

-a 

-^■ 

n> 

3 

O" 

n> 



o^ 
Cn 



Table 4-4. 925. '930 Computers, Extended Mode I O Test Program (Sheet 7 of- 20) 



00350 
00351 



35 01444 


289 


ST A 


Tl 


51 00323 


290 


3F?R 


MAKECH 




291 


* 




00000000 


292 


MAKETB DATA 


0*0100 



SAVE UNIT Ne. BJl^T 
EXIT 



00352 

0035 3 00 000 100 

00354 20000000 

00355 20000100 



I 



00356 





71 





01650 


00357 





46 


30003 


00360 


2 


35 





01344 


00361 





55 





01651 


00362 





41 





00350 


00363 





23 





01230 


00364 





23 





01233 


00365 





23 





01236 


00366 





13 





01237 


00367 





71 





01643 


00370 





75 





01652 


00371 





76 





00431 


0037? 





43 





00610 


00373 





23 





01226 


00374 





40 


20040 


00375 





01 





00416 


3 7 6 





23 





01231 


00377 





02 





02641 


00400 





1? 





01653 


00401 





1? 





01654 


00402 





12 





01655 


00403 





12 





01656 


00404 





46 


00014 


00405 





16 





01635 


00406 





35 





00407 


00407 





12 





ooooc 


00410 





61 





004D7 


0J41 1 





41 





OO407 


00412 





0? 


14000 


00413 





40 


14000 


00414 





01 





00413 


00415 





01 





00234 


00416 





43 





00476 


00417 





23 





01224 


00420 





01 





00422 


00421 





23 





01227 



tUT 



293 

294 

295 

296 

297 9 

298 

299 

300 

301 

?02 0UT4 

303 

104 



305 

306 

307 

30d 

30i 

310 

31 1 

312 

313 

314 

31d 

316 

317 

315 

31^ 

320 

321 

322 

323 

324 

325 

320 

327 

32d 

329 

330' 

331 

332 



0*0100*020000000*020000100 



PAGE 
PAPER TAPE PUNCH OUTPUT SECTION. 



3 
cr 



•o 

On 



9UT? 



GQTQP 



0UT4A 



LDX =-64**0177777 

CLR 

STA IMAGE+64*X 

ADD =01000000 

BRX $-? 

EXU PTL 

EXU PALC 

LCH piesp 



LDX =-4**0177777 

LDB =ERMSLil 

LDA PCATC 

BRH uCZ 

EXU PCET 

BPT 4 

BRU 9LiT4A 

EXU PDIS 

TYP 0*1 .4 

MIB =3'^2121225 

MIB =051514651 

MIB =3 12246451 

MIB =0314b2712 

KAB 

MRG MIBX 

STA J+1 

MIB 00 

MIN $-1 

BRX S-? 

T9P 

CAT 

BRU S-1 

BHU KYBD 

BRM 9UTPIN 
EXU ~ PCAT 

BRU $+2 

EXU PPT 



SET UP OUTPUT IMAGE UITh 64 WORDS 



START PUNCH UITH LEADER 
ALERI CHANNEL 
L9AD leSP IMAGE,64 

SE J UP FOR SUBROUTINE TP TYPE: 
I9SP, OUTPUT 

UAIT FOR CHANNEL COUNT = ZERO 
ERROR ON OUTPUT 
YES, CHECK BP4 FOri N9 SlOP 
N3, N9 STOP 8N ER^OR 
ERROR, DIi>C9NNECf CHANh-L 
TY=E GENERAL ERROK M-3S^GE 
1 E 
RR3R 
J JR 
IN3 
Tr=>£ SPECIFIC ERRdR MESSAGE 



TO BE REPLACED AT RUN TlME 



1/1 
CO 

-O 
O 
O 

On 

00 

cn 
O 



G3 PIN ANU C^LC^ ^--A^Ji^JEi. ADDRcSd 
IF CHANNEL INACTIVE REAuDRESS PuNCi- 



4^ 

I 

ro 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 8 of 20) 



004 22 

00423 

00424 

00425 

00426 

0042 7 

00430" 

00431 

00432 



23 
23 



q_13 
71" 



00433 
00434 
00435 
00436 
00437 
00440 



00441 
00442 
00443 
00444 

00445 
00446 



00447 
00450 
00451 



00452 
00453 
00454 



00455 
00456 
0045 7 
00460 
0q461 
00462 



00463 
00464 
00465 

00466 



00467 
00470 
00471 
00472 
00473 
00474 
00475 



75 
76 



43 
23 

01 



23 
40 
01 
01 
43 
46 



01233 
01210 
01211 
01643 
01657 
00431 
00610 
01224 
00431 
012 26" 



333 
334 



E X U" 
LCH 



PALC 
PieSD 



35 
9 23 
23 



23 
9 13 
71 



75 
76 
43 



G 23 
01 
23 



40 
01 

4 3 
53 

01 



01 
76 
35 
01 









20040 
004 32 
003 7 6 
00476 
30003 
014 52 
01230 
01233 
01210 
0121 t 
^01643 
01667 
00431 
0061 
01224 
00452 
1226^ 
20040 
00450 
00376 
004 7 6 
01452 
00454 
00 4 57 
01670 
01452 
00442 



335 90TT 
336 

337 

333 " 



LDX 
LD8 
LDA 



BRM 

339 PCATC EXU 
340 BRU 

EXU' 



=-4**0177777 

SERMSG2 

PCATC 

UCZ 

PCAT 

$-1 



LOAD CH. leSD IMAiiE*64 

SET UP" ERR d R 7ME S S AliE : ~ 
IOSD# OUTPUT 



40 20400 

01 00234 

40 20200 

01 00640 

40 20100 

01 00640 

01 00356 



341 
342 
34 3^ 
34 4 
345 
346 



BPT 

B_R^_ 

BRU 

BRM 

CLR 



PCET 
4 

^2 

OUT 2 
OUTPIN 



UA I T~F e"R~C"e U NT E Q U A L Z E K 6" 
CHAN. ACTIVE? 

Y^S 

NO, ERROR? 

YES, IS STOP ALLOWED? 

NO ERROR OR NO ST3P 



TRR^R"~Frol5~Ai:LBW£13 
Ca PIN AND CHECK CHANNEL ADDRESS 



347 

348 eUTlA 

349 

350 

351 



STA 

EXU 
EXU 



PRF 
PTL 
PALC 



R(?UNCH REPEAT) 



LCH 



LDX 



PIOSD 



^'A**Q177777 



LOAD leSD niAGE#64 



SET UP ERROR MESSAGE 



352 
353 
35J_ 
"555 
356 
357 



LDB 
LDA 
BRM 



=ERMSG2 

PCATC 

UC? 



EXU 
BRU 
EXU 



PCAT 

$-1 

PCET 



CHAN. ACTIVE? 

YES 

NO* CHAN. ERROR 



358 
359 

361 
362 
363 
364 
365 
366 
367 
360 * 

369 * 

370 OU 
371 
372 
373 
374 
375 
376 

377 • 

378 * 



T3 



BPT 

BRU 

BRU^ 

BRM" 

SKN 

BRU^ 

BRU 

LDA 

STA 

BRU 



BPT 

BRU 
BPT 
BRU 
BPT 
BRU 
BRU 



4 

$ + 2 
eUT2 
"OUT PIN" 
PRF 
$ + 2 



YES* IS ERROR STOP ALLC^^TD 
NO*NO 

JTES^ 

GO PIU AND CHECK CHANNEL ADDRESS" 

PUNCH REPEAT 

RESET 



0UT3 
= -1 
PRF 
eUTl A 



1 

KYBD 

2 

IN 

3 

IN 

OUT 



SET 

S(PUNCH REPEAT) 



GO OR STOR 

STOP 

G3* CYCLE? 



YES 

ONE ONLY 



CO 
CO 

o 
o 
o* 
c» 

n 



SUBROUTINE TO CHECK CHAi^NEL AUDRESS 



in 

(\> 
TJ 

-f 

a> 
3 
cr 

fD 



vO 

o> 

Ol 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 9 of 20) 



004 7 6 00 O 000 30 



00477 





23 





01232 


00500 





33 





01444 


00501 





76 





01444 


00502 





17 





01671 


00503 





72 





01670 


00504 





40 


20040 


00505 





51 





00476 


00506 





37 





01445 


00507 





46 


00014 


00510 





16 





01635 


00511 





35 





00530 


00512 





76 





01671 


00513 





43 





00537 


00514 





35 





00577 


00515 





36 





006DO 


00516 





76 





01444 


00517 





43 





00537 


00520 





35 





006D5 


00521 





36 





006D6 


00522 





23 





01231 


00523 





71 





01672 


00524 





02 





02641 


00525 


2 


12 





00574 


00526 





41 





005?5 


00527 





71 





01445 


00530 





12 





00030 


00531 





61 





00530 


00532 





41 





00530 


00533 





71 





01673 


00534 


2 


12 





00610 


00535 





41 





00534 


00536 





01 





00412 



00537 00 00030 

00540 71 01674 

00541 46 20005 

00542 6700 003 

5 4 3 2 3 5 O' 01 4 56 

00544 76 

00545 41 



t 



01675 

00542 

46 "30003 
71 01674 



00546 
00547 
00550 6720 006 



379 * 

380 9UTPIN 
381 

382 

383 

384 

385 

386 

387 

388 

389 

390 

391 

392 

393 

394 

395 

396 

397 

39d 

399 

400 

401 

402 

40.S 

404 

405 

406 9TPIN1 

407 

406 

409 eTPIN2 

410 

411 _ 

412 

413 * 

4^1^ « 

415 ♦ 

416 * 

4 LL^Ii^^ cj; 

413 
419 

420 

421 
422 
423 



PZE 
EXU 
PIN 
LOA 
EQR 
SKA 
BPT 
BRR 
SIX 
XAB 
MRG 
STA 
LDA 
BrtM 
STA 

sTe 

LDA 
BRM 
STA 
ST>:i 

EXU 
LDX 
TYP 
MIB 
8KX 
LDX 
MIB 
MIN 
BRX 
LDX 
MIB 

BRU 





PASC 

Tl 

Tl 

=IMAGE+64 

= -1 

4 

9UTPIN 

Tl + 1 

MI8X 

eTPiNi 

=IMAGt+64 

MKPCT 

8TPNM1 

eiPNMl*! 

Tl 

MKOCT 

8TPNM2 

eTPNM2+l 

PDIS 

=-15**0177777 

0«1«4 

0TPNM+15-X 

J-1 

Tl + l 

00 " 

$-1 

=-12**0177777 

eTPN12'»-3*X 

$-1 



G9T0P 



ALERl 
ST9RE 



T8 STORE 
ADDRESS 



PUNCH CHANNEL 



CO 

m 
■o 

3 
u- 

(T> 



On 



C8MPARE UITH EXPECTED 

NOT EQUAL 

EJJAL eR ERROR STOP NOT PERMIfTcD 
SAVE LENGTH OF ERROR MFaSAGE 
SET UP ERROR OUTPUTTER 



GENERATE EXPECTED PIN UORD IN BCD 

SAVE EXPECTED 

GENERATE ACTUAL PIN UORj IN BCD 

DISCPNNECT PUNCH CHANNEL 

eUTPUf MESSAGE 

RjrPUT SPECIAL MEiSA:»^ 

OUTPUT RECEIVED AWD EXPiC TED' HESS AGE 



CO 

c/> 

o 
o 
>o 

On 

CD 

n 



SUBROUTINE TO MAKE ONE JORD Ii><T9 9 BCD OCTAL DIGITS 



PZE^ 
LDX 
ABC 
_L_SJH_ 
STA 



=-8**0177777 



LDA 
BRX 



Tl+lO-X 

«0 

$-3 



TO WORD TO B 
SHIFT OUT OCTAL D IGIT 
"SAVF"BCD~~CH7rRACTlR 
CLEAR A 



424 
425 

426 



CLR 
LDX 
LCY 



=-8**0177777 
6 



REASSEMBLY BCD CHARACTERS INTO A ■». 3 



I 

ro 
4*. 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 10 of 20) 



00551 2 

00552 

00553 

00554 51 00537 



16 


01456 


427 


41 


00550 


42d 


46 


00014 


429 



00555 52254524 



00556 


12212424 


00557 


51256262 


00560 


12265146 


00561 


44122330 


00562 


21454525 


00563 


43122431 


00564 


24124546 


00565 


63122127 


00566 


51252512 


00567 


66316330 


00570 


12256747 


00571 


25236325 


00572 


24122126 


00573 


63255112 


00574 


25674725 


00575 


23632524 


00576 


12121212 


00577 


00000000 


00600 


00000000 


00601 


73121252 


00602 


51252325 


00603 


31652524 


00604 


12121212 


00605 


00000000 


00606 


00000000 


00607 


33125252 



00610 





00 

35 


00030 


00611 





00617 


00612 





55 


01657 


00613 





35 


00614 


00614 





40 


12000 


00615 





01 


00617 


00616 





51 


00610 


00617 





40 


14000 


00620 





01 


00614 



430 

431 * 

432 * 



HRIT 
BRX 
XAB^ 
""BRR 



$-2 



MK8CT 



TXTT 



43'3 * ERR9R MESSAGES FOR CHANNEL ADDRESS TEST SUBROUTINE 

434 * 

435 8TPNM BCD 52#1END ADDRESS FROM CHANNEL DID NOT AGREE WITH EXPtCTE 



436 


BCD 


8.D AFTER 


437 


BCD 


UNEXPECTED 


438 


OTPNMl DATA 


0»0 


439 


BCD 


16.. IRECEIVED 



CO 

O 

CO 

^o 
o 
o 
c> 

00 

en 

n 



440 0TPNM2 DATA 



0.0 



441 BCD 4.. U 

442 PAGE 

443 * 

444 * WAIT "FOR" CeUNT"^E^3U AL ZER9 SUBROUT I NT. 

445 * 

ENTRY 



446 WCZ 


PZE 


447 


STA 


448 


ADD 


449 


STA 


450 


CZT 


45i 


BRU 


452 


BRR 


453 


CAT 


454 


BRU 



$ + 6 
= 1 

$+1 



00 
$ + 2 

UC2 



00 
$-4 



SAVE R/PCAT 
MAKE A CZr 

SAVE R/PCZT 

C = 027 
NO 

YES 

C H A N"N E L AC T T VET 
YES 



CO 

ro 

ro 
3 

O" 

ro 



o 
en 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 11 of 20) 



00621 





40 


20040 


-ooe.zz- 


"-0 


-5-1- 


-0 00610 :" 


00623 





37 


01444 


00624 





46 


00014 


00625 





16 


01635 


00626 





35 


00634 


00627 





71 


01676 


006 30 ' 


0' 


"02" 


026 4r' 


00631 


2 


12 


01500 


00632 





41 


00631 


006 3 3' 


^ 


'7 1 


1444 


006J4 





12 


OOODO 


C0635 


c 


51 


00634 


00636 


D 


41 


00634 


C0637 


\J 


31 


0412 



00640 


B 


43 





01177 


00641 





02 


20001 


00642 





23 





01243 


00643 


Q 


23 





01212 


00644 


9 


13 





01213 


00645 


3 


23 





01235 


00646 





01 





00657 


00647 





23 





01234 


00650 





40 


20040 


00651 





01 





00670 


00652 





71 





01676 


00653 





02 





02641 


D0«54 


2 


12 





01525 


00655 





41 





00654 


00656 





01 





00412 


00657 





23 





01234 


00660 





01 





00645 


00661 





23 





01235 


00662 





01 





00654 


00663 





01 





00670 


0Q664 





71 





01645 


00665 





75 





01677 


00666 





76 





00647 


00667 





43 





00610 


00670 





76 





017D0 


00671 





75 





01701 


4^ 00672 





43 





01065 


ho 00673 

U1 





43 





01177 



455 
456 
457 
458 
459' 
460 
461 
4 62 
463 
464 
■46 5 
466 
46 7 

4ey 
470 
471 
472 
473 
474 
475 
476 
477 

478 
479 

480 
461 
462 
463 
484 
465 
486 
487 
488 
489 
490 
491 
492 
493 
494 
496 
496 
497 
498 
499 
500 
501 



3PT 


4 


8 R R " 


" ' wcz 


SIX 


Tl 


XAB 




"MKG 


"~ If rex 


5TA 


$ + 6 


LDX 


=-13**0177777 


TYP 


0*1*4 


MIB 


DISM5 3+13#X 


BRX 


$-1 


LDX^ 


Ti 


MI = 


00 


M I N 


S-1 


3 R X ' 


$-2 "" 


BRu 


G9T3^ 


PAGE 





INPUT SECTION 



IN BRM STARTP 

Rev 

EXU RALC 

LCh RieSD 



INOB EXU RC2T 

BRU INC 

RCATC EXU RCAT 

BPT 4 

BRU INOA 

LDX =-13**0177777 

TVP 0*1*4 

MIB ERMSG4+13*X 

BRX $-1 

BRU G9T9P 
* 

INO EXU RCAT 

BRU INOB 

EXU RCZT 

BRU $*? 

9RU INOA 

LDX =-3**0177777 

LDB =ERMSG5 

LDA RCATC 

6RM UC? 

INOA LDA =033120152 

LDB =eUFFER*64 

BRM CHECK 

INI 3Rri STARTP 



N9, INHIBIT ERRQRo 

YES ' 

NQ* PRINT ERRQR MESSAGE 



3 
zr 



vO 

o^ 



STARI READER 

ALERT 

LOAD leSD bUFFEW.64 

C = 

NO 

YES* CHAN. ACTIVE 

YES* ERROR STOP PEPMITTtD 

N9, NO CONl. 

YES 



CO 

O 

o 
o 

Os 

00 

n 



CHAN 

YES 
NO, 
NO 
YES 

SET UP 



ACTIVE STILL? 



C = 



ERP9K MESSAGE 



GO DP DISCONNECT ERROR lEST 

BLOCK NO. 1 

END ADDRESS ExPECirD 

GO CHECK DATA 

STAR] READER IF DATA CHECKED 



O.K 









Table 4-4. 


925/930 Computers, Extended Mode I/O Test Program (Sheet 12 of 20) 




00674 


02 


20001 


502 


RBV 








00675 


G 23 


01243 


503 


EXU 


RALC 






00676 


23 


01214 


504 


LCH 


Kiesp 


L9AD leSP BUFFER, 65 




00677 


13 


01215 












00700 


76 

35 


01670 
014 51 


505 
506' 


LDA 
ST A 


= -I 






00701 


SPF 


S(I9SP INPUT) 




00702 


23 


01237 


507 IN4 


EXU 


RCIT 


INTERRECeRD C9NDITI9N 




00703 


01 
"001 


00735 
007 32 


5oa 

50 9 


BRU 


$ + 2 


N3 




00704 


BRU 


1N2 


YcS 




00705 


23 


01234 


510 


EXU 


RCAT 


CHAN. ACTIVE 




00706 


01 


00716 


511 


BRU 


INIA 
4 


YES 




00707 


40 


20040 


512 


BPT 


N9, ERR9R STeP PERMITTED 




00710 


01 


00732 


513 


BRU 


IN2 


NO 




00711 


71 

02 


01672 


514 


LDX 


=-15**0177777 


YES 




00712 


02641 


515 


TYP 


0.1*4 






00713 


2 12 


01547 


516 


MIB 


ERMSG6+15.X 






00714 


41 

or 


00713 
00412 


517 

5ia 


BRX 


$-1 






00715 


BRU 


GQT9P 












519 * 










00716 


23 


01235 


520 INIA 
521 


EXU 


RCZT 


C»0 


oo 


00717 


01 


00732 


BRU 


IN4 


N9 


1/1 


00720 


23 


01237 


522 


EXU 


RCIT 


YES, CHAN. INTER-RECORD 


-o 


00721 


01 
40" 


00732 


523 


BRU 


IN2 


N9 


8 


00722 


20040 


524 


BPT 


4 


YES, ERROR ST9P PcRMlTTcD 


?s 


00723 


01 


00732 


525 


BRU 


IN2 


N9 


n 


00724 


23 

7 1 


01241 
01732 


526 


EXU 


RDIS 


YES, ST9P TAPE 




00725 


527 


LDX 


=-17**0177777 






00726 


02 


02641 


528 


TYP 


0*1.4 






00727 


2 12 


01570 


529 


MIB 


ERnSG7-H7,X 






00730 


41 


00727 


530 


BRX 


$-1 






00731 


01 


00412 


531 

532 * 


BRU 


G9T9P 






00732 


23 


01236 


533 IN2 


EXU 


RCET 


IF CHANNEL ERROR 




00733 


4 51 


00733 


534 


sev 




SET OVERFLOW 




00734 


23 
53 


01241 


535 


EXU 


RDIS 


ST9P TAPE 




00735 


01451 


536 


SKN 


SPF 


I9SP INPUT FLAG 




00736 


01 


00756 


537 


BRU 


IN3 


RESET 




00737 


76 


01733 


53d 


LDA 


=033120252 


SET, GET BL9CK NO, 2 




00740 


75 


01444 


539 


LDB 


BUFFER*64 


END ADDRESS EXPECTED 




00741 


43 


01055 


540 


BRM 


CHECK 


CHECK DATA INPUT 










541 * 






IF CORRECT CONTINUE. 




00742 


43 


01177 


542 


BRM 


STARTP 


START TAPE 


CO 


00743 


02 


20001 


543 


Rev 






■D 


00744 


23 


01243 


544 


EXU 


RALC 


ALERT 


3 
cr 


00745 


23 


01216 


545 


LCH 


RIBSPl 


L9AD leSP BUFFER, 32 


00746 


13 


01217 










-I 


00747 


71 


01645 


540 


LDX 


=-3**0177777 


SET UP ERROR MESSAGE 


o 


00750 


75 


01734 


547 


LDB 


=ERMSG8 




en 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 13 of 20) 



I 

N3 



00751 





76 





00647 


00752 


0L4 3 





00610 


00753 





23 





01236 


00754 


4 


51 





007 54 


00755 





23 





01234 


00756 





01 





007 50 


00757 





23 





01240 


00760 





23 





01243 


00761 





23 





012?0 


0076? 





13 





01221 


00763 





46 


30003 


00764 





35 





01461 


00765 





01 





00732 


00766 





76 





01735 


00767 





75 





01731 


00770 





43 





01055 


00771 





43 





01177 


00772 





23 





01243 


00773 





23 





01222 


00774 





13 





01223 


00775 





23 





01234 


00776 





01 





00775 


00777 





71 





01674 


01000 





76 





01636 


1 00 1 


2 


72 





01444 


01002 





01 





01024 


01003 





41 





01031 


01004 





71 





016?4 


1 005 





76 





01642 


01006 


2 


35 





01444 


01007 





55 





01657 


01010 





41 





01036 


0101 1 





76 





01736 


01012 





75 





01737 


01013 





02 


20001 


01014 


9 


43 





01035 


01015 





40 


20400 


01016 " 


" 


01 





00234 


01017 





40 


20200 


01020 





01 





00356 


01021 


0" 


'4 


20100 


01022 





01 





00640 


01023 





01 





003 56 


01024 





40 


20040 


01025 





01 





01034 


01026 





71' 





01674 



548 


LDA 


RCATC 


54 V* 


3RK 


UCZ 


550 


EXU 


RCET 


551 


sev 




552 


EXli 


RCAT 


553 


BRU 


INS 


554 


EXU 


RPT 


555 IN5 


EXU 


RALC 


556 


LCH 


RIORP 


557 


CLR 




55a 


STA 


SPF 


559 


BRU 


|N4 


560 * 






561 IN3 


LDA 


=033120352 


562 


LDB 


=BUFFER+64 


563 


BRM 


CHECK 


564 


BKM 


STARTP 


^65 


EXU 


RALC 


566 


LCH 


KIPRD 


567 


EXU 


RCAT 


566 


BRU 


$-1 


369 


LDX 


=-8**0177777 


570 


LDA 


= 077 


371 


SKA 


8UFFER+64.X 


572 


BRU 


IN3A 


573 


BRX 


$-2 


574 IN3b 


LDX 


=-8**0177777 


575 


LDA 


= 070 


570 


STA 


BUFFER+64#X 


577 


ADD 


= 1 


576 


BRX 


S-? 


57v^ 


LDA 


=033120452 


580 


LUB 


= aL'FFLK + 56 


581 


Rev 




582 


BRM 


CHECK 


583 


BPT 


1 


584 


BRU 


KY8D 


585 


BPT 


2 


586 


BRU 


8UT 


58 7 


BPT 


"3 ' 


588 


BRU 


IN 


589 


BRU 


QUI 


590 * 






591 iN3A 


BPT 


4 


392 


BRU 


IN3B 


59 J 


"'LDX 


-=-e**0177777 



G9 WAIT F8R 0=0 

IF CHANNEL ERROR 

SET OVERFLOW 

IS READER STILL RUNNING 

YES 

NO, RESTART TAPE READER 

LOAD lORD BUFFER+32#33 



RCIOSP INPUT) 



(D 

-o 
o- 

(0 



>o 

en 



BLOCK NO. 3 
END ADDRESS EXPECTED 
GO CHECK DATA 
STARI TAPE 

LOAD lORD BUFFER. 56 

CHAN. ACTIVE 
YES, WAIT POR STOP 
CHAN. INACTIVE 

CHECK FOR 0*S IN LAST 8 CHARACTERS 



O.K. INSERT CORKECr 8 CHARACTERS 



BL9CK NO. 4 

€.^^D ADDRESS EXPECTED 

GO CHECK DATA 

TEST STOP? 

YES 

TEST CYCLE? 

YES 
■ t E 5 T 9 N E 9 N L Y . 
READ 
PUNCH 



en 
^O 

8 

o^ 

00 
Oi 

O 



ERR3H STOP PERM I r FED 
NO 
FQRrAr LAST EIGHT : - 4 -< AC TERS TQ'R TYPT 









TabI 


e4-4. 9 


25/930 


Computers, Extended Mode 1/ 


/O Test Program (Sheet 14 of 20) 


00 

01027 





46 30003 


594 




CLR 






01030 


2 
0" 


76 01444 
6700 003 ' 


595 
"596 


IN3D 


LDA 
"USH ' 


BUFFER+64*X 




01031 


3 




01032 


2 


16 01444 


597 




MRG 


BUFFER+64,X 




01033 






14 01710 

16 017 rr 


593 
599 




ETR 


= 0707 
=052120000 




01034" 




"KRG ' 




01035 





6700 006 


600 




LSH 


6 




01036 


2 



35 01055 
4 1 01030 


601 
602 




STA 


MSGIMG+8,X 
IN3D 




01037 




BRX 




01040 





71 01712 


603 




LDX 


=-19**0177777 


OUTPUT ERR9R MESSAGE 


01041 



2 


02 02641 
12 01616 


604 

' "60 5 




TYP 


0*1.4 




01042 


"HTB"" 


ERMSG9+19#X 




01043 





41 01042 


606 




BRX 


$-1 




01044 






02 14000 
40 14000 


607 




TOP 







OT04 5 


60d 




"ITAT" 







01046 





01 01045 


609 




BRU 


$-1 




01047 






02 02041 
71 016 74 


610 




TYP 


0«1«1 


eUTPuT 8 CHARACTERS 


01050 


611 




~LDX " 


=-8**0l77777 




01051 


2 


12 01055 


612 




MIB 


«SGIMS+8,X 




01052 





41 01051 


613 




BRX 


$-1 




01053 


12 015D3 


614 




MIB 


ERr^SGl+3 


OR 


01054 





01 00412 


615 




BRU 


GOTOP 










616 
617 


* 
* 

















01055 






618 
619 
620 


MSGlriG 

* 


RES 
PAGE 


8 










621 


* CHECK INPUT DATA SUBROUflNE. 










622 


* 








01065 





00 Q OOODO 


623 


CHECK 


PZE 






01066 





35 01626 


624 




STA 


ERMSGO+6 


SAVE BLOCK N9. 


01067 





23 01236 


625 




EXO 


RCET 


CHECK F9R ERR8R 


01070 





01 01141 


626 




BRU 


PARERR 


GO TO PARITY ERROR ROUTINE 


01071 





40 20001 


627 




OVT 




CHECK FOR PREVIOUSLY NOfED ERROR 


01072 





01 01141 


62d 




BRU 


PARERR 


GO TO PARITY ERROR ROUTINE 


01073 


Q 


23 01242 


629 




EXU 


HASC 


STORE CHANNEL ADDRESS 


01074 





33 01444 


630 




PIN 


Tl 




01075 





36 01445 


631 




SIB 


Tl*l 


SAVE EXPECTED 


01076 





76 01444 


632 




LDA 


Tl 




01077 





17 01445 


633 




EOR 


Tl + t 


COMPARE ACTUAL UITH EXPcCTED 


01100 





72 01670 


634 




SKA 


= -1 


AGREE 


01101 





01 01154 


635 




BRU 


PINERR 


NO 


01102 





71 01650 


636 


CHECK2 


LDX 


=-64**0177777 


YES 


01103 





76 01675 


637 




LDA 


= 0C 




01104 





75 01636 


63d 




LDB 


= 077 




01105 


2 


70 01444 


639 




SKM 


BUFFER+64.X 


CHECK INPUT BUFFER 


01106 





01 01112 


640 




BRU 


CHECKl 


ERROR 


01107 





55 01657 


641 




ADD 


= 1 





a 

CO 

o 
o 
o^ 

00 

n 



-o 

3 

u- 

a» 



^0 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 15 of 20) 



OHIO 
01111 

01112 
01113 
01114 
01115 
01116 
01117 
01120 
01121 
0112? 
01123 
01124 
01125 
01126 
01127 
01130 



01131 
01132 

01133 
01134 
01135 
01136 
01137 
01140 



41 01135 
51 01055 

40 20040 
51 01055 
35 O 01444 

6700 003 
16 01444 
14 0171C 
6700 006 
16 01713 
35 01631 
2 76 01444 
5600 003 
2 76 01444 
6700 003 
14 01710 
6700 006 
16 01713 
35 01634 
71 01676 
23 01241 
02 02641 



12 01635 
41 01136 
01 00412 



I 



01141 





40 


20040 


01142 





51 


01055 


01143 





23 


01241 


01144 





02 


02641 


orR5~ 





71 


01714 


01146 


2 


12 


01627 


01147 





41 


01146 


01150 





"02" 


14000 


01151 





40 


14000 


01152 





01 


01151 


1T5 3" 


0" 


01 


0X132 


01154 





40 


20040 


01155 





01 


01132 


01156 





76 


01444 


01157 





43 


00537 


01160 





35 


00635 



642 
64J 
644 
645 

646 
647 

646 
649 
65U 
651 
652 
653 
654 
65d 
656 
657 
658 
659 
660 
661 
662 
663 
664 
665 



CHtCKl 



9RX 
BHR 

BPT 

3KR 
STA 

LSh 
MRG 
ETR 
LSH 
MKG 
SM 
LDA 
r^SH 
LDA 
LSH 
ETR 
LSH 
MRG 
STA 
LDX 



EXU 
TYP 
MIB 
BRX 
BRU 



$-3 

CHFCK 

4 

CHECK 

Tl 

3 
Tl 

=0707 

6 

=012000052 

ERHSGO+9 

dUFFE«+64,X 

3 

aUFFE«+64*X 

3 

=0707 

6 

=012000052 

ERMSGO+12 

=-13**0177777 

RDIS " 

0«1«4 

ERHSG0+13.X 



666 
667 
_668 

669 " 

670 * 

671 PARERR BPT 
672~ 
673 
674 
675~ 
676 
677 
6TS~ 
679 
680 
66"!"" 
662 

683 

68X"* 

685 PIMERR 

686 

68 7 
688 
689 



$-1 

SOTOP 



PARITY ERROR SUBR9UTINE 



"BR1?~ 
EXU 
TYP 

T13X 
MIS 
BRX 

"TUP^ 
CAT 
BRU 
ffRU" 



"CHEXK 

RDIS 

0#1*4 
^-^**017777T" 

ERMSGP+9-X 

$-1 





$-1 



CHECKS 



EXIT IF ALL CORRECT 

ERROR STOP PERfllTfED? 
NO. EXIT 

YES 

FORMAI EXPECTED 



SraRE EXPECTED 
FORMAT KECEIVED 



■D 

3 
en 






SrSRE RECEIVED 



D I SC tf N N E C T R E A D E R CHANNEL 



tn 

S3 
O 
O 

o> 

00 

n 



ERROR STOP PERMITTED? 

YES* DISCONNECT READER CHANNEL 



OUTPUT PARITY ERROR MESSAGE 



KtlUKN TO CHhCK NUMBcHS 



PIN ADDRESS ERROR SUBROUTINE 



BPT 
BRU 



LDA 
BRM 
STA 



4 

CHECK2 
Tl 

MKOCT 
eTPNM2 



ERROR STOP PERMITTED 
NO 

EXPAND ACTUAL TO BCD 
SAVE 



■^ 












CO 

o 














01161 





36 





00636 




01162 





76 





01445 




01163 





43 





00537 




01164 





35 





00577 




01165 





36 





00630 




01166 





23 





01241 




01167 





02 





02641 




01170 





71 





01672 




01171 


2 


12 





00574 




01172 





41 





01171 




01173 





12 





01624 




01174 





12 





016?5 




01175 





12 





01626 




01176 





01 





00533 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 16 of 20) 



01177 00 00030 



01200 





71 


01650 


01201 





46 


30003 


01202 


2 


35 


01444 


01203 





41 


01232 


01204 





23 


01240 


01205 





51 


01177 



01206 002 146 30 

01207 0100 01 244 

01210 002 142 30 

01211 0100 01244 



01212 
1 21 3 

01214 

01215 

0J^2J^ 

01217 

01220 

0122J^ 

01222 

01223 



002 142 30 
0100 01344 
00 2 146 30 
01,01 01344 
002 146 30 
6040 01344 
00 2 144 30 
0041 01404 
6"02 T40'0 30 
0070 01344 



690 




STB 


8TPNM2+1 


691 




LDA 


Tl + l 


692 




BRM 


MKeCT 


693 




STA 


9TPNM1 


694 




STB 


OTPNMl+l 


695 




EXU 


RDIS 


696 




TYP 


0*1*4 


697 




LDX 


=-15**0177777 


696 




MIB 


eTpNfi+is-x 


699 




BRX 


s-i 


700 




HIB 


ERr'SGO + 4 


701 




MIB 


ERrSGO+5 


702 




Mlti 


ERHSGO+6 


703 




BRU 


eTPlN2 


704 


* 






705 


* 


START TAPc 


READER SUBRBJTI 


706 


* 






707 


STARFP PZE 




706 




LDX 


=-64**0177777 


709 




CLR 




710 




STA 


BUFFER+64,X 


711 




BRX 


S-1 


712 




EXU 


RPT 


713 




BRK 


STARTP 


714 




PAGE 




715 


* 






716 


* 


I/e CHANNE 


L COMMANDS 


717 


* 






718 


PI9SP lesp 


IMAGE#64 



EXPAND EXPECTED T3 BCD 



SAVE 

DISCBNNECT READER 

OUTPUT GENERAL MESSAGE 
OUTPUT BLOCK NO. 

GO OUTPUT RECEIVED AND cXPECTED 



CLEAR BUFFER 

START TAPE 
EXIT 



O 

CO 

>o 
o 
o 

00 

n 



720 * 

721 RIOSU leSD 

7l2" RI3SP lOSP 

723 RIOSPl [OSP 

724 RI9RP lORP 

725 RIORD lORD 



BUFFER*64 

B"LrFFER"#65 
BUFFER*32 
BUFFER+32#33 

BUFFERV56 



01224 40 14000 



7 26 * 

^727 "* ' 

>2Q ♦ I/O CHANNEL INSTRUCTIONS. 

7 29 * 

730 PCAT cat ' ' 



CO 

(t 

-*■ 

a> 
3 
u- 





■O 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 17 of 20) 



01225 
01226 

01227 
01 230 
01231 
01232 
01233 



01444 
01461 
01462 



40 12000 
40 1 1000 



02 
02 



02044 
00044 



02 00000 
02 12000 
02 50000 



01234 40 14000 

01235 40 12000 

01236 40 11000 

01237 40 10400 

01240 02 020D4 

01241 02 00000 

01242 02 12000 

01243 02 50000 



01244 
01344 



01463 52233021 



I 

CO 



01464 
01465 
01 4 5 6 
014 6 7 
01470 
01471 
014 72 
01473 
01474 
014 7 5 
01476 



454 5254 3 
12255151 
46514664 
62437012 
24316223 
46454525 
23632524 
12222526 
46512512 
23130073 
12246451 



CZT 

GET 



PPT 
PTL 
DSC 
ASC 
ALC 



CAT 
CZT 
CET 
CIT 

RPT 
DSC 
ASC 
ALC 






0«1«1 
0»1*1 







1«1 



731 PCZT 
7 32 PCET 

733 * 

734 PPT 

735 PTL 

736 PDIS 

737 PASC 
736 PALC 

739 * 

740 * 

741 RCAT 

742 RCZT 

743 RCET 

744 RCIT 

745 * 

746 RPr 

747 RDIS 

748 RASC 

749 RALC 

750 * 

751 * 

752 * OUTPUT IMAGE AREA, INPUT BUFFcR AREA 

753 * 

754 IMAGE RES 64 

755 BUFFER RES 64 

756 * 

757 * 

758 * 

759 • 

760 Tl 

761 SPF 

762 PPF 
763 
764 * 
76 5 ♦ 

766 • 

767 DISMSG BCD 



fD 

-a 

3 
cr 






en 

o 

CO 

vO 
O 
O 

o 
o 



TEMPORARY STORAGE AND FlAGS 



RES 
RES 
RES 

PAGE 



13 

1 

1 



lOSP INPUT FLAG 
PUNCH REPEAT FLAG 



ERROR AND STATUS MESSAGES. 



52#1CHANNEL ERROROUSLY DISCONNECTED BEFORE C=0» DURING 






01477 31452712 

01500 31466247 

01501 73124664 

01502 S3476463 

01503 331252^52 

01504 31466224 

01505 73124664 

01506 63476463 

01507 33125252 

01510 5223 3021 

01511 45452543 

01512 12243124 

01513 12454663 

01514 12243162 

01515 23464545 

01516 25236312 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 18 of 20) 



768 ERflSGl BCD 16,I9SP, BUFPUT. il 



769 ERI1SG2 BCD 16,iaSD# 8UTPUT. ii 



01517 66302545 

01520 12231300 

01521 12464512 



01522 


31466224 


01523 


12314547 


01524 


64635212 


01525 


31466224 


01526 


73123145 


01527 


47646352 


01530 


52233021 


01531 


45452543 


0t532 


12243162 


01533 


23464545 


01534 


25236325 


01535 


24122464 


01536 


51314527 


01537 


12314662 


01540 


47123145 


01541 


47646373 


01542 


12233163 


01543 


12452565 


01544 


25511212 


01545 


ft35l6425 


01546 


33125212 


01547 


52246451 


01550 


31452712 


01551 


31466247 


01552 


12314547 


01553 


64631223 


01554 


13001231 


01555 


45243123 


01556 


21633145 



770 ERriSG4 BCD 52#1CHANNEL DID NOT DISCONNECT WHEN C=0 9N lOSD INPUT! 



771 ERriSG5 BCD 12*I9SD. INPUT! 



772 ERMSG6 BCD 52*1CHANN£L DISCONNECTED DURING lOSP INPUT, CIT NEVER 



773 BCD 8. TRUE. 1 

774 ERHSG7 BCD 48,1DURING lOSP INPUT C=0 INDICATING EOR PAoT BUT C 



CO 

i/» 
"O 

o 
o 

o* 

CO 

Or 

n 



3 
cr 



o 
o^ 

en 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 19 of 20) 



01557 


27122546 


01560 


51124721 


01561 


62631222 


01562 


64631223 


01563 


31631266 


01564 


21621245 


01565 


25652551 


01566 


12635164 


01567 


25331252 


01570 


31466247 


01571 


73123145 


01572 


47646352 


01573 


§2314651 


01574 


24124645 


01575 


12314547 


01576 


64631224 


01577 


31241245 


01600 


46531231 


01601 


27454651 


01602 


25126330 


01603 


25124321 


01604 


62631210 


01605 


12233021 


01606 


51212363 


01607 


25516273 


01610 


12226463 


01611 


12512521 



775 



BCD 20#IT WAS NcVER TWU£. I 



i/v 

a 

3 
cr 






776 ERf1S«8 BCD 12.I9SP. INPUTl 



777 ER!1S(i9 BCD 52*118RD 9N INPUT DID NO I IGNORE THE LAST fi CHARACTERS, 



C/1 
CO 

o 

8 

On 
00 

n 



778^ 



bzh' 



24* 8irr~RErAJ the FffUt^T/TNGT 



0J^12 24126330 
0"T6 r3 251 22 64 6 



01614 

01615 

01616 

01617 

0162 

0162~r 

01622 

01623 



01624 
01625 
0162 6 
01627 
01630 
01631 
01632 
01633 
01634 



43434666 
31452752 
f2"52 47"2l 
51316370 
52314547 
"64 631225^ 
51514651 
i 23^1 45 1 2 
22434623 
42124546 
33124552 
25674 7 25 
2363^524 
12242452 
51252325 
31652524 
12242452 



7 ^9 "TR KS l^^CI! ^aTTTFTfRTTT 

760 ERflSGO BCD 40#iINPUT EKRaR IN BL9CK N8. NiEXPECTED DDl 



781 



BCD 



12*RECEIVED DDl 



CO 



01635 12 00000 



782 * 

783 MIBX MIB 



OUTPUT INSTRUCTION 



J^ 




Ca) 




-1*^ 






00000200 


01636 


00000077 


01637 


00606047 


01640" 


00606051 


01641 


00606062 


01642 


00000070 


01643 


00177774 


01644 


50277677 


0164S 


00177775 


01646 


57737677 


01647 


^^277777 


01650 


77777776 


01651 


00002000 


01652 


00177766 


01653 


fG277777 


01654 


00000004 


01655 


00000003 


01654 


00040000 


0165:f 


00000001 


0166Q 


00177700 


01661 
0166^ 


01000000 


00001500 


0166S 


52121225 


01664 


51514651 


01665 


12246451 


01666 


31452712 


01667 


00001504 


01670 


77777777 


01671 


00001344 


01672 


00177761 


01673 


00177764 


01674 


00177770 


01675 


00000000 


01676 


00177763 


01677 


00001525 


01700 


33120152 


01701 


00001444 


01702 


00177757 


01703 


33120252 


01704 


00001570 


01705 


33120352 


01706 


33120452 


01707 


00001434 


01710 


00000707 


01711 


S2120000 


01712 


00177755 


01713 


12000052 


01714 


00177767 



Table 4-4. 925/930 Computers, Extended Mode I/O Test Program (Sheet 20 of 20) 



784 



783 
786 



END 



BEGIN 



CO 

O 

S3 
O 

00 
Oi 

n 



00 

(? 

3 



SD 



September 1965 



SDS 900685C 



Paragraphs 4.64 to 4. 73 



4.64 Operation 

4.65 To select the reader and punch units to be used 
enter: 

"CU" P to select punch, 

"CU" R to select reader. 

The letter C is the channel number and may be any 
digit 0-7 and the letter U is the unit, either one or 
two. The reader and punch need not be on the same 
channel. 

4.66 The test is started by entering the letter "S". 
Control of the test operation is then a function of the 
Breakpoint Switches. Table 4-5 summarizes the switch 
functions. 

4.67 When running cyclic tests from punch to read, 
the tope from the punch should be inserted into the 
reader. 

4.68 Punching 

4.69 The program punches four blocks of 64 characters 
each in one pass. The choracters form a counting 
sequence from 00 to 778- The first block is started with 
leader and output with an lOSP. All punching is done 
in the one character per word mode. When the word 
count reaches zero, an lOSD is loaded to punch a 
second block of 64 characters. No leader is punched 
between the first and second blocks. This results in 
one physical block 128 characters long. Starting with 
leader, two additional blocks of 64 characters are then 
punched with an lOSD. 



4.70 At the conclusion of each output operation, the 
channel address register is stored and compared with the 
expected value. If they do not agree, the program 
types the expected and actual values. 

4.71 The program tests the channel during the output 
operation to see if the channel should erroneously dis- 
connect before the word count reaches zero. 

4.72 Reading 

4.73 Each of the four blocks is read with a different 
set of commands and counts so as to test as many opera- 
tions as possible. After reading a block, a general sub- 
routine checks for input parity errors, for channel end 
address agreement with the expected address, and the 
data read character by character. Error messages with 
block numbers ore typed in the event of any one of these 
tests failing. In the event of a test falling, reference 
should then be made to the test program flow diagram 
and troubleshooting information contained in Section 5 
of this manual. The handling of each block is as 
follows: 

a. Block 1. The first block is one-half of a 128 
character physical block. Reading one character per 
word, an lOSD with a count of 64 is used to read this 
block. The program checks to see if the count reaches 
zero and the channel becomes inactive at the same time. 

b. Block 2. This is the second half of the first 
physical block and is read with on lOSP with a count of 
65. The read should terminate because of the end of 
record. The program checks to see that the word count 
does not reach zero and the channel remains active after 
the CIT (inter-record test) instruction skips. The tape is 





Table 4-5. 9300 Computer Breakpoint Swi 


tch Functions 


Breakpoint 

Switch 


Reset 


Set 


1 


Run in the normal mode as determined 
by the other switches 


Stop and return to keyboard 
control at the end of the 
current pass (punch or read) 


2 


Continue to run test selected by 
switch 3 


Cycle test runs from punch to 
read to punch and so on 


3* 


Selects punch mode 


Selects to punch and so on 


4 


Stop and type diagnostic messages 
whenever an error occurs 


Do not stop and type on errors 
but continue to run 



*Used when switch 2 is reset or when starting test 



4-35 



Paragraphs 4. 74 to 4. 75 



SDS 900685C 



September 1965 



finally stopped with a disconnect before the data is 
checked. 

c. Block 3 . Block 3 is a 64 character physical 
block. It is read with two channel commands. The first 
is an lOSP with a count of 32. If the count goes to zero 
before the channel disconnects, an lORP with a count 
of 33 is loaded. This should cause the inter-record 
indicator to be turned on at the end of the record. The 
count should not reach zero and the channel should 
remain active. The tape is again stopped with a dis- 
connect before the data is checked. 



^' Block 4. This is the third physical block of 64 
characters and is read with an lORD with a count of 56. 
The program waits for the channel to be inactive then 
checks to see if the channel ignored the last eight 
characters. If the tape was erroneously stopped after 
the 56th character, it will show up as a failure on the 
first block of the next read pass. 

4.74 Test Program 



4.75 Table 4-6 gives the test program for the 9300 
computer I/O extended mode. 



4-36 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 1 of 20) 



00022124 



I 

CO 



1 


T 


2 


* 


3 


* 


4 


* 


5 


* 


6 


* 


7 


* 


8 


* 


9 


* 


10 


* 


11 


* 


12 


* 


IJ 


* 


14 


* 


15 


* 


16 


• 


17 


* 


19 


* 


19 


* 


20 


* 


21 


* 


22 


* 


23 


« 


24 


* 


25 


* 


26 




27 


* 


28 


* 


29 


* 


30 


* 


31 


* 


32 


♦ 


33 


« 


34 


* 


35 


* 


36 


* 


3 7 


* 


38 


* 


39 


* 


40 


* 


41 


* 


42 


* 


43 


* 


44 


* 


45 


* 


46 


* 


47 


• 


46 


* 



TYPE 



ECU 



9300 



MACHINE definition: 9300 



EXTENDED MODE 1/9 TEST PReGRArt. < 925/930/9300 ALL CHANNELS) 

A.W. ENGLAND, SDS 



THIb PROGRAM USES THE PAPcR TAPE READER AND PUNCH T9 CHECK THE 
OPERATION OF THE I/O CHANNELS IN THE EXTENDED INTERLACE MODE OF 
0PERATI3N. THE READER AND PUNCH MAY BE CONNECTED TO ANY INTERLACED 
TMCC OR DACC. THEY NEED NOT dE ATTACHED TO THE SAME CHANNEL. THE 
PROGRAM ADDRESSES THE K£Y90ARiJ FOR INFORMATION ABOUT UNIT AND CHANNEL 
SELECTION. 

TO SELECT PUNCH TYPE: *CU'P 

TO SELECT READER TYPE: 'CU'R 

UHERE 'C REPRESENTS CHANNEL NO. AND MAY HAVE Th£ VALUES 0-7; 
AND 'U* REPRESENTS UNIT NO. AND MAY HAVE THE VALUE 1-2. THE LETTER 
P OR R CAUSE THE SELECTION TO BE MADE WITH THE TUO PREVIOUS DIGITS. 
SPACES SHOULD NOT BE TYPED BETWEEN DIGITS OR CONTROL CHARACTER. 

TO START THE TEST TYPE: S 

PAGt 



BREAKPOINTS OR SENSE SWITCHES CONTROL THE RUNNING OF THE PROGRAMS 



CD 

n 

3 
cr 



o^ 



o 

CO 

o 
o 

00 

en 

n 



SWITCH 



BP 

sw 



BP 

sw 



BP 
SW 



RESET 



RUN IN THE NORMAL MODE 
AS DETERMINED BY THE 
OTHER SWITCHES. 



CONTINUE TO RUN THE 
TEST MODE SELECTED BY 
SWITCH 3. 



SET 



STOP AT THE END OF THE CURRENT 
PASS AND RETURN TO KEY BOARD 
CONTROL 



CYCLE TEST RUNS FRCJM READ 
PUNCH TO READ, ETC. 



SELECTS PUNCH MODE 
(USED UHEN SUITCH 2 



SELECTS READ MQDE. 
IS RESET 9W JhEN STARTING Th£ TEST) 



BP 4 



STOP AND TYPE DIAGNOSTIC DO NOT STOP 3P TYPE ON ERROhS, 



■^ Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 2 of 20) 



CO 
00 



l/l 



49 ♦ SW 4 MESSAliES WHENEVER AN C©NTINUE RUNi>JlNS REGARDLESS. 

50 * ERR9R 9CCLiRc>. 

51 * 

52 * 

53 * M8TE: to RJN caNTIN9US Ff^BH READ TO PUNCH THE OUTPUT OF THE PUNCH 

54 * SHtfULO dE FED INTO fHE READER. A LOOP SHOULD BE USED TO RUN 

55 * CONriUPUS OiM THE READER. 

56 PAGE 

57 * 

58 * THE FOLLOWING SECTION OF CODE DEFINES EITHER A 925/930 INSTRUCTION 

59 * SET OR A 9300 INSTRUCTION SET. THIS IS DONE ON THE BASIS OF THE 

60 • MACHINE TYPE STATEMENT AT THE BEGINNING OF THE DECK. 

61 * 

62 * 

63 * 

64 * 

65 PROC 

66 DF9300 NAME 

67 SINST FORM 3*6,15 

68 P PROC 1 DEFINE INDEX OP'S TO IMPLY XI. 

69 $LDX NAME 017 O 

70 $STX NAME 077 ^ 

71 SBRX NAME 057 § 

72 INSr (P(*i)*/2)**1.P(0>#P<1) g^ 

73 END Pj 

74 P PROC 1 

75 $XAB NAME 037733 DEFINE COMPATIBLE REGISTER OP'S 

76 $ABC NAME 037731 

77 $BAC NAME 037713 

78 $CLR NAME 037711 

79 INST 0*040. P(0) 
PO END 

81 P PROC 1 

62 $RSh NAME 000 DEFINE COMPATIBLE SHIFTS 

83 $RCY NAME 002 

84 $LSh NAME 004 
86 $LCY NAME 006 

86 SNOD NAMt 044 

87 ^SHFF FORn 3*6*6*9 

88 SHFF P(2 ).060*P(0)*P(1)**0777 

89 END 

OO P PROC 1 DEFINE MISC. COMPATIBLE OP'S. ^ 

91 Jf^lN NAME 071 <t> 

Q2 $f^IB NAMt 03C ^ 

QJ $RIM NAMt 03? 3 

94 INST (P<*1 )*/2) + + P(2)*P(0)*P( 1 ) ^ 

95 END - 

96 * ^ 



CO 

Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 3 of 20) ^ 

3 

97 $X EQU 1 DEFINE INDEX TAG'X' FOR XI g" 

98 * E5JD CONSTANT 

99 AORG 0177 ^ 

100 SEODC DATA 04000000 EOD CONSTANT S 

101 * 

102 SSJTFRM FORM 3*6#3-12 

103 PROC 1 

104 SBPT NAHE 0400O0 

105 $PVT NAME 014040 

106 $R9V NAME 04000 

107 $SOV NAME 00040 

108 SUTFRM O.C2?#Q(0)*/(-12)**7,Q(OI**0777 7 + 'KQ< 1 )>0)*/( 6-0(1 > ) 

109 END 

110 END 

111 * 

112 PROC 

113 DF930 NAME 

114 ♦ 

115 • IF NOT A 9300 THEN DO THE FOLLOWING OPERATIONS 

116 * i^ 

117 P PROC 1 DEFINE I/O INSTRUCTIONS S 

118 $M1B NAME 012 -o 

119 SBIM NAME 032 8 

120 INST FORM 3#6,1.14 oo 

121 INSl P(2),P(0).P(*1 »,P(1) n 

122 END 

123 * 

124 $X ECU 2 DEFINE INDEX FAG 'X* FOR 2 ON 930 

125 * 

126 * 

127 AORi 0177 

128 JiFODC DATA 0400000 EOD CONSTANT 

129 * 

130 * 

131 N PROC 1 SET OVERFLOW 
112 $S3V NAME 

133 BRR $#4 

134 END 

135 * 

136 M PROC 1 BRANCH AND CLEAR INTERRUPT 



137 $PRC NAME 

138 DO M(*l».l,2 

139 BRU M(n 

140 BRU *$*1 

141 PZE M(n 

142 END 

t 143 P PROC 1 

^ 144 $DSC NAME 



I 

o 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 4 of 20) 









145 


$ALC 


NAMt 


050000 










146 


$ASC 


NAMl 


012000 










147 


$T9P 


NAME 


014000 










14S 


I 


FdRn 


3#6*15 










14 9 




I 


Ft 1 )*#2.(P(1 )**4) 


* / 3 ♦ ♦ 2. P ( ) ♦ ♦ ( P ( 1 ) • * 1 ) • / 6 








150 




END 












151 


P 


PRec 


1 










152 


SCAT 


NAME 


014000 










153 


$CET 


NAME 


011000 










154 


JCIT 


NAME 


010400 










155 


$CZT 


NAME 


012000 










156 


I 


FORM 


3#6,15 










157 




I 


PU )**2*040-P(0) + + (P(l )**4)*/12-»-+(P(l )**n*/6 








158 




END 












159 




END 












160 




DO 


TYPE=9300 




00177 


04000000 


161 




DF9300 












162 




DB 


TYPE<9300 










163 




DF930 












164 




PAGE 












165 


* 














166 


* THE 


START 


OF THE PROGRAH 










167 


« 








00200 






168 




A ORG 


0200 




00200 





16 002D3 


169 


BEGIN 


LDA 


BRUGO 


INITIALIZE RECOVERY LOCATIONS 


00201 





76 OOODl 


170 




STA 


1 




00202 





76 00032 


171 




STA 


032 




00203 





01 00234 


172 


BRUGQ 


BRU 


KYBD 




00204 





21 01241 


173 


KY3D 


EXtj 


RDIS 




00205 





21 01231 


174 




EXU 


PDIS 




00206 





40 37711 


175 


cea 


CLR 






00207 





3 76 01444 


176 




STA 


Tl 




00210 





02 02031 


177 




RKB 


0*1*1 




00211 





32 01445 


178 


GOl 


BIM 


Tl + 1 


READ CHARACTER 


00212 





16 01445 


179 




LDA 


Tl + 1 




00213 





14 01636 


180 




LDB 


= 07 7 




00214 





55 01637 


lei 




SKM 


= ' p' 


CHECK FOR CONTROL CHAR. 


00215 





01 00217 


182 




BRU 


S + 2 




00216 





01 00233 


183 




BRU 


PO 




00217 





55 01640 


184 




SKM 


= ' R' 




00220 





01 00222 


185 




BRU 


$ + 2 




00221 





01 00256 


186 




BRU 


RQ 




00222 





55 01641 


187 




SKM 


s* 




00223 





01 00225 


18 8. 




BRU 


S + 2 




00224 





03 00317 


189 




BRM 


SO 




00225 





54 01642 


190 




SKA 


= 070 


CHECK FOR DIGIT 


00226 





01 00236 


191 




BRU 


GO? 


IF NOT CONTROL OR DIGIT CLEAR 


00227 





14 01444 


192 




LDB 


Tl 





CO 

o 

8 

CO 

n 



CO 

(0 
T) 

3 
cr 






00230 7A 01446 
002 31 3 7 6 014 44 
00232 Ul 00211 



00233 
00234 
00235 
00236 
00237 
00240 
00241 
00242 
00243 
00244 
00245 
00246 
00247 
00250 
00251 
00252 
00253 
00254 
00255 
00256 
00257 
00260 
00261 
00262 
00263 
00264 
00265 



03 00323 
17 01643 

1 16 01234 
11 01644 
13 01446 

76 00235 
57 00235 
17 01645 

1 16 01227 
11 01646 
13 01447 

76 00243 
57 00243 
17 01643 

1 16 01212 
11 01647 
13 01450 
76 00251 
57 00256 
57 00251 

16 01230 



11 
13 

76 
13 

76 

01 



01650 
01444 
01230 
01651 
01227 
00234 



I 



00266 





03 00323 


00267 


1 


17 01643 


00270 





1 16 CI 244 


00271 





i 1 Q1644 


00272 





13 01446 


00273 


1 


76 0027C 


00274 


1 


57 00270 


00275 


1 


17 01643 


00276 


9 


1 16 01240 


00277 





11 01646 



Tab 


\e4-6 


>. 9300 C 


Computer, Extended Mode I/O 1 


193 




ST9 


Tl+2 


194 




51 A 


Tl 


195 




BRU 


GSl 


196 




PA (it 




197 


* 






198 


* 


PUNCH CHANNEL SET UP RfluriNE 


199 


* 






200 


PO 


BRM 


MAKECH 


201 




LDX 


=-4«*0177777 


202 




LDA 


PALC+1. X 


203 




ETR 


= 0'=;0277677 


204 




MRG 


Tl + 2 


205 




STa 


*$-3 


206 




BRX 


$-4 


207 




LDX 


=-3**0177777 


208 




LDA 


PCFT+1,X 


209 




ETR 


=057737677 


210 




MRG 


Tl + 3 


211 




STA 


*$-3 


212 




BRX 


$-4 


213 




LDX 


=-4**3177777 


214 




LDA 


PieSD+2.X 


215 




ETR 


=0^0277777 


216 




MRG 


Tl+4 


217 




STA 


*$-3 


213 




BRX 


$♦1 


219 




BRX 


i-5 


220 




LDA 


PTL 


221 




ETR 


= -2 


222 




MRG 


Tl 


223 




STA 


PTL 


224 




MRG 


=02000 


225 




STA 


PPT 


226 




BRU 


KYPD 


2^7 


* 






228 


* 


READER 


CHANNEL SET UP KOUTINt 


229 


* 






230 


* 






231 


PC 


HRM 


M A K t C H 


232 




LDX 


=-4**Jl7777; 


23J 




LDA 


RALC+1#X 


234 




ETR 


=050277677 


235 




MRG 


Tl*2 


236 




STA 


*J-3 


237 




BRX 


$-4 


238 




LDX 


=-4**0177777 


239 




LDA 


RCIT-t-l,X 


240 




ETR 


=057737677 



SAVE CHANNEL NUMBER IN 
SAVE UNIT NUMBER IN H 



11 +2 



<6 

3 



c-n 



GET CHANNEL NO. BUILT, 
UPDAIE E8M/L0D'S 



SAVED IN Tl*2 



INSERT CHANNEL DESIGNATION 



UPDATE SKS'S 



UPDAIE CHANNEL COMMANDS 



tn 

O 
O 
O 

o» 

Ol 

O 



UPDAIE UNIT NO, 



MAKE NO LEADER E9M 



GlT CHANNlL Nft gUILT 



BUILD SKS'S 



t 






1 






00300 





13 01447 


00301 


1 


76 00276 


00302 


1 


57 00276 


00303 


1 


17 01652 


00304 





1 16 012?4 


00305 





11 01653 


00306 





13 01450 


00307 


I 


76 00334 


00310 


1 


57 00311 


00311 


1 


57 00304 


00312 





16 01240 


00313 





11 01650 


00314 





13 01444 


00315 





76 01240 


00316 





01 00234 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 6 of 20) 



00317 02 00000 

00320 22 4 0013 

00321 01 00640 

00322 01 00356 



00323 








00 00030 


00324 





4C 


1 37711 


00325 








16 01446 


00326 








54 01654 


00327 








14 00177 


00330 








74 01450 


00331 








11 01655 


00332 








76 01446 


00333 


1 


17 


' 01446 


00334 








16 O1450 


00335 





1 


13 00352 


00336 








76 01446 


00337 


e 


4C 


I 37713 


00340 








54 00177 


00341 








14 01656 


00342 





4C 


) 37 7 33 


00343 





1 


13 00352 


00344 








76 01447 


00345 








16 01444 


00346 








11 01657 


00347 








12 01657 



241 




MRG 


Tl+3 




242 




S1A 


*$-3 




243 




BRX 


$-4 




244 




LDX 


=-10**0177777 


BUILD CHANNEL COMMAND 


24 5 




LDA 


RieRD+2#X 




246 




ETR 


=070277777 




247 




MRG 


Tl + 4 




246 




SI A 


*$-3 




249 




BRX 


S-i-l 




250 




SRX 


$-5 




251 




LDA 


RPT 


BUILD RPT WITH UNIT 


252 




ETR 


= -2 




253 




MRG 


Tl 




254 




STA 


RPT 




255 




BRU 


KYBD 




256 


* 








257 


* 








258 


* 


START TEST 


RUNNING 




259 


* 








260 


SO 


DSC 





DISCONNECT 


261 




BPT 


3 


START READ OR PUNCH? 


262 




BRU 


IN 


READ 


263 




BRU 


OUT 


PUNCH 


264 




PAGE 






265 


* 








266 


♦ 


BUILD CHANNEL NO. SUBRtJUTINE 




267 


* 








268 


MAKECH PZE 






269 




CLR 






270 




LDA 


Tl + 2 


GET CH. NO. 


271 




SKA 


= 4 


EOD REQUIRED 


272 




LDB 


E9DC 


YES 


273 




STB 


Tl + 4 


NO, SAVE EOD BIT. 


274 




ETR 


= 3 




275 




STA 


Tl+2 




276 




LDX 


Tl + 2 




277 




LDA 


Tl+4 




278 




MRG 


MAKETB»X 


BUILD EOM/EOD SELECT 


279 




STA 


Tl + 2 


SAVE EOM 


280 




BAC 




BUILD SKS SELECTION 


281 




SKA 


E9DC 




282 




LDB 


=040000 




28 3 




XAB 






284- 




MRG 


MAKETB*X 




285 




STA 


Tl+3 


SAVE SKS 


286 




LDA 


Tl 


BUILD UNIT NO. BIT 


287 




ETR 


= 1 




289 




ESR 


= 1 





EOM/EBD'S 



NO. 



I/) 

so 

8 

00 

n 



CO 

(B 

3 

D- 

fD 



vO 
O- 
Ui 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 7 of 20) 



00350 76 01444 

00351 -0. 41 003 23 

00352 00000000 

00353 00000100 

00354 20000000 

00355 20000100 



00356 


1 


17 01660 


00357 





40 37711 


00360 


9 


1 76 01344 


00361 





05 01651 


00362 


1 


57 00360 


00363 





21 01230 


00364 





21 01233 


00365 





21 01236 


00366 





31 01237 


00367 


1 


17 01643 


00370 


B 


14 01662 


00371 





16 00431 


q00372 


, 


03 00610 


00373 





21 01226 


00374 





22 4 0004 


00375 





01 00416 


00376 





21 01231 


00377 





02 02641 


00400 





30 01663 


00401 





30 01664 


00402 





30 01665 


00403 





30 01666 


00404 





40 37733 


00405 





13 01635 


00406 





76 00437 


00407 





30 00000 


00410 





71 00407 


00411 


1 


57 00407 


00412 





02 14000 


00413 





20 14000 


004 14- 





01 00413 


00415 





31 00234 



00416 03 00476 

00417 21 01224 
01 00422 
21 01227 



2^9 


STA 


11 


290 


BRR 


MAKECH 


291 


* 




292 


MAKETB DATA 


0»010Q 



SAVE UNIT NO, BIT 
EXIT 



0»0 100* 020000000*020000 100 



C/1 

-a 

(0 

3 

(0 



^O 

o» 



■f 00420 
h 00421 



293 
294 
295 

296 * 

297 8UT 
29a 
299 
300 

301 

302 eUT4 

303 

304 

305 
306 
307 
308 
309 
310 
311 
312 
313 
314 
315 
316 
317 
31d 
319 
320 
121 
322 
323 
324 
325 
326 
327 
32b 
329 
330 
331 
332 



Pf^Gz. 



PAPER TAPE PUNCH 8UTPUT SECTION. 



0UT2 



c-eiep 



3L'T4A 



LDX =-64**0177777 

CLR 

STA IMAG£+64*X 

ADD =01000000 

BRX $-2 

EXU PTL 

EXU PALC 

LCH PIPSP 

LDX =-4**3177777 

LDB =ERMSG1 

LDA PCATC 

BRM UCZ 

EXU PCET 

BPT 4 

BRU eUT4A 

EXU PDIS 

TYP 0#1*4 

MI8 =052121225 

MIB =051514651 

MIB =012246451 

MIB =031452712 

XAB 

MRG MIBX 

STA $+1 

MIB 00 

MIN J-1 

BRX $-? 

TPP 

CAT 

B R IJ $ - 1 

3RU KVBD 

9Ki1 9UTP1N 

EXU PCAT 

BRU $+? 

EXU PPT 



SET UP OUTPUT IMAGE WITH 64 WORDS 



START PUNCH WITH LEADER 
ALERT CHANNEL 
L9AD I9SP IHAGE*64 

SET UP FBR SUBROUTINE TP TYPE: 
I9SP, ftUTPUT 

WAIT FOR CHANNEL COUNT = ZERO 
ERROR ON OUTPUT 
YES, CHECK BP4 FOR NO STOP 
NO* NO STOP ON ERROR 
ERROK, DISCONNECT CHANNEL 
TYPE GENERAL ERROR MESSAGE 
I E 
RR9R 
DUR 
li^G 
TY^E SPECIFIC ERROR MESSAGE 



TO BE REPLACED AT RUN TIME 



C7 
oi 

o 
o 
o 

cx> 
en 

n 



Q3 PIN AND CHECK CHANNEL ADDRlS;> 
IF CHANNEL INACTIVE -HEADDRESS PUNCH 



00422 





21 


01233 


00423 





21 


01210 


00424 





31 


01211 


00425 


1 


17 01643 


JD04.2-6 


0- 


u 


-016^7 


00427 





16 


00431 


00430 





03 


00610 


00431 





21 


01224 


00432 





01 


00431 


00433 





21 


01226 


00434 





22 4 


0004 


00435 





01 


00437 


00436 





01 


00376 


00437 





03 


00476 


00440 





40 37711 


0044 1 





76 


01462 


00442 





21 


01230 


00443 





21 


01233 


00444 


9 


21 


01210 


00445 





31 


01211 


00446 


1 


17 01643 


00447 





D 14 


01667 


00450 





16 


00431 


00451 





03 


00610 


00452 





21 


01224 


00453 





01 


00452 


00454 





21 


01226 


00455 





22 4 


0004 


00456 





01 


00450 


00457 





01 


00376 


00460 





03 


00476 


00461 





53 


01452 


00462 ■ 





01 


00454 


00463 





01 


00457 


0464 





16 


016 7 


00465 





7b 


01452 


00466 





01 


00442 


00467 





22 4 


0043 


0O4 7O 





01 


002 34 


0O471 





22 4 


0023 


00472 





01 


006 40 


00473 





22 4 


0013 


0047 4 





01 


00640 


00475 





01 


00356 



Table 4-6. 9300 Computer, Extended Mode l/O Test Program (Sheet 8 of 20) 



333 




EXU 


334 




LCH 


335 


euTi 


LDX 


3-3-6 




L D-B 


33 7 




LDA 


338 




BRM 


339 


PCATC 


EXU 


340 




BRU 


341 




EXU 


342 




9PT 


343 




BRU 


344 




BRU 


345 




BRM 


346 




CLR 


347 




STA 


348 


©UTl A 


EXU 


349 




EXU 


350 




LCH 


351 




LDX 


352 




LDB 


353 




LDA 


354 




BRM 


355 




EXU 


356 




BRU 


357 




EXU 


358 




BPT 


359 




BRU 


360 




BRU 


361 




BRM 


362 




SKN 


363 




8RU 


364 




BRU 


365 




LDA 


366 




STA 


367 




BRU 


368 


* 




369 


* 




370 


9UT3 


BPT 


371 




BRU 


372 




BPT 


373 




BRU 


374 




BPT 


375 




BRU 


376 




BRU 


377 


* 




378 


* SUBROUT 



PALC 


PIOSD 


=-4**0177777 


= ERM-S-G2 


PCATC 


UCZ 


PCAT 


$-1 


PCET 


4 


$ + ? 


8UT2 


OUTPIN 


PRF 


PTL 


PALC 


PICtSD 


=-4**0177777 


=ERMSG2 


PCATC 


UC7 


PCAT 


$-1 


PCET 


4 


$ + ? 


eUT2 


8UTPIN 


PRF 


$♦? 


OUT 3 


= - 1 


PWF 


8UT1A 


1 


KYBD 


2 


IN 


3 


IN 


euT 



L9AD CH. I9SD IMAGE, 64 

SET UP ERR9R MESSAGE: 
I3SD, OUTPUT 

WAIT FOR CeUNT EQUAL ZERO 

CHAN. ACTIVE? 

YES 

NO, ERROR? 

YES, IS STOP ALLOWED? 

NO ERROR OR NO STOP 

ERROR STOP ALLOWED 

GO PIN AND CHECK CHANNEL ADDRESS 

RCPUNCH REPEAT) 



LOAD lOSD IMAGE, 64 



SET UP ERROR MESSAGE: 



CHAN. ACTIVE? 
YES 

NO, CHAN. ERROR 
YES. IS ERROR STOP ALLftJED 
NO, NO 
YES 

GO PIN AND CHECK CHAMNEL ADDRESS 
PUNCH REPEAT 
RESET 
SET 
S(PJNCH REPEAT) 



GO OR STOR 

STOP 

GO. CYCLE? 

YES 

ONE ONLY 



CO 

C 

CO 

^o 

8 

On 
00 



SUBROUTINE TO CHECK CHANNEL ADDRESS 



CO 

a 

3 



On 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 9 of 20) 



a047.6^ 


0^ 


-0 00 


ooa^a 


00477 





21 


01232 


00500 





J3 


01444 


0050 i 





16 


01444 


00502 





12 


01671 


00503 





54 


01670 


00504 





22 4 


0004 


00505 





41 


00476 


00506 


1 


77 01445 


00507 





40 37733 


00510 





13 


01635 


00511 





76 


00530 


00512 





16 


01671 


00513 





03 


00537 


00514 





76 


005 7 7 


00515 





74 


006D0 


00516 





16 


01444 


00517 





03 


00537 


00520 





76 


006D5 


00521 





74 


00636 


00522 





a 21 


012 31 


0052 3 


1 


17 01672 


00524 ■ 





02 


0264 1 


00525 


1 


30 00574 


00526 


1 


57 0052^1 


00527 


1 


17 01445 


00530 





30 00000 


00531 





71 00530 


00532 


1 


57 00530 


00533 


1 


17 01673 


00534 


1 


30 00610 


00535 


1 


57 00534 


00536 





01 


00412 



I 

0\ 



00537 





00 00000 


00540 


1 


17 01674 


00541 





40 37731 


00542 





60 04 003 


00543 





1 76 01456 


00544 





16 01675 


00545 


1 


57 00542 


00546 





40 37711 


00547 


1 


17 01674 


00550 





60 06 005 



37y 


* 








3^ft0~^ 


aUTPl-W 


PZE _ 





381 






EXU 


PASC 


382 






PIN 


Tl 


383 






LDA 


Tl 


384 






EOR 


=IMA5E+64 


385 






SKA 


= -1 


386 






BPT 


4 


387 






BRR 


eUTPIN 


388 






SIX 


Tl*l 


389 






XAB 




390 






MRG 


MIBX 


391 






STA 


OTPINl 


392 






LDA 


=IMAGE+64 


393 






BRM 


MxecT 


394 






STA 


OTPNUl 


395 






STB 


&TPNM1+1 


396 






LDA 


Tl 


397 






BRM 


MKeCT 


398 






STA 


8TPNM2 


399 






STB 


eTPNf1?+l 


400 






EXU 


PDIS 


401 






LUX 


=-15**0177777 


402 






TYP 


0.1*4 


403 






MIB 


eTPNn+l5,x 


40 4 






BRX 


J-t 


405 






LDX 


Tl + l 


406 


9TPIN1 


MTB 


00 


407 






MIN 


$-1 


408 






BRX 


$-2 


409 


0TiPIN2 


LDX 


=-12**0177777 


410 






MIB 


8TPNM2-»-3,X 


411 






BRX 


$-1 


412 






BRU 


GSTSP 


413 


* 








414 


* 








415 


* 


SUBROUTlNd 


TQ MAKE ONE WO 


416 


* 








417 


MKOCT 


PZE 





413 






LDX 


=-8**0177777 


419 






ABC 




420 






LSH 


3 


421 






STA 


T1+10#X 


422 






LDA 


= 


423 






BRX 


$-3 


424 






CLR 




425 






LDX 


=-8**0177777 


426 






LCY 


6 



ALERI Td STORE PUNCH CHANNEL 
STORE ADDRESS 

COMPARE WITH EXPECTED 

NOT EQUAL 

EajAL OR ERROR STOP NOT PERMITTED 
SAVE LENGTH OF ERROR MESSAGE 
SET UP ERROR OUTPUTTER 



GENERATE EXPECTED PIN UORD IN BCD 

SAVE EXPECTED 

GENERATE ACTUAL PIN WORD IN BCD 

DISCONNECT PUNCH CHANi\»EL 

OUTPUT MESSAGE 

OUTPUT SPECIAL MESSAGE 

OUTPUT RECEIVED AND EXPECTED MESSAGE 



CO 

(b 
-a 

(0 

3 

D" 



vO 



CO 

c 

CO 

«o 

O 
O 

o. 

00 

Cn 

n 



INTO 8 BCD OCTAL DIGITS 



TO UORD TO B 
SHIFT OUT OCTAL DIGIT 
SAVE BCD CHARACTER 
CLEAR A 



REASSEMBLY BCD CHARACTERS INTO A ♦ 6. 



I 

St 



00551 1 13 01456 

00552 1 57 00550 

00553 40 37733 

00554 41 00537 



00555 


52254524 


00556 


12212424 


00557 


51256262 


00560 


12265146 


00561 


44 122330 


00562 


21454525 


00563 


• 43122431 


00564 


24124546 


00565 


63122127 


00566 


51252512 


0056 7 


66316330 


00570 


12256747 


00571 


25236325 


00572 


24122126 


00573 


63255112 


005 74 


25674725 


00575 


23632524 


00576 


12121212 


00577 


00000000 


00600 


00000000 


00601 


T3121252 


00602 


51252325 


00603 


31652524 


00604 


12121212 


00605 


00000000 


00606 


00000000 


00607 


33125252 



00610 





00 00030 


006 1 1 





76 00617 


00612 





05 01-657 


00613 





76 00614 


00614 





20 12000 


00615 





01 00617 


00616 





41 00610 


00617 





20 14000 


00620 





01 00614 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 10 of 20) 

427 MRG Tl+10*X 

423 BRX $-2 

429 XA8 

430 8RR MKeCT FXIT 

■4'3-l- * ■• - - - - 

432 * 

433 * ERROR MESSAGES F9H CHAN'^^EL ADURESS TEST SUBRaUTINc 

434 * 

435 OTPNM BCD 52*1END ADDRESS F-^OM CHANNEL DID NOT AGREE WITH EXPECFE 



436 
437 

43d eiPN 
439 

440 eTPNtl2 DATA 



BCD 


8,D AFTER 


BCD 


12*EXPECTED 


DATA 


0#0 


BCD 


16,. IRECEIVED 



0.0 



441 




BCD 


4.. 


442 




PAGE 




443 


* 






444 


* 


WAIT FOR 


COUNT 


445 


* 






446 


wcz 


PZE 




447 




ST A 


$ + 6 


44 d 




ADD 


= 1 


449 




STA 


$♦1 


450 




CZT 


00 


451 




BRU 


$♦2 


452 




BRR 


VICZ 


453 




CAT 


00 


454 




BRU 


$-4 



ENTRY 

SAVE R/PCAT 

MAKE A CZT 

SAVE R/PCZT 

C = 02? 

NO 

YES 

CHANNEL ACTIVE? 

YES 



on 
•o 

8 

00 

n 



I/) 

■o 

3 
cr 



o> 



*|^--v"^ 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 11 of 20) 



00621 





22 4 0004 


00622- 


0"0 41 006ia 


00623 


1 


77 01444 


00624 





40 37733 


00625 





13 01635 


00626 





76 00634 


00627 


1 


17 01676 


00630 





02 02641 


00631 


1 


30 01500 


00632 


1 


57 00631 


00633 


1 


17 01444 


00634 





30 00000 


00635 





71 00634 


00636 


I 


57 00634 


00637 





01 00412 



I 



00640 





03 


01177 


00641 





22 


4003 


00642 





21 


01243 


00643 





21 


01212 


00644 





31 


01213 


00645 





21 


01235 


00646 





01 


00657 


00647 





21 


01234 


00650 





22 4 


0004 


00651 





01 


00670 


00652 


1 


17 01676 


00653 





02 


02641 


00654 


1 


30 01525 


00655 


1 


57 00654 


00656 





01 


00412 


00657 





21 


01234 


00660 





01 


00645 


00661 





21 


01235 


00662 





01 


00654 


00663 





01 


00670 


00664 


1 


17 01645 


00665 





14 


01677 


00666 





16 


00647 


00667 





03 


00610 


00670 





16 


01730 


00671 





14 


01731 


00672 





03 


01055 


00673 





03 


01177 



455 




BPT 


4 


456 




BRR 


wcz 


457 




STX 


Tl 


45« 




XAB 




459 




MRG 


MIBX 


460 




STA 


$ + 6 


461 




LDX 


=-13**0177777 


462 




TYP 


0«1*4 


463 




MIB 


DISMSG'H3,X 


464 




BRX 


$-1 


465 




LDX 


Tl 


466 




Mie 


00 


467 




MIN 


$-1 


46d 




BRX 


$-2 


469 




BRU 


G-^TOP 


470 




PAGt 




471 


* 






472 


• INPUT SECTION 


473 


* 






474 


IN 


BRM 


STARTP 


475 




ROV 




476 




EXU 


RALC 


477 




LCH 


RIPSD 


476 


I NOB 


EXU 


RCZT 


479 




BRU 


INO 


460 


RCATC 


EXU 


RCAT 


481 




BPT 


4 


482 




BRU 


INOA 


463 




LDX 


=-13**0177777 


484 




TYP 


'0«1*4 


485 




MIB 


ERr^SG4 + 13#X 


466 




BRX 


$-1 


467 




BRU 


GUTOP 


486 


* 






469 


INO 


EXU 


RCAT 


490 




BRU 


INOB 


491 




EXU 


RCZT 


492 




BRU 


$ + 2 


493 




BRU 


INOA 


494 




LDX 


=-3**0177777 


495 




LDB 


=ERMSG5 


496 




LDA 


RCATC 


497 




BRH 


UCZ 


496 


INOA 


LDA 


=033120152 


499 




LDB 


=eUFFER+64 


500 




BRM 


CHECK 


501 


INI 


SRtI 


STARTP 



N8, INHIBIT ERRdRS 

YES 

NO* PRINT ERROR MESSAGE 



(D 

3 
tr 

- <D 



>o 



STARI READER 

ALERI 

LOAD lOSD BUFFER. 64 

C = 

NO 

YES, CHAN. ACTIVE 

YES, ERROR STOP PERHITTED 

NO, NO CONT. 

YES 



CO 

S3 
O 

00 
Oi 

O 



CHAN. ACTIVE STILL? 

YES 

NO. C=0 

NO 
YES 
SET UP ERROR MESSAGE 



GO DO DISCONNECT ERROR TEST 

Block no. i 

END ADDRESS EXPECTED 

GO CHECK DATA 

START READER IF DATA CHECKED O.K 



I 
c» 



00674 
00675 
00676 
00677 
007^00 
00701 
0.0702 
00703 
00704 
00705 
00706 
00707 
00710 
00711 
00712 
.00713 
00714 
007 1 5 

00716 
00717 
00720 
00721 
00722 
00723 
00724 
00725 
00726 
00727 
00730 
00731 

00732 
00733 
00734 
007 35 
00736 
00737 
0074 
00741 

007 4 2 
007 4 3; 
007 4 4 
007 4 5 
00746 
00747 
00750 



22 
21 
21 
31 
16 
76 
21 
01 
01 
21 
01 
22 4 
01 
17 01 
02 
1 30 01 
1 57 00 
O 01 



4003 

01243 

01214 

01215 

01 '6-70 

01451 

1 23 7 

00735 

007 32 

01234 

00716 

0004 

007 32 

672 

026 41 

54 7 

713 

00412 



O 2 

2 

22 

2 
17 
02 
30 
57 




01235 
00732 
01237 
00732 
0004 
00732 
01241 
01702 

02641 
01570 
00727 

1 00412 



21 01236 
22 004 3 
21 01241 
53 01451 











01 007 56 

O 16 017 33 

14 01444 

03 01OS5 



03 01177 
2? 4003 
21 01243 
21 01216 
31 01217 
17 01645 
14 01734 



Toble 4-6. 


9300 ( 


502 


RBV 


503 


EXU 


504 


LC»^ 


50-5 


LDA 


506 


STA 


507 IN4 


EXU 


503 


BRU 


509 


BRU 


510 


EXU 


511 


BRU 


512 


BPT 


513 


BRU 


514 


L D X 


515 


TYP 


516 


MIB 


517 


BRX 


513 


BRU 


519 * 




520 IMA 


EXU 


521 


BRU 


522 


EXU 


523 


BRU 


524 


BPT 


525 


BRU 


526 


EXU 


527 


LDX 


528 


TYP 


529 


MIB 


530 


BRX 


531 


BRU 


532 * 




533 IN2 


EXU 


534 


sov 


535 


EXU 


536 


SKN 


537 


BHU 


53 3 


LDA 


53 9 


LDB 


540 


BRM 


5'41 * 




542 


3RM 


543 


ROV 


5 44" 


EXU 


545 


LCH- 


546 


LDX 


547 


LDB 



9300 Computer, Extended Mode I/O Test Program (Sheet 12 of 20) 



RAIC 




Rir^SP 




SPF 




RCIT 




$♦2 




IN2 




RCAT 




INIA 




4 




IN2 




=-15*« 


0177777 


0«1«4 




ERMSG6 


♦ 1 5 > X 


$-1 




GQTeP 




RC7T 




IN4 




RCIT 




IN2 




4 




IN2 




RDI5 




=-17** 


0177777 


0.1,4 




ERHSG7 


♦ 17, X 


$-1 




G9T0P 





RCFT 

RDIS 

SPF 

IN3 

=033120252 

BUFFER+64 
CHECK 

STARTP 

RAIC 
RIftSPl 

=-3**0177777 

=ERMSG8 



LOAU If^SP BUFFER*65 



S(I9SP INPUT) 

INTERRECeRD CQNDI ildH 

Nd 

YES 

CHAN. ACTIVE 

YES 

N9, ERROR STOP PERMITTED 

N9 

YES 



C = 

NO 

YES, CHAN. INTER-RECORD 

NO 

YES, ERROR STOP PERMITTED 

NO 

YES, STOP TAPE 



o 
o 
o 
o> 

00 

n 



IF CHANNEL ERROR 

SET OVERFLOU 

STOP TAPE 

I9SP INPUT FLAG 

RESEI 

SET, GET BLOCK NO. 2 

Ef^iD ADDRESS EXPECTED 

CHECK DATA INPUT 

IF CORRECT CONTINUE. 

STARI TAPE 

ALERI 

LOAD lOSP BUFFER, 32 

SET UP ERROR MESSAGE 



a> 

3 
cr 

(D 



o^ 



00751 





16 


00647 


t)^0752 — 0"a 1J3 


OO610 


00753 





21 


01236 


00754 





22 


004 3 


00755 





21 


01234 


00756 





01 


007 60 


00757 





21 


01240 


00760 





21 


01243 


00761 





21 


01220 


00762 





31 


01221 


00763 





40 37711 


00764 





76 


01461 


00785 





01 


00732 


0O766 





16 


017D5 


00767 





14 


017D1 


00770 





03 


01055 


00771 





03 


01177 


00772 





21 


01243 


00773 





21 


01222 


00774 





31 


01223 


00775 





21 


01234 


00776 





01 


00775 


00777 


1 


17 01674 


01000 





16 


01636 


01001 





1 54 


01444 


01002 





01 


010 24 


01003 


1 


57 01001 


01004 


1 


17 01674 


01005 





16 


01642 


01006 





1 76 


01444 


01007 


• 


05 


01657 


010 10 


1 


57 01006 


01011 





Q 16 


01736 


01012 





14 


01737 


01013 


8 


22 


4 00 3 


01014 





03 


01055 


01015 


a 


22 4 


004 3 


01016 





01 


00234 


01017 





22 4 


0023 


01020 





01 


00356 


01021 





22 4 


OOID 


01022 





01 


00640 


01023 





01 


00356 


01024 





22 4 


0004 


■^ 01025 





01 


01034 



Table 4-6. 


9300 Co( 


mpufrer. Extended Mo 


548 


LDA 


RCATC 


549 


BRft 


wcz 


550 


EXU 


RCET 


551 


SOV 




552 


EXU 


RCAT 


553 


BRU 


IN5 


554 


EXU 


RPT 


555 IM5 


EXU 


RALC 


556 


LCH 


RIPRP 


55 7 


CLR 




558 


STA 


SPF 


559 


BRO 


IN4 


560 * 






5*1 IN3 


LDA 


=033120352 


562 


LDB 


=BUFFER*64 


563 


BRM 


CHECK 


564 


BRM 


STARTP 


565 


EXU 


RALC 


566 


LCH 


RIGRD 


567 


EXU 


RCAT 


568 


BRU 


$-1 


569 


LDX 


=-8*«0177777 


570 


LDA 


-077 


S71 


SKA 


aUFFER*64,X 


572 


BRU 


IN3A 


573 


BRX 


$-? 


574 I^3B 


LDX 


=-e«*0177777 


575 


LDA 


*070 


576 


ST A 


BUFFER+64*X 


577 


ADD 


= 1 


576 


BRX 


S-2 


579 


LDA 


-033120452 


580 


LD8 


= 3llFFER + 56 


581 


R8V 




582 


BRM 


CHECK 


583 


BPT 


1 


584 


BRU 


KYBD 


585 


BPT 


2 


586 


BRU 


OUT 


587 


BPT 


3 


588 


BRU 


IN 


589 


BRU 


OUT 


590 * 






591 IN3A 


BPT 


4 


592 


BRU 


IN3B 


593 


LDX 


=-8**0177777 



G8 WAIT FOR C«0 

IF CHANNEL ERROR 

SET OVERFLOW 

IS READER STILL RUNNING 

YES 

NO, RESTART TAPE READER 

LOAD lORD BUFFERt'32.33 



RCIOSP INPUT) 



BLOCK NO. 3 
END ADDRESS EXPECTED 
GO CHECK DATA 
START TAPE 

LOAD lORD BUFFER*56 

CHAN. ACTIVE 
YES. WAIT FOR STOP 
CHAN. INACTIVE 

CHECK FOR O'S IN LAST 8 CHARACTERS 



O.K. INSERT CORRECT 8 CHARACTERS 



BLOCK NO. 4 

E;^D ADDRESS EXPECTED 

GO CHECK DATA 

TEST STOP? 

YES 

TEST CYCLE? 

YES 

TEST ONE ONLY. 

READ 

PUNCH 

ERROR STOP PERMITTED 
NO 
FORMAT LAST EIGHT CHARACTERS FOR TYPE 



CO 

0) 

■o 
(? 
3 
o- 

Cb 



en 



en 
O 

•o 
o 
o 
o. 

00 

o 



4^ 

1 






o 






01027 


9 


40 37711 


01030 





1 16 01444 


01031 





60 04 003 


01032 





1 13 01444 


010^3- 


^H> 11 0^1 7H> 


01034 





13 01711 


01035 





60 04 006 


01036 





1 76 01055 


01037 


1 


57 01030 


01040 


1 


17 01712 


01041 





02 02641 


01042 


1 


30 01616 


01043 


1 


57 01042 


01044 





02 14000 


01045 





20 1400O 


01046 





01 01045 


0104 7 





02 02041 


01050 


1 


17 01674 


01051 


I 


30 01D65 


01052 


1 


57 01051 


01053 





30 01503 


01054 





01 00412 



Table 4-6. 
r 



9300 Computer, Extended Mode I/O Test Program (Sheet 14 of 20) 



01055 



01065 








00 


00030 


01066 








76 


016 26 


01067 








21 


01236 


01070 








01 


01141 


01071 





22 1 


404 3 


01072 








01 


01141 


01073 








21 


01242 


01074 








33 


01 444 


01075 








74 


01.445 


01076 








16 


01444 


01077 


e 





12 


01445 


01100 








54 


01670 


01101 








01. 


01154 


01102 


1 


17 01660 


01103 








16 


01675 


0:i 1 04 








14 


01636 


01105 





I 


55 


01444 


01106 








01 


01112 


01107 








05 


01657 


OHIO 


1 


57 01105 



594 
595 
596 
597 

5-9-a 

599 
600 
601 
602 
603 
604 
605 
606 
607 
608 
60 9 
610 
611 
612 
613 
614 
615 
616 
617 
616 
619 
620 
621 
622 
623 
624 
625 
626 
62 7 
628 
629 
630 
631 
632 
633 
634 
635 
636 
637 
638 
639 
640 
641 
642 



IN3D 



M S Q I M G 



CLP 
LDA 

bSh 

«RG 
ETR- 
MRG 
LSH 
ST A 
BRX 
LDX 
TYP 
MIB 
BRX 
T9P 
CAT 
BRU 
TYP 
LDX 
MIB 
BR X 
MIB 
BRU 



RES 
PAGE 



BIJFFER'«'64,X 

3 

8UFFER'»-64#X 

-a7-07 

=052120000 

6 

MSGIMG+8#X 

IN3D 

=-19**0177777 

0.1*4 

ERHSG9+19.X 

$-1 





S-1 

0«1 >1 

=-P**3177777 

MSGinG+3*X 

J-1 

ERMSGl+3 

G9T(?P 



* CHECK INPUT DATA SUBROUTINE. 

* 

CHECK PZE 

STA ERM3G0+6 

EXU RCET 

BRU PAPERR 

9VT 

BRU PARERR 

EXU RASC 

PIN Tl 

STB Tl+1 

LDA Tl 

EOR Tl+l 

SKA =-1 

BRU PINERR 

CHECK2 LDX =-64**0177777 

L D A =00 

LD6 =077 

SKM BUFFER'^64,X 

BRU CHECKl 

ADD =1 

BRX $-3 



OUTPUT ERROR MESSAGE 



OUTPUT 8 CHARACTERS 



CR 



to 

oo 
o 

8 

O^ 
C» 
Ul 

O 



Save block no. 

check for error 

go to parity error routine 

check for previously noted error 

go to parity error routine 

store channel address 

save expected 



COMPARE 
AGREE 
NO 
YES 



ACTUAL WITH EXPECTED 



CHECK 
ERROR 



INPUT BUFFER 



CO 

0) 
T3 

-^ 
fl) 

3 
o- 



NO 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 15 of 20) 



01111 41 01055 



01112 
01113 
01114 
01115 
on 16 
01117 
01120 
01121 
01172 
01123 
01 124 
01125 
01126 
01127 
01130 
01131 
01132 
01133 
01134 
01135 
01136 
01137 
01140 



01141 
01142 
01143 
01144 
01145 
01146 
01147 
01150 
01151 
01152 
01153 



22 4 0004 
41 01055 
76 01444 
6C 04 003 
13 01444 
11 01710 
60 04 005 
13 01713 

76 01631 

1 16 01444 
50 00 003 

1 16 01444 
60 04 003 
11 01710 
60 04 005 
13 01713 
76 01634 
17 01676 

21 01241 

02 02641 
30 01635 
57 01136 

01 00412 



22 4 0004 
41 01055 
21 01241 
02 02641 
01714 
01627 
01 146 
14000 
14000 
01 01151 



17 

30 

57 

02 

20 



01 011D2 



01154 22 4 0004 



I 



01155 








01 


01132 


01156 








16 


01444 


01157 








03 


00537 


01160 








76 


00635 


01161 








74 


006 36 



643 BRR 

644 ♦ 

645 CHECKl BPT 

646 BRR 

647 STA 

648 LSH 
64"^ MRS 

650 ETR 

651 LSH 

652 MRG 

653 STA 

654 LDA 

655 RSH 
65b LDA 

657 LSH 

658 ETR 

659 LSH 

660 MRG 

661 STA 

662 LDX 

663 EXU 

664 TYP 

665 MIB 

666 BRX 

667 SRU 

668 * 
669 

670 * 

671 PARERR BPT 

672 BRR 

673 EXU 

674 TYP 

675 LDX 

676 HIB 

677 BRX 

678 TOP 

679 CAT 

680 BRU 

681 BRU 

682 * 
683 

684 * 

685 PINERR BPT 

686 BRU 

687 LDA 

688 BRM 

689 STA 

690 STB 



CHECK 

4 

CHECK 

Tl 

3 

Tl 

= 0707 

6 

=012000052 

ERHSGO+9 

BUFFE'V464,X 

3 

BUFFER+64,X 

3 

= 0707 

6 

=012000052 

ERMSGO+12 

=-13**0177777 

RDIS 

0*1«4 

ERMSG0+13,X 

$-1 

G8T8P 



PARITY £RR©R SUBR3UTINE 



A 

CHECK 

RDIS 

0«1«4 

=-9**0177777 

ERMSGP+9,X 

$-1 





$-1 

CHECK? 



PIN ADDRESS ERR9R SUBRdUTINE 



4 

CHECK2 

Tl 

MK8CT 

eTPNM2 

eTPNM2+l 



EXIT IF ALL CORRECT 

ERR9K STOP PERMITTED? 
NO, EXIT 

YES 

FORMAT EXPECTED 



SrSRt EXPECTED 
FORMAI RECEIVED 



CO 

CD 
TJ 

3 
o- 



>o 
o^ 
en 



STORE RECEIVED 

DISCONNECT READER CHANNEL 



CO 

o 
o 
o 
o 

00 

Cn 

n 



ERROR STOP PERMITTED? 

NO 

YES, DISCONNECT RtADER CHANNEL 



OUTPUT PARITY ERROR MESSAGE 



RETURN TO CHECK NUMBERS 



ERROR STOP PERMITTED 

NO 

YES 

EXPAND ACTUAL TO dCD 

SAVE 



en 
ro 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 16 of 20) 



0U6? 





16 01445 


011-63 





03 00537 


01164 





76 00577 


01165 





74 00630 


0-1-166- 





21 -0-124 1 


01167 





02 02641 


01170 


1 


17 01672 


01171 


1 


30 00574 


01172 


1 


57 01171 


01173 


9 


30 01624 


01174 


P 


30 01625 


01175 





30 01626 


01176 





01 00533 



01177 





00 00030 


01200 


1 


17 01660 


01201 





40 37711 


01202 





1 76 01444 


01203 


1 


57 01202 


01204 





21 01240 


01205 





41 01177 



R 01206 002 146 30 

01207 0100 01244 

R 01210 002 142 30 

01211 0100 01244 

R 01212 002 142 30 

01213 0100 01344 

R 01.214 002 146 30 

01215 €101 01344 

R 01216 002 146 3C 

01217 0040 01344 

R 01220 002 144 30 

01221 0041 01404 

R 01222 002 140; 3C 

01223 0070 01344 



01224 20 14000 

01225 20 12000 



691 






LDA 


Tl + 1 


692 






BRIi 


MKeCT 


693 






ST A 


9TPNM1 


694 






STB 


9TPNM1+1 


■6-9-:> 






E-X-i> 


■R0I S 


696 






TYP 


0*1.4 


697 






LDX 


=-15**0177777 


698 






MIB 


eTPN!^ + 15*X 


&99 






BRX 


$-1 


700 






MIB 


ERMSGO-t-4 


701 






MIB 


ERMSGO+5 


702 






MIB 


ERMSGO+6 


703 






BRU 


eTPIN2 


704 


* 








705 


* 


START TAPE 


READER SUBROUTINE 


706 


* 








707 


STARTP 


PZE 




703 






LDX 


=-64**0177777 


709 






CLR 




710 






STA 


BUFFER+54.X 


711 






BRX 


$-1 


712 






EXU 


RPT 


713 






BRR 


STARTP 


714 






PAGt 




715 


* 








716 


* 


I/O 


CHAl^iNtL 


COMMANDS 


717 


• 








718 


PI9SP 


IQSP 


IMAGE. 64 


719 


PI9SD 


I9SD 


IMAGE. 64 


720 


* 








721 


RI9SD 


I9SD 


BUFFER. 64 


722 


RI9SP 


I9SP 


BUFFER. 65 


723 


RIdSPl 


I9SP 


BUFFER. 32 


724 


RI9RP 


I9RP 


BUFFER+32.33 


725 


RIORD 


I9RD 


BUFFER. 56 



FX'^AND EXPECTED TcJ BCD 

SAVE 

DISCONNECJ READER 

OUTPUT GENERAL MESSAGE 
OUTPUT BLOCK NO. 

GO OUTPUT RECEIVEu AMD EXPECTED 



CLEAR BUFFER 

START TAPE 
EXIT 



CO 



8 

o^ 

00 

n 



726 * 

727 * 

723 * I/O CHANNEI INSTRUCTIONS. 

729 * 

730 PCAT CAT 

731 PCZT CZT 



-o 

n 

3 

n> 



o^ 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 17 of 20) 



01226 





20 


11000 


01227 





02 


02044 


01?30 





02 


00044 


01231 





02 


00000 


01232 





32 


12000 


01233 





0? 


5000C 


01234 





20 


14000 


01235 





20 


120.00 


01236 





20 


1 1000 


01237 





20 


104 30 


01240 





02 


02004 


01241 





02 


00000 


01242 





02 


12000 


01243 





02 


50000 



01244 
01344 



014 4 4 
01461 
01462 



I 

CO 



01463 


52233021 


01464 


45452543 


01465 


12255151 


01466 


4 5514664 


01467 


62437012 


01470 


24316223 


014 71 


46454525 


01472 


23632524 


01473 


12222526 


01474 


46512512 


01475 


23130073 


01476 


12246451 


01477 


31452712 



732 
733 
734 
735 
736 
7 37 
738 
73^ 
7 40 
7^1 
74> 
74 3 
74^ 
745 
746 
747 
748 
749 
750 
751 
752 
753 
754 
755 
756 
f57 
758 
759 
760 
761 
762 
763 
764 
765 
766 
767 



PCET 



PP 
PT 

PD 

PA 
PA 



RC 

RC 

PC 

* 

f^P 

RD 

RA 

RA 



BU 



Tl 

SP 
PR 

* 
* 
* 
DI 



T 

L 

IS 
5C 
LC 



AT 
ZT 
ET 
IT 

T 
IS 

sc 

LC 



GET 

PPT 
PTL 

DSC 
ASC 
ALC 



CAT 

CZT 
CET 
CIT 

RPT 
DSC 
ASC 
ALC 





0*1 
0*1 









1* 1 



9UTPUT IMAGE AREA, INPUT BUFFcR A^EA 



AGE 
FFER 



RES 
RES 



64 
64 



TEMPORARY STORAGE AND FLAGS 



RES 
F RES 
F RES 

PAGt 



13 

1 

1 



I6SP INPUT FLAG 
PUNCH REPEAT FLAG 



CO 
0) 
■D 

n 

3 
cr 

fD 



o 

en 



Lr> 

O 
O 
O 
O^ 
00 
Oi 

n 



ERROR AND STATUS MESSAGES. 
SHSG BCD 52#1CHANNEL ERRORdUSLY DISCONNECTED BEFORE C«0* DURING 



1 




■!:>> 




01500 


31466247 


01501 


73124664 


01502 


63476463 


01503 


33125252 


01 504 


J1466224 


01505 


73124664 


01506 


S3476463 


01507 


33125252 


01510 


52233021 


OiSll 


45452543 


01512 


12243124 


01513 


12454663 


01514 


12243162 


01515 


23464545 


01516 


25236312 


01517 


66302545 


01520 


12231300 


01521 


12464512 


01522 


31466224 


01523 


12314547 


01524 


64635212 


01525 


31466224 


01526 


73123145 


01527 


47646352 


01530 


52233021 


01531 


45452543 


01532 


12243162 


01533 


23464545 


01534 


25236325 


01535 


34122464 


01536 


51314527 


01537 


12314662 


01540 


47123145 


01541 


47646373 


01542 


12233163 


01543 


12452565 


01544 


25511212 


01545 


63516425 


01546 


33125212 


01547 


52246451 


01550 


31452712 


01551 


31466247 


01552 


12314547 


01553 


64631223 


01554 


13001231 


01555 


45243123 


01556 


21633145 


01557 


27122546 


01560 


51124721 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 18 of 20) 

768 ERMSCl BCD 16«I9SP* 9UTPUT. U 

769 ERHStt2 BCD 16»I8SD* SUTFUT. 11 

770 ERNSG4 BCD 52*1CHANNEL DID N9T DISCONNECT UHEN C-0 9N lOSO INPUTI 



771 ERMSbS BCD 



12*I9SD, INPUTI 



772 ERf1SG6 BCD 52#1CMANNEL DI SC0i^NECTED DURING lOSP INPUT, CiT NEVER 



773 BCD 8-TRUE. I 

774 ERHSG7 BCD 48,iDURING I(?SP INPUT C = INDICATING £5R PAST BUT C 



CO 

<•> 
>o 

8 

00 

en 

n 



n> 
-a 

-♦ 
n> 
3 

O" 
(D 



>o 

On 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 19 of 20) 



01561 

01562- 

01563 

01564 

01565 

01566 

01567 

01570 

01571 

0157? 

01573 

01574 

01575 

01576 

01577 

_01601 
01602 
01603 
01604 
01605 
01606 
01607 
01610 
01611 
01612 
01613 
01614 
01615 
01616 
01617 
01620 
01621 
01622 
01623 
01624 
01625 
01626 
01627 
01630 
01631 
01632 
01633 
01634 



6P631222 
64631223 
31631266 
21621245 
25652551 
12635164 
25331252 
31466247 
73123145 
47646352 
52314651 
24124645 
12314547 
64631224 
31241245 
46631231 
27454651 
25126330 
25124321 
62631210 
12233021 
51212363 
15516273 
12226463 
12512521 
24126330 
a5l22646 
43434666 
31452792 
52524721 
51316370 
52314547 
64631225 
$1514651 
12314512 
22434623 
42124546 
33124552 
256747^5 
23632524 
12242452 
51252325 
31652524 
12242452 



01635 30 00000 



775 



BCD 20#IT WAS NEVER THUE. 1 



00 

-*- 

3 






776 ERISAS BCD l2#nSP, INPUTI 



777 ERHSiiQ BCD 52,1I3RD 8N INPUT LID NOT IGNORE THE LAST P CHARACTERS, 



778 



BCD 



24« BUT READ THE FOLLOWING! 



CO 



8 

o^ 

00 

n 



77^ ERflSCP BCD 
760 ERHS60 BCD 



8#I|PARITY 

40*1INPUT ERROR IN BLOCK NO. NIEXPECTEO DDl 



On 



781 



762 • 

763 HI§X 

764 * 
7fi5 • 



BCD 



MIB 



12*RECEIVE0 DOl 



OUTPUT INSTRUCTION 



^ 






00000200 


01636 


00000077 


01637 


00606047 


01640 


00606051 


01-641- 


00606062 


01642 


00000070 


0164 3 


00177774 


01644 


fO 27 7 67 7 


01645 


00177775 


01646 


^7727677 


1647 


S02777 77 


01650 


77777776 


01651 


00002000 


01652 


00177766 


01653 


702777 77 


01654 


00000004 


01655 


00000003 


0t6&6 


00O40OO0 


01697 


90000001 


01660 


00177700 


01661 


OlOOOOOO 


01662 


00001500 


01 663 


52121225 


01664 


11514651 


01665 


12246451 


01666 


31452712 


01667 


00001504 


01670 


77777777 


01671 


0000134 4 


01672 


OOl 77761 


01673 


0017 7764 


01674 


00.177770 


01675 


oooooooo 


01676 


00177763 


01677 


00001525 


01700 


33120152 


01701 


00001444 


01702 


00177757 


01703 


3312025?. 


01704 


000015 70 


01705 


33120352 


01706 


33120452 


01707 


00001434 


01710 


00000707 


01711 


S2120000 


01712 


00177755 


01713 


12000052 


01714 


00177767 



Table 4-6. 9300 Computer, Extended Mode I/O Test Program (Sheet 20 of 20) 
766 END BEGIN 



CO 

oo 
o 

8 

o^ 

00 

en 

n 



cr 



>o 
o 
Cn 



September 1965 



SDS 900685C 



Paragraphs 5. 1 to 5. 12 



SECTION V 
TROUBLESHOOTING 



5.1 GENERAL 

5.2 This section contains information useful when 
troubleshooting the Model 932XX series TMCCs. 

5.3 Troubleshooting information contained herein is 
based on the test programs given in Section 4 of this 
manual. When an error is indicated during performance 
of the tests given in Section A, reference should first be 
made to the Programming Flow Charts illustrated in 
figure 5-1 and then to the applicable referenced data. 

5. 4 TEST PROGRAM FLOW CHART 



5.5 Figure 5-1 illustrates the programming flow data 
for the extended mode test programs given in Section 4. 
An example of the usage of the flow charts is given in 
the following paragraphs. 

5. 6 FLOW CHART EXAMPLE 

5.7 In presenting the example of usage of the flow 
charts, the following points will be assumed: 

a. Paper tape reader connected to one of the 
interlaced channels. 

b. Breakpoint 1 switch reset. 

c. Breakpoint 2 switch reset. 

d. Breakpoint 3 switch set. 

e. Breakpoint 4 switch reset. 

f. An error exists in block 4. 

5.8 At the initialization of the test, the channel num- 
ber has been inserted on the typewriter, the unit number 
being used, and the character "R" for the paper tape 
reader. The program begins at the top of sheet 1 of 
figure 5-1. The program initializes restart location, 
disconnects all channels, addresses the keyboard and 
reads the character typed. As the character typed is an 
"R", the flow proceeds to the right from CHAR: R to = R 
and is picked up again on sheet 2. The program then 
builds channel and unit mask words, and builds: RPT, 
RCAT, RCET, RCZT, RCIT, RALC, and RDIS (Read 
Paper Tape, Channel Active Test, Channel Error Test, 
Channel Zero Count Test, Channel Inter-Record Test, 
Alert Channel, and Disconnect Channel, respectively). 
The EOM/EOD commands are then constructed and the 
keyboard addressed to determine if the letter "S" has 



been inserted to start the test. The program returns to 
sheet 1, KYBD, where the keyboard is addressed, the 
character "S" is read and Breakpoint Switch 3 is inter- 
rogated. As Breakpoint Switch 3 is set (paragraph 5. 7d) 
the line S is followed to IN. 

5.9 The program proceeds to sheet 8 (circle labeled 
IN), the tape Is started, lOSD 64 is loaded (block 1), 
a check is made to determine if the count reaches zero 
and the channel is inactive. As the count has reached 
zero and the channel is not active, the program then 
proceeds to check the data as given on sheet 12. The 
subroutine is then performed to check End Address, 
Parity, and Input Data. The block number is then saved, 
no error exists, the channel address Is stored and checked 
against the expected and the input data is compared. 
As the input data does compare, the program exits from 
the subroutine and is picked back up again on sheet 8 
and proceeds to IN 1. 

5. 10 IN 1 continues on sheet 9, the tape is started 
again and lOSP 65 Is loaded (block 2). The program 
checks that the word count does not reach zero and the 
Inter-record test occurs (CIT). It then proceeds from 
CIT? to IN 2. 

5. 1 1 The program then checks to determine if an error 
exists (sheet 10) and stops the tape before the data is 
checked. While the tape Is stopped, the data check 
subroutine is performed (sheet 12). After comparison of 
the data, block no. 2 Is entered and the program exists 
from the subroutine and proceeds (sheet 10) to start the 
tape (sheet 13) and then loads lOSP 32 (block 3). 

5. 12 Subsequent to loading lOSP, the subroutine Wait 
For Count Zero (sheet 6) is again performed. When the 
count equals zero, the program exits from the subroutine 
and returns to the main program (sheet 10). As no error 
existed and the channel Is not active, the tape is started 
again (sheet 13) and lORP 33 is loaded, SPF is reset, 
and the Inter-record indicator (CIT, sheet 9) is turned 
on at the end of the record. The count should not reach 
zero and the channel should remain active. As no error 
exists (sheet 10), the tape is stopped and SPF is inter- 
rogated. SPF has been reset and the program then con- 
tinues to IN 3 (sheet 11). The data is then checked 
(sheet 12) and as it does compare, the program exits 
from the subroutine, block no. 3 is entered, and the tape 
Is started again (sheet 11). The program then loads lORD 
56 (block 4), waits for the channel to be inactive and 
checks to determine If the channel ignored the last eight 
characters. As the last eight words were not ignored 
(paragraph 5.7f), an error exists and the program 



5-1 



SDS 900685C 



September 1965 




Initialize Re- 
start Location 



Disconnect 
All Channels 




Address 
Keyboard 



I 



READ 
CHAR 



( CHAR : P y 



f CHAR : R \ 





R 



( CHAR : S J ^ 'f BP3 j »^ OUT j 



I 



SAVE CHAR 




Figure 5-1. Test Program Flow Chart (Sheet 1 oJF 13) 



5-2 



September 1965 



SDS 900685,C 





Build Channel 

and Unit 
Mask Words 



Build Channel 

and Unit 

Words 



Build: RPT, 
RCAT, RCET, 
RCZT, RCIT, 
RALC, RDIS 



Build: PPT. 
PTL, PCAT, 
PCET, PALC, 
PCZT. PDIS 



Fix All 
Channel Comm. 
For EOM/EOD 




Fix All 
Channel Comm. 
For EOM/EOD 




Figure 5-1. Test Program Flow Chart (Sheet 2 of 13) 



5-3 



SDS 900685.C 



Sepfember 1965 



fo\j'r\ 




Generate 64 

Words of 
Image 



Start Punch 
With Leader 



Start Punch 



Load: 
lOSP 64 



fiub. WCZ > 

(wait for C=0 
\lOSP, Output); 



z' \yes /^ 

( ERROR J ^ f 



I 



NO 



rSubr. Outpin 
Check End 
VAddress 



NO 




Channel Act 



y 



YES 



Load: 
lOSD 64 




BP4 



.R 





Disconnect 
Channel 



Type: ERROR 
DURING- - 




Figure 5-1. Test Program Flow Chart (Sheet 3 of 13) 



5-4 



September 1965 



SDS 900685C 



/ OUT \ 



^ubr. WCZ 
(Wait for C=0 
yiOSD, Output) 




Figure 3-1. i -st Piogram Flow Chart (Sheet 4 of 13) 



5-5 



SDS 900685C 



September 1965 




Punch With 
Leader 



Load: 
lOSD 16 



Subr. WCZ 
Wait for C=0 
UIOSD, Output 




Figure 5-1. Test Program Flow Chart (Sheet 5 of 13) 



5-6 



September 1965 



SDS 900685C 





YES 



(exit V-*- 



f wcz^ 



* NO 
(Channel Active \l£^ 



NO 



(ZEiI) 



Type: Channel 
Errorously Dis- 
connected 

Before C=0 
During- 




Wait For 
Count Zero 
Subroutine 



Figure 5-1. Test Program Flow Chart (Sheet 6 of 13) 



5-7 



SDS 900685C 



September 1965 




Subroutine to 

Check End 

Address From 

Channel 



YES 




Format and 

Store Expected 

and Received 

Addresses 



Type Message 

With Expected 

and Received 

Addresses 




Figure 5-1 . Test Program Flow Chart (Sheet 7 of 13) 



5-8 



September 19*65 



SDS 900685C 



( 



Subr. WCZ 
(lOSD, Input) 




^2£2ri^7\S. 



Type: Chamu-I d i (i* 
not Disconiunt | 
When C=0 on 
lOSD Input 



Enter With 
Block No. 1 




Figure 5-1. Test Program Flow Chart (Sheet 8 of 13) 



5-9 



SDS 900685C 



September 1965 




Load: 
lOSP 65 




YES 



S(SPF) 



Set lOSP 
Input Flag 




CIT? 



y^~p) 



NO 






Stop Tape 



I 



Type: lOSP 
Input: C = 
but no CIT 




Channel 



Active j 



NO 



BP4 



> 




Type: Channel 
Disconnected , 
During lOSP In- 
put, but no CIT 




IN 2 



Figure 5-1. Test Program Flow Chart (Sheet 9 of 13) 



5-10 



September 1965 



SDS 900685C 




R 




YES 



S(OVF) 



NO 



Stop Tape 



I 



f SPF ) 

— F~^ 



Check Data ) 



I 



Enter With 
Block No. 2 



Start Tape 

znz. 



Load: 
lOSP 32 



I 



Subr. WCZ 

lOSP, Input 





Lioad: 
lORP 3 3 



R(SPF) 




Figure 5-1. Test Program Flow Chart (Sheet 10 of 13) 



5-11 



SDS 900685.C 



September 1965 



Type: lORD on 
Input did not 
Ignore Last Z 
Words 




Enter With 
Block No. 3 



Clears Image 




R r r>«^ ^ NO /"Last 8 words \ 
.^IJ BP4 Y^A of Image = ) 

pES 



Insert Correct 
Last 8 Words 




( BP3 )-*-( BP2 jr*-\ BPl )-•— { 



Check Data 




)-- 



Enter With 
Block No. 4 



Figure 5-1. Test" Program Flow Chart (Sheet 11 of 13) 



5-12 



September 1965 



SDS 900685C 




Save Block No, 



Subroutine to 
Check End 
"~ ""jAddress , Parity, 
and Input Data 



ERROR 



NO 



OVF 




Store 
Channel 
Address 



BP4 



R 




Type 'Parity' 



Equal to 
Expected? 



YES 



Compare 
Input Data 




Non-compare 



YES 



BP4 



NO 




BP4 



R 





R 




Type Error 

Message With 

Received and 

Expected Char. 



I' orrnat Rt-ieived 
and Expected 



Type Message 

With Received 

and Expected 




Figure 5-1. Test Program Flow Chart (Sheet 12 of 13) 



5-13 



5DS 900685C 



September 1965 




Subroutine to 

Clear Buffer an< 

Start Tape 

Reader 



Clear Input 
Buffer 



Start Reader 

1 Character 

Per Word 




Figure 5-1. Test Program Flow Chert (Sheet 13 of 13) 



5-14 



September 1965 



SDS 900685C 



Paragraphs 5. 13 to 5. 21 



interrogates Breakpoint Switch 4. Breakpoint Switch 4 
is reset (paragraph 5. 7e), therefore, the program types 
out: lORD on Input did not ignore last two words. 
Reference should then be made to table 5-8 for informa- 
tion concerning lORD on Input, 

5.13 TROUBLESHOOTING INFORMATION 

5. 14 The error printout during the test program is deter- 
mined by the type of device used with the program. If 
the device is an output device, the following type of 
error codes may be printed out: 

a. Typewriter — Error during lOSD output 

b. Paper Tape — Error during lORD/lOSD output 

c. Cards — Error during lOSD/IORD output 

d. Printer ~ Error during lOSD/lORD output 

e. Magnetic Tape — Error during lORD/lORP 
output. 

5. 15 If the device is an input device, the following types 
types of error codes may be printed out: 

a. Typewriter — Error during lOSD input 

b. Paper Tape — Error during lORD/lOSD/lORP 
input 

c. Cards — Error during lORD/lOSD input 

d. Magnetic Tape — Error during lORD/lORP 
input. 



5.16 TROUBLESHOOTING 

5. 17 If a failure occurs during performance of the test 
program and an error message is printed out, determina- 
tion must be made whether the malfunction is in the 
central processor unit (CPU), in the input/output device, 
or in the TMCC. Normally, this con be determined by 
performing a portion of the applicable test routine for 
the input/output device and checking for proper opera- 
tion. 

5. 18 If the determination is made that the malfunction 
is in the TMCC, reference should then be made to the 
applicable table (tables 5-1 thru 5-10) for that function. 
The table describes the function and references the 
paragraphs in the Theory of Operation section (Section 
3) where a detailed description of that function is 
described. 

5. 19 The logic equations pertaining to the particular 
function can be determined from the description in the 
theory of operations. A comparison of the logic equa- 
tions and terms will indicate the particular terms peculiar 
to the function which has failed. Reference to the logic 
layout drawings (listed in Section 1) will indicate the 
module in which the tenn is used, the physical location 
of the module, and the terminal connections where the 
term can then be found. 



5.20 Normal troubleshooting procedures can be per- 
formed to pinpoint the malfunction to a particular com- 
ponent or terminal. 



5. 21 Physical location of components and schematics of 
each module can be found in Section 6. 



Table 5-1. lOSP Output Function, W (A) Channel 



Iwg 


Iwh 


Iwl 


Output Function 


Sec. 3, Par. Ref. 


1 


1 


1 


1. Ilwat Iwf if Iwk 

When the channel counts C down to zero (Iwf), the channel generates 
a zero word count interrupt (Ilw), if armed (Iwk), indicating the pro- 
gram should reload the interlace portion of the channel to continue 
writing in the same record. Failure to reload the interlace before the 
buffer transmits all of the characters in its registers and before the 
peripheral device requests the next character from the buffer sets the 
channel error indicator. 


3.152 

thru 

3.157 



5-15 



SDS 900685C 



September 1965 



table 5-2. lORP Output Function/ W (A) Channel 



Iwg 


Iwh 


Iwl 


Output Function 


Sec. 3, Par. Ref. 


1 


1 





1. Ilwatlwflflwk 

2. At Iwf, reset WO 

3. I2w at Mtgw or Whs Wl 1 if Iwj 

4. AtWhsWll, disconnect 

When the channel interlace counts C down to zero (Iwf), the channel 
generates a zero word count interrupt (11 w), if armed (Iwk), notify- 
ing the channel buffer that it has received the last word that is to be 
output. At zero word count (Iwf), the Halt Interlock flip-flop, WO, 
is reset to inhibit additional time-share requests. When the device 
receives the last word from the buffer, it sends an End-of-Record 
response (Whs Wl 1) back to the buffer. If armed, (Iwj), the buffer 
generates an End-of-Record Interrupt (I2w) and sets the inter-record 
indicator. If the device is magnetic tape, an End-of-Record response 
(tape gap signal, Mtgw,) signal is sent to the buffer but the tape 
continues to move. If the program does not execute an EOM to write 
a new tape before the tape gap signal drops, the channel disconnects 
(Whs Wl 1) and the tape stops. 


3.144 

thru 

3.151 



Table 5-3. lOSD Output Function, W (A) Channel 



Iwg 


Iwh 


Iwi 


Output Function 


Sec. 3, Par. Ref. 


1 





1 


1. Ilwat Iwf if Iwk 

2. At Iwf, reset WO 

3. Disconnect at Iwf Wl 1 or Whs 

4. I2w at disconnect, if Iwj 

When the channel interlace counts C down to zero (Iwf), the channel 
generates a zero word count interrupt (Ilw), if armed (Iwk), indicat- 
ing the last character has been transmitted. At zero word count (Iwf), 
the Halt Interlock flip-flop (WO) is reset inhibiting additional time- 
share requests. For devices other than magnetic tape (Wl 1), the Halt 
Detector flip-flop (Wh) is set on reaching zero word count (Iwf) when 
the last character has been clocked from the buffer. The Halt Detector 
also sets on occurrence of a Holt Signal (Whs). Setting of the Halt 
Detector initiates a buffer disconnect sequence. The Sighal Complete 
flip-flop (Wcs) is set and if the End-of-Record Interrupt Enable (Iwj) 
has been previously armed, an End-of-Record Interrupt (I2w) is 
generated. 


3.140 

thru 

3.143 



5^16 



September 1965 



SDS 900685,C 



Table 5-4. lORD Output Function, W (A) Channel 



Iwg 


Iwh 


Iwl 


Output Function 


Sec. 3, Par. Ref. 


1 








1. Ilwat Iwf if Iwk 

2. At Iwf, reset WO 

3. Disconnect at Whs 

4. I2w at disconnect, if Iwj 

When the channel counts C down to zero (Iwf), the channel generates 
a zero word count interrupt (11 w), if armed (Iwk), indicating that the 
last characters have been transmitted. At zero word count (Iwf), the 
Halt Interlock flip-flop (WO) is reset inhibiting additional time-share 
requests. If Holt Signal (Whs) is received, the Halt Detector (Wh) is 
set and a disconnect occurs. The Signal Complete flip-flop (Wsc) is 
set and, if armed (Iwj), an End-of-Record Interrupt (I2w) is generated. 


3.134 

thru 

3.139 



Table 5-5. lOSP Input Function, W (A) Channel 



Iwg 


Iwh 


Iwi 


Input Function 


Sec. 3, Par. Ref. 


1 


1 


1 


1. Ilwat Iwf If Iwk 

2. At Mtgw or Whs Wl 1, flush and store last character(s) if Iwf 

3. I2w at Mtgw or Whs W 1 1 if Iwj 

4. Disconnect at Whs Wll 

When the channel counts C down to zero (Iwf), the channel generates 
a zero word count interrupt (11 w), if armed (Iwk), indicating the pro- 
gram should reload the Interlace portion of the channel to continue 
reading the record. If the End-of-Record (Mtg or Whs Wl 1) occurs 
before zero word count (Iwf), the buffer is flushed and the completed 
word is stored in memory. If the End-of-Record Interrupt Enable (Iwj) 
has been armed, an End-of-Record interrupt (I2w) is generated when 
a tape gap (Mtgw) or halt signal (Whs) is detected from the device. 
For magnetic tape operation (Wll), a new EOM may be given within 
one millisecond from the occurrence of I2w to permit the tape system 
to proceed to a new record. Failure to give an EOM results in the 
tape stopping and the buffer disconnecting. 


3.176 

thru 

3.179 



5-17 



SDS 900685C 



September 1965 



Table 5-6. lORP Input Function, W (A) Channel 



Iwg 


Iwh 


Iwi 


Input Function 


Sec. 3, Par. Ref. 


1 


1 





1. Ilw at Iwf if Iwk 

2. Inhibit rate errors if Iwf 

3. At Mtgw or Whs Wl 1, flush and store last character(s) if Iwf 

4. I2w at Mtgw or Whs Wl 1 if Iwj 

5. Disconnect at Whs Wll 

When the channel counts C down to zero (Iwf), the channel generates 
a zero word count interrupt (Ilw), if armed (Iwk), indicating the pro- 
gram should reload the interlace portion of the channel to continue 
reading the record. Additional characters entering the channel after 
zero word count are precessed into the W register. Parity and rate 
errors cannot occur after zero word count because of Iwf. Detection 
of magnetic tape gap (Mtgw) or a holt signal (Whs) sets the End-of- 
Record detector. If the End-of-Record detector is set before zero 
word count has occurred (Iwf), the buffer is flushed and the completed 
word is stored in memory. If the End-of-Record Interrupt Enable (Iwj) 
has been armed, an End-of-Record interrupt (I2w) occurs. Failure to 
reload the interlace within one millisecond of I2w results in the tape 
stopping and the buffer disconnecting. 


3.168 

thru 

3.175 



Table 5-1. lOSD Input Function, W (A) Channel 



Iwg 


Iwh 


Iwi 


Input Function 


Sec. 3, Par. Ref. 


1 





1 


1. Ilw at Iwf If Iwk 

2. At Whs, flush and store last character(s) if Iwf 

3. Disconnect at Iwf Wl 1 or Whs 

4. I2w at disconnect if Iwj 

When the channel counts C down to zero (Iwf), the channel generates 
a zero word count interrupt (Ilw), if armed (Iwk). Should an End-of- 
Record (Whs) occur before zero word count (Iwf) is established, any 
characters remaining in the W register are flushed and stored. The 
Halt Detector Is now permitted to set by Iwf Wl 1 or Whs Wl 1 and the 
channel is disconnected. If the End-of-Record Interrupt Enable (Iwj) 
has been armed, an End-of-Record interrupt (I2w) occurs. 


3. 164 

thru 

3.167 



5-18 



September 1965 



SDS 900685C 



Table 5-8. lORD Input Function, W (A) Channel 



Iwg 


Iwh 


Iwi 


Input Function 


Sec. 3, Par. Ref. 


1 








1. Ilwot Iwf if Iwk 

2. Inhibit rate errors if Iwf 

3. At Mtgw or Whs Wl 1, flush and store last character(s) If Iwf 

4. Disconnect at Whs 

5. I2w at disconnect if Iwj 

When the channel counts C down to zero (Iwf), the channel generates 
a zero word count interrupt (Ilw), if armed (Iwk). Parity and rate 
errors (We) are inhibited by Iwf after zero word count is established. 
Should an End-of-Record (Mtgw or Whs Wl 1) occurbeforezeroword count 
is established (Iwf), the End-of-Record detector Is set and any charac- 
ters remaining in the W register are flushed and stored. The Halt 
Detector (Wh) is permitted to set by Whs, the buffer is cleared and the 
channel disconnected. If the End-of-Record Interrupt Enable (Iwj) has 
been armed, an End-of-Record Interrupt (2w) occurs. 


3.158 

thru 

3. 163 



Table 5-9. Output Functions, Y Channel 



lyg 


lyh 


lyi 


Output Function 


Sec. 3, Par. Ref. 


1 


1 


1 


lOSP 

1. Ilyatlyf if lyk 


3.152 

thru 

3. 157 


1 


1 





lORP 

1. Ilyatlyf if lyk 

2. At lyf, reset YO 

3. I2y at Mtgyor Yhs Yll if lyj 

4. At Yhs Yll, disconnect 


3.144 

thru 

3.151 


1 





1 


lOSD 

1. Ilyatlyf if lyk 

2. At lyf, reset YO 

3. Disconnect at lyf Yl 1 or Yhs 

4. I2y at disconnect, if lyj 


3.140 

thru 
3.143 


1 








lORD 

1. Ilyatlyf if lyk 

2. At lyf, reset YO 

3. Disconnect at Yhs 

4. I2y at disconnect, if lyj 


3.134 

thru 

3. 139 


The output functions for the Y channel are identical to those of the W 
channel given in tables 5-1, 5-2, 5-3, and 5-4. The only difference 
is the substitution of the letter "y" for "w" in the logic terms. 



5-19 



SDS 900685C 



September 1965 



Table 5-10. Input Functions, Y Channel 



lyg 


lyh 


lyi 


Input Functions 


Sec. 3, Par. Ref. 


1 


1 


1 


lOSP 

1. Ilyatlyf if lyk 

2. At Mtgy or Yhs Yl 1, flush and store last character(s) if lyf 

3. I2y at Mtgy or Yhs Yl 1 if lyj 

4. Disconnect at Yhs Yll 


3.176 

thru 

3.179 


1 


1 





lORP 

1. Ilyatlyf if lyk 

2. Inhibit rate errors if lyf 

3. At Mtgy or Yhs Yl 1, flush and store last character(s) if lyf 

4. I2y at Mtgy or Yhs Yl 1 if lyj 

5. Disconnect at Yhs Yl 1 


3. 168 

thru 

3.175 


1 





1 


lOSD 

1. Ilyatlyf if lyk 

2. At Yhs, flush and store last character(s) if lyf 

3. Disconnect at lyf Yl 1 or Yhs 

4. I2y at disconnect if lyj 


3.164 

thru 

3.167 


1 








lORD 

1. Ilyatlyf if lyk 

2. Inhibit rate errors if lyf 

3. At Mtgy or Yhs Yll, flush and store last character(s) if lyf 

4. Disconnect at Yhs 

5. I2y at disconnect if lyj 


3.158 

thru 

3.163 


The input functions for the Y channel are identical to those of the W 
channel given in tables 5-5, 5-6, 5-7, and 5-8. The only difference 
is the substitution of the letter "y" for "w" in the logic terms. 



5-20 



September T965 SDS 900685C Paragraphs 6. 1 to 6.6 

SECTION VI 
DRAWINGS 

6. 1 GENERAL 6.5 The type and quantity of each module are listed in 

Section 1, table 1-4. Physical location of each module 

, T TL> i.' 1. • J • r I I . I I is illustrated in Section 4, figure 4-4. 

b.2. This section contains drawings useful when trouble- 
shooting and maintaining the TMCC. , , ai • i i ■ . u . .. . .i <- . i . 

6.6 Also included in this section is the Semiconductor 

Cross Reference which provides a cross-reference between 

6.3 SCOPE OF SECTION Scientific Data Systems semiconductor numbers, commer- 
"""" cial Electronic Industries Association (EIA) numbers, 

6.4 Included in this section are ossembly drawings, specification numbers, and replacements for obsolete 
schematic diagrams, and material lists for each module. semiconductors. 



6-1 






110365 5 lAl 



POLARIZING pins: 18 I 22 



+ I6V 470- 
-I6V 460- 



+ 4V 450- 



+_|_CI J_C2 

T T 

)UND 440 ' I 1 



' O 



I90 



?oO- 




6 ?R7 >R» 



■Rl >R2 >R3 >R4 >RS >R 



66666666c 

41 40 39 26 22 16 17 15 5 




RI4 CRI CR2 

■H- 



CH3 




'•'ill 

ro ro 2 ^ 3 

. . I''' I* i i ;i 



I _ 

T 
- I 



JO 2 

f3 lo 

I 



, , , I I I III 

1 11 3 2 ? ? 2 3 

2 2 2 ro 

T T T |-^ 
til o> ->4 

III 



" r I 

CR3-8^ 



2 
ro 
I 

,09 .«0 



3 I I 

rp 2 3 
|0 I T 



& 



Q2-I i" 



',1. 



L I 



_CR2-2_Q 
RI4-2 



Q_CRI-5_ 
RI4-5 



CR2-8_ 



_CRh8_Q 
_RI4-8 _ 



2 _ 

_ ro M I 

= = T J. — a 

- 5 w l" -^ 

III ,= 

^3-12^ ' 

0-CR2-IL 
qJCRI-IL 

R 14-1 1 



>V^ _Ri4-2_ _Ri4-5_ S _RW-8 _ _Ri4-n_ 

1 - ~ ^---^_CR2-3>-^ \XCR2-6. ^^^ _CR3-9>r _CR2-9 V^ >r:tR2-l2. ^-^ 
(ijA I _CRI-3^ "^0^1-6. _CRI-9_o ^o^H2_ g 

_CR3-3_Q _RI4-3_ _RI4-^ rvCR3-6_ _RI4-9l_ _RI4-I^ ± 



O 



" csioaiD 






_J2-£0 

-CR1-4-0 
_PI4-4_ 



O^^ - 
OCRI-7 - 
Rl4-7_ 



'-0 

Q_CR3-6 _RI4-9l_ 

■ O-OO-O 

^^2H 0O ^-6^R2-I3>-^ 

CR3-IQO -CRI-IO-O 
CR3-7_ _RI4-I0_ 



OJCRI-l3_ 
QJCR3-I3L. 



'HD. 



. RIO-3 

O — '*' — _Rio-2_ 



R2 



,RI0-4_ 
RIO-3. 
RIO-2. 
R3 



_RI0-7 _ 
_RlO-6_ 
_RI0-5_ 



— R4 



R6 _ 
R7 _ 



RIOHq_ 

pl0-9_ 

_RI0-8_ 
_ R8 _ 



QI-13 
_RI0-I3_ 
_RI0-I2_ 
_RIO-ll . 
R9 _ 



-a 



n 

o 



3* 



1 


< 

o 


NATtRUt LIST ^|551-- 


^ 


»af a Avsvi 

g^2 > 


III 1 •^* N*— , 


S7 




1 103657 


A 




•Aft ^^ j^i SMir j •^.ia 


f 

t 


ITIN 


[ »vt, riTU 


OW«M« 


M.lltQ 


MMAMl M Cir. M«l€. 


• 


1 


board, PrinUd Wirlns 


L03656 


1 




i 


2 


iandle. Circuit Card 


100014 


I 






3 


i^VAlAf. TiiKiilai* 


in^AQ4-01^ 


7- 




^ 


4 




100197 


i 




s 


5 


Contact. ConnUnngr 


mm 


" 






6 


Contact, Conn Lower 


100098 


24 






7 


Transistor i&DS 216) 


103242 


7A 


Ql,2 




8 


Diode (SDS 103i 


innnoi 


^Q 


CR1,2, 3 




9 












10 




100308-103 


3 


C2.3.4 




11 


Capacitor. Tantaluna 


inn^i2-i<;^ 


1 


r-i 




12 


Resistor, i watt 


innii i-AiiA 


13 






13 


Resistor, i wa.tt 


100111-151 


9 


Rl thru RQ. 




14 


Resistor, i watt 


100111-221 


13 


RIO 




15 


Resistor, i watt 


innin-17? 


13 


Rll 




16 


R«»flintni* 4 waff- 


100111-272 


13 


R12 




17 


Wire, Solid Bare 


100042-024 


12 in 






18 




100274-022 


12 in 
















































' 






































































































































































































1 


kll-l 


»IQ% 








■ 



I<{ 



IS 



POLARIZING pins: 20 1 44 



1(03724 |AI 



?f^ 



! 

m m 



yz 



5 

O 



'I 



tfii 



i 



h\ 



lin 



mi 



■H6V 470- 



-I6V 460 



-t-4V 4SO- 



C-ROUNO 44 O- 



' O 



+ I6V +I6V 








' 










"^-^R. , _R6-7 C5-7 
RI-7 O^^^-^ ^^ ' _C6-7_ _R7-7_ 

PP « 2 « R6-5 C5-5 _R6-8 ^C5-8_ 

R3-3 ^1 ' OO Oq 1 r^ 1 

«'-« ' OOvO ^^-^ V-^ ''-' 

R2-6 ^ Q^-^^--^^^-^ 5 

- — d, i R6-3 C5-3 __R6-6 C5-6__ 

_R2-?_ g^ ^ ^^_^ 

_R3-3_ :^' OO Oqi I Oil 

:"--:4D0ia'S.'-' 9-''-- 

_R2-4_^ t R6-I C5-I _R6-4_ ^C5-4_ 
_R2-I_ 'Jj g ~ " "- ~" 'J' C6-l_ 

_-.3-,_ i^OOOoi.ij A 1 

R2-2 (^ R6-2 C5-2 O 
C3 _ E _ C4 _ _ C2 _ 

1 






Pin 1 

Connector 
End 

Pin 47 










Receiver Inverter Buffer AB53 
103726A 











a 



s 

41 



o 



NATCRtAt LIST 

OWO. TITtI 

ASSY. P. W. 

RfiCEIYER. INYF.RTF.R RTTFFF.R 




NOO § AB53 DATt 



ML 


•W*. M. 


MV 


_iA3Z^. , 


A 



ITF.H 



DVQ, TITU: 



AB5? 



owcito, wcmQ utmmi o> ctTt •••!•« 



i 12/14 1 

SSBBBBS 



•Nttr 



Board, Printed Wiring 



_103211 



Handlti Gircttit C>rd 



Eyelet, Tubvilar 



IQQQU 



103896-016 



Strip. Marker 



Contact. Conn Upper 



100197 
109097 



IL 



Contact. Conn Lower 



100098 



24 



Tran«igtor,( SDS 216) 



103242 



32 



Ql thru Q4 



8 



Diode (SDS 103} 



100091 



32 



CRl thru CR4 



10 



Capacitor, Mylar 



100308-103 



C2.3.4 



11 



Capacitor, 



Tantolum 



100312-156 



CI 



12 



Reeietor. k watt 



twm-Mo 



£3l 



13 



Reeistor, \ watt 



100111-151 



Ra 



14 



Reel a tor, \ watt 



100111-221 



R5 



15 



Resiator, \ watt 



100111-122 



R4 



16 



Resistor, \ watt 



100111-302 



R2 



17 



Resistor, \ ipatt 



18 >^^e. Solid Bare 

19 Tubing, Teflon 



100111-562 



t990«-9g4 

100274-022 



16 






Rl,3 



wiTirCTr 



w 



i 



Ji 



POLARIZING pins: 32 t 46 



•••16V 470- 
-I6V AbQ- 



+ 4V 450- 



T 

)UND 440 ^ 



+J_CT _J_C4 C5 



I a O — 

30 O — 
lO-- 



T 



Ii04e3elcl 



' RM >RI2 >RI3 >RI4 >RI3 > RI6 



660666 
36 25 22 9 6 3 



1 



LJ O 

X 

I u uj 

I U) -J 



Is 



CO 

«o 

00 
T 
O 



10 



|— 



3 






S^ 



CRI CR3 CP- 



J 43 38 

343 !« 



VRI 



;r7 <nfl 



CR« 



<n( 



VRZ 



%) 



o o 



•G 12 T 



at 



_ ro 



hi 



fO 



-CR3-I-0 
0-CR4-I- 
R2-J_ 

R7-!_ R7-2. 

R8-I R8-2 



' Ic 



I ro 

OCR3-2- 
-CR4-2-0 
R2-2 



OQ,.. 



LM 



TO-Ji 



-CR3-3 O 
OCR4-3- 
R2-5_ 



OCR3-4- 

-CR4-4-0 
R2-4 



■n TO 
|i|* 






,oi ± 



lui 



loU 

-CR3-5-0 
0-CR4-5- 









o>ro 



0-CR3-6- 

-CR4-6-0 
R2-6 



:tx:)roa:Da::.oOo,.e 



_R7-3_ 
R8-3 



__R7-4_ 
R8-4 



CR8-I_r> 

CRT-Ig 



|->i ^R3-l 



_R3-I. 

R4-J_ 

__C2-I 

_VR21^ 

_VRI-lI^ 
Cl-I 




_R9-I_ 

R5-I 



/-vjCR8-J_ 
^R7-^ 

R3-2 

R4-2 

<LyR2-J_ 
_C2-2_ 

CI-2 

^RI-2_ 

R9-2 

Q4-2. 



lO^Ol 



_CR8-3_Q 
_CR7-?V 

__R3-3 

__R4-3 

__C2-3 

Ji.R2-3_,> 

Cl-3_ 

R9-3 

Q4-3 



_R7-5 ^R7-6_ 

R8-5 ^ R8-6 



qCR8-4 
^R7-^ 

^R3-4 

R4-4 

_C2-4 

<piR2-^ 
^Rl-^ 
CI-4 



R9-4 



_CR8-5_^ 
CR7-5q 

_R3-5 

_R4-5 

C2-5__ 

CI-5 

JiRl-1^ 
R9-5 



q^R8-J_ 
q£R7-6_ 

R3-6_ 

R4-6 

C 2-6__ 

CI-6 



I \,,_^y 



uo 

I' Of 



Q4-4, 

Ol 
!0 



Q4-5 Q4-6 



R9-6_ 
R5-6 



6 ^' 



Rll — — RI2 



Q3-3 A AQ3-4 
— ^^ — RI3 — 



k iOl Ol --- 

'"OSiQ^-e 

Q3-5 T RI5 

— RI4 — O 



5* 



3 
GL 



n 

o 

o 
o 



3* 



I 



ill 



NATmtAt ttST 
•WO. TITtI 

ASSY. P. \^ CAELE nRTVFP ^ft 




•mmmwwm 



f^^ # AB55 



rg 



104840 



DAft 



B 



ITRN 



DV«, TITI.K 



DVO.HO 



M^JIi 




smii. 






n 



3oar d, Printed Wiring 



iandle. Circuit Card 



Hy^l^t T»h»lait. 



iM8.39. 



IJMii. 



in^fl9hTfll6 



g^TtPi MirKtr 



1P91?7 



S ::ontact. Conn Upper 



100097 



il 



Contact, Conn Lower 



100098 



24 



Transistor, SDS 216 



103242 



12 



Ql,2 



Transistor, SDS 217 



104389 



12. 



Jii^ 



Diode SDS 103 



100091 



42 



CR1>CR3 thru CR8 



10 



Diode SDS 101 



umiL 



IL 



YRtig 



11 



£iAGLfiJiii]iA£^dSJiL£fiJMiiMU^ 



inninTi??! 



1 7 



ni 



•i^ 



12 



Capacitor. Mvlar 



■""^""-■"^ 



ri*MiZMML 



13 



Capacitor. Tantalum 



iQQ3U-i56 



r7 



14 



fte si e t ep i y w a tt 



1 (» 0111 470 ' 



4^i^_ 



15 



Resistor, \ watt 



100111-151 



Rll. 12. 13. 14. 15. 16 



16 



Resistor, i watt 



jQQiu-iaa 



J^ 



R^.4.7ift 



17 



I^esistor, lY^^^t 



lQQUl-30a 



J^ 



18 



Resistor, i watt 



t^rni. 



tQQUi-33a 



i£. 



19 



Resistor, j watt 



100111-822 



JL^ 



.j^JSuJ. 



20 



Resistor, j watt 



100111-153 



R6 



21 



Wire, Solid Bare 



100042-024 



15 in. 



JLL 



TH^ingi T^fl9ii 



100274-07.7 



15. 



AIL 



wi-r-iiii 



d I 



«i 



s< 



Il063l5lt 



P0LARI2IN6 PINS 94 4 40 



+ 25V 47 O- 



-2SV 46 O 



+ «V 450- 



6ROUN0 44 O 



:^ 



+J|_CI JCi Jj:5-I _Lc5-3 Xc5-5 _LcS-7 C3 ( 

T T T T T T 




m 



4 



Ill 11 t i 



1 



O 




CIRCUIT 1 


M 


3 


4 


2 


14 


10 


2 


J 


23 


13 


15 


4 


12 


22 


21 


5 


57 


27 


2e 


6 


26 


36 


35 


7 


39 


38 


40 



20 


19 


IS 


30 


33 


29 


34 


33 


32 


4! 


43 


42 





I o£R5-i _ C5-L_ f^^r-H> 



_ a '^ 



"l£R7-7_Q 

•5"n 



.R6-7_ 
R7-7 



— R8-7- 
C5-7 



I ^R2iLo 



ILL I 



oa 




C5-3 






-CR7-2-0 



. Q2 - 
<J-VRI-4;r 



R3-6 



^4 «4:4-^ v^6a«'";>^Woi^3 

., . Uijjj^UU'ij. lA 



R2-7 



CR6-7 Q 

_C_RI-7 

.R|-7_ 

R9-7 



^~o 



RI0-6_ j^m| |«|tJi RI0-4_ JM|w jwiw RI0-2_ PI I I 

_R6-6_ ^.R5.5_ _R6-4_ 

R7-6_ ^R4-5_Q __R7-4_ -_C R4-.3q 

_Re-§_ QC R3-5, _R8-^ O CR3^ _R8-2_ OCRS-I- 

Q/-vCRI-5_ -CR2-5-0 OoCRI-3-. -CR2-3-0 -CR2-I-0 

X5£R4-fi. _R2-5_ XqJ:R4-4_ -CRS-iQ — R2-I- CR6-I^ 

5X£R3-&^ JlR6-io 5^R3-4o —"2-3- Qo^R4-2_ -cr3.2<-> 

<}.o£B2-2"' JLRi-£o ^O^^-^ _R2-4_ XgCRG-J. ^R2-J>. 

•^g _R2-ir ' QCR6-4. _CR|-4^ Sg^Rl-J- TrI-I^ 



pj_CR5-J_ R6-2_ pvCR5-J_ 

^^R4-3^ R7-2 ^jCR^lLo 



M-5_ _R'-6_ 



■RI-3— — RI-4- ' — "' '— 



R9.5— — R9-6- — R9-3— — R9-4- — R2-2— 



_RI-2_ 
R9-2 



— R9-I- 



— R8-5— 



_ R8-3_ 



Re-i_ 



VI 



n 

o 



-o 
5* 



NATCNUt LIST 

ovo. riTti 



8/D\S ••-- 

ASSY. P. W. CABLE DRIVER MOO § 



.. |ml 



106317 



AK53 



ITRM 



OVQ, TITI>: 



DI^G.HO, 



OATt 2-10_iHttT 2 



iio,mq jttmiULi o> c»Tt DUft 






c 



Board, Printed Wiring 



106316 



-Jandle, Circmt Card 



^ 



Tt 



Cyelet, Tubular 



4 Strip. Marker 



100016 



103896-016 






100197 



V- 



Contact. Conn Upper 



100097 



23 






100098 



24 



T ransistor. SDS 216 



103242 



Ql 



T ransistor, SDS 201 



100092 



Q2 



ransistor. SDS 209 



100697 



14 



Q3,4 



IQ. 



Dinflr.fiPfi IQ^ 



JJQMU 



AL 



CRl.2.3.5.6.7 



il 



Difldfi. SnS tQi 



JQQQaS 



.^£1 



IL 



±3_ 



JjL 



Resistor, i watt 



100111-330 



M. 



lQOUl-331 



100111-392 



JLl. 



-P-iJSLi 



14 



R4iS 



JuSl.,. 



lQQUl-56^ 



R2 



LL 
.11 
.12. 



iQQiU-^22 



^ 



2Qaaiarr±3sitc: 



l Q0 111 " 3 9 a 



Capacitor, Mylar 



100308-103 



C2, 3,4, 5. 1,5-3,5-5,5-7 



20 I Capacitor, Tantalum 



100312-156 



2L 



WircStfUdP^rg 



IL 



100042-024 



1^\>imt Tffion 



100274-022 



2iX^ Rf;aiflt.nri i wfltit 

24 Resistor, t watt 

25 jl^^sMl^oyi i w^tt. 



1 ,— .». .^,.. ,- 



SOS- 1£- 106 



100111-223 
100111-393 

1Q01U-68Q 



.L 

i2, 
32 



CI 



i: L 



ii 



i-1 



-Li. 



R1Q.12 
R6.7 



-~i- 



POLARIZING pins: 3 t 31 



+ Z5V 47 0- 



■25V 460- 



-♦^SV 450- 
GROUNO 440- 



I I 



666666666666666666 

I 3 6 7 10 12 15 16 19 20 24 27 28 31 32 36 39 40 



■I 

iji 



1 



'-> '2 



O 



i a 



iliih 



+ «v 






CR3 

-N— 



6 

CIRCUIT I 34 




+ 5.6V CRI 



1'. CR4 
JLCR5 
:LCR6 



VRI 



25V 
4 



CR7 



Re R9 

Q6 
VR2 




+ 25V ■+ 5.6V 
A A 



-Z5V 
+ 8V 



05 

J 



6 6 

36 41 



25 29 



6 6 
42 37 



M IS 




I I 



l< 06 



^ 



m 



o 7 7 r "^ IS 



^R2-J_ 



Ql-I 



-sCR3-l V->^ 
^ Q2-I 

;i"0 



qC.R4H_ 
CR5-I 



CR6: 
R7-I 



o 



R4-j 
R8-I 



I I I 

3) 3> 31 

? ? T 

Ira Iro |i>» 



Q_CR222_ 



^1 
?3,Q 



|ro o) 



QI-2 



— CR3-2 ^"^ — ' 
^ Q2-2 



Ills" 

a) 3J aj ,7 3)0 
5 o> = w wjc 

|w |W |w ' 



o 

en O 

11 3) 

|0< OD 



Q_CR2-3 



QI-3 



^3-2 



R2- 



^R4-^ 



^R5 
.CR6 



R7-2 



_R.-3_ Q 
,"" Q3-3 

to 

■i- 02-3 



i 



I, L I 3 I 



3) 3) 
0) — 

li 1^ 



n- 



Q_CR2::4 



i 3) 



QI-4 



Q_CR3-3 

R3-3 

R2- 

^R5-3 
QJCR6 
R7-3 



R3-4~ Q3-4 

-"^-t o 

0CR^:± 0^4 
o£R6-4. \^ 

R7-4 



R4-2 

R8-2 



^Rl-L. 
.CR7-I 



06-1 



07- I 



o S2 



i 



b o 



-^ 05-2^^ "«i_ Q5.3 



06-2^^ VR2-2i 



07-2 
04-1 



Do 



07-3 
04-2 



R4-3_ 
R8-3 

V^ qCR7-j_ 

J^R2-3^ 



05-4^ — "''"■V 



Oi 
Do 



R4-4. 
R8-4_ 

r>)0^m-4_ 
Vv_y o£R7-4_ 

_VR2-4jv 
RI-4^ 



04-3 



O:: 
Do 



04-4 



RI4-I 



RI4-2 



RI3-3 



_RI3-I_ _RI3-2_ 



— RI4-3_ — ■ 



RI4-4. 
RI3-4 






n 

o 



-a 
S' 



i 


< 








AL LIS 






ML 


DRAWING NO. 


REV. 


1 ^V^^ 


<M MATERI 


>T 






107234 


A 


SCICNT 

A 

DRAW 
TITL 


IPIC DATA SYSTEMS 


MODEL NO. — 




6 

z 



z 

i 

< 

K 



o 
t— 1 


.ssy, p. W. 

jNO SCHMITT TRIGGER 


AK54 


nATP ' aurp-r 2 of 2 1 




1 


ITEM 
NO. 


DRAWING Tl TLE 


DWG. NO. 


NO. REQ. 


REMARKS ON CKT. OESIG. 


1 


Board, Printed Wiring 


107233 


1 




2 


Handle, Circuit Card 


100016 


1 




. 1 


? 


Evelet. Tubular 


103896-016 


2 




4 


Strip, Marker 


100197 


1 






5 


Contact, Conn. Upper 


100097 


23 






6 


Contact, Conn. Lower 


100098 


24 






7 


Transistor (SDS 216) 


103242 


24 


Ql, 3, 4, 5, 6, 7 




8 


Transistor (SDS 219) 


106378 


4 


Q2 




9 


Diode (SDS 101) 


100025 


8 


VR1,2 




10 


Diode (SDS 103) 


100091 


36 


CRl thru CR9 




11 


Diode (SDS 106) 


100323 


1 


VR3 




12 


Resistor. 1/2 Watt 


100111-392 


28 


Rl. 2. 3. 4. 6.8.9 




13 


Resistor, 1/2 Watt 


100111-153 


12 


RS.IO.U 




14 












15 


Resistor, 1/2 Watt 


100111-821 


8 


R13,14 




16 


Resistor, 1/2 Watt 


100111-102 


4 


R7 




17 


Resistor, 1/2 Watt 


100111-222 


1 


R12 




18 


Capacitor, Tantalum 


100312-156 


1 


CI 




19 


Capacitor. Mvlar 


100308-10: 


4 


C2. 3,4, 5 




20 


WirejSolid Bare 


100042-02 


t 9 i 


1 




21 


Tubing, Teflon 


100a74-02 


: 9 i 


1 







































































































































SDS-E-106B 




I I 

JO 31 
00 U> 

I i I 



o 



CR22- 





n 

CM 



_CR23_Q 
RI6. 



ro 
ro 



RI5 



_RII _RI6_ S "^ I i*^-^ 

_RI2 _C5 _ I- I I I I I 

__RI4_ -CR30-Of ~ ~ 

R5 -CR270 CR20 

— — Qi rv- — 

^Tz O ^""'- 



Al 



A4 



I I 



* aj 



A7 



)q7 



_R42. 



o- '^' 

C2 

RI7 

_R4 

R44 

_R45_ 



Q_CRI9_ 

99 I 

n O -n 



^T^X 



30 JO 



n 

Mill 
JO 



5 5? 



" i" " Cl 

5 5 5 a> 

— Z: -g <3> oi 

6i(!)66 

•CRI6- 



IS L 0-CR42 

' ' X I - R4'_ _CR44^ 

, M CR37 ' ^ 

■ III — - 



6 4 



O— — ^ 016 014 



_R27_ 



5* 



^ 



n 

o 

3 



■TO 

5* 



I 


(D 


t J 

9SICMTI 


*TT^f^ MATERI 


AL LIST 




ML 


• nawiNo NO. 


IMV.| 




n)74i 




Pt9 SAT* »'r'»mi» ■" 


...^ ^ DB50-i 


-^.. 




5 


MAjMNa At ay. PW ShUt Register 


I 


i^-» f/^/iS ^,„ 2 «. 


3 


ITSM 

Ma 




MM. NO. 


NOkMO. 


MHAIIKS ON OCT. OtSIO. 


^m 


\ 


Board. PrlatedWirifiB 


M 1 74 


1 






2 


tUndl«, Cir cult C»rd 


100016 


1 




-_J 


3 


Cy«l«t, Tubular 


103896-016 


2 




4 


Strip. Marker 


100197 


I 






5 


Contact, Conn. Upper 


100097 


23 






6 


Contect, Conn. Lower 


100098 


24 






7 


Traaeletor. SOS 216 


103242 


10 


Ql. 4.5.6. 9.10.11.14.15.16 




• 


Trai^eUtor. SDS 220 


106781 


5 


Q2.3.12.1i8 




f 


Diode, SDS 103 


100091 


44 


CRl thru CB46 




10 


latecrated Oct. SDS 301 


108217 


9 


Al thru A9 






U 


Reelster. ^ Watt 


100111-332 


5 


R1.2. 3.4.29 




12 


Xeeleter. 1 Watt 


100111-222 


5 


R5.26.31. 27.28 




13 


mesietor, i Watt 


100111-153 


2 


R6,30 




14 


Retlitor. * Watt 


lOaill-102 


8 


R7. 10.13. 14.24.25.40.41 






15 


Xeelstor, ^ Watt 


100111-562 


4 


R8.9.33.34 




U 


lesUtor. 1 Watt 


100111-101 


5 


Rll.16.38.43.21 




17 


Keeletor, { Watt 


100111-822 


4 


R12.15.39.42 




It 


■eeUtor. i WaU 


100111-122 


2 


R20, 19 




H 


Xeelfltor. 1 Watt 


100111-182 


1 


R17 






Keelator, | Watt 


100111-681 


1 


R13 




21 


Beslater. { Watt 


100111-103 


1 


R22 




22 


r _ . 


, 








23 


Reeletor. * Watt 


100111-302 


3 


R32. 3^.23 




24 


KesUter, i Watt 


100111-470 


2 


R36. 37 




?5 


KeeUter. i Watt 


100111-151 


2 


R44. 45 




?' 


Capacitor. Tantalum 


100312.154 


2 


CI. 10 




27 


Capacitor. Mvlar 


100308-101 


3 


C2.3.4 




2t 


Capacitor. Mica 


100107-S20 


4 


C5.6.8.9 




29 


Capacitor. Mica 


100107-221 


1 


C7 




30 












31 




■ 




1. 




32 








1 



SD8-4S-10eB 



I 



a) 



^ 

N 




MATERIAL 



LI8T 



ML 



• ll*«IN« MO. 



\\\7^\ 



TiCT* AttY. PW fttfl Rf riittf 



nn-l •mjLSJi^mwMTl^ow 



• IIAW4M« TITCt 



IMMAItKS •« CUT. •K«ia, 



33 



Tr«n»Utor, 8DS 217 



I043«f 



Q7 



34 



Tubing, Tallea 



100274-t22 



• la. 



3S 



Wir«. Solid B*r< 



imi<-ff?^ 



liSi 



36 



K«sl«ter 



lOOUl-Ul 



R46,47 



37 

il 

40 



Dto4», <SDS U4) 

■chonaatlc 

Drswlng Litt 
T»«t >p»c 



101711 
^^"7 3 9 
U\74Z 

tn743 



V»l 



U. 



izd: 



,5;- 



9 



Hi . 
"Co 



ffl 



II0420I|b| 



POLARIZING pins: 2B « 34 



+ I6V 47 0- 
- 16V 4« Q- 



+ 4V 45 O 1 1 

+_[ci _|_CZ _1_C3 C4 



GROUND 44 



' O 



IE 



«J li- 



1 b5 1^ 



5 5 



o 

CO 
O 



la 



n 



III it h 



-f 16V 



h-^ 




R7 CR28 



CRI9 



+ I6V 
it 



@-H 






RI2 



CR29 RB 
— H VVAr- 



J^CH23 



:lcr24 ::cr25 



R5< ■i' 



+ I6V 
R22> 



cr3i:l 



CR32 
— H- 



+ 4V 



:LCR27 



CR22 

-k— 



CRII 



CR3 



CR30 
-14— 



:;. JL 



:!l-KJ-5f 



JL >R6 



CR20 
—14— 



CR 

41 37 38 

-*\ M— H- 



CR CR ^ + 



OOOOOOOOO 00 

41 35 36 — 40 31 37 39 38 43 42 CIRCUIT I 

26 20 22 21 25 31 23 24 36 43 42 CIRCUIT 2 

12 7 6 — II 31 9 10 36 43 42 CIRCUIT 3 



:: :l y. 



6 O O 

30 32 33 

16 32 17 

4 32 5 



6 o o 6 6 

29 — 34 27 28 

15 19 13 13 14 

- — 623 



SIGNAL 

NAME 



— C3 r>£P2l-3 CR r>£^27::3 C4 

_C9-3_ fj -^ ■ . CKR403-._O-C«'^ 



K> K>" i' •? 

i5^ S 2 



CR(OCRI9-2S- „„ 

^ QcR22-y rvcf 




'^ R3-3 






actra: 



g^«r" ace « i —"^-L- SSooi 

iJi?*J,l,J,'0-cm3^- 

Pi 



5?^ 2 



— R2-3- 
RI-3 



ip roipiol 

n iA*i. 

/-vCRI2-:3_ ooooi 
gCRII-3_ TT I I 






.oc.oc. 



R3~2 



«> 5 ' E o: — RI-2 — I2« ^ i £) 



CVJ 

51 

'-2- 



T 



-CR23^<; CK9S-2- 

OCR2l=J - OCR27-I- 

_^-^ C>cR22-r rK;R2o-i- 

o 



ggn-f Y^M^ri 



qC^R40H 



T:.;tjcj^ 





o^' 



RI6-I 



q£RI5zL ij i^ 

(D(0 f>- — 

R3-I KO: tc (T 



^R3r^ ~CR234-Ocr',9> ><^'^'^-'- 
— R22 - -CR3I-0 — R20 ogS £ « 



'1^ 



VJ — (C 

^vCR36 r 

I I ^R34^ 
^ £J C2 






I I 



Pin 1 



Connector 
End 



Pin 47 



Triple Flip-Flop FB52 
104203D 



a 


C 


Inatc 
ovo. 


8/dIs 

MBLY.P. W. — ' *— 


^ ••MllVtVfl* PAT A eVSTI 

_ liOD # FB52 1 


1^^, Mm. M. MV 


- r*- 104203 d" 


* 
o 

• 
o 


a 

o 


■ A5SE 


TRIPLE E!l.IP_FLOR 


tklt 12/4/3Mlt«T 2 •'^^ 


ITRN 


DVQ, TJTIK 


DVO.HO, 


NCRIQ 


MNAUI M CRT. VMIt. 


1 


Board, Printed Wiring 


104202 


I 




2 


Handle. Circviit Card 


100016 


1 




3 


Evelet. Tubular 


103896-016 


2 




s 


4 




100197 


1 




5 




100097 


23 






6 


Contact. Conn. Lower 


100098 


24 






7 


Traniistor, SDS 216 


103242 


21 


Ql thru Q4, Q7 thru Ql 1 




8 


Trantittor, SDS 220 


106781 


6 


Q5.6 




9 


Diode, SDS 103 


100091 


92 


CRl thru CR35, 37, 38, 41 




10 




— 10Q107 aao 


7 


C8i 9i 6 




11 


■ JU lister, ^ watt 


100111-103 


1 


R21 




12 




100107-820 


6 


C6.7 




13 


Caoacitor. Mvlar 


100308-103 


3 


C2.3.4 




14 


Capacitor. Tantalum 


100312-156 


1 


CI 




15 


Resistor, i watt 


100111-102 


3 


R25 




16 


Resistor, i watt 


100111-562 


6 


R17.18 




17 


Resistor, i watt 


100111-302 


6 


R15.16 




18 


Resistor, \ watt 


100111-470 


7 


R13. 14 .23 




19 






f 












J\L M. i t'C 




20 


Resistor, i watt 


100111-101 


6 


R7.8 




21 


Resistor, k wa^t 


100111-822 


6 


R9.10 




22 


Resistor, i watt 


100111-153 


6 


R5.6, 




23 


Resistor, J watt 


100111-332 


13 


Rl.2,3,4. 27 




24 


Resistor, ^ watt 


100111-122 


1 


R22 




25 


Resistor, i watt 


100111-681 


1 


R20 




'f 




100111-182 


1 


R19 




27 


Resistor, i watt 


100111-543 


1 


R24 




28 


Wire, Solid Bare 


100042 -02'( 


35 in 






29 


Tubing Teflon 


100274-022 


35 in 






^n 




100107-47C 


1 


C5 




































































































1 


(OS-K 


•lOfk 









I0456llcl 



22j 



i-roo 



POLARIZING PINS-. 32 k 38 



+ I6V 47(3- 



-I6V •««0- 



-+_|_CI _[c2 

T T 

JUNO 4«0 ' 1 ' — 



I o- 



R2 C9 
-Wv II- 



CRS CRT CR8 
-M > ( > l 



y. :i y. y. 



6 6 6 6 6 

CIRCUIT I — 23 22 21 — 

2 — 27 26 36 — 

3 — 15 14 13 — 

4 — 20 19 18 — 
5—56 T 12 

CIRCUIT 6 3 2 10 11 4 



^ 




1 



if 



^ 






lo 



1^ kJ bJ kJ 

<. ^ ^ * 

U> O O O 

+ I6V 



+ I6V 
4t 



&^ 



RI7> >RI8 
RI9 



"6 C7 /3L 



y. y y. 



CR20 
CR2i 



Q5 



y. y. :'. 





•f 16V 
it 



R26^ ^R27 R30 

CR36 

-H 



;R23 R24< 



:: y. 



< RIO 
-I6V 



6 6 6 6 6 6 

3! 42 41 33 40 32 




R25< 

-I6V 



Qli 
/trS CI2 R28 



y. y. 



O 

34 35 30 



6 60 

29 2S 37 



o 2 ^ 



If) i/> 



?cl 



1.111,1 



1 1 



I I 






I III I Ll LI I Ll l„| 



3) " 
CM <? 



.CM it** .CM .A 



.R34_ 
R33 



o 



013 



I - 



q£R23_ 

Cll 

R22 



C8 



CR22 



'c^CR29^'="!:r,^ 



' OV-/""" QIP -CR2_5-0Q6 03 
SX> "CR30-O 



R4-2 
C6-2 



— "^^ — I C6-Z_ C6-4 



CR2I 



C5-I 



r°"0(T ocr I -;- 




R2-2 



R3I 



.R7 



0-CR32-~O-Clf33- -CR36-0 

— 9 OCRI6- -CRI8-0 -CRI9-0 

— o _R9 _ -Cftl7-U 



— R26 — 

R2I 




R30 



^>CR8-J_ 

r r^R6-T_^ 

_CR8-1X 
^~_CR7-2_''^ 
*^6-2^ 



r* n I 

R4-4 

C6-4 

^C5-3 

R2-3 

C5-4__ 

R2-4_ 

CR8-3 



' <* 



= _R|7 __ OCR34- 
1^ CRI4 0-CR35- 

O-^^'^- OCRI3 - 

5 _R5_ ._cRI2-0 _CR3I_Q - «'cl5.2 

__ R6 _ OCR38- (>Cir39 - C>|7 .-^ 

R 28 . : t40«O ;:!■, ■ -O 



rrr' n 

R4-6 

C6-6 

°Dt) 

p5-5 

^R2-5_ 

C5-6 

R2-6 

' /-y£R8-5_ 
2^^R7-5^ 
(jtf\CR6-5_ 
I ^R5-5_pj 
_CR8-iy 
qCR7-6J^ 



\!SP7-3^ 
f^ CR6-3 
^XR5-3p. 

_CR8-4X 
^R7-4r^ 



o • oCRio_ 



'A 



qJ;r9 

_R35 

R36 



CI2 



_CH42^ _CR3-Lo -^ 

CR43~X CR4-i7r ry£^ 

~ nJR2-I^ ^^^ 

S^R3-2 



CR3"-Jy»^ 

CR4-3j^ 
^R2-4J^ 
rvCR3-4_ 
qXR4-^ 



-CR6-6-0 
RI-6_ ^ 

Q CR5-6 ai 
3R4-5^ t , 
CR3-5^Ai b 



<f _CR2-5y-v 
pXR4-£y 
XCR3-6_ 






— OCR4-2- 



5* 



3 
Q_ 



o 

O 

n> 
o 



-a 

5' 



li> 



^NATCNtAL LIST 

OVQ. TITtI 

ASSEMBLY. P. W. 
NAND, Ffajfp ridW 



o 




»W» # FB54 OATt 



ITF.M 



ova. TJTl.»: 



P¥0,|iO. 



WO. mo 




otmiuLi 00 cor. ototOi 



1 Board, Printed Wiring 



IM&R 



Handle, Circuit Card 



100016 



Eyelet, Tubular 



103896-016 



Strip, Marker 



100197 



Contact. Conn Upper 



100097 



23 



11 



Cflntaclii Conn Lower 



iQQQ98 



.^ 



Transistor, SDS 216 



103242 



16 



Di o de, S DS 103 



Capacitor, Silver Mica 



10 ! Cap acitor. Silver Mica 



Capacitor, Mylar 



100091 



•rt 



100107-470 



100107-820 



100308-103 



Ql thru Q3, 5, 6, Q8 thru 13 



GRl I hftt CR44 



C5,7,/a, 



£SjJ1 






C2, 3,4 



^ji-jta 



12 



Capacitor, Tantalum 



100312-156 



CI 



13 



Resistor^ ^ watt 



100111-470 



10 



R2, 6, 16, 19,28 



14 



Resistor, j watt 



100111-101 



R14, 22 



15 
16 



Resistor, j watt 



100111-151 



R8, 



, 27, 35, 36 



Resistor, t watt 



100111^22 



R12,23 . 



17 



Resistor, i watt 



100111-681 



MA. 



18 



■ 



Resistor, ^ watt 



100111-102 



MLJ± 



19 



Resistor, f watt 



100111-222 



R34 



20 



21 



Resistor, f watt 



100111-302 



R17, 18 



Resistor, ^ watt 



100111-332 



10 



Rl, 5, 9, 26,30, 



22 



Resistor, 2 watt 



100111-562 



R13, R21 



JJl 



24 



RfigUtgri i watt 



Resistor, j watt 



iOQUi-lOl 



100111-223 



JS^lX 



MIl^ 



25 



Resistor, i watt 



100111-563 



8 



R?.7.<8? 



26 



27 



28 



Wire, Solid Bare 



100042-024 



18 in. 



Tubing, Teflon 



100274-022 



Resistor, \ watt 



100111-121 



i8 In^ 
1 



R37 



29 



Resistor, ^ watt 



100111-182 



R31 



30 



31 



Tr^n^^st^Qr, §p§ g^Q 



106781 



Q4,Q7 



Diode. SDS 103 



10009; 



72 



CRl thru CR5 . 7 thru 12.14 



GR1$. l6.ly>l8»2Q thru 3Q 



CR32 thry 38.40 thru 46 



■f^BBnevw 



soITEtTW 



POLARIZING pins: 12 I. 32 



•••16V 470- 
-I6V •»60- 



+ 4V 450- 



+J_C9 J_CIO jj. 



:niu 



•»-4V 



1103 8821b 



HI > R2 > R3 > R4 > Re ^ RT > R8 



6 6 6 6 6 6 6 

42 41 38 40 3 4 5 






1! 



^3 
H O 

< o 

Z3 



in< 



fi\ 

I' I I 



¥ 



00 \i. 



lo 



r 



■H6V 
>RI7 



R2I 
-VW- 



CR27 CRI6 CRI7 
— W >l »l 



CIRCUIT 1 


37 


39 




2 


36 


35 




3 


32 


31 




4 


29 


28 




5 


12 


t3 




6 


9 


10 


CIRCUIT 7 


e 


r 




4 


j> 


SISNAL 








MME 







o 

43 

34 
33 

30 

II 
8 
2 



o 

17 



11 y. y. 



CR28 CRie CR20 
4— H M— 



6 



:i :: m 



6 



+ I6V 
> R20 



Je^-HH^ 



CR30 CR22 CR23 

-M H — H- 



CR2B 



6 6 

20 22 21 



CH2S CR26 

-H H- 



6 

27 



R25-Z_ <V 



_CI-7_ (^ 

o 

b 



— ^'"^— jCRI6-7«r> 
Q.CRI7-7_ ^^ 
— R2I-7— 



__R29-7_ 

_J«l7-6_ 
__R25-5_ 

R26_ 



— R29-6- 

_C5-6_ 



0-CRI5-7- Q^^TzL 



"= K » 

q: 



"O 



CI-6 

_CRI6-60 "" 

0-CRI7^6- ^^R27-6 

-R2I-6— 0-CRI5-6- *-'"., 7" 

-R29-5- _CI-5_ 



I I 



— C5-5- _CRI6-4^ _CRI-5 



r^ 



R26_ ^V— ^ 



-R2l-5^ C>CRI5-5. qCR27j:5 
— R30_ __C2 _ 

— C6 — 



CI2 

R28_ S. 



R28_ V^^ 

_ R20_ (^ ) 



O— C9 _ 

_R27_ (^ 
— CM _ T 

__R25-4_ V_y 
__RI7-3_ 2 

_R25-3_ 
_pi7-2_ 

_R25-2__ 

_p29-|_ 

— ci-i_ 

_R25-I_ 



^RI-7^ 
^R2-7_o 

XRi-i-o 

_CR2-6_Q 
^R2^5q 

-R22X_ 0_CRI8_ O^^^}^ — ^"5—0 

_CR3_Q 

_C8 — _CR25_o — ^^ — _CRI4_^ 

0-CR26- , CR'2__r\ CRI3j^ 

- R24'-:: 0-CR24- ^ziT^ -^"'Lq^ 

_R23_ rS^^\ O— CR7 ~ "^ 

_CR9_o 



-CRI9. 
0- 

_R3f_ 



»Z3- — 



.C7_ -CR22-0 -^'*^ -O 

~R3I 

-R2I-4- 0-CRI5-4. 



C3 



■$:cRiT«-""°-" -e-""^ ^'-* 



O 



O 

b 



_C5-4"- -CRI6-40 
_ R29-4_ 

O-CRIT-S-" 

— C5-3-* -CRW-30 

-R29-3- 
-R2I-2- O-CRB-Z- 
0-CRI7-2- ^ 

— C5-2- -CRI6-aO 

_R29-2_ 

-R2I-I- O-CRIS-L 

O-CRIT-ri 
-C5-I— -CRI6-I-0 



_CI-4_ 

^R27j:3 
_CRI-3_Q 

^CI-3 

q£R27^ 

_CI-2 

q_CR27H 
_CRI1^ 



f^ 



^2 



_CR2:£^ 
_CRI-J^-' 

CR2-1^ 






CIO 



Pin 1 



Connector 
End 



Pin 47 



NAND Module IB52 
103884D 



I 


c^ 


Imati 


RIAL tttT p— « 
If. PRINTED WIRInIp' VS 


ft »^^ 




Mil •^•- "•• "^1 




"S'Af^ 


1 Mitiitirie •«*« eir.Tt 

- »»#-IB52 


[ 103884- 


o 


^"' 


o 


ASS 




NANO MODULE 


DAW §mn g m ^ 4 


s 

• 


ITKH 


Dtia. TITt.K 


DVO.HO, 


NO.RIQ 


MMAtil m CKT. Mttt. 


1 


Board. Printed Wirinii 


103883 


1 




2 


Handle, Circuit Card 


lOOOU 


1 




3 


Eyelet, Tubular 


103896-016 


2 




^ 


4 




100197 


1 




5 




1Q00Q7 


23 






6 


Contact, Conn. Lower 


100098 


24 






7 




103242 


10 


OK 2. \.A 




S 


Diede (&DS lOli 


- -4040^1 


(^ 


€Ri^-tiiru^Biftd#- 




9 


Capacitor. Silver Mica 


100107-^7^ 


10 


Cfi.6.7.8 




10 












1| 




looiftft-in^ 


^ 


rin 1112 




12 




100312-lRf 


1 


rQ 




13 


Resistor, i watt 


100111-332 10 


R17.18.19.20 




14 




iooiii-4m| 10 


R21 22. 23. 24 




1? 


Resistor. 4 watt 


100111 -If ij 10 


R2'5.2A.27.^A 




U 


Rftsiator. 4 watt 


100111.151 


7 


ni t>.^ii 4 A 7. 8 




17 


Wire, Solid Bare 


100042-024 


LOin. 






18 


Tubinff. Teflon 


100274-022 


10 in. 






19 


Diode (SDS 103) 


100091 


56 


CRl thru CR14,16,17,18,20, » 






* 






22. 23.25 thru 30 












































































































































































































N 


I 


»S«K- 


.J« 









1104554 IbI 



P01ARI2IN6 PINS : 32 ( Se 



+ 16 V 47 O- 



- 16 V 46 O- 



+ 4 V 4S O- 



SROUND 44 O- 



1 o- 



+ CI JcZ Jc3 Jc4 



Tl 



is 

5l 



lf> 

i2 



lo 



HI 1 





2 




3 




4 




5 




6 




7 




S 




9 




10 


CIR 


CUIT II 



36 
36 
42 

6 



CR2 



CR3 



CR5 

± 



R2 



CRt 



CRK) CRII 

-H — H- 




40 
31 



5 
13 
38 
30 



I 



I i' 



' J 

I Ol I 

,0.1 



I - - 



o I 

0> (O 



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r>i 



I I 



70 
ro (x — ( 

-.-I I 



I- L ? 2 I 



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C6-I0 



01-10 



D 




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_CRI-iOQ 

In lo lo 
i<jt 'ro | — 



A. 



qte 01-9 

oO 

C5-8 

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C5-9 

R2-9 

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pvCRIO^y 

^^Rs-^iy 

XcRii-e_ h 
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ai o> I I 

ri ' 



.= 1 



Mil 

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' rri 



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oo.oO 



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[=fCRI-5_ 



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C5-3 

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I _CRII-J^ 
-^Riq^ 
XCR9-_3^ 
j-vCRS^iy 
X£RIIH_ 
^RI0H>-v 
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OCR9-I- 
I -CR8-I-0 

SocRi-3- - 

T* OCR 2-3- - 

I S.^^-Ln 

O _CR5-rX 

-CR^-Io 

^R3-TJ^ 
_CR2-7^ 



QI-7 01-6 

QO 



.C6-2_ 

__C6-II 
ii-ll QI-2 



.C5-7_ 
R2-7_ 
C5-6_ 
R2-6 



^ 



_CRII-6^ 
^RIO^^ 
XCR9-6j^ 

XCRII-7_ 
^RIO^ 
CR4-_3_pj ~^ 

Z_XR9Kr 
^R8-7^ 
_CRI-7^ 



^ 




C5-II 



_R2-II. 

_C5-2_ 

R2-2 



-I 



-SRii-^O 
rv£RiO:2r 

^R9-2_o 

/-vCRe-iy 

fv£RII-lJ_ 
^RIO-iL-j 
/-yCR9-liy 
^^R8-iJ_pj 

o rLCRi-2y 

=gCR3-2_ 
5^^R4-2_ 

0-CR5-2- 



-CRI2-2-0 






3 
Ql 



n 

o 

O 



5* 



I 


Uj 


MATC 

ovo. 


"i"- "" ofirSlc:. 


% - . _ 




... ML 


9VQ. VO. 


car 


tiTtI CjL/lO •••■"▼•»••••»••»•»« 


104556 


.£ 


• 

o 

• 


m 

o 


ASS£ 


HAND 12 NOO J IB 56 1 


DATt 


12/4 SKSBT 2 Of 2 . 


ITKN 


•v«, rirti: 


OMO.ItO, 


HO.RtQ 


Kciuiuf ea cir* Diato* 


1 


Board. Pi-l«t»H W4i.i«|' 


104555 


1 




2 


Handle, Circwlt Card 


lOOOU 


I 






3 


flyeUti TuhuUr 


1018H-016 


2 




1IAI 


4 


Strip, Marker 


100197 


1 




5 




100097 


23 






t 


Contact. Conn Lower 


10009t 


24 






7 




103242 


11 


Ql 




ft 


Diode. SDS 103 


100091 


67 


CR^ thruCRB. GRID. 11. 12 




9 




100107-470 


11 


C5 




f9 




100308-103 


3 


:2.3.4 




V 


Caoacltor. Tantalum 


100312.156 


1 


:i 




12 


Reatator. \ watt 


lOOlH-lSl 


I 


R4 




1} 


Reeiator. \ watt 


100111-470 


11 


R2 




14 


Reeiator. \ watt 


100UU332 


11 


Rl 




15 


Reeiator. * watt 


1001U>563 


11 


P3 




U 


Wire. Solid Bare 


100042-024 


S^A^' 






17 


Tubing, Teflon 


100274-022 


2-^/V- 




























































































































































































. 


























































J 


»os.r 


.IOC 1 









9,9,1 



OC^ R p] ?5 S" £ 

« _ s _ ' 6 ' 6 ' 

r)_CR24_ 

OJCR23 , 

^„^^ 0-CR25- 
0_CR26_ 



C4 



RI6 _ 

_ RI4__ 

_ R9 _ 

RI2 _ 

_ RIO __ 
_CI4 

R36 

_ R33 

R32_ 

_ R29_ 



I J 



DO 



J ' ' 

a> oo r- 

CNJ CM OJ I . , 

CC (E (T CM — o 

U O U CM CVI OJ 



ro 



_c._-Qg:=-: 

_CI2 _ 



_R34_ 



- (^c>CR63_ 



Rll _ 
R35 __ 

Q_CR69_ 
0-CR68_ 

_R3I _ 

O-CRei _ 
O_CR60l_ 



666 



_CR64 



•n to t^ C* 

ai iO iO fO 
CC. 01 (T. OC 
O O O O 

666' 



'-0 

? 



_ R30_ 



^J 



CIO _ _ R27 _ 



_R28 
_R25_ 






0_ CR53_ 
0_ CR54_ 
C8 _ 



_ R24_ 
R2I 

_R20_ 

RI7_ 

R2 _ 

_ R3 _ 

Rl __ 

R6 _ 

— R8 _ 

. CI8 _ 



C7 O^^^o-CR46_ 

_R22_^— ^_C6 _ 



O.CR52_ 
OCR5l_ 
_R23_ 

Q_ CR45_ 
0-CR44_ 

_ RI9 _ 



05 °^^0-CR39_ 



o o o o 

Ad)66 

_CR50o 
J -CR49^rj 

S ?99 

_ CM a: 
* S " 

Ye B: I I 
* ^ o 

to <-> I 

o 



495"; 



I 



RI8_ 



.CRI0_ 



_ R4 _ 



(;;>.CR38_ 

?9<?'?JJ 






Dt) ■''" 



-CM lO J CC g 
(E (r CK K " . 
o o o o I I 

III' 



(J 



en 92 t — f^ 

5 a: ir (E tc 

5 o o <J 1 

■ I JL I I 



_CRI3uo 
' _CRI2_o 
_CRII_o 



9^ I 

IE , lO 
(J ' (E 



Pin 1 



S 



__ 02 _ 



CI7 



016 

015 



V.IO _o 



Connector 
End 



Pin 47 



BAND NAND IB57 
104488D 





Q 


fUTCniAt List r— « 


1 




■St 


ML 


DifQ. no* 


CJlf 


ASSY.PRINTEDWIRINCr— ' ^— • 
BAND - NAND MOO ib57 1 


104488 


D 


J 

• 
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00 
00 

o 


»T«12/4 •HCCT 2 „ Cr 2 


ITf.M 


OVQ, Tirt.K 


OVG.HO. 


ilO«IIKQ 


KBMARIg en CKT. DBSta. 


1 


RaaM, printed. Wiring 


104487 


1 




2 


Handle. Circuit Card 


100016 


1 




3 


Eyelet, Tubular 


103896-016 


2 




_J 


4 


Strip. Marker 


100197 


1 




5 




10t»0Q7 


23 






^ 


Contact. Conn Lower 


10009a 


24 






7 


Transistor, SDS 216 


103242 


13 


Ql thru Q13 




e 












? 




1 nnoii 


71 


/-n 1 fcV r^ntt 














10 












11 


Ca->acitor. Mica 


100107-470 


5 


C5.7.9.11.13 




17- 




inn^fiA-ini 


^ 






P 




\nn%i7.\f,k 


I 


C15 




14 


Resistor, t watt 


100111-151 


2 


R37.38 




15 


Resistor, \ watt 


100111-470 


5 


R18.22.26. 30. 34 




16 


Resistor. \ watt 


100111-332 


9 


R1.5.Q. H 17 >i 7^-79';\^. -- 
















17 


Resistor, { watt 


100111-153 


4 


R3,8. 12. 16. 




IB 


Wire. Solid Bare 


100042-024 


10 in 






19 


Tuhin-^. Teflon 


100274-022 


10 in 






20 


Resistor. \ watt 


100111-563 


5 


R20. 24, 28. 32, 36 




21 


Resistor. \ watt 


100111-302 


4 


R2.6. 10. 14 


N 


22 


Diode: SDS 103 


100091 


62 


CRl thru 7, 9 thru 15 












CR17 thru 24. 26 thru 29 












CR31 thru 36. 38 thru 44 












CR46 thru 51. 53 thru 60 












CR62 thru 68. 70,71 








































































































































SOS-K 


-I0» 















Ii04894|b| 



Is 



POLARIZING PINS'. 42 I 4* 



+I6V 47 O 



-I6V 4« O 
+4V 45 Q 



GROUND 44 Q 




1 






55 



O 



lO 



lUih 




CIRCUIT 1 


5 


2 


6 


3 


13 




12 




24 




2 7 




23 




22 


9 


26 


10 


31 


II 


33 


12 


37 


13 


36 


14 


42 



21 
26 
30 

34 
36 



c 



















— ■■ '-. 
















1 

3) 


. . I • , ,11, ,11, , 


5 2 1 1 5 ? 1 1 


« 1 , . 
2 5 1 






1 5 ? ? i jb S ? = 5 S ? « » ? ? 


^r? ?r?? ?rr^?L, 






L o 1* P 1 1, " H 1 5 ,"11," l"- 


1^ <!"|lf> Hl^i^I 






A OI II II 


1 1 


1 1 


1 1 


1 1 


' • 1 






0-CR4-I3L 


0-CR4-ll_ 


0-CR4-9- 


0-CR4-7_ 


0-CR4-5- 


0-CR4-3_ 


o-c?J-'- 






.-CR5-I30 


-CR5-II.O 


_CR5-9^ 


_CR5-7.^ 


_CHb-5^ 


_CR5-3-^ 


-CR5-I-0 






0-CR6-I3. 


0-CR6-ll_ 


0-CR6-9_ 


0-CR6-7_ 


0-CR6-5_ 


Q_CR6-3- 


0-CR6-l_ 






_CR7-l3o 


-CR7-II-0 


^R7-9_o 


_CR7-7«o 


-CR7-5-0 


_CR7-3^ 


.XR7-I-0 






JCR4-I4.0 


-CR4i2<) 


_CR4-I0^3 


_CR4-8^ 


jCR4-6_o 


_CR4^4^ 


-fto-O 






O-CRb-W- 


O-CRS-C- 


Q-CR5-I0_ 


OXR5-8_ 


0_CR5-6_ 


0-CR5-4_ 


0-CR5-2_ 






-CRS-W^O 


_CR6-12-o 


_CR6-IO<5 


_CR6-8_o 


_CR6-6.0 


_CR6-4^ 


_CR6-2^ 






O.CR7-I4. 


0-CR7-l2_ 


O-CKMO- 


0-CR7-8_ 


QJLH/-6_ 


0-CR7-4_ 


0-CR7-2_ 






On 


On 


On 


On 


On 


On 


On 


■ - ' .V • ''■ ' 




QJ-13 


QNI , 


yy 


Toy 


yy 


yy 


yp 






- " 1 

F § 


a 'o 


a 1 




? > 


^ 1 

en 


o 1 


. ,■:■■'. : ■: ■! l ^-t^iy,^ 




^ t f !? t t 


r s r 9 ^ ^ 


■ -' ''iy''.''h 






1 > o. 


1 1 1 i !■ 1 


1 n'fe 1 1' r 








* Vui 3??|0|V'3' S 


s 


T 1 -« r\> 








1 

_CR3-6_0 


O S aj G a) 

0-CR3-3. 1 ~,^ r 
OCR2-3_ A^ 1 




z 




^ 6 Ao S lODQ-CR'-^- 
(!X>CR3-I3. _CR3.l2i? S S^ S6oCR3-5- 


_CR2-6.0 


OCRI-3_ 6 0-CR3-I— 




> 




_CR2-7_o 


_CR3-4-OTO-CR2-l- 




z 
^^ 
fez 




' 




i ^(o O-CRi-5- 


^R3-7_Q 


_CR2-4.070-CRI-l- 






_R3-5- O 


^p 










c^ 










_, 










DO 










Ol 






o 


3 ? 


-o 




3 3 


3* 






— 




^ Q- o 











•»•»•••• IML 
* tfs? Dm 






o 



S9 



'O* 



00 

o 



NATCNtAt LIST 

owo. riru 
ASSY,P,W. NAWnfi 




ITRH 



DVO. Tirii: 



••••HViria VAVA 



104896 



J^ 



DwciKi, wotWiQ nimm m ciTt Mtu. 



3oard, Printed Wiring 



iandle. Circuit Card 



Eyelet, Tubular 



104895 



12mJL 



103896-016 



^^TtPi MtrlFf '^ 



m\ii 



finntirti finnn llnniir 



Jb 



n,^r>t»nt. r^nn T.ftw^y 



Tranaistor. SDS Z16 



1QQQ97 



2J^ 



IQQQ^a 



.^ 



10321^ 



14 



jai 



P\9iu 8Pg t9? 



10 



fiiMfitoriSilYir Mif.i 



Capacitor, Mylar 



ifioim. 



J4. 



CRl ftri CR# 6 7 



1QQ107-II2 

100308-103 



I± 



1^1 



??i 3| 4 



11. 



Capacitor. Tantalum 



100312-156 



CI 



12 



Re»iitor, t watt 



100111-332 



14 



M 



13 



Reiiitor, i watt 



t09tU'5t3 



14 



.M. 



JJL 



RfiiUtor. i watt 



lQQUi-l7Q 



1± 



JLL 



15 



r " ' ' 

16, 



Wire, Solid Bare 



100042-024 



?4 i, 



Tttbingi TcfloB 



tQQa7i"Qaz 



ses-K-io% 



1 104641 IbI 



13.1 



POLARIZING PINS : 2« t 40 




inii 

ii 






. a. 

u UJ 

^9 



iiith 



Im 



'J- 
o 



lo 



VRI 



9 3» 

10 35 

11 35 

12 3S 

13 3S 
M 35 

15 35 

16 37 

17 37 

18 37 

19 37 



o 

8 
7 
6 
13 
10 
9 
19 
20 
16 
27 
22 
21 
26 
34 
33 
36 
38 
39 
31 



+ 



+ 

o ^ 

4^ a> 

n S' 

o 

(D 

z 

DC7 

o 



I 1, 1. 1. 1, 1, 1. 1 









I, I, I. 

ro M IN) 



<o o> 



= lo r 



a ,ai ,A 



a ' 

-^ODTO O O OO O 



ro N T* 
I(i> I" I* 



la . 1.1, I 



» aj 

M ro ro 

' ■ . > 

iw lio - 



QI-19 



-VRH8-> QI-15 QH3|<j QI-12 Ql-IOQI-9 

o:a , . oij o 



jQI-«»^l-4 




QI-8 V V7 QI-5 



OO ro o 



q£R2-!9. 

-CR2-I70 

OCRI-19- 
__RI-I6 

_CR2-I6q 

OCR2H8- 
-CRI-I6-0 
OCR I -18- 
Rl-I7_ 

-CRI-I7-0 
_R3-I§_ 



RI-15 



_VRI-^ 
RI-7 



^Rl-i_ 
RI-4 



0-CR2-I5- 



-CR2-I0O 



.R3-I9_ 
R3-I6 



-R3-I5- 
qCRI-JS. 

RI-14 
qCR2-I4 

_R3-I4_ 
QCRI-J4. 

RI-13 

qCR2-]3 

OCRI-13- 
__R3-I3_ 

R3-I7 



-CRI-IOO 
R3-I0 

Rl-ll 



OCR2-7- 
R3-7_ 

^Rl-i_ 

RI-8 



-CR2-II-0 

CRI-II Q 

R3-II 
RI-12 
C_R2-J2q 



OCR2-8- 
_R3-^ 

qCRI-J. 

RI-9 



-CR2-40 
_R3-4_ 

cn\-±Q 

RI-5 

CR2-J^ 
_R3-5_ 
CRI-5 Q 
RI-6 



OCR2-9- 



" " qCRI-J_ 



R3-I2 



- R3-6- 



QI-3 Ql-I 

!0 



1^ 

T7 QI-2 
<iyVRM 

^Rl-J. 
RI-3 



qCR2-J. 

R3-3 

qCRI-3_ 

Rt-I 

^R2-J_ 
^R3-J_ 

QgR|-|___ 

RI-2 



-CR2-6-Q O^^^ 



R3-2_ 

^RI-2_ 



3* 



o 

= i 



-o 
5* 



1 


<^ 


lUTciiut t»T Q/pn-r 


» . . 




L.i 1 •«• »•• l«irl 


^KS^^rirt^ ^D\& -—"• — |mi-| ^.^^^^ |^ | 




9 

o 


+8 To +4 INTERFACE MOO f ^^^^ | 


iiATt §mtT z m 2. 


• 

s 

« 


ITRH 


Otf«, TITt.K 


DVO.IfO, 


NO^IIBQ 


RBmillf M CKT. 0Bat«« 


1 


Board, printed Wiring 


104762 


1 




2 


■landle. Circuit Card 


100016 


1 




3 


•^yeUt, Tubular 


103896-016 


a 




s 


4 




loniQ7 


1 




5 




lonoQ? 


2^ 






6 


Contact, Conn Lower 


100098 


24 






7 


Iransistor, SDS 216 


103242 


19 


Ql 




8 


Mode, SDS 103 


100091 


38 


CRl . CR2 




9 


Diode. SDS 115 


107063 


21 


VR1.VR2.VR3 




10 


Capacitor , Mylar 


100308-103 


a 


CI, 2 




U 


Keiiftor, i watt 


100111-332 


19 


Rl 




12 


Resistor. \ watt 


100111-393 


19 


R2 




13 


Wire. Solid Bare 


100042-024 


18 in. 






14 


Tubing, Teflon 


100274-022 


18 in. 






15 


Resistor, i watt 


100111-153 


19 


R3 




16 


Resistor, i watt 


100111-471 


1 


R4 






























» 




































































































































































































































1 




1 


Wi-K 


>io» 









lQ4864lcl 



POLARIItNO PINI 34 4 M 



■•K5 It OMITTED ON NIX. 



+ 25V 4T0- 



-25V 4tO- 



♦ •V 48 O- 



GROUNO 440- 



I o- 






( 


:> 


CIHCUIT 1 


42 


2 


40 


3 


3a 


4 


36 


9 


34 


6 


32 


r 


30 


a 


2S 


9 


26 


10 


24 


II 


22 


18 


20 


13 


18 


14 


16 


15 


14 


16 


12 


IT 


10 


18 


8 


19 


6 


20 


4 


21 




2 



LI 



43 

41 
39 
37 
39 
33 
31 
29 

2r 

25 
23 

21 
19 
17 
15 
13 
II 
9 
7 
S 
3 






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^^< 

5 I L. 

3 tr a 

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I I I I I I T I 

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e. 



1 


1 


1 


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1 

lO 


1 

lO 


1 

(0 


1 


M 






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^ 


CM 


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CM 


Q 


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CM 


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■^ 


*l 


"l 


■=1 


1 


a: 
1 



I I I I I I 

o> a> 2 2 = = 



CM ro 



^, 



. - e 
I I I I 



lO CM 



CM N 
CM A 



I I I I I I I 



lo lo <o u> r» N 
I I ' I 1 I 

CM lO £J lO CM lO 



I I I I I I I i 



CM l*> 

I i 



CM lO w !2 gi 

"=1 -^1 '"I "=1 "=1 



_R2-2I. 

.R3-2I. 

RI-20 



.RI-12 _ 



OD «D __ 



S £ _LI-6 _ 



lO * Y — 

lO CM C 

QC K OC 

I I I 



.LI-2 



O- CI 
C2 



.RI-21 _ 
_LI-2I 
Rhl9 



LI -20 _ 


Ll-i9 _ 


__RI-I8 _ 


_RI-I7 _ 


LI -18 


LI-17 _ 


__RI-I6_ 


_RI-I5 _ 


U-16 


LI-15 


__RI-I4_ 


_RI-I3 _ 



_LI-I3 
.Rl-ll _ 



LI-12 


Ll-ll 


— RI-IO__ 


_RI-9 _ 


Li-m 


LI -9 


_RI-8_ 


_RI-7 _ 


1 i-fl 


LI-7 _ 


__RI-6 _ 


_RI-5_ 


LI-6 


LI-5 


_RI-4 __ 


_RI-3 _ 


LI-4 


LI-3 _ 


— RI-2__ 


_RI-I _ 



.Ll-I 



C3 
C4 



Pin 1 



Connector 
End 



Pin 47 



Drive Cable Interface NB52 
104866B 



1 



41 



Mod 
kSSY. P. W. DRIVER rARl.TT. TMTTrDirA/-ir # NB52 



00 

o 



NATmiAt tier 




ITftH 



DVQ. riTU: 



P¥0,iiO. 




SSiSSSL 



9 

If 



3oar d, Printed Wiring 



m48^ 



n 



■landle. Circuit Card 



10001^ 



Cyi>l#>t. Tiihnlar 



inihUwOih 



i ?trW. Mi^rKtr 



1Q0197 



5 Contact. Conn Uoncr 



1Q0Q97 



i&l 



Contact, Conn Lower 



100098 



24 



[Capacitor, Mylar 



,QQ3flft"in^ 



n?, ^,4 



i^apacitor, Tantaliun 



QQ3U-i5f> 



r.i 



kfllfltnr. i watt 



l991U-i§t 



^ 



10 



nductor, Molded 



mn-iii 



^ 



JUL 



11 

12 

13 



Wire, Solid Bare 
Tubing, Teflon 

Resistor, t watt 



|100Q42-Q24 
100274-07,7 
100111-102 



i^JBk 



JAi 



ii. 



,Bi^ 



MLK'-IU 



1" 

IS 



s's 






"E 



o 

o 
1- 



M il 1 1 



II 



POLARUING PINS: 12 k 40 



+4v/+IV 45 O- 



GROUND 440- 



• o- 



R4 >R9 <R6 <Rr 



RI9 <RI« <RI7 ^Rl( >RI9 <R20 



66666666666666666660 

2 3 4 9 6 7 S » 10 II 12 13 14 l» 16 17 It 19 20 21 



:r22 <;r23 •;r24 |;r2» <;r26 |r27 l;R2a 



|r30 ii 



>Rdt j:i 



6666666666666666666666 

22 25 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4! 42 43 



C4 

.R2 

R4 

.R6 

.R8 

.RIO 

RI2 

RI4_ 

RI6 

RI8 

.R20_ 
R22_ 
.R24_ 
.R26_ 
. R28_ 
, R30_ 
.R32_ 
.R34_ 
. R36_ 
. R38_ 
. R40_ 
.R42_ 

C2 



Pin 1 



R3 

R5 

R7 

R9 

Rll 

RI3 

RI5 

RI7 

RI9 

R2I 

R23_ 

R25 

R27 

R29_ 

R3I 

R33 

R35_ 

R37 

R39_ 

R4I 

R43 



.CI 



Connector 
End 



Pin 47 



Termination Module +4 ZB50 
104016A 



I 


< 


MATtniAL LIST r— 


n«- 


% - . - 




... ML 


PVO* M« 


Mr 


P. W, TCRMIWATIQW MODULE +4 MOO # ZB50 ( 


104016 


A 




o 


DAnV/c/43 Mtir 2 or a 


o 

• 


ITf-M 


Wl%. TITU: 


DVG.HO, 


NO.IIIQ 


MIUIIKS M Cir. DItlO. 


1 


^^f rd. Printed Wiring 


104015 


1 




2-^ 


? 


iandle. Circuit Card 


100016 


1 




3 


Ey«let| Tubular 


; _. - 


103896-016 


2 




S 


4 


StriD. Marker 


100197 


1 




5 


Contact. Conn. Uooar 


100097 


23 






6 


Contact. Conn. Lower 


100098 


24 






7 


Capacitor. Mylar 


100308-334 


3 


C2. 3.4 




8 


Capacitor, Tantalum 


100312-156 


1 


CI 




9 


Resistor, ( watt 


100111-151 


42 


R2 thru R43 




10 


Wire. Solid Bare 


100042-025 


5 in. 


„ 




11 




100274-022 


5 in. 














































































































































































































- 














































































































1 


;os-ic- 


•j» 


1 






.Z ,,.- >^' 




\ 104329 |C| 




<i 11 i I 



E 



rO 
O 



|o 



POIARIZINO FIN»I 30 i 31 



CROUNO 44 Q- 



6o6 6o6o6 66 4o66 

42 99 36 33 2T M 21 II 15 12 9 6 3 I 



O 

46 



i: |R2 5r3 i >R4 Srs :i: ?R6 ^RT :i: >R8 JrS ifr 



cr 



>RII :^ >RI2 SRI3 



6666666666666666666 

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 



t^» |r,4 ^RlstlP'O I 



Rl€ ^RI7 4: ^Rt« ^Bl*: 



+ CI2 > 

T f 



R2I=: >R22>R23;i: 



CI4 



>RZ5:^ 



666666666666666666 

21 20 19 18 17 16 19 14 13 12 II 10 9 8 7 6 5 4 



••R26 :± 













R26 










o— 


Cl 


^_ 








R24 






R25 






o- 


CI4 






R23 






R22 








•WMBia^ 












o— 


CI3 


^.^ 






R20 






R2I 




^^~ 
















o- 


CI2 


^_ 






RI9 






RI8 








o- 


Cll 


^^ 




^^^ 


RI6 






RI7 








o- 


CIO 


__ 






RI5 






RI4 




















o- 


C9 


^_ 




— ^ 


RI2 


o- 


C8 


RI3 






Rll 






RIO 








o- 


C7 


^^ 




— 


R8 


o- 


C6 


R9 






R7 






R6 








o- 


C5 


^^ 




^_ 


R4 






R5 








o- 


C4 


^_ 






R3 






R2 






R28 


o- 


C3 


"" Rl 








o- 


C2 














R27 





Pin 1 



Connector 
End 



Pin 47 



Cable Termination Module ZB52 
10433 IE 



a 


\a^^ 


RIAt LIST r— -« 
TlTt« B/Dl£ 




ImlI "^•- "•• 


ov 




^IDWO. 


J ••ffSMVirie 1 


••^* •"••■— I'^LI 


1043^1 


B 




• 
o 

• 


ASSEMBLY. P- W. CABL£ ' 


:B52 






m 
c 


TEUMHUATlOKlSCOTUi:^; -^ HOO # 2 


OATt 12/3 Mtn Z m Z 




ITf.H 


O^fk. TJTIK 


DVG.IIO, 


NQ.IIIQ 


MIURIS OH CKT. Ditia. 




1 


Eoard, Printed Wiring 


104330 


1 






2 
3 


Handle, Circuit Card 


100016 


I 






Eyelet, Tubular 


103896-016 


2 






-J 


4 


StriD. Marker 


100197 


1 






5 


Contact. Conn. Uoner 


100097 


23 








6 


Contact, Conn. Lower 


100098 


24 








-7 




100308-103 


M 


03 thru C16 






8 


Capacitor. Tantalum 


100312456 


1 -^ 

1-* 


CI, thru C14- 






9 


Resistor. Metal Film 


100680-330 


26 


Rl thru R2lk 






10 


Wire. Solid Bare 


100042-024 


1 in 








11 


Tubina, Teflon 


100274-022 


1 in 








1 n 














-+■«■ ■ 












13 


Heatsink (Extruded) 


106579 


1 








14 


Screw. :Flaf HH- Phillin. 100 


> lOOOll-iO-i 


2 








15 


Washer, Flat 


10001 8.30( 


2 








16 


Washer, Lock Int Tooth 


100024-30( 


2 








17 


Nut, Hex Machine 


100008-300 


2 




































































■ 












































' 


























































- 


























































« 


















I 




■k 
















^ 
























I 


», J 


' 




-.3 o- ^ ( 




2 


»OS-K- 


.10% 










—— 





TT- 



IQ4993lAi 



1. R3, R5 THRU R9, HII, RI4 THRU R33, 
R35, R40, R4I t R42 ARE OMITTED. 



n 



il 



A 



u 



< z 

z o 

cz 
u 



111 



O 
1 — 

J 



lo 



iulljl 



POLARIZING PINS: 12 t 40 



+4v/+8V 450- 

6R0UND 44C- 
lO 



;;a3 ?R4 ?R5 |b6 |r7 |fl« |r9 |riO |riI ?RIZ |rI3 ?RI4 |rI5 |rI6 |Rir |riB ?RI9 ?R20 |r2I 



66666666666666606000 

2 3 4 5 6 7 B 9 10 H 12 13 14 15 16 1/ 18 19 ZO 21 



|R23 ?R24 |r25 ?R26 |R27 fR28 |h29 |R30 |R3I |r32 ^R33 |r34 ?R35 |r36 |R3r |fl3S |r39 5r40 |r4I ?R42 ^R43 



66666666666666666 6,0 00 

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 



t *., 



C4 

.R2 

R4 

.R6 

.R8 

.RIO 

. RI2 

.RI4_ 

RI6 

. RI8 

.R20_ 
. R22_ 
.R24_ 
.R26_ 
.R28_ 
. R30_ 
.R32_ 
_R34_ 
. R36_ 
. R38_ 
. R40_ 
_R42_ 

C2 



Pin 1 



R3 

,R5 

,R7 

.R9 

Rll 

RI3 — 
.RI5 

RI7 

.RI9 

.R2I 

. R23 

.R25 

.R27_ 

.R29 

. R3I 

. R33 

.R35_ 

. R37 

_R39_ 
_R4I_ 
-R43_ 



-CI 



Connector 
End 



Pin 47 



Termination Module ZB55 
104994B 



a 


ti. 


NATf.ULLIST o/F^c. 


^ 




«e 


ML 


mi%. 99* 


Z2f 


" ASSY, P. W. ' ^— 

TERMINATION MODULE MOO # ZB 


eve eveve 


104994 


-; 


• 
: 




» eAn3/24 iHttr i ^ ^ \ 


ITfM 


ov«. Tiri>. 


OVO.IIO, 


PO.itQ 


•xiuui M cir. •liu. 


1 . 




J—- 
1 




ifiaAi« 


1 




io 




100014 


- I 




1 " 


3 


Xy«l*t, Tubul»r 


103896-016 


2 




_j 


4 


Strip, Marker 


100197 


I 




^ 


5 




1 00007 


23 






ft 


Contact. Conn Lower 


100098 


24 






7 


Capacitor, M'^ar 


100308-334 


3 


C2, 3. 4 




8 


Capacitor. Tantalum 


100312-156 


1 


CI 




« 




innni -Ml 


11 


n> a ift 1? 11 XA \t..V7.%fi 




10 


Wire, ^lid Bere 


100042-024 


13 in 






11 


Tubinf , Teflon 


100274-022 


13 in 




• 














































1 
























1 

i 




















; 














































.^ 



































- 
















— -■ 








■ 










; 




- — 










t 
1 






















1 






















■ 










































I- 


iOS-K 


• 151 











■N»^, 



113043 |a| 



U- 



I* 



o 

45 



'>'i 



t 



EI 



z 
.o 

ujtt 2 



.m!.I 
liiiili 



lo 



POLARIZING PINS-' 30 *. IB 



GROUND ««0~ 



66666666666666 

42 S9 36 33 ?7 » 2! 18 15 12 9 5 3 I 



C4 



R2 >R3 =t >R4 <R6 i >R6 ?R7 i >RB >R9 4= ?RIO >RII i ?RI2 SRI3 



6666666666666666666 

40 39 S« 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 



C7 



i" ^R,4^Rlsi^'° |ri6 ^RI7i^" ^R,8|R19i<^'=' ^R20^2l*Jf" ^REa^RZS^" |R24 |R25'4f"* |r26 W: 



-'-"■- >R28 



666666666 66666666666666 

21 20 19 IB 17 16 15 14 13 12 II 10 9 6 7 6 5 4 3 2 43 42 41 















R26 
















R24 


o- 


Cl 


— 


R25 










R23 


o- 


CI4 


— 


R22 






R20 


o- 


CI3 


— 


R2I 








o- 


CI2 


_~ 






^^ 


RI9 
RI6 


o- 


Cll 





RIB 

RI7 




^^^ 


















o- 


CIO 


^_ 




1 




RI5 








RI4 








o- 


C9 


_ 








RI2 
Rll 


o- 


C8 


^^■" 


RI3 

RIO 






R8 


o- 


C7 


— 


R9 








o- 


C6 


^^^ 






— 


R7 


o- 


C5 




R6 




^— 


R4 


o- 


C4 





R5 




— 


R3 


o— 


C3 





R2 







R28 








Rl 










o- 


C2 


^_ 












- 








— 


R27 


















- 





Pin 



Connector 
End 



Pin 47 



Cable Termination Module ZB73 
in 991 A 



i 


< 


f^TTTft.rSI MATERIAL LIST 




ML 


ONAwiNO NO. etv. 

Ill OO 1 A 




I 


■•iCMTirte OAT* cyaTCMs 

Asay, P. W. Cable 
»;*??•• Termination Module ZB73 


OAT^IJ 


/65 .«,„2 «^ 2 


rr«M 

NO. 


OnAWIMS TITLE 


BWO. NO. 


MO.IIM. 


aCMAIIKS ON CKT. osaio. 


= 


I 


Board. Printed Wirin£ 


104330 






{ 


Handle. Circmt Card 


loeou 






-J 


3 


Eve let. Tubular 


103896-016 






4 


StriD. Marker 


100197 




r 




? 


Contact. Conn. Upper 


100097 


23 






^ 




100098 


24 


' 




7 


Capacitor. Tantalum 


100312*156 


14 


CI thruC14 




1 


Kesiator. MeUl Film 


..OafiMlbllfl 


28 


Rl thruR28 




9 


Wire. Solid Bar* 


100042-024 


lin 






10 


Tubing, Teflon 


100274-022 


lin 








Heatai^( Extruded) 


I04S79 










Screw, rut Hd. PhUlipa °°'' 


100012-30' 










Waaher. Flat 


10001S-30( 










Waaher. Lock Int. Tooth 


100024-30( 










Nut. Hea Machine 


100008- 30( 










Schematic 


1 r3043 




ref 






OwM Liat 


113044 




ref 






Teat Spec 


11^045 




ref 














































































































































1 



























SDS-E-10SB