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UNIVAC ® CALCULATING TABULATOR 
PROCESSOR MANUAL 



SECTIONS: 4 &5 
APPENDIX: C 



COMPANY CONFIDENTIAL 

REGISTERED CIRCULATION 

The information contained in this manual is the property 
of the Sperry Rand Corporation and is Company Confidential. 
It is submitted in confidence and should not be disclosed 
to others unless so disclosed in confidence with the per- 
mission of Remington Rand Univac. Division of Sperry Rand 
Corporation, being first obtained. This copy is numbered 
and is so registered in your name in our records. The 
document is not to be reproduced or duplicated without 
express permission in writing from a duly authorized 
representative of the Sperry Rand Corporation. This 
manual is subject to recall. 



REMINGTON RAND UNIVAC 
DIVISION OF SPERRY RAND CORP, 
Philadelphia, Pa. 
March 1958 



SECTION IV 

TABLE OF CONTENTS 

Paragraph Title Page 

4-2 Basic Operation Cycle 4-1 

4-5 Search-for-Instruction Step, 4-2 

4-9 Locating the Memory Address 4-2 

4-20 Comparison and Head Selection 4-12 

4-40 Band Selection 4-16 

4-47 Staticize-Instruction Step 4-18 

4-52 Storing the p7 Digit 4-20 

4-54 Storing the Instruction Word 4-20 

4-55 Staticizing the Instruction 4-20 

4-58 Search-for-Operand Step 4-21 

4-61 Instruction Code Characteristics 4-21 

4-62 Locating the Operand 4-22 

4-67 Execute-Instruction Step 4-23 

4-70 Two-Execution-Step Instructions 4-23 

4-72 Timing of the Basic Operation Cycle 4-24 

4-74 Processing a Typical Instruction 4-24 

4-77 Search for Operand 4-32 

4-83 Execute the H(60) Instruction 4-33 

4-88 Memory Write Operation 4-34 

4-92 Arithmetic Operations 4-35 

4-93 Addition and Subtraction 4-35 

4-94 Add Instruction 4-35 

4-96 Al Step 4-36 

4-109 A2 Step 4-41 

4-112 Subtraction 4-41 

4-116 Sample Problems 4-42 

4-118 Addition 4-42 

4-120 Subtraction 4-43 

4-127 Multiplication 4-45 

4-135 General Description 4-46 

4-138 Detailed Description 4-47 

4-139 Ml Step 4-47 

4-144 M2 Step 4-50 

4-145 IER Phase 4-51 

4-150 IER Phase 4-51 

4-153 Division 4-52 

4-156 General Description 4-52 

4-175 Detailed Description 4-56 

4-176 Dl Step 4-57 

4-183 D2 Step 4-58 

4-184 OR Phase 4-59 

4-186 Complementing and Left Shift of rA 4-59 

4-187 Complementing and Left Shift of rX 4-59 

4-188 Complementing the LSD of rA 4-59 

4-190 Jam MQC * 4-62 

4-191 Initiate OR Phase 4-62 

4-192 OR Phase 4-62 



4-193 Addition 4-62 

4-194 End of D2 Step 4-63 

4-195 D3 Step 4-63 

4-196 Interchanging rA and rX 4-63 

4-199 Sign of the Quotient 4-65 

4-200 Error Circuits 4-65 

4-202 Memory-Check Flip-Flop 4-66 

4-206 Timing-Error Flip-Flop 4-67 

4-210 Cycling-Unit Error Flip-Flop 4-68 

4-213 Input-Output 4-68 

4-217 Manually-Controlled Operations 4-69 

4-220 One-Line Print 4-69 

4-226 One-Card RPU 4-71 

4-228 One-Card HSR 4-71 

4-230 One Instruction 4-71 

4-232 Comparison Stop 4-71 

4-235 Keyboard Input 4-72 

4-237 Manual Operation 4-72 

4-243 Depressing a Key 4-74 

4-246 Releasing a Key 4-75 

4-249 Signing and Releasing the Word 4-76 

ILLUSTRATIONS',, 

Number Title Page 

4-1 Search Step of Basic Operation Cycle 4-3 

4-2 Drum Quadrants 4-5 

4-3 Drum Quadrants under Fast-Access Heads 4-8 

4-4 Quarter Addition of QS2 FF Inputs 4-9 

4-5 Staticize Step 4-19 

4-6 Timing of Basic Operation Cycle 4-25 

4-7 Execute Step of H(60) Instruction 4-32 

4-8 Add Instruction 4-39 

4-9 Multiplication Process 4-48 

4-10 Multiply Instruction 4-49 

4-11 Division Process 4-54 

4-12 Dl Step of Division 4-57 

4-13 D2 Step, OR Phase 4-60 

4-14 D2 Step, OR Phase 4-61 

4-15 D3 Step 4-64 

4-16 Keyboard Input Operation 4-77 

TABLES 

Number Title Page 

4-1 Oddness and Evenness of Biquinary Combinations 4-7 

4-2 Head Selection 4-11 

4-3 Instruction Code Combinations 4-27 

4-4 Keyboard Encoder 4-74 



ii 



SECTION IV 
THEORY OF OPERATION 



4-1. Section II t by explaining the use of logical sym- 
bols and elements, enables the reader to interpret the 
logical circuitry of the processor. Section III, by 
describing the logical components of the processor, 
familiarizes the reader with the specific circuits 
encountered in this section, section IV, and in the 
Analysis of UCT Instructions manual. The purpose of 
this section is to apply the knowledge gained in the 
foregoing sections to actual computer operations in 
which more than just an understanding of the logical 
circuits is necessary. Types of instructions not de- 
tailed in this section are treated on the more general 
level in section V. All instructions are treated in 
complete detail in the Analysis of UCT Instructions 
manual. 

4-2. BASIC OPERATION CYCLE 

4-3. The basic operation cycle consists of the steps 
necessary to perform any instruction completely. All 
instructions require at least three basic steps. 
Instructions requiring only three steps are those in 
which no operand is involved, such as a simple register- 
to-register transfer. Most instructions, however, 
require four basic steps because of the need for an 
operand. For this reason, a basic operation cycle con- 
sists of four steps. In instructions requiring only 
three steps the third or search-f or-oper and step is by- 
passed. The four steps of the normal cycle, with the 
search for the instruction as the starting point, are: 

(1) Search for the instruction (Sc). 

(2) Staticize the instruction (Sz). 

(3) Search for the operand (Sc-m). 

(4) Execute the instruction (Ex). 

4-4. When an instruction is completed, an ending pulse 
is generated which clears the static register and starts 
the next cycle by initiating a search for the next in- 
struction in the program (search for the instruction). 



4-1 



When an instruction has been located on the drum it is 
read from storage by the read circuits and is stored in 
the static register and register C (rC) (staticize the 
instruction). If the instruction requires an operand 
another search is made for this quantity (search for the 
operand). When the operand is located, the first step 
of the instruction is executed (execute the instruction). 
Any further steps in the instruction are executed in order 
after the first execution step. At the completion of the 
execution of the instruction, an ending pulse is produced 
to start the sequence once more. 

4-5. SEARCH-FOR-INSTRUCTION STEP 

4-6. After an instruction has been completed a signal 
is applied to the ending pulse buffer of the static 
register. As shown in figure 4-1, the ending-pulse 
buffer generates the EP signal which is applied to the 
restore gates of the seven static-register flip-flops. 
The high EP signal restores all seven flip-flops to their 
barred outputs, which indicate bits at tllB of the 
execute step of the preceding instruction. The new out- 
puts of the static register drive the instruction decoder. 

4-7. Only the search (Sc) gateline of the instruction 
decoder is permissive to the bits. The search gate 
interprets the two O's in the two lowest-order bit posi- 
tions, STR1 and STR2, and generates the 1A function 
signal. Function signal (FS)-IA drives the function en- 
coder and generates function signals 1, 58+, 63 and 74. 
These four function signals and FS 1A control the search- 
f or-instruction step. 

4-8. In the search-f or-instruction step, the storage ad- 
dress specified by the c address in rC must be located, 
the specified band selected, and the memory-read circuits 
alerted to read the instruction word contained in the 
address. 

4-9. LOCATING THE MEMORY ADDRESS. In the search for a 
memory address the following must be determined: the word 
channel and drum quadrant containing the desired address, 
the proper band, and the read-write head which is to be 
energized to read the contents of the location. One of 
four heads must be selected in reading from a fast-access 
band. In normal access, however, only one head can be 



4-2 



Set 
Flip-Flop 

74 



DRUM 
MEMORY 




CP FF 



r 



Alert 
Input Gates 



Memory Address 



TIMING BAND 
READ CIRCUITS 



TS Signals 



M 
BUFFERS 



Pl,p2 



p3,M1 



c ADDRESS STORED BY 
PRECEDING INSTRUCTION 



plO p9 p8 p7 p6 p5 p4 p3 p2 p1 

1 1 1 r~ 



— i 1 r 

REGISTER C 
i i i i i i 



3 



c Address 



I I I 



m 



CT 



Alerts 

c Output 

Gates 



BUFFERS 



p1,p2 



P3 



58+) 

Blocks Input 
From rA 



FS1 FS58+ FS63 FS74 



I t I 



FUNCTION ENCODER 



FS1A 



INSTRUCTION DECODER 



i — r 



r 



STATIC REGISTER 



~1 







END OF 
PRECEDING INSTRUCTION 



ENDING 
PULSE 
BUFFER 



EP 



FF8 FF7 FF6 FF5 
T 



FF4 



FF2 



FF1 



l_ 



J 



INITIAL FORCE 
DECIMAL CARRY 



BINARY 

EQUALITY 

GATES 



COMPARATOR 



QUINARY 

EQUALITY 

GATES 



EQ 



_!_ 

TS 
FF 



TS 



I 



p4 



Step to SZ Step When Address Locoted * * 



J 



QUADRANT 

SELECTION 

FF1 



QUADRANT 

SELECTION 

FF2 



BAND 
SELECTION 
FLIP-FLOPS 

(p3) 



BAND 

SELECTION 

FLIP-FLOPS 

(p4) 



RTS 
CIRCUIT 



SWITCH 

SELECTION 

GATING 

MATRIX 



MEMORY 
SWITCHES 



READ FROM 

SELECTED 

ADDRESS 



READ 
CIRCUITS 



READ 
FLIP-FLOP 



* m ADDRESS IN SEARCH FOR OPERAND STEP 
** STEP TO EXECUTE STEP IN SEARCH FOR OPERAND STEP 



Figure 4-1. Search Step of Basic Operation Cycle 



4-3 



HEAD 
00 Address 019 



Address 169 




HEAO 



hMt* 
It 



Address 069 



Address 119 



Figure 4-2. Drum Quadrants 



4-5 



selected since there is only one head per track. In a 
search for an address, the bits of the four c-address 
digits stored in rC are used as follows: 

p4 p3 p2 pi 

x ^xxx ^xx \x; x^ocxx xxxxj 

I I > 

select one of j select 4 of 200 

25 bands | channels around 

I the drum 

select one 

of four channels, 

quadrants, and 

heads 

4-10. Because there are four heads spaced at 90 degree 
intervals around the drum in fast-access storage, it is 
necessary to theoretically divide the surface or circum- 
ference of the drum into quadrants. It is necessary to 
refer to quadrants in normal access because both types 
of access storage use the same circuits. One of the four 
fast-access heads must be energized to read or write at 
the time the quadrant containing the desired memory 
address is approaching that head t minimizing the time 
required to read from or write onto the drum. 

4-11. The pi digit and the three lowest-order bits of 
p2 partially represent the channel across the drum in 
which the correct address is found. If the complete 
address is 4469, pi represents the 9 digit. However, the 
3 lowest-order bits of p2 do not fully represent the 6 
digit; they merely show that the digit is either 1 or 6. 
Since addresses 000 through 199 are found within a band, 
the word can be in any one of channels 019, 069, 119, or 
169. These four possible combinations for the time sel- 
ection bits are shown in figure 4-2. The most signifi- 
cant bit (MSB) of p2 and the MSB and least significant 
bit (LSB) of p3 choose one of the quadrants, completing 
the selection of a channel and also selecting the head 
to be energized for reading. The remaining bits of digit 
p3 and the bits of digit p4 select the proper band. 



4-6 



4-12. Digit p2 of 4469 is 6 t l00l in biquinary code. The 
three lowest-order bits, 001, are common to both 1 and 6 
in biquinary code. Therefore if the MSB of p2 is a O f 
the address is either Oj.9, or 119; if it is a l t the 
address is either 069 or 169. In address 4469 the MSB 
of p2 is 1; therefore the address is in either quadrant 
01 or 11 (addresses 169 or 069) as shown in figure 4-3. 

Table 4-1. Oddness and Evenness of 
Biquinary Combinations 



P 3 



Biq 


uinary 


Code 


De 


cimal 


Even or 


Odd 3 


MSB 




LSB 


Equiva 


lent 


MSB 


LSB 
























and 





= 











1 




1 







and 


1 


= 1 








1 







2 







and 





= 








1 


1 




3 







and 


1 


= 1 


> 


1 










4 







and 





= 


1 













5 






and 





= 1 


1 








1 




6 






and 


1 


= 


1 





1 







7 






and 





= 


1 





1 


1 




8 






and 


1 


= 


1 


1 










9 






and 





=* 1 



= even; 1 = odd 

4-13. Address 069 has an even-hundreds digit; address 
169 has an odd-hundreds digit. The least-significant 
bit of p3 designates one of the two quadrants selected 
by the MSB of p2 . Selection is accomplished by combining 
the LSB of p3 with the MSB of p3 to ascertain the evenness 
or oddness of p3. 



4-7 




Figure 4-3. Drum Quadrants under Fast-Access Heads 



4-8 



S4 



n 1 



GATE 37A 




GATE 37B 



S4 1 

§1 






Ml 




GATE 37C 



S4 

§1 

Ml 

A 




S4 1 



GATE 37H 



S1 



Ml 



P- 






> 



A PRESENT (LOW) 



GATE 370 



S4 1 

Si 

M1 

A 



Zh 



GATE 37E 



S4 

Sf 

M1 

A 



D- 




1 



GATE 37F 



S4 

r« 

Ml 
A 



°~1— °— 1 

' 



S4 1 

SI 1 



D-o-i 



GATE 37G 



Ml 



A PRESENT (LOW) 



Figure 4-4. Quarter Addition of QS2 FF Inputs 



4-9 



4-14. This combination of the MSB and LSB of p3 is neces- 
sary because the least-significant bits of the biquinary 
code do not form a pattern by which the oddness or evenness 
of a digit can be determined. The first column of table 
4-1 shows that the LSB of p3 (0), if taken alone could 
indicate either an odd or even decimal digit. The last 
column shows that by combining the LSB and MSB of the 
combinations for each digit, a definite pattern is formed. 
When the combined bits equal 0, the digit is even? when 
they equal 1, the digit is odd. 

4-15. In the 4469 address digit, p3 is 0100 (4) which 
is an even-digit combination (0). Therefore digit p3 
signifies that the address is contained in a location 
having an even hundreds digit, such as 069, ,269, £69, 669, 
or 869. The MSB of p2 already has designated either the 
169 or 069 channel. The p3 digit, being even, specifies 
the 069 channel and therefore quadrant 01. 

4-16. The MSB of p2 and the LSB of p3, both of which 
determined the correct quadrant, also select one of the 
four heads in a fast-acces9 band. With the 000 address 
in a band under the 00 head, the four quadrants and four 
heads are as shown in figure 4-2. To determine the head 
to be energized, the MSB of p2 and the LSB of p3 from 
rC and the timing combination from memory are quarter 
added. Table 4-2 lists the possible combinations of these 
bits. The four conditions shown under table 4-2a refer to 
the drum position in figure 4-3a; that is, quadrant 00 is 
under head 00. The conditions under table 4-2b refer to 
the possible conditions when quadrant 01 is approaching head 
00. Similarly, table 4-2c and figure 4-3c show the possi- 
ble conditions when quadrant 10 is approaching head 00; 
table 4-2d shows the possible conditions when quadrant 11 
is approaching head 00. 

4-17. The cutaway view of the drum in figure 4-4a shows 
the conditions specified in table 4-2a. It must be remem- 
bered that the quadrant called for in the c address is 
represented by the two quadrant selection bits of rC, that 
is, the MSB of p2 and the LSB of p3. If the 00 quadrant 
is under the 00 head, as in all four cases of table 4-2a, 
and the 00 quadrant is called for by rC, combination of the 
two quadrants results in selection of the 00 head. If 
the desired address is X in quadrant 00, the 00 head must 
be selected as the drum rotates in a counterclockwise dir- 
ection. If the drum quadrants are in the same position 
and quadrant 11 is specified in the c address, the 01 head 
must be selected* 



4-10 



Table 4-2. Head Selection 



Timing Band 
Combinations 


c Address 


Head 
Selected 


Table 
Sect ion 


p3 p2 
Ml M4 


p3 p2 
SI S4 
S4 












00 







1 


11 


a 





1 


10 







1 1 


01 




1 





01 




1 


1 


00 


b 


1 


1 


11 




1 


1 1 


10 




1 





10 




1 


1 


01 


c 


1 


1 


00 




1 


1 1 


11 




1 1 





11 




1 1 


1 


10 


d 


1 1 


1 


01 




1 1 


1 1 


00 





4-11 



4-18. With any of the other three quadrants under the 
00 head, as in figure 4-3a, 4-3b and 4-3c, head selec- 
tion again depends on the quadrant to be read. For 
example, in figure 4-3c t the 10 quadrant is under the 
00 head. Therefore, if the 11 quadrant is to be read, 
the 11 head, which is most immediately in the path of 
counterclockwise rotation of the drum and quadrant 11, 
is selected. The same conditions in table 4-2c (last 
line) verify the head selected in figure 4-3c. 

4-19. Thus far, digits pi, p2 , and part of p3 have 
selected the proper memory channel, the quadrant con- 
taining the address, and one of four heads to be ener- 
gized in reading that address. Digit p3 and the three 
LSB's of p4 determine which of five fast-access bands 
contain the address. Digit p3 determines the third digit, 
the hundreds digit, of the address; the three lowest- 
order bits of p4 determine the fourth, or thousands digit 
of the address. A detailed explanation of the memory 
search process is given in paragraph 4-20. 



4-20. COMPARISON AND HEAD -SELECTION. The comparison 
operation (figure 4-1) begins with the comparison of the 
timing band channel addresses with the address contained 
in rC. As shown in the figure, the timing band signals 
enter the comparator on the M lines from the M buffers; 
the c-address signals from rC enter on the S lines from 
the S buffers, (Figure 4-1 and the logical diagrams in 
Appendix A are pertinent throughout this description.) 

4-21. Function signal 63 alerts the c-address output 
gates of rC. The gates are made permissive by the CT 
signal from the conditional transfer flip-flop (CT FF). 
The CT FF is restored to CT by the RCT outputs of the 
static register at the end of every search operation. 
Digits pi, p2, and p3 of the c address in rC are 
transferred, through the permissive output gates, to 
the S buffers. The p4 digit goes directly from rC to 
the band-selection flip-flops. The output signals of 
the four output gates of rC (figure A-l) are C12, C22, 
C32, and C42. The c address from rC can enter the S 
buffers and the S lines because FS 58+ has blocked the 
(rA) outputs which normally enter the S buffers. The 
pi and p2 digits of the c address are transferred on 
the S lines into the quinary and binary equality gates 
of the comparator. 



4-12 



4-22, Function signal 1 alerts the input gates of the 
M buffers from tO to t2B. The timing band combinations 
signals TS1 through TS4 from the timing-band read circuit 
enter the M buffers and the M lines, 

4-23. Function signal 74 sets the complement (CP) FF of 
the sign-and-control circuit to produce a complement (CP) 
signal for the comparison operation. The CP signal alerts 
the binary and quinary equality gates of the comparator. 
Function signal 74 also generates a CP5 signal from the 
CP FF for use in the comparison operation. The CP5 signal 
drives the initial force-decimal-carry circuit which 
generates the A and C decimal-carry signals. These signals 
alert the quinary equality gates and binary carry gates 
of the computer. 

4-24. The pi digits from rC and memory arrive on the M 
and S lines at time tlB. The quinary bits of pi (Ml, M2 t 
M3, and Sl t S2 t S3) are compared in the quinary equality 
gates of the comparator. Equality between the three M 
bits and the three S bits makes one of the eight gates 
permissive and causes a high output from one of the quinary 
equality gates. The high output goes to a non-complement- 
ing amplifier which produces a high EQ output at t2B. 



4-25. Before the comparison operation a 
previous word time the time selection fl 
(figure 4-1) was set. The set state of 
cates equality of the M and S bits. Ine 
M and S bits restores the TS FF t indicat 
timing-band address under the TS head at 
does not match the c address in rC. At 
the TS output is sampled to see whether 
obtained. Restoring the TS FF causes an 
cycle to be initiated at the time TS is 
flip-flop remains set, it indicates equa 
ing address bits with the c-address bits 
input gate_2l (figure A-12) restores the 
only when EQ is low at time t2B or t3B. 
low only when the quinary bits are unequ 
_a__low output from the quinary equality g 
EQ signal blocks input gate 21 to keep t 



t tllB of the 
ip-flop (TS FF) 
the TS FF indi- 
quality of the 
ing that the 

that instant 
various times 
a match has been 
other search 
sampled. If the 
lity of the tim- 

. The TS FF 

flip-flop to TS 
The EQ output is 
al t resulting in 
ates. The high 
he TS FF set„ 



4-26. The binary bits of pi also are compared in the 
binary equality gates of the comparator at the same time 
(tlB) as the quinary bits are compared. Equality of bits 
M4 and S4 in the gates alerted by CP produces a high out- 
put signal which is buffed into a non-complementing 



4-13 



amplifier to generate a high A* at t2B. This indication 
of equal binary bits goes to gate 20, an input gate of 
the TS FF. The high A 9 signal blocks the gate and the 
TS FF remains set, 

4-27, Inequality of M4 and S4 cause the binary equality 
circuit to produce a low output to the non complementing 
amplifiers. The output of the amplifiers is a low A* 
signal. Input gate 20 of the TS FF is permissive to low 
signals at time t2B, and the low A* signal restores the 
TS FF to indicate inequality, 

4-28, At time t2B, the quinary bits of digit p2 are 
compared for equality in the quinary equality gates. 
The comparison is accomplished in th e same manner as for 
the quinary bits of pi. The high EQ signal, indicating 
equality of the quinary bits of p2 9 occurs at t3B and 
keeps the TS FF set, 

4-29, The binary bits of digit p2, M4 and S4, are com- 
pared in the binary equality gates which are alerted by 
the low CP signal at t2B, 'Equality of the bits produces 
a high A* signal. The most significant bit of p2 indicates 
whether the desired address is above or below 50; it 
therefore contributes to quadrant selection. 

4-30, The high A 1 * signal goes to the quadrant selection 
1 flip-flop (QS1 FF) of the memory selection circuit 
(figure A-18), The signal blocks gate 3 3 o f the QS1 FF t 
keep ing the flip-flop restored to a low QS1 output. The 
low QS1 output indicates a in the LSB of the quadrant 
address: either 00 or 10, If the A* signal on gate 33 
is low at time St3B v the gate operates to set the flip- 
flop to a low QS 1 output. The QS1 signal indicates a 1 
in the LSB of the quadrant address: either 01 or 11. 
The QS1 FF output goes to the switch-selection gating 
matrix, 

4-31, Also at St3B t the input gates of the QS2 FF sam- 
ple the conditions which affect the selection of the MSB 
of the quadrant address. The output of the QS2 FF is the 
MSB of the two-digit head address shown in table 4-2, 

4-32. All of the input gates of QS2 FF logically quarter 
add their inputs. For example, gate 37E of the fHp-flop 
is permissive only to low signals ST, SI, Ml, and A 
(figure 4-4). The Si" and SI signals are the MSB and LSB 



4-14 



of the p3 digit. Quarter addition of these two bits 
produces a 1. The Ml signal indicates a 1 bit, and it 
is quarter added to the result of the quarter addition 
of S4 and SI bits. Quarter addition of a 1 bj,t (S4 t SI) 
to a 1 bit (Ml) again produces a bit. The A signal, 
which has a value of 1, is quarter added to the previous 
bit result to produce a final result of 1. The QS2 FF 
is, as a result, set to a QS2 output to select a quad- 
rant address with a MSB of 1. If either bit of the 
quadrant address selected by the quadrant selection 
flip-flops is a 1, the fast-access bands are involved. 
If the 00 quadrant is selected, normal access may be involved 

4-33. The low A signal has a value of 1 when the p2 
digit from the timing band is less than 5 and the p2 digit 
of rC is 5 or larger. The low A signal has a value of_0 
under all conditions except those associated with the A 
signal. Gates 28, 29 and 31 of the comparator (figure A-12) 
determine__f rom comparison of the MSB's of p2 whether the 
A or the A signal is low. If one of the inputs to each 
one of these gates is high, the A signal is low. This can 
occur only when the M4 bit* is a and the S4 bit is a 1. 
If this condition is not present, one of the gates is 
permissive to the low inputs, generating a low A signal. 
The low A signal is present when the MSB of the timing- 
band p2 digit is equal to the MSB of the rC p2 digit or 
if the MSB of the timing-band p2 digit is a 1 and the 
MSB of the rC p2 digit is a 0. 

4-34. The conditions necessary to set the QS2 FF to a 
QS2 (1) output are shown in figure 4-4. If none of the 
ei ght gates is permissive, the flip-flop is restored to 
a QS2 (0) output. The outputs of the QS1 and QS2 FF • s 
go to the memory switch selection matrix together with 
the outputs of the band-selection flip-flops. 

4-35. If the quadrant address selected by the outputs 
of QS1 FF and QS2 FF is 10, 01, or 11, the input gate 
which produced the 1 output (a high output is necessary 
for 1) also causes a high signal to go to amplifier 39 
to generate a low RTS signal. The low RTS signal goes 
to gate 22 of the TS FF (figure A-12). 

4-36 . Th e signals which make gate 22 permissive are low 
S3 and S4 which indicate 0*s in the S3 and S4 bit positions 
of p4. When S3 and S4 are 0, addresses 0000 through 3999 
(normal access) are involved; when S3 is 1, addresses 
4000 through 4999 (fast access) are involved. 



4-15 



4-37. If either of the quadrant selection flip-flops 
has, by generating RTS, indicated a fast-access head and 
the low S3 and S4 bits indicate a normal-access location, 
gate 22 (figure A-18) restores the TS FF. When the QS1 
and QS2 flip-flops select a 00 head, the RTS signal is 
high. The high RTS signal blocks gate 22, keeping the 
TS FF set so that the selected head can be energized to 
read or write, 

4-38. When the search operation is unsuccessful, a high 
TS signal is generated by the restored TS FF and sent to 
input gate 7 of static register flip-flop 1. 
The high input blocks the gate to keep the flip-flop set 
to a bit. The flip-flop cannot be stepped to a 1 bit 
output until the TS input is low at t5B or tlOB. 

4-39. During instructions H, X, and J f which involve 
writing on the drum because they are transfer-to-memory 
instructions, the TS signal is sampled at gate 8 of static- 
register flip-flop 1. A low TS signal indicates that the 
timing band combination matches that of the c or ra address 
in rC # 

4-40. BAND SELECTION. The final step in locating an 
address is the selection of the band specified by the p3 
and p4 digits in rC. The correct band is selected by 
digit p3 and the three lowest-order bits of p4. These 
seven bits indicate the hundreds and thousands digits of 
the address and whether the address is in fast- or normal- 
access storage. 



4-41. The band is selected by th 
flops. See figures 4-1 and A-18. 
these flip-flops is explained in 
3-227. The input gates of the ba 
flip-flops are alerted at St3B t t 
quadrant selection flip-flops are 
the three highest-order bits of t 
on the S lines. The S inputs to 
ate MS signals which indicate one 
addresses specified by the hundre 
Digit p3 specifies one of the fol 
000 through 199, 200 through 399, 
through 799, 800 through 999. Th 
circuits determine, at the same t 
of such a band address. 



e band sel 
The oper 
paragraphs 
nd selecti 
he same ti 

alerted, 
he p3 digi 
the p3 fli 

of five p 
ds digit o 
lowing ban 

400 throu 
e quadrant 
ime, a spe 



ect ion 
at ion 

3-224 
on p3 
me as 

At th 
t from 
p-f lop 
ossibl 
f the 
d addr 
gh 599 

selec 
cif ic 



flip- 
of 

through 
and p4 
the 
is time, 

rC are 
s gener- 
e band 
address, 
esses: 
• 600 
t ion 
quadrant 



4-16 



4-42. The band selection p4 flip-flops sample the two 
lowest-order bits of digit p4 to determine the thousands 
digit of the address. At time St3B f direct outputs of 
rC are sampled by the MS10 and MS20 flip-flops. The C 
signals are sent directly to the flip-flops without being 
delayed at the S buffers so that all of the band and 
quadrant selection operations are initiated at time St3B. 

4-43. The fast/normal flip-flop determines whether the 
desired address is in fast- or normal-access storage. 
At St3B # the third lowest-order bit of digit p4 is sam- 
pled by the input gates of the flip-flop. The C33 and 
C34 signals from rC indicate whether the desired address 
is in normal-access locations OOOO to 3999 or fast-access 
locations 4000 to 4999. For normal-access selection the 
flip-flop generates the NM signal; for fast-access selec- 
tion the flip-flop generates the FM signal. These sig- 
nals go to the switch selection matrix and to the read- 
write circuits to control reading and writing by fast- 
or normal-access heads. 

4-44. The outputs from all' the band selection and quad- 
rant selection circuits appear at the switch selection 
matrix at t4B. The clear-band selection circuit, which 
is explained in paragraphs 3-228 and 3-229 clears all 
of the band selection flip-flops and also the quadrant 
selection flip-flops if the pi and p2 digits are found 
to be unequal. 

4-45. If the search operation has located the correct 
address, as indicated by a low TS signal, FSl makes gate 
42A (figure A-19) of the read flip-flop permissive at 
t8B. The permissive gate sets the flip-flop, the output 
of which goes to gates 45A and 45B. One of these gates 
is made permissive at t9B by the FM or NM signal from 
the fast/normal selection flip-flop (figure A-18). If 
gate 45B is made permissive, the low RGF signal alerts 
the fast-access read output gates (figure A-20) to enable 
the instruction word in the specified fast-access storage 
location to be read from the drum onto the DM lines. If 
gate 45A is made permissive, a low signal (figure A-19) 
alerts the normal-access read-output gates to enable the 
instruction word to be read from normal-access storage onto 
the DM* lines. The instruction word thus is read from the 
memory to be stored in the static register and rC, during 
the staticize step. (See section 6-239, for a discussion 
of read circuits in detail.) 



4-17 



4-46, Paragraphs 3-231 through 3-234 explain switch 
selection and the operation of the memory switch circuits, 

4-47. STATICIZE-INSTRUCTION STEP 

4-48, The primary function of the staticize step 
(figure 4-5) is to store the two instruction digits of 
the instruction word so that they can control the execu- 
tion of the instruction. Other functions of the staticize 
step (SZ) are to store the entire ten digits of the 
instruction word in rC and to store the p7 digit of the 
instruction word in the mult iplier/quot lent counter. 
The word stored in rC f in addition to containing the 
two instruction digits, contains the storage address of 
the operand to be used in the instruction (m address) and 
the address of the next instruction word (c address). 
The p7 digit of the instruction word specifies the number 
of shifts necessary in a shift instruction and the number 
of the output stacker to be selected in the card reader 
in a select stacker instruction. It is stored in the 
MQC on every instruction so that no special preparation 
is necessary if a shift instruction is called for by the 
program. 

4-49. At tlOB of the search step, the output of the TS FF 
is sampled to make certain that the search step was success- 
ful. If the search was successful, the TS signal is low 
at gate 7 of STR FF1 (figure A-2) JL _ Function signal 1 alerts 
this gate which also samples the OF output of the overflow 
FF at tlOB of the search step. Because the conditions 
necessary to generate a high OF signal are explained in 
paragraph 3-143, it is sufficient to say here that the 
low OF signal indicates that no abnormal conditions are 
present. When gate 7 is permissive to these signals, it 
sets FF 1 to a low STR1 output, which indicates a 1 bit, 
and generates a high RCT1 signal which restores the CT FF 
(figure A-12), 

4-50, Every staticize step causes the CT FF to be restored 
to CT. This condition causes the c address to be read 
unless at a later time the CT FF is set to CT. As a re- 
sult, an instruction which requires an operand sets the 
CT FF at the end of the staticize step; otherwise the 
next search is for the c address. 



4-18 



INSTRUCTION WORD 

FROM MEMORY 

(DM Signals) 



M 
BUFFERS 



® 



RECIRCULATION 
GATES 



pt Through plO Digits 



INPUT 
GATES 



£ 



REGISTER C 



© 



CLEAR 

MQC 
CIRCUIT 



CLQ 



p7 Digit 



MQC 
FLIP-FLOPS 



FS2 FS2+ FS62 FS58 + 
AAA 



1 



FUNCTION ENCODER 



FS2A 



STOP 
FLIP-FLOP 



SP 



INSTRUCTION DECODER 



r 



FF8 



p9 ond plO Digits 



INPUT 
GATES 



S 



FF7 



FF6 



FF5 



FF4 



FF2 



l i A I A A n 

■i i i • 1 i i 



~] 



FF1 
J — f 



TS 

id ( 

\Seorch Step 



/ End of \ 

i- . _. ^ 



I STATIC R 



STATIC REGISTER 



J 



Figure 4-5. Staticize Step 



4-19 



4-51. When FF1 is set to a 1 output (figure 4-5), the 
input to the instruction decoder is OOOO 0X01, since 
only that flip-flop has changed. The decoder converts 
this combination into FS 2A, which drives the function 
encoder to generate function signals 2, 2+, 62, and 58+. 
These signals control the functions of the staticize step. 

4-52. STORING THE p7 DIGIT. Before storing the p7 digit 
in the four flip-flops of the MQC, the flip-flops must 
be cleared of previous information. At tOB of the static- 
ize step, FS 62 at gate 19 of the clear-MQC circuit 
(figures 4-5 and A-14) generates the CLQ signal. The CLQ 
signal restores the four flip-flops to at gates 5 f 6 t 
7, 8. 

4-53. Function signal 2 alerts the input gates of the 
flip-flops at t7B f the time interval during which digit 
p7 is on the M lines. The four bits of digit p7 enter 
the flip-flops to be stored for future use if the 
staticized instruction is a shift or select stacker 
instruction. 

4-54. STORING THE INSTRUCTION WORD, At tOA of the 
staticize step, the pO digit of the instruction word from 
memory is present on the DM or*DM f lines of the read- 
output circuits (figures A-19 and A-20). These signals 
go directly to the M buffer and are on the M lines at 
tOB. Function signal 2+ blocks the recirculation gates 
of the four subregisters of rC at tllB+ of the search 
step, clearing the register. Thus, at tOB of the 
staticize step, the pO digit of the instruction word 
enters the permissive input gates of rC. Function signal 
2 alerts the input gates to the digits of the instruc- 
tion word on the M lines. 

4-55. STATICIZING THE INSTRUCTION. Once they have per- 
formed their functions, the function signals generated 
by the staticize step must be removed. At t8B of the 
staticize step, FS 2 is low at gate 114 of the static 
register (figure A-2). This restores STR FF1 to a 
output, which causes the function signals of the staticize 
step to be lost at tllB. 

4-56. At t9B the p9 digit of the instruction word is 
present on the H lines as shown in figure 4-5. Function 
signal 2 alerts the input gates of FF1, FF2, and FF4 at 
t9B so that the p9 digit can enter. (Only three bits of 
the p9 digit are of use in the processor.) To make certain 



4-20 



that no function signals are generated in the one pulse 
time between the time digit p9 is staticized (t9B) and 
digit plO is staticized (tlOB), the high SP signal blocks 
the instruction decoder for one pulse time. At t9B, 
function signal 2 sets the stop flip-flop ; gate 20 of 
the stop fHp-flop generates a high SP signal (figure A-5). 
The high SP signal blocks the instruction decoder. 

4-57. At tlOB, the plO digit is present on the M lines. 
Function signal 2 also alerts the input gates of flip- 
flop 5, flip-flop 6 t flip-flop 7 and flip-flop 8 at tlOB 
so that the plO digit can enter. By tllB the two instruc- 
tion digits are completely staticized in the static 
register. Function signals required to execute the 
staticized instruction are available from the instruction 
decoder at tOA, and from the function encoder at tUB. 

4-58. SEARCH-FOR-OPERAND STEP 

4-59. In the search for an operand step, the memory 
address designated by the m address of the instruction 
word is searched for in the same manner as in the search- 
f or-instr uct ion step. When located, the operand is read 
from memory in time to be used in the execution step of 
the instruction. In some instructions, the m address does 
not contain an operand. It may instead contain one of 
the following: a location in memory to which information 
must be transferred, the number of shifts in a shift 
instruction, a stacker number in a select-stacker instruc- 
tion, or the number of lines to be advanced in the print 
instruction. 

4-60. The search-f or-oper and step is not required for 
all instructions. It is necessary only in instructions 
which require one of the following: an operand from 
memory, a memory location to be read from or written 
onto, shift instructions, or select-stacker instructions. 
The arithmetic instructions require an operand as do the 
instructions which transfer information from or to memory. 

4-61. INSTRUCTION CODE CHARACTERISTICS. Instructions 
requiring operands can be identified by their instruction 
code. When the LSD (digit p9) of a staticized instruction 
is a decimal or 5, a search for operand step is necessary 
The two lowest-order bits of decimal and decimal 5 are 
00. The 00 bits indicate to the control unit that the 
memory location designated by the m address of the in- 
struction word in rC either contains an operand or is 



4-21 



the location into which information is to be transferred. 
The least significant digits of instructions which do 
not involve an operand or storage location are other than 
or 5; therefore the two lowest-order bits of such in- 
structions are not 00 t but 01 or 10. Table 4-3 shows 
the characteristic codes of instructions requiring a 
search-f or-operand step. 

4-62. LOCATING THE OPERAND. The search process required 
to locate an operand in memory is identical to the search- 
f or-instruct ion process. Control of the operand search, 
however, differs from control of the instruction search. 
Figure 4-1 is also a block diagram of the search-for- 
operand step. Differences between the instruction search 
and operand search in the figure are indicated by the 
notes. In locating an instruction, the c address in rC 
is compared with the timing band addresses; in locating 
an operand, the m address in rC is compared with the 
timing band addresses* 

4-63. Although FS 63 alerts both the m-address output 
gates and the c-address output gates of rC, the CT FF 
determines which address is to be read out and compared. 
When an instruction is staticiz.ed, the output of STR FF2 
determines whether an operand is necessary. Table 4-3 
shows that the STR2 position of the staticized instruc- 
tion is always when a search for operand is required. 

. ■ "nil 

4-64. The STR2 output of the static register is sampled 
by gate 12 of the CT FF (fig ure A-12) at tlOB of the 
staticize step. If the STR2 signal is low, indicating 
that a search must be made for the m address, the gate 
is permissive. When gate 12 is permissive the CT FF is 
set to CT, which controls readout of the m a ddre ss from 
rC. When gate 12 is blocked by high signal STR2, the 
CT FF is restored to CT, which controls readout of the 
c address. The staticized instruction, however, has 
generated new function signals for executing the instruc- 
tion so that the CT signal has no effect on rC until after 
the execution step. 

4-65. The CT output of the CT FF is available at the m- 
address output gates of rC at tOB. The LSD of the m 
address, p5, goes from rC to the S buffers and the S lines 
and is available at the quinary and binary equality gates 
of the comparator (figure A-12) at tlB. The comparison 
and memory selection processes for the search-f or-operand 
step are the same as those of the search-f or-instruct ion 
step, (paragraph 4-5). 

4-22 



4-66. The H t X, and J transfer instructions require a 
search-f or-operand step t but the operand is a memory 
location into which information must be written. Because 
these three instructions entail writing in the memory, 
time must be allowed for the write circuits to be prepared 
For this reason, the H t X, and J instructions generate 
FS 3 for use in the search operation in addition to the 
normal search (Sc) function signals* Function signal 3 
alerts gate 8 of STB FF1 to sample the TS signal at t5B. 
(In normal search, the TS signal is sampled three pulse 
times later, at t8B.) Sampling at t5B allows the write 
circuits to prepare for writing by the time the execute 
step begins. If the TS signal is low at t5B t the STR FF1 
is set to a 1, initiating the execute step of the instruc- 
tion stored in the static register. 

4-67. EXECUTE-INSTRUCTION STEP 

4-68. The execute-instruction step is initiated when the 
seven bits of the two instruction digits are staticized 
in the static register and either of the two lowest-order 
bits of the p9 digit is a 1 ( search-f or-operand step is 
unnecessary), or when the search for-operand step has 
been completed and the STR FF1 has been stepped to a 1 
output. In both cases the combination of bits stored in 
the STR represents a specific instruction and can be 
decoded by the instruction decoder. The combination in 
the static register goes to the instruction decoder and 
function encoder to generate one or more function signals 
which execute the staticized instruction. 

4-69. The Analysis of UCT Instructions manual lists the 
function signals generated for each instruction and the 
purpose of each of these signals. Sections 4-74 through 
4-199, and the input-output manuals explain the details 
of the execution steps of typical instructions. The 
instructions not covered in detail in these sections and 
the input-output manuals are treated in functional block 
diagram form in Section V. 

4-70. TWO-EXECUTION-STEP INSTRUCTIONS. Many instructions 
involve two execution steps. The add instruction (70), 
for example, adds two quantities in the first execution 
step and complements if necessary the sum of the addition 
in the second execution step. The function signals 
generated for the first step (Al) of the add instruction 
include FS 64. At tlOB of the Al step FS 64 at the 
stepping gate of the STR (figure A-2) restores FF1 and FF2 



4-23 



Flip-flop 1 had been previously set to a 1 to accomplish 
the Al step. Setting FF2 to a 1 output sets up the com- 
bination in the static register for step A2 ; as a result, 
a new set of function signals is generated to control 
the A2 step. The stepping gate similarly controls FF1 
and FF2 during many other instructions* 

4-71. Table 4-3 shows the code combinations for the 
steps of all UCT instructions. The table is divided into 
instructions which require only one execution step and 
those which require more than one. It is subdivided 
further into instructions which require a search-for- 
operand step and those which do not. The third column, 
STR code, lists the code combinations for each step 
of each instruction after it has been staticized in the 
static register. The code positions marked by X are 
bits which are unnecessary to the staticize step. The 
X in the LSD - STR3 position is included only to balance 
each combination with the eight bits of the biquinary 
code. 

4-72. TIMING OF THE BASIC OPERATION CYCLE 

4-73 The four steps of the basic operation cycle re- 
quire a minimum of four word times to complete. In- 
structions requiring no search-f or-operand step* take 
only three word times,, Instructions with more than 
one execution step require more than four word times. 
The timing of the basic operation cycle with and with- 
out a search for operand step is shown in figure 4-6. 
The timing of the various operations of the search- 
for-operand step is identical to that of the search- 
f or-instruction step. Therefore the search-for- 
operand step shows only the timing of operations 
unique to it. Although many other operations occur 
during each word time t only the ones necessary to ex- 
plain the timing of the whole cycle are included* 

4-74. PROCESSING A TYPICAL INSTRUCTION 

4-75. This section applies the previously discussed 
details of the basic operation cycle to the proces- 
sing of an actual instruction. In the search-for- 
instruction step, the operation of the memory read 
circuits was explained* Use of the H(60) instruction 
in this section permits explanation of the memory 
write circuits because the instruction requires a 
transfer of information in a register to a storage 
location* 

4-76. In the search-for-instruct ion step t the H(60) 
instruction was located in the memory. In the stati- 
cize step the instruction word was stored in rC t and 

4-24 



PREVIOUS 
INSTRUCTION 



SEARCH FOR INSTRUCTION STEP 




t6 



EP GENERATED 

STR CLEARED TO ZEROS 

SC FS (JA) GENERATED 

TS FF SET 

SC FS GENERATED 

pi LEAVES rC 



p1 ON M AND S LINES 

p2 ON M AND S LINES 



p3 ON M AND S LINES 
p4 ON C LINES 



BAND CHANNEL 
AND QUADRANT SELECTED 



SELECT NORMAL MEMORY SWITCH 

SELECT FAST MEMORY SWITCH 

SAMPLE TS WHEN WRITING 



t7 



t8 




t3 



pO OF INSTRUCTION ON DM LINES 
SZ FS (2/J) GENERATED 



SZ FS GENERATED 
pO OF INSTRUCTION WORD ENTERS rC 



READ FF SET 



SAMPLE TS 
WHEN READING 



STEP STR FF1 TO 1 
INITIATE STATICIZE STEP 



CLQ 
GENERATED 



MQC CLEARED 



STATICIZE STEP 



t4 



t5 



t6 



p7 ENTERS MQC 



to 

A | B 

m 

TED I 



SC FS (1A) GENERATED 

CT FF SET 
SC FS GENERATED h~ 
READ m ADDRESS OUT OF rC 




plO ENTERS STR 
SP HIGH 



INSTRUCTION DIGITS STATICIZED 



A PHASE FS GENERATED 
TO EXECUTE INSTRUCTION 



B PHASE FS GENERATED 
TO EXECUTE INSTRUCTION 



t2 



t2 



SEARCH FOR OPERAND 



t3 



14 



t5 



t6 



REPEAT SEARCH FOR INSTRUC 



EXECUTE INSTRUCTION 



t3 t4 



t5 



t6 



EP GENERAT 



Figure 4-6, Timing of Basic Operation Cycle 



R INSTRUCTION STEP 



t5 

'M 



t6 



ITCH 
ITCH 
TING 



t7 



t8 




STATICIZE STEP 



t3 



t4 



pO OF INSTRUCTION ON DM LINES 
SZ FS (2/5) GENERATED 



SZ FS GENERATED 
pO OF INSTRUCTION WORD ENTERS rC 



READ FF SET 



SAMPLE TS 
WHEN READING 



STEP STR FF1 TO 1 
INITIATE STATICIZE STEP 



CLQ 
GENERATED 



MOC CLEARED 



t5 



t6 



p7 ENTERS MOC 



SEARCH FOR OPERAND STEP 



SC FS (1A) GENERATED 

C F 
>RE 

/ 



to 

A | B 

m 

rED I 



CT FF SET 

SC FS GENERATED 

READ m ADDRESS OUT OF rC 




p9 ENTERS STR 



plO ENTERS STR 
SP HIGH 



INSTRUCTION DIGITS STATICIZED 



A PHASE FS GENERATED 
TO EXECUTE INSTRUCTION 



B PHASE FS GENERATED 
TO EXECUTE INSTRUCTION 



t2 



t3 



t4 



t5 



t6 



t7 



18 



t9 



tlO 



HI 



REPEAT SEARCH FOR INSTRUCTION STEP 



to 

A | B 

wM 



EXECUTE 
STEP 



pO OF OPERAND ON DM LINES 

pO OF OPERAND ON M LINES 















EXECUTE INSTRUCTION STEP 










to 


ti 


t2 


t3 


t4 


t5 


t6 


t7 


t8 


t9 


HO 


t11 


\ 


ij 


i 




















% 





INITIATE SEARCH 
FOR NEXT 
INSTRUCTION 



EP GENERATED ON MOST INSTRUCTIONS 
EARLIER ON ALL OTHERS 



Figure 4-6, Timing of Basic Operation Cycle 



4-25 



Table 4-3* Instruction Code Combinations 



INSTRUCTIONS WITH ONE EXECUTE STEP (SEARCH) 



Instruction 



Biquinary 



STR Code 



Steps 



05 (Y): (m) 



rX 



10 



S S S S S S S 

T T T T T T T 

R R R R R R R 

8 7 6 5 4 2 1 



XXXX XXOO 
1X01 



(Sc 00) 
(Y 06) 



20 (P): Superimpose (m) and 
(rA) > rA 



10 



XXXX XXOO 
0X10 0X01 



(Sc 00) 
(P 21) 



25 (B): (m) >rA 



10 10 



XXXX XXOO 
0X10 1X01 



(Sc 00) 
(B 26) 



30 (L): (m) 



-> rL 



11 



XXXX XXOO 
0X11 0X01 



(Sc 00) 
(L 31) 



35 (E): Logically multiply 

(ra) and (rA) — > rA 



11 10 



XXXX XXOO 
0X11 1X01 



(Sc 00) 
(E 36) 



50 (J): (rL) > ra 



1000 0000 



10 0X00 
10 0X01 



(J-Sc 50) 
(J-Ex 51) 



60 (H): (rA) > m 



10 1 



1X01 XXOO 
1X01 0X01 



(H-Sc 60) 
(H-Ex 61) 



65 (X): (rX) > m 



10 1 10 



1X01 XXOO 
1X01 1X01 



(X-Sc 65) 
(X-Ex 66) 



4-27 



INSTRUCTIONS WITH ONE EXECUTE STEP ( NO SEARCH) 



Instruction 


Biquinary 


STR Code 


Steps 


12 (G): RR >UCT 

(rA) + (rX) >rA 


0001 0010 


S S S S S S S 
T T T T T T T 
R R R R R R R 
8 7 6 5 4 2 1 

0X01 0X10 


(G 12) 


17 (R): OCT >RR 


0001 1010 


0X01 1X10 


(R 17) 






47 (Z2): Select output 
stacker of 
fast reader 


10 10 10 


10 1X10 


(Z2 47) 


67 Stop 


10 1 10 10 


1X01 1X10 


(Stop 67) 


72 (CC): Feed one card 
fast reader 


10 10 10 


1X10 0X10 


(CC 72) 


77 (K): (rA) >rL 


1010 1010 


1X10 1X10 


(K 77) 


82 (Q): (rA) : (rL) 

If (rA) = (rL) t go to m 
If (rA) ^ (rL) t go to c 


1011 0010 


1X10 0X10 


(Q 82) 


87 (T): (rA) : (rL) 

If (rA) > (rL), go to m 
If (rA) < (rL), go to c 


10 11 10 10 


1X11 1X10 


(T 87) 



4-28 



INSTRUCTIONS WITH TWO OR MORE EXECUTE STEPS (SEARCH) 



Instruction 


Biquinary 


STR Code 


Steps 


55 (D): (m) * (rL) — >rA 


1000 1000 


S S S S S S S 
T T T T T T T 
R R R R R R R 
8 7 6 5 4 2 1 

XXXX XXOO 

10 1X01 

10 1X11 

10 1 1X11 


(Sc 00) 
(Dl 56) 
(D2 58) 
(D3 68) 




70 (A) : (m) -t- (rA) — >rA 


10 10 


XXXX XXOO 
1X10 X X 1 
1X10 X X 1 1 


(Sc 00) 
(Al 71) 
(A2 73) 


75 (S): (rA) - (in) — >rA 


1010 1000 


XXXX XXOO 
1X10 X X 1 
1X10 X X 1 1 


(Sc 00) 
(SI 76) 
(S2 78) 


85 (M): (m) x (rL) — >rA+rX 


1011 1000 


XXXX XXOO 
1X11 1X01 
1X11 1X11 


(Sc 00) 
(Ml 86) 
(M2 88) 



4-29 



INSTRUCTIONS WITH TWO OR MORE EXECUTE STEPS (NO SEARCH) 



Instruction 


Biquinary 


STR Code 


Steps 


11 (PR1): memory — >print buffer 


1 1 


S S S S S S S 
T T T T T T T 
R R R R R R R 
8 7 6 5 4 2 1 

0X01 X X 1 

0X01 X X 1 1 


(PR1 11) 
(PR2 13) 


16 (PF1): paper advance 


1 10 1 


0X01 X X 1 
0X01 XX11 


(PF1 16) 
(PF2 18) 


22 (111): Test read punch unit 
card buffer 

If loaded, go to ra 

If not loaded, go to c 


0010 0010 


0X10 0X10 
0X10 X X 1 1 


(111 22) 
(112 23) 


27 (121): If printing or paper 
feeding, go to c 

If not printing or 
paper feeding, go to m; 
(rC) > rA 


10 10 10 


0X10 1X10 
0X10 X X 1 1 


(121 27) 
(112 28) 


32 (N): Right circular shift 

|rA| >rX; 

|rX| >rA n places 


11 10 


0X11 X X 1 
0X11 0X11 


(Nl 32) 
(N2 33) 


37 (V): Left shift rA n places 
Lose MSD 
Replace LSD with 


11 10 10 


0X11 X X 1 
0X11 1X11 


(VI 37) 
(V2 38) 


42 (131): Test card buffer fast 
reader 

If loaded, go to m 

If not loaded, go to c 


10 10 


10 0X10 
0X10 X X 1 1 


(131 42) 
(112 23) 



4-30 



INSTRUCTIONS WITH TWO OR MORE EXECUTE STEPS (NO SEARCH) (cont) 



Instruction 


Biquinary 


STR Code 


Steps 


46 (Wll):Read punch unit 
card buffer — > 

main memory 


OlOO 1001 


S S S S S S S 
T T T T T T T 
R R R R R R R 
8 7 6 5 4 2 1 

10 1X01 
10 1X11 


(Wll 46) 
(W12 48) 


62 (2S1): Zero suppress 
Rem Rand word 
in rA 


10 1 10 


1X01 0X10 
1X01 0X11 


(2S1 62) 
(252 63) 


81 (W21): Start read punch unit 

and main memory — > 

Read punch unit card 
buffer 


10 11 1 


1X11 0X01 
1X11 0X11 


(W21 81) 
(W22 83) 


96 (W31): Fast reader card 
buffer main memory 


110 10 1 


110 1X01 
110 1X11 


(W31 96) 
(W32 98) 



4-31 

















































rA 
SIGN FF 


















WRITE 
INPUT GATES 














1 


M Lines 








PHASE 

MODULATION 

CODER 








READ- 
WRITE 
HEADS 






— . h 


M 
BUFFERS 










WRITE 








AMPLIFIERS 








i 


CHECK BIT 
CIRCUIT 




Alert 
























WRITE 
FLIP-FLOP 




( 




Set 












♦ 


k 












FUNCTION ENCODER 






i 










Disconnect 


READ 
AMPLIFIERS 






® 








INSTRUCTION DECODER 






1 








1 








1 




STATIC REGISTER # 




1 


r 






t 


i 




EP 


ENDING 

PULSE 

BUFFER 




















































SIM 



Figure 4-7. Execute Step of H (60) Instruction 

the two instruction digits, 60, were staticized in 
the static register* In the H instruction the con- 
tents of rA must be transferred to a memory location* 
The address of that location is the operand in the 
instruction. The execute step of the H instruction 
controls the writing of the word from rA into the 
specified memory location on the drum* 

4-77. SEARCH FOR OPERAND 

4-78. The H(60) instruction is staticized in the 
static register flip-flops by the staticize step as 
1001 0X00. The two lowest-order bits of the p9 digit 
are O's, indicating a search. This combination is 
picked up by the H-X-J-Sc and Sc gate lines of the 
instruction decoder and generates FS 1A and FS 3A* 
(The search steps of the H t X f and J instructions re- 
quire the same function signals; therefore* all are 
on a common instruction decoder gate line*) 



4-32 



4-79„ Function signal 1A generates FS 58-f, FS 74, 
FS 63 and FS 1« Function signal 58+ blocks readout 
from rA onto the S lineso Function signal 74 sets 
the CP FF to produce a CP signalo Function signal 63* 
in conjunction with the CT signal* causes readout of 
the m address from rC onto the S lines* Function sig- 
nal 1 alerts the input gates of the M buffer to enable 
the timing band signals from the drum to enter the M 
lines. 

4-80. The 1001 0X00 STR output combination also gen- 
erates FS 3A (H-X-J Sc gate) which generates FS 3 to 
alert the STR FF1 stepping gate. At t5B of the search- 
for-operand step t the output of the TS FF is sampled 
by gate 8 of FF1. A low TS signal and FS 3 make gate 8 
permissive and step FF1 from a output to a 1 output. 
The new STR output combination of 1001 0X01 (61) is 
present at the instruction decoder at t6B. 

4-81* At t6B, FS 3 sets the write FF (figure A-19) 

at gate 5B to prepare the write circuits for the execute 

step of the instruction. 

4-82. When gate 8 of STR FF1 is permissive at t6A, a 
high RCT2 signal is generated which goes to the input 
gates of the CT FF and to buffer 104 of the write cir- 
cuits. The hic^h RCT2 signal restores the CT FF, gener- 
ating the low CT signal which controls readout of the 
c address from rC and generates the write pedestal 
(paragraph 6-243). The new STR combination causes the 
function signals for search to end at t7A. The search- 
for-operand step has located the operand, which is the 
storage location designated by the m address* 

4-83. EXECUTE THE H(60) INSTRUCTION 

4-84. In the execute step of the H(60) instruction 
(figure 4-7) t the contents of rA is recorded in the 
storage address located by the search-for-operand step. 
During the execution step, certain function signals are 
generated by the new combination in the static register. 
These signals control the transfer of the contents of 
rA onto the M lines and into the memory write circuits, 
the preparation of the write circuits to record on the 
drum, and eventually the ending of the instruction. 

4-85. At t7A of the search step the H gate line of the 
instruction decoder generates FS 11A which generates 
FS 11 and FS 21. These signals control the writing of 
the contents of rA onto the memory drum. 



4-33 



4-86. Function signal 11 alerts input gates 7A, 7B, 
7C, and 7D of the M buffers (figure A-6) . These gates 
are permissive to the four bits of the pO digit (AIM* 
A2M, A3M, and A4M) from rA at t7B t and the contents of 
rA enters onto the M lines* Gate 6 of the M buffers* 
also alerted by FS 11, also is permissive at t7B to a 
low A- signal. This condition indicates that the sign 
of the contents of rA t which has been stored in the rA 
sign flip-flop, is minus* If the sign of rA is plus* 
low A- is absent from gate 06. The sign position of 
the word (t7B) on the AIM lines contains 0, indicating 
a plus sign* The word and its sign are sent from rA 
onto the M lines and into the write circuits (figures 
A-19 and A-20) ♦ 

4-87* At t4B of the execute step FS 21 operates gate 
19 of the static register to generate the EP and Reset- 
TS signals* Because the H, X, and J instructions in- 
volve writing on the drum and therefore require less 
time for execution than most instructions, the EP 
signal is generated early* The function signals for 
the instruction are lost at t7B* The TS FF is restored 
so that the set output of the flip-flop, TS* cannot 
set the read flip-flop. Normally, at t8B, the read 
flip-flop (figure A-19) is set by FS 1, TS and OF. 
All these signals will be present at t8B because the 
function signals for search, will be available at t7B. 
To keep the read flip-flop restored until reading is 
required, the Reset-TS signal restores the TS FF, keep- 
ing the TS signal high. High TS blocks gate 42A of 
the read flip-flop, keeping it restored. The zero 
combination in the STR initiates a search for the next 
instruction. 

4-88. MEMORY WRITE OPERATION 

4-89. During a write operation, information and check 
bits are sent on the M lines to the phase-modulation 
coder where each input signal is coded into a phase- 
modulated pulse representation for memory recording. 
The resulting pulse is amplified in the write amplifier 
and drives the write heads. 

4-90. At t7A t FS 11A electronically disconnects the 
read amplifiers from the write circuits by generating 
the write pedestal (paragraph 6-243). Control signal 
RCT2, present for only one pulse time, has generated 
the write pedestal from t6A until t7A. For writing on 
the fast-access bands the IR output of the write- 
pedestal generator disconnects the read amplifiers of 
the fast-access heads. 



4-34 



4-91. The bits of each digit to be written are sent 
in parallel to the check-bit circuit and to the write 
input circuits* The check-bit circuit is explained in 
paragraph 4-202? Each of the four bits of the digit 
to be written is delayed a pulse time by two comple- 
menting amplifiers before going to the input gates of 
the phase-modulation coder, so that the check bit, 
and the information bits can be written simultaneous- 
ly. Computing the check bit requires a full pulse time. 
At t9B the information bits and a check bit are present 
at the input gates to the phase-modulation coder. The 
write flip-flop output alerts the input gates at t8B 
and for a full word time thereafter. The operation of 
the phase-modulation coder is explained in paragraphs 
3-208 through 3-212. The bits are converted into a 
phase-modulated waveshape which goes directly to the 
read-write heads and is written on the drum in the 
location specified by the m address. 

4-92. ARITHMETIC OPERATIONS 

4-93. ADDITION AND SUBTRACTION 

4-94. ADD INSTRUCTION. The functions of the add in- 
struction are: add algebraically the quantity in the 
storage location designated by m to the contents of 
rA t store the result in rA, compute the sign of the 
sum and store the sign in the rA sign flip-flop. The 
quantity in the memory is the addend; the quantity in 
rA is the augend. 

4-95. Before addition takes place: 

(1) The search for the instruction has been 
completed. 

(2) The add instruction (70) has been staticized. 

(3) The staticized instruction has initiated a 
search for the operand (m address), which 
in this instruction is the addend. 

(4) The augend has been stored in rA by a pre- 
vious instruction and its sign has been stored 
in the register A sign flip-flop. The add 
instruction requires two execution steps, 

Al and A2. 



4-35 



4-96. A-l STEP. In the first step of addition, Al, (figure 
4-8a) , the signs of the augend and addend are compared at the 
input gates of the CP FF. The gates determine from the 
two signs whether the augend is to be complemented (CP) 
or not complemented (CP) before addition. This infor- 
mation controls the complementing circuit of the quin- 
ary adder. The sign of the augend is compared with 
the CP output of the complement flip-flop at the input 
gates of the rA sign flip-flop to determine the sign 
of the sum. Once determined, the sign of the sum is 
stored in the rA sign flip-flop. The augend in rA is 
sent on the S lines into the binary and quinary adders. 
The addend from the memory location designated by the 
m address is sent on the M lines into the binary and 
auinary adders. The adders add the two quantities digit by digit 
and transfer the sum on the £ lines into rA . 

4-97. The staticized digits of the Al step (71) gen- 
erate function signals 4, 50, 55+ t 64 f and 75 at tOB to 
execute the Al step. Function signal 4 alerts the 
input gates of the complement (CP) FF. Gates 8 and 9 
of the CP FF (paragraph 3-138) operate during the add 
instruction to sample the signs of the two quantities. 
If the signs are unlike, one of the gates operates to 
set the CP FF to CP T which will cause the augend digits 
to be complemented. If the signs are alike, gates 8 
an d 9 are blocked, the flip-flop remains restored to 
CP, and the augend is not complemented. 

4-98. Function signal 55+ blocks the recirculation 
gates of rA, and the digits of the augend go to the S 
buffers and the S lines. Function signal 50 alerts the 
quinary and binary adders gates at tOB. 

4-99. The quinary bits of the pi digit of the addend 
(Ml, M2 t and M3) go to the input gates of the decimal 
carry adder (figure A-ll) and the quinary carry gates 
(figure A-12) . The input gates of the decimal carry 
adder sample the A and C signals from the binary and 
quinary circuits to determine whether a carry bit is to 
be added to the two digits being added. Because the pi 
digits ar_e thje first to be added there can be no carry, 
and the A or C signal, or both, will be low. The out- 
puts of the decimal carry adder go to the quinary adder. 
They represent the quinary bits of each digit of the 
addend. 

4-100. The quinary bits of the pi digit of the augend 
(SI, S2, and S3) go to the input gates of the comple- 
menting circuit (figure A-ll). If the CP (complement) 

4-36 



signal alerts the gates* the circuit produces the com- 
plement of the input bits. If the CP (no complement) 
signal alerts the gates, the quinary S bits pass 
through the circuit unchanged* 

4-101. The quinary S bits and M bits also are sent in 
parallel to the quinary carry circuit. Any combination 
of quinary bits which indicates the need for quinary 
carry generates C and C signals from the quinary carry 
circuit. The gates are blocked by combinations which 
require no quinary carry, generating the low C signal. 
The low C signal, if generated, is used in conjunction 
with the A signal to indicate a decimal carry into 
the addition of the next two digits. The low C sig- 
nal indicates the presence of quinary carry and causes 
a carry bit to be added in the addition of the binary 
bits in the binary adder. 

4-102. The quinary outputs of the decimal carry ad- 
der and those of the complementing circuit are added 
in the quinary adder gates. One or two of the adder 
gates is permissive to the input combinations, pro- 
ducing a high output signal. A high output signal 
indicates a 1 bit, a low output signal indicates a 
bit. 

4-103. The binary bits of the two quantities are 
added in the binary adder (figure A-12) at the same 
time as the quinary bits. Initially* the M4 and S4 
binary bits are compared in the binary equality gates. 
The gates* alerted by CP, sample the two binary bits 
during a normal addition. If either bit is a 1, a 
signal indicating the 1 bit goes to the binary carry 
circuit to generate a binary carry signal A t which 
will be used with the C signal, if present, in the 
addition of the next two digits. The carry circuit also 
sendj; the A* signal to gate 6 of the binary adder. If 
the C signal is low, gate 6 is permissive to the A' 
signal and the j042 output is high, indicating a 1 bit 
in the MSB of the sum digit. No decimal carry will 
be generated if the C signal is low. 

4-104. If the M4 and the S4 bits each has a value of 
1, gate 30 of the force decimal carry circuit is per- 
missive and the A and C signals are generated to force 
an indication of a decimal carry to the next addition. 



4-37 



105. If the M4 and the S4 bits each has a value of t 
the binajry equality gates are blocked, generating low 
signals A and A' which indicate no binary carry. The 
low A* signal goes to gate 7 of the binary adder which 
is permissive only if quinary carry is present t a con- 
dition indicated by the low C* signal. If the gate is 
permissive* the 041 output is high, indicating a 1 in 
the MSB position of the sum digit. If quinary carry 
is absent, the C* signal is high blocking gate 7 and 
producing a low 041 bit. A low 041 output signal in- 
dicates a in the MSB of the sum digit. The signal 
outputs of the quinary adder and the binary adder are 
sent to the sum input buffers of r A . The sum digits 
are stored in rA during the Al step. 

4-106. If the sum of two quantities with unlike signs 
is zero, the sign of that sum must be forced to plus. 
The TS FF is used as a control circuit to indicate this 
condition to the rA sign flip-flop. Function signal 75 
alerts restore gates 16 and 17 of the TS FF during the 
Al step. If the signs of the two quantities being added 
are unlike, the CP FF is set to CP . The CP t A, and C 
signals are present during addition when the signs are 
unequal. These signals alert the quinary-equality 
gates, which compare for equality the digits being 
added in the adders. The CP signal alerts the binary- 
equality gates which also compare for equality. If 
the first nine digits of the quantities being added are 
equal, the TS FF remains set to TS . The TS signal goes 
to the rA sign flip-flop to force the sign of the sum 
to plus if the sum of the quantities is zero. 

4-lOf. At tllB, FS 4 alerts the input gates of the rA 
sign flip-flop and the overflow flip-flop. Gates 3, 
6, and 7 of the rA sign FF compute the sign of the sum 
(paragraph 3-126) and store it in the flip-flop. Dur- 
ing addition, the overflow flip-flop (OF FF) is set at 
gate 29 when the input signals indicate that the sum 
has exceeded the capacity of r A . When this possibility 
is expected, the programmer provides for it by program- 
ming a routine in the c+1 address, to be used only if 
overflow occurs. The set output of the OF FF, OF, sets 
the overflow delay flop to 0F2+ during the next search- 
f or-instruction step. The OF2+ signal keeps the TS FF 
set at buffer 82 to delay for one word time the read- 
ing of the selected instruction word address. This 
causes the c+1 address to be read instead of the c 
address • 



4-38 



MEMORY 



Compute 
Sign of (4 
Sum 



CP 



rA 
SIGN FF 



SIGN OF SUM 



READ 
AMPLIFIERS 



RECIRCULATION 
GATES 



SUM INPUT 
BUFFERS 



REGISTER A 



Sum 



Sign of Augend 



Addend 



M 
BUFFERS 



COMPLEMENT 
FLIP-FLOP 



CP (Unlike Signs) 



CP (Like Signs) 



r 



Sign of 
Addend 



M Lines (Quinory Bits) 



M Lines ( Binary Bits) 



Augend 



S 

BUFFERS 



S Lines (Quinory Bits ) 



S Lines (Binary Bits) 



Complement 



COMPLEMENTER 
CIRCUIT 



DECIMAL 
CARRY 
ADDER 



QUINARY ADDER 
50) 



~l 



r 



BINARY 

EQUALITY 

GATES 



BINARY 
CARRY 
CIRCUIT 



QUINARY 
CARRY 
GATES 



QUINARY 
ADDER 
GATES 



01 



| Q2 



I Q3 , 



1 . 



COMPARATOR (50 
Binary Carry 



Quinary Corry 



BINARY 
ADDER 



04 



Sum 



I 



OVERFLOW 
J FLIP-FLOP 



a. A1 Step 



RECIRCULATION 
GATES 



SUM INPUT 
BUFFERS 



REGISTER A 



Final Sum 



SIGNS OF AUGEND 

AND ADDEND 

FROM A1 STEP 



Sum 



S 
BUFFERS 



COMPLEMENT 
FLIP-FLOP 



S Lines 



CP 



CP 



Complement Sum 



Leave Sum Unchanged 



COMPLEMENTER 
CIRCUIT 



QUINARY ADDER (50 



COMPARATOR 



BINARY 

EQUALITY 

GATES 



BINARY 
CARRY 
CIRCUIT 



~l 



QUINARY 
ADDER 
GATES 



01 



02 



03 



-*< 



1 



—\ 



BINARY 
ADDER 



04 



Finol Sum 



I I 



b. A2 Step 



Figure 4-8. Add Instruction 



4-39 



4-108. Function signal 64 alerts the STR stepping gate 
at tlOB of the Al step. If the EP signal is low, the 
gate steps FF1 and FF2 to 1 outputs. At this point, 
however, FF1 is already generating a 1 bit output, so 
that, in effect, only FF2 is stepped. The new 11 
reading in the lowest-order STR bits is converted in- 
to function signals for the A2 step by the instruction 
decoder and function encoder. The function signals 
generated for the A2 step are 50, 55+ and 67. 

4-109. A2 STEP. If the sum determined during Al is 
the complement of the true sum, it must be complemented 
to its true form in the A2 step (figure 4-8). The 
sum determined during Al and stored in rA reads out 
onto the S lines. Register A is cleared by FS 55+ to 
make room for the true sum which will be determined in 
the A2 step. 



4-110. Function signal 50 a 
nary and quinary adders. Th 
the complementing circuit an 
for complementing if necessa 
unnecessary (paragraph 3-138 
and the sum merely passes th 
circuit. It also passes thr 
nary adders, as in the Al st 
addition takes place in the 
quantity on the M lines to b 
however, a 1 is automaticall 
from rA in the decimal carry 



lerts the gates of the bi- 
e sum on the S lines goes to 
d the binary equality gates 
ry. If complementing is 
), the CP signal is present 
rough the complementing 
ough the quinary and bi- 
ep, and returns to rA. No 
adders because there is no 
e added. (In subtraction, 
y added to the quantity 
adder. ) 



4-111. Function signal 67 operates gate 17 of the 
ending-pulse buffer circuit at t9B. At tlOB the EP 
signal is generated to clear the static register of the 
add instruction and initiate a search for the next 
instruction. 

4-112. SUBTRACTION. The execution of add and subtract 
instructions is identical; the two instructions differ 
only in control functions. The function of the sub- 
tract instruction is to subtract algebraically the 
contents of the storage location designated by the m 
address from the contents of r A , store the difference 
in rA., compute the sign of the difference and store it 
in the rA sign flip-flop. The quantity in the memory is 
the subtrahend; the quantity in rA is the minuend. The 
subtract instruction also requires two execution steps, 
SI and S2. 



4-41 



4-113. Although the instruction code for subtract is 
75, the staticized digits cause the same function sig- 
nals to be generated as those generated for the stati- 
cized add instruction. The STR FF4 output for subtract 
is an STR4 signal. As a result, gates 10 and 11 of the 
CP FF operate during subtraction to determine whether 
the subtrahend is to be complemented. 

4-114. When quantities with unlike signs are subtract- 
ed, the process is the same as when quantities with like 
signs are added* The sign of the subtrahend is changed, 
and the two quantities are added. These conditions 
cause the CP FF to be restored to CP so that no com- 
plementing takes place. 

4-115. A special circuit in the function encoder oper- 
ates during addition and subtraction to control the CP FF 
and complementing in the A2 or S2 step. The operation 
of this circuit is described in paragraph 4-123. 

4-116. SAMPLE PROBLEMS 

4-117. The many similarities and the few dissimilarities 
of addition and subtraction may be illustrated by two 
sample problems. In the sample two digits are first 
added and then subtracted. 

4-118. ADDITION. In this sample addition problem 
column (A) indicates the digits, (B) indicates 
their biquinary equivalents t (C) indicates the bits of 
the digits as signals on the M and S lines, and (D) 
represents the outputs of the decimal carry adder and 
complementing circuits. The M4 and S4 bits are not in- 
cluded because they are added within only the binary adder. 

(A) (B) (C) (D) 

ADD: +2 ADDEND (m) 0010 M4 M3 M2 IT M3U M2U M1U 

-hi AUGEND (rA) 0001 S4 S3 S2 SI S3C S2C SIC 
+3 

LOW LOW HIGH HIGH 
SUM AFTER Al and A2: 04 03 02 01 = 0011 or +3 

4-119. Like signs in the add instruction restore the C P 

FF to CP. The quinary bits of the augend, M3, M2, and Ml, 
go to the decimal carry adder which does not cha nge 
thei r v alue. The outputs of the circuit are M3U, M2U, 
and M1U which have the same quinary value (010) as the 
inputs. The quinary bits of the addend S3, S2, and SI 
go to the complementer circuit which does not complement 

4-42 



because the CP sign al is lo w* The outpu 
plementer circuit* S3C* S2C* and SlC t al 
value (001) as th e inputs. The binary b 
digits* M4 and S4, go to the binary carr 
two bits and CP generate a low 04 output 
adder* A low output signal on the lin 
which goes to the A4 subregister of rA* 
the decimal carry adder and complementer 
the quinary adder. Only gate 34 of the 
missive to the input combination* Gate 
high 012 output which goes to the Al and 
of rA* Hence the two lowest order bits 
l*s. Because only gate 34 is permissive 
are blocked. As a result, inputs to the 
from the quinary adder are low signals 
bit. The sum determined during the Al 
is 0011* or 3. In the A2 step this sum 
changed through the complementer circuit 
CP FF remains restored to CP. The rA si 
termines from the signs of the two quant 
sign of the sum is plus* 



ts of 
so hav 
its of 
y circ 

from 
es i s 

The o 

circu 
adder 
34 pro 

A2 su 
of the 
, the 

A3 su 
• indi 

step » 
recirc 

becau 
gn fli 
i ties 



the com- 
e the same 

the two 
uit. These 
the binary 
a bit* 
utputs of 
its go to 
is per- 
duces a 
bregi ster s 

sum are 
other gates 
bregi ster 
eating a 

therefore* 
ulates un- 
se the 
p-flop de- 
that the 



4-120* SUBTRACTION. The same quantities which were 
added in the sample problem shown in paragraph 4-118 are 
subtracted in the sample problem at the end of this para- 
graph* In the first step of subtraction* SI* the input 
M and S bits indicated by (C) which go to the decimal 
carry adder and the complementer are the same as in 
addition. In subtraction* however* the decimal carry 
adder adds a 1 to the subtrahend and the complementer 
produces the 9*s complement of the minuend if the CP sig- 
nal is present* (Paragraph 4-122 explains the complementing*) 



Sis 



(A) 



(B) 



(C) 



(D) 



+2 MINUEND 



SUBTRACT: 



(rA) 



+1 SUBTRAHEND (m) 

HIGH 
SUM AFTER Sis 04 



0010 

0001 

HIGH 
03 



S4 S3 S2 SI 
M4 M3 M2 Ml 



LOW 
02 



LOW 
01 



■> complement — > S3C S2C SIC 

■> add 1 > M3U M2U M1U 

1100 or 9 



S2: (E) (F) (G) 

1100 (from rA) = S4 S3 S2 Si > complement > S3C S2C SIC 

0000 (on M lines) = M4 M3 M2 ST > add 1 > M3U M2U M1U 



SUM AFTER S2s 



LOW 
04 



LOW 
03 



LOW 
02 



HIGH 
01 



0001 or 



4-43 



4-121. At tOB of the first step of subtraction (SI) the 
plus signs of the two digits and the STR4 signal set the 
CP FF to CP at gate 11, At tlA, high signal CP4 is gen- 
erated for one pulse time. Signal CP4 goes to the initial 
f orce-decimal-carry circuit to force generation of the 
decimal-carry signals, A and C. The A and C signals re- 
present the 1 bit which is to be added to the subtrahend 
in the decimal carry adder. Signals A and C, because 
they were generated by the CP4 signal, last for only one 
pulse time. The quinary M inputs to the decimal carry 
adder represent a decimal 1; the outputs (D) represent a 
2. The reason for the addition of a 1 to the subtrahend 
is explained in paragraph 3-119. 

4-122. Complementing of the S input combination to the 
complementing circuit is not evident from the output com- 
bination (D) which retains the same quinary value. The 
result of complementing, however, is evident at the out- 
puts of the adders. Only gate 46 of the adder is permis- 
sive to the outputs of the decimal-carry adder and com- 
plementer circuits ; it produces high 03 and low 02, and 
()1 outputs. The M4 and S4 bits, with CP, send a low sig- 
nal to gate 6 of the binary adder. None of the quinary 
carry gates alerted by CP is__permissive to the M and S 
inputs. As a result, a low C signal alerts gate 6 to pro- 
duce a high 04 output, indicating a binary 1 bit. The 
input bits to rA at the end of the SI step therefore 
have a value of 1100 or 9. The decimal 9 is the 10*s 
complement of the true answer. 

4-123. Because addition of the two combinations in the 
Si step produced no decimal carry, the A and C signals 
from the comparator (figure A-12) are low at tllB of the 
SI step. Gates 62 and 63 of the function encoder (figure 
A-4) , alerted by the CP j^ignaljt are permissive at tllB of 
the SI step* to the low A and C signals. When the gates 
are permissive, low FS 74 is generated. This function 
signal keeps the CP FF set to CP and also generates the 
CP5 signal for one pulse time. The CP5 signal forces 
decimal carry signals A and C to low from tlB until t2B 
of the S2 step. 

4-124. In the S2 step, the 1100(E) (paragraph 4-120) 
combination returns to the S lines from register A as S4, 
S3 t S2, SI (F). The three lo west o rde r S b its go to the 
complementer which produces a S3C, S2C, SIC (G) output 
combination , 

4-125. During the S2 step there is no information on the 
M lines* and the barred M signals are all low (F) (para- 
graph 4-120). The A and C signals, which are present for 



4-44 



one pulse time, however t cause a 1 to be added to the 

value of the M bit s . The resulting output of the decimal 

carry adder is M3U, M2U, M1U (G) (paragraph 4-120). 

4-126. The outputs of the decimal carry adder and com- 
plementer go to the quinary adder. Only gate 32 is per- 
missive to the input combination. Gate 32 produces a 
high 01 output, while the 02 and 03 outputs of the quin- 
ary adder and the 04 output of the binary adder are low. 
The output combination of the quinary and binary adders* 
0001 or one, returns to the sum input gates of r A . The 
plus sign of the result is computed by the rA sign 
flip-flop (paragraph 3-120). 

4-127. MULTIPLICATION 

4-128. Multiplication in the UCT system is accomplished 
by iterative additions and shifts of the multiplicand. 
The multiplicand is added to itself the number of times 
specified by each digit of the multiplier. The multipli- 
cation process has two steps* Ml and M2. The processor 
can multiply a ten-digit multiplicand by a ten-digit multi- 
plier. In such a case the 20-digit product will be stored 
in rA and rX. The least significant part of the product 
is stored in rX ; the most significant part of the product 
is stored in r A . 

4-129. Before mul t ipl i cat ion, the multiplicand is placed 
in rL by a programmed transfer instruction. In the first 
step of multiplication (Ml) the multiplier is transferred 
from its location in the memory to rX. A code combination, 
the multiplier sentinel, is placed in the LSD position of 
r A . The sentinel will signal the end of multiplication 
and cause the multiplication process to end. 

4-130. In the second step, M2, the multiplicand in rL is 
added to itself in the adder the number of times indicated 
by the LSD of the multiplier. The LSD of the multiplier 
is stored in the multiplier quotient counter (MQC) which 
counts the number of additions. The sum of these additions 
is returned to rA . The contents of rA and rX are next 
shifted right one digit position, placing the LSD of rA 
into the most significant digit (MSD) position of rX. The 
LSD in rA before each shift becomes the LSD of the product. 
This process of adding and shifting continues until the 
least significant digit of the product is the LSD of rX. 



4-45 



4-131. The sentinel also is shifted during the shift op- 
erations. Initially it is shifted from the LSD position 
in rA to the MSD position of rX. Every ensuing shift 
operation shifts the sentinel one more place to the right 
until it reaches the LSD position of rX. It is then 
shifted into the MQC where it ends the multiplication 
process. 

4-132. The M2 step consists of two phases* designated 
IER and IER. 

4-133. During each IER (shift) phase, the contents of rA 
and rX are shifted one place to the right, the sentinel is 
shifted one place, and the LSD of rX, which contains the 
multiplier, is shifted into the MQC to control the number 
of additions. 



4-134. During the IER (add) phase, the mult ipl i can d is 
added to the sum of additions from the previous IER phase 
the number of times specified by the multiplier d igi t in 
MQC. The new sum is returned to rA for the next IER 
phase* 

4-135. GENERAL DESCRIPTION. The multiplication method 
used in the processor is illustrated by the sample problem 
in figure 4-9. In the problem, the number 1234 is multi- 
plied by 4321. Although the processor can multiply two 
ten-digit numbers, the sample problem is confined to two 
four-digit numbers. Figure 4-9a shows the method used by 
the computer; figure 4-9b shows the method as used in the 
processor circuits. The circled digits and the final four 
digits in figure 4-9a are the product digits. The first com- 
puted product digit is 4 and it is the LSD of the final product. 



4-136. During the Ml step, the multiplication 
(S) is placed in the LSD of rA, and the multipl 
in rX. The M2 step begins with a shift phase i 
sentinel is shifted from rA to the MSD position 
The multiplier in rX is also shifted right, cau 
LSD, 1, to be transferred to the MQC. The next 
M2 is the add phase in which the multiplicand f 
added to the contents of rA the number of times 
by the digit stored in MQC. The MQC digit is 1 
the multiplicand 1234 is added to the contents 
at this point is 0000. The sum of the addition 
returned to rA. The MQC counts down to after 
sary number of additions has occurred, and a ze 
MQC initiates the next shift phase. 



sentinel 

ier is placed 

n which the 

of rX. 
sing the 

phase of 
rom rL is 

specified 
; therefore 
of rA, which 
, 1234, is 

the neces- 
ro digit in 



4-46 



4-137. In the next shift phase, the contents of rA 
(1234) is shifted to the right, causing the LSD of the 
first partial product, 4, to be shifted into rX. At the 
same time that rA and rX are shifted, the sentinel ad- 
vances to the right one more place. The LSD of the multi- 
plier in rX, 2, is shifted into MQC to control th a number 
of additions in the next add phase. The multiplicand* 
1234* is added to the shifted contents of rA, 0l23 t twice 
as specified by the MQC. The two additions produce the 
second partial product, 2591. The second partial product 
is also shifted, the LSD, 1, becoming the second quotient 
digit when placed in the MSD of rX. The product digits 
and sentinel in rX again shift to the right* creating the 
MSD vacancy into which the partial product digit, 1, is 
placed. The LSD of rX, 3, is transferred to the MQC. 
The MQC therefore permits three additions of the multi- 
plicand, after which a zero reading starts the next shift 
phase. This process of alternating shift and add phases 
continues until the sentinel reaches the LSD position of 
rX and is shifted into MQC. The sentinel combination in 
MQC ends the multiplication with the most significant 
part of the product in rA and the least significant part 
in rX. 

4-138. DETAILED DESCRIPTION. The following preparations 
for multiplication take place before the Ml step: 

(1) The multiplicand is placed in rL and its sign 
in the rL sign flip-flop by a transfer in- 
struction. 

(2) The instruction word is located in the search- 
f or-instruction step. 

(3) The multiply instruction, 85, is staticized in 
the static register. 

(4) The multiplier in the storage location designated 
by m is read from the memory in the search-for- 
operand step. 

(5) The STR flip-flop 1 is jammed to 1. The combina- 
tion in the STR is 1011 1X01, which generates 
function signals at tOA and tOB to carry out the 
Ml step. 

4-139. Ml STEP. The sign of the final product in multi- 
plication is determined during the Ml step (figure 4-lOa) 
by the rA sign flip-flop, which compares the signs of the 
multiplier and multiplicand. The sign of the multiplicand 
already has been stored in the rL sign flip-flop during the 
transfer instruction. The sign of the multiplier enters the 

4-47 



Multiplicand 
Multiplier 

First partial product 123^) 

2468 
Second partial product 25SQ 

3702 
Third partial product 3960 

4936 
Final partial product 5330 — 




Shift 



0533 „ 2114 S = 
\ | End mult, 
Most sig- Least sig- 
nificant nificant 
part of P art °i 
product product 



Figure 4-9. Multiplication Process 



3113 



4-48 



RECIRCULATION 
GATES 



Multiplier 



READ 
AMPLIFIERS 



M 
BUFFERS 



INPUT 
GATES 



REGISTER X 



SIGN OF 

MULTIPLICAND 

IN rL 



Sign of 
Multiplier 



IER (SHIFT) PHASE 



RECIRCULATION 
GATES 



RIGHT 
SHIFT 
GATES 



REGISTER A 



rX 
SIGN FF 



rA 
SIGN FF 



© 



RECIRCULATION 
GATES 



MULTIPLIER 

SENTINEL 

GATE 



REGISTER A 



Insert 
Sentinel 



Block 
Normol 
Outputs 



o. M1 Step 



RECIRCULATION 
GATES 



CIRCULAR 
SHIFT 
GATES 



RIGHT 
SHIFT 
GATES 



SIGN OF 
PROOUCT 



rX 
SIGN FF 



SIGN OF 
PRODUCT 



IER 
Signal 



REGISTER X 



LSD of r X 



MOC 
FLIP-FLOPS 



IER-OR 
Signal 



I 

IER (ADD) PHASE 



CONTROL 
NUMBER 

OF ADDITIONS 





f») 


REGISTER L 1 »> 


OUTPUT 
GATES 


Multiplicand 


M 

BUFFERS 


M Lines 










L 

r 

S Lines | 


ADDER 

AND 

COMPARATOR 

CIRCUITS 












A 












RECIRCULATION 
GATES 


® 






1 


















SUM 

INPUT 

BUFFERS 




I », 




Partial Products 


S 
BUFFERS 


_ 


^ 








Alert 
Adders 


















Par 


tiol Product 



REPEAT SHIFT AND ADD PHASES 



b. M2 Step 



Figure 4-10. Multiply Instruction 



4-49 



rX sign flip-flop at tOB at gates 34 and 35, which are 
alerted by function signal 78. At tOA t the rA sign flip- 
flop is set to A- by FS 13A to prepare for the comparison 
of the signs of the multiplier and multiplicand. At tllB 
of the Ml step* FS 86 alerts gates 1 and 2 of the rA sign 
flip-flop. If the signs of the multiplier and multipli- 
cand are alike (X+ and L+ f or X- and L-) , the flip-flop 
is restored to A+. If the signs are unlike, gates 1 and 
2 are blocked and the flip-flop remains set to A-. 

4-140. At tOA, FS 62 operates gate 19 of the clear-MQC 
circuit. At tlA the CLQ signal clears the MQC FF's which 
receive the LSD of the multiplier in the M2 step. At tOB t 
FS 56+ blocks the recirculation gates of rX, and FS 76 
alerts the input gates to the multiplier which enters on 
the M lines. 

4-141. Register A is cleared during the Ml step so it 
can receive the partial products during the M2 step. At 
tOB, FS 55+ blocks the recirculation gates of rA. At 
tlB, FS 13 operates the multiplier sentinel gate of rA. 
When this gate operates, it jams l f s into the Al and A3 
subregisters. As a result, the LSD of rA is the multi- 
plier sentinel combination, 0101. Register A now contains 
the sentinel and nine zero digits. Function signal 58+ 
blocks the normal output gates of rA so that the sentinel 
remains within the register. 

4-142. At tlOB of the Ml step, FS 64 alerts the SIR step- 
ping gate which jams STR FF2 to a 1 output to initiate the 
M2 step. Function signals for the M2 step are generated 
at tOA and tOB of the M2 step. 

4-143. At tllB, gate 11 of the IER FF samples the STR 
output signals which_indicate that the M2 step has been 
staticized, and the Q (0) outputs of the MQC FF*s, which 
indicate that the circuit has been cleared. If these tw 
conditions are met, the IER FF is set at tOB to initiate 
the IER phase of the M2 step. The flip-flop generates low 
control signals IER at tOB and IER-OR at tlB, high control 
signals IERA1+ from tOA to tOB only, IERA2+ at tlA, and 
IER+ at tlB. These signals control the IER phase of the 
M2 step. 

4-144. M2 STEP. The M2 step staticized in the static 
register generates FS 55+ and 66 . These signals are pre- 
sent during both the IER and IER phases of M2. Other 
function signals, however, are generated during each of 
the two phases by the outputs of the IER FF. 



4-50 



o 



4-145. IER PHASE. At the beginning of the IER shift 
phase* control signal IERA1+ generates FS 59 for one 
pulse time from tOB to tiB. Beginning at tlB* control 
signal IERA2+ is high* and it generates FS 59 and 56+. 

4-146. At tOA of the IER phase, FS 14-1A jams the rX sign 
flip-flop to X+. At tOB of the IER phase* the low IER con- 
trol signal alerts rX sign flip-flop, gate 33 which samples 
the sign of rA from the rA sign flip-flop. If the sign of 
rA is minus* the rX sign flip-flop is restored to X-; if 
it is plus, the flip-flop remains set to X+. Thus the 
signs of both parts of the final product will be identical. 

4-147. Function signal 59 alerts the right shift gates 
of rA and rX and the circular shift gates of rX so that 
a right shift of both registers can take place. Function 
signal 56+ blocks the recirculation gates of rX; function 
signal 55+ blocks the recirculation gates of r A • During 
the first IER phase* the right shift operation causes the 
multiplication sentinel* in the LSD of rA, to be shifted 
into the MSD position of rX. The LSD of the multiplier 
in rX is at the same time shifted into the MQC FF*s. The 
IER-OR control signal alerts the input gates of the four 
MQC FF's to receive the outputs of the rX subregi sters . 

4-148. Function signal 66 alerts the output gates of 
rL* which stores the multiplicand during multiplication. 
The multiplicand in rL is transferred to the M lines and 
i nto the adder circuits in preparation for the add phase 
(IER). The partial products stored in rA after every 
shift phase are on the S lines and are also inputs to the 
adder circuits. 

4-149. During every IER shift phase* the IER control sig- 
nal alerts gate 18 of the ending pulse-circuit to sample 
for the 0101 sentinel in MQC. When the sentinel is pre- 
sent in the MQC FF's, the gate is permissive and the EP 
signal is generated to end multiplication. 

4-150. IER PHASE. During this phase the contents of rA 
are added in the adder to the multiplicand from rL. The 
IER add phase is initiated at tllB of the IER phase by the 
tllB+ timing signal at gate 40 of the IER FF. The signal 
restores the flip-flop at tOA* and the polarities of the 
signals generated by the flip-flop during the IER phase 
are reversed for the IER phase. The IER+ output* which is 
now low* goes to the instruction decoder. If the staticized 
M2 signals are present and the IER+ signal is low* FS 14-2A 
is generated. Function signal 14-2A in turn generates FS*s 
50 and 61. Function signal 50 alerts the binary and quinary 
adders. Function signal 61 alerts the countdown gates of 
the MQC. 

4-51 



4-151. The partial product in rA» after every shift phase* 
and the multiplicand are added in the binary and quinary 
adders, just as in addition (paragraph 4-94). The sum of 
each addition is returned to rA. The MQC countdown cir- 
cuit counts down to zero from the multiplier digit stored 
in it during the shift phase* When the reading in the 
MQC FF's is zero, the IER FF is set to initiate the IER 
shift phase again. 

4-152. After the last multiplier digit has been processed 
and the necessary additions have been performed* the sen- 
tinel is shifted into the MQC FF*s. In the next shift 
phase, the IER signal alerts the ending pulse gate 18. If 
the sentinel (0101) is stored in MQC, the Ql and Q3 signals 
from the MQC FF*s are low. Only the sentinel has 1 bits 
in these positions. The EP is generated and, at tOB, a 
search for the next instruction is initiated. 

4-153. DIVISION 

4-154. In the method of non-restoring division used in 
the OCT system the programmer scales the dividend so that 
it will be smaller than the divisor. Within the processor 
the dividend is logically multiplied by ten and comple- 
mented. The divisor is added to this new form of the 
dividend until addition produces an overflow carry. The 
remainder is complemented and multiplied by ten (shifted 
left), and the divisor is again added to this new dividend* 

4-155. The number of divisor-to-dividend additions is 
monitored for each step and these numbers (or their com- 
plements) become the final quotient digits. The end of 
the division process is signaled by a sentinel that has 
been stored in the least significant digit position of a 
register and is shifted with each step toward the most 
significant digit position* When the sentinel becomes the 
most significant digit, the division process ends* 

4-156. GENERAL DESCRIPTION. In the first phase of the 
division process, the dividend is shifted left and com- 
plemented. In the next phase, the divisor is added to the 
complemented dividend. Because the dividend is in its 
complemented form, the resulting quotient digit is also 
in complemented form. The quantity which remains after 
the di vi sor-to-complemen ted-div idend additions is the 
complemented remainder as shown: 

complemented quotient 

divisor ] complemented dividend 
/+ divisor 



complemented remainder 
4-52 



The complemented remainder becomes the dividend of the 
next phase in which the next quotient digit will be de- 
termined. Before being used as the next dividend* how- 
ever, this complemented remainder is complemented again 
to return it to its original or true form as shown: 



quotient 



divisor 



Jdi vidend 
/+ divisor 

remainder 

4-157. In the next succeeding phase the dividend, quotient* 
and remainder again become the complemented form of their 
actual value. The cycles of the shift and complement 
phases alternate throughout the division process* and are 
differentiated as even cycles and odd cycles. 

4-158. The odd cycles of the shift and complement phase 
always precede the even cycles. In the odd cycles the 
dividend* the quotient* and the remainder less the divisor 
are the 9*s complement of their real value. In the even 
cycles the three quantities are represented in their un- 
complemented form. 

4-159. It must be remembered that although the quantity 
contained in rA at the end of every add phase is the re- 
mainder of that phase it becomes the new dividend necessary 
for the determination of the second quotient digit. There- 
fore* to arrive at a five-digit quotient* there must be 
five dividends* each dividend being the remainder of the 
previous division. 

4-160. The quotient digits derived from each cycle are 
stored in rX* the contents of which is left shifted and 
complemented until division ends. The quotient digit de- 
rived during an odd cycle is complemented an odd number 
of times so that when it is transferred to rA it is in its 
true form. The quotient digit derived during an even cycle 
is complemented in rX an even number of times so that when 
transferred to rA it too is in its true form. 

4-161. In the sample division problem (figure 4-11) the 
divisor, 0.133* is divided into the dividend* 0.032. The 
MQC column shows the state of the MQC countdown circuit 
at each successive addition. The Phase column shows 
whether the computer is in the shift-complement phase 
(OR) or the add phase (OR). The distinction between odd 
and even OR phases is explained in paragraph 4-174. 



4-53 





Step 


MQC 


Phase 


rA 


rX 


rL 




Dl 







003200 


000001 


013300 




D2 


10 


OR odd 


mi 

967990 


iiiii 

999980 


013300 




9 
8 
7 


OR 


+ 133 


999980 

llll 






981290 
+ 133 




994590 
+ 133 




C007890 

llll 




10 


OR even 


921000 


000120 






9 
8 
7 
6 
5 
4 


OR 


+ 133 


000120 

llll 






934300 
+ 133 




947600 
+ 133 






960900 
+ 133 


.2406 
.133: .0320000 
266 
540 
532 
800 
798 
02 




974200 

+ 133 


987500 
+ 133 


C000800 

llll 


10 


OR odd 


991990 


998750 




9 


OR 


+ 133 


998750 

llll 










C005290 

llll 




10 


OR even 


947000 


012400 






9 
8 
7 


OR 


+ 133 

960300 
+ 133 

973600 
+ 133 

986900 
+ 133 


012400 






C000200 




D3 







024060 

Final 
Quotient 


000200 
Carry 


013300 
Divisor 



OR 



shift and complement phase OR = add phase 



4-54 



Figure 4-11. Division Process 



3115 



4-162. For simplification the division process described 
is for a six-digit register rather than the 12-digit regis- 
ter used in the UCT system. The least-significant digit 
position in each register is the sign position and remains 
unchanged throughout the process* The most significant 
digit is the SBW position. 

4-163. In the Dl step the following takes place: 

(1) MQC is cleared to 0. 

(2) The dividend is placed in rA. 

(3) The division sentinel (0001) is stored in LSB 
position of rX. 

4-164. The first phase of D2 is the odd OR phase, in which 
the contents of rA and rX are individually shifted left and 
complemented. The 003200 combination in rA therefore be- 
comes the quantity 967990. Similarly, the 1 sentinel and 
the contents of rX become the quantity 999980. 

4-165. In the next phase, the OR phase, the divisor is 
added to the dividend. The 133 divisor can be added to 
the complemented dividend three times before a decimal 
carry occurs. Meanwhilje, the MQC counts down from ten to 
seven. This ends the OR phase with a 7 digit in MQC, the 
remainder in rA, and the rX sentinel shifted one digit 
position to the left. 

4-166. In the next phase, the even OR, the remainder is 
shifted left and complemented to the quantity 921000, 
which becomes the new dividend for the computation of the 
next quotient digit. In the left shift operation, a 
replaces, in the LSD position, the MSD shifted to the left 
out of the register. The quotient digit 7, stored in MQC, 
is placed in the LSD position of rA after the sentinel is 
shifted left, and both are complemented. The quantity in 
rA becomes 000120, of which the 1 is the sentinel and 2 is 
the first quotient digit. At the end of the OR phase the 
MQC is jammed to ten. 

4-167. In the next OR phase a count of the divisor is 
again added to the dividend. Six such additions take place 
before a decimal carry occurs. As a result, the- MQC counts 
down to 4 and the OR phase ends. 

4-168. The next OR phase causes the remainder, 000800, to 

4-55 



be complemented and shifted, the sentinel to be shifted, 
the digit 4 from MQC to be placed in rX, and the contents 
of rX to be complemented. The MQC is again jammed to ten. 

4-169. Addition of divisor to dividend (remainder) again 
takes place in the OR phase. Only one addition takes place 
before decimal carry occurs; thus, the digit in MQC is 9. 

4-170. In the next OR phase, the remainder 005290 is 
shifted and complemented to a quantity of 947000, the 
new dividend for the last add phase. The sentinel is 
shifted into the next MSB position. The quotient digit 
9, computed in previous add phase, enters the MSB posi- 
tion of rX, and the contents of rX is complemented. The 
quantity in rX is now 012400. The is the SBW, 1 is the 
sentinel, 2 is the first final quotient digit, 4 is the 
second final quotient digit, and is the sign position. 

4-171. The final addition phase, CHR, steps MQC down to 6 
and leaves a remainder in rA of 0C0200. 

4-172. In the previous OR phase the 1 sentinel was shifted 
to th^e MSB position of rX , signifying the end of division. 
The OR add phase takes place as described, but the sentinel 
has begun to initiate the D3 step, which starts as OR ends. 

4-173. In the D3 step, the contents of rA and rX are inter- 
changed; the final quotient is stored in rA and the final 
remainder in rX. The quotient digit, 6, derived from the 
last set of additions, goes uncomplemented to the LSD posi- 
tion of rA to become part of the quotient. The sign of the 
quotient also is computed during D3 in the rA sign flip-flop. 

4-174. Examination of the problem shows that the quotient 
digits resulting from an odd OR phase are complemented an 
odd number of times; the quotient digits resulting from an 
even OR phase are complemented an even number of times. 
This process ensures that the final quotient, transferred 
to rA t is the true quotient. 

4-175. DETAILED DESCRIPTION. The following assumptions 
are made in the discussion of the D instruction: 

(1) The search-for-instruct ion step has taken place. 

(2) The instruction has been staticized. 

(3) The dividend (operand) has been located by the 
second search step. 



4-56 



MEMORY 



READ 
AMPLIFIER 



Sign 



Dividend 



M 
BUFFERS 



M Lines 



r 



rX 
SIGN FF 



SIGN OF 
DIVIDEND 



RECIRCULATION 
GATES 



INPUT 
GATES 



BUFFERS 



I 



REGISTER A 



© 



CLEAR 
MQC CIRCUIT 




' 


CLO 

1 




MQC 
FLIP-FLOPS 


^ 

•> 

^ 

^ 



rA 
SIGN FF 



A- 



RECIRCULATION 
GATES 



DIVISION 

SENTINEL 

GATE 



OOOI 



Insert 
Sentinel 



OR 
FLIP-FLOP 



REGISTER X 



ORA+ v 


INITIATE OR 


OR 


SHIFT-COMPLEMENT 


IER-OR 


PHASE 



Figure 4-12, Dl Step of Division 



(4) The divisor has been placed in rL by a previous 
instruction, either an L or K instruction. 

4-176. Dl STEP, In the first execution step of division, 
Dl, (figure 4-12) registers A and X are prepared for division. 



4-57 



the rX and rA sign flip-flops are prepared for the com- 
putation of the sign of the quotient and the sign of the 
remainder, MQC is cleared, the division sentinel is placed 
in rX.and at the end of Dl the static register is stepped 
to D2. The divisor has been stored in rL by a previous 
instruction . 

4-177, Function signal 55+ blocks the recirculation gates 
of rA to clear the register of its contents. Function 
signal 77 alerts the input gates of rA, making them per- 
missive to the M and S lines. However, since only the 
dividend on the M lines is to be read into rA at this time, 
FS 82A holds the outputs of the S buffers low so that the 
S lines cannot read into rA. 



4-178. Function signal 56+ blocks the recirculation gates 
of rX to clear the register. The division sentinel is 
generated by FS 15 at the division sentinel gate to place 
an 0001 combination in the LSD position of rX. 

4-179. Function signal 62 alerts gate 19 of the clear MQC 
circuit at tOB to generate the CLQ signal at tlB. The CLQ 
signal clears the MQC FF's to zeros. 

4-180. The sign of the divisor has been stored in the rL 
sign flip-flop by a previous instruction. At the beginning 
of Dl, the rX sign flip-flop is set to X+ at tOB by FS 78 
at gate 35. If the sign of the dividend is minus, gate 34 
is permissive, causing an X- to be stored. The signs of 
the divisor and dividend are sampled in the D3 step to de- 
termine the sign of the quotient. 

4-181. At tllB of the Dl step FS 15 alerts gate 9 to set 
the OR FF, (figure A-15) initiating the first OR cycle of 
D2 at tOB. The flip-flop generates the IER-OR, 0RA+, and 
OR control signals. 



4-182. At tlOB of Dl FS 64 alerts the STR stepping gate 
to step STR flip-flops 1 and 2 to outputs STRl and STR2. 
The combination in STR is now 1000 1X11 which generates 
the D2 function signals. 

4-183. D2 STEP. The D2 step consists of alternating shift 

and complement phases (OR) and add phases (OR). The first 

phase of D2 is always the OR phase and is followed by the 
OR phase. 



4-58 



4-184. OR PHASE. The OR phase (figure 4-13) is initiated 
by the setting of the OR FF at the end of Dl (figure 4-12). 
The Dl function signal 15 sets the flip-flop at tllB at 
gate 9. 

4-185. The ORA+ control signal, generated during Dl, is 
a high signal which sets the CP FF t producing a low CP 
output. Signal 0RA+ also generates a CLQ signal at the 
clear-MQC circuit at buffer 42. The CLQ signal clears the 
MQC flip-flops. 

4-186. COMPLEMENTING AND LEFT SHIFT OF r A . The contents 
of rA (dividend) normally reads onto the S lines; when 
normal recirculation of the register is blocked by FS 55+, 
the register is cleared. The first three bits of the 
dividend (SI, S2 , and S3) on the S lines are read into the 
quinary-adder complementer circuit. The CP signal, which 
alerts the complementing gates, causes the first three bits 
of the dividend to be complemented. The quinary bits (SIC, 
S2C, and S3C) return to rA at the left shift gates. In re- 
circulating through the complementer circuit the first three 
bits are delayed one pulse time, the xime necessary to effect 
a left shift of rA. The fourth bit of rA is delayed (shifted 
left) within rA and recirculated to the left shift gates as 
an A"4 signal. The fourth bit is complemented by gate 42 
which is alerted by the CP signal. Function signal 71 alerts 
the rA left-shift gates, and the left-shifted, complemented 
dividend enters and is stored. 

4-187. COMPLEMENTING AND LEFT SHIFT OF rX . Function signal 
56+ blocks the recirculation gates of rX, and the contents 
of the register including the sentinel enter the input gates 
of the MQC FF*s. The IER-OR control signal, generated during 
Dl, alerts these gates. The MQC FF f s, which have been cleared 
by the CLQ signal, supply one pulse time of delay for the XI, 
X2 f X3, and X4 outputs of rX . One pulse time after entering 
the flip-flops the X input bits become the outputs of the 
flip-flops and return to rX at the quotient complementing 
gates. The OR control signal alerts these gates, which com- 
plement the Q inputs from MQC. In the first OR cycle only 
the sentinel is stored in rX whereas in succeeding OR cycles 
the sentinel and quotient digits are stored in rX* The entire 
contents of rX is complemented and shifted left. 

4-188. COMPLEMENTING THE LSD OF rA. In the first OR phase 
the original dividend is complemented and left .shifted* 



4-59 



ORA + 
Set 



COMPLEMENT 
FLIP-FLOP 



CP 



Complement 
Binory Bit 



CP 



RECIRCULATION 
GATES 



LEFT SHIFT 
GATES 



71 OR 



LSD 

COMPLEMENTER 

GATE 



Dividend 
Quinory 
-, Bits 



REGISTER A 



Dividend Binary Bit 



BUFFERS 



Complement 



COMPLEMENTER 
CIRCUIT 



Left Shift 



Complement SBW of rX 



OR 



Complement 



RECIRCULATION 
GATES 



QUOTIENT 

COMPLEMENTING 

GATES 



IER-OR 
I Alert 



REGISTER X 



MQC 
INPUT GATES 



MQC 
FLIP-FLOPS 



Shift Left and Complement Sentinel and Quotient Digit 



OR 



t1lB + 



Jam 



MQC 
FLIP-FLOPS 



COUNT OF TEN 



OR 
FLIP-FLOPS 



♦ OR+ 

(Initiate OR Phase) 



Figure 4-13. D2 Step, OR Phase 



4-60 



Divisor 

















M Lines 




Alert 
Adders 

(£) 






RECIRCULATION 
GATES 




REGISTER L | 




rL 
OUTPUT 
GATES 










M 
BUFFERS 














visor 




S Lines 
















ADDER 

AND 

COMPARATOR 

CIRCUITS 
















<5M 


Dividend 




Lines 




RECIRCULATION 
GATES 


Sum 


























S 
BUFFERS 






SUM INPUT 
BUFFERS 








_ 




















Sun 


i 











OR 



Alert 



Alert 



SENTINEL 
FROM rX 



SENTINEL 

SAMPLING 

GATE 



Set 



MOC 

COUNTDOWN 

GATES 



Reduce count- by one 



MQC 
FLIP-FLOPS 



Number of Additions Performed 



SIGNALS INDICATING 
DECIMAL CARRY 



© 



OR 
FLIP-FLOP 



OVERFLOW 

FLIP-FLOP 



OF 



ORA + 

OR 

IER-OR 



INITIATE 

NEXT 
OR PHASE 



Figure 4-14. D2 Step. OR Phase 



4-61 



In an ordinary left shift of rA instruction, the vacancy 
created in the LSD position is filled with a 0. However, 
since in division the dividend is complemented, the digit 
which becomes the LSD also must be complemented. On alter- 
nate phases, therefore, the LSD of rA is either a 9 or a 0. 
During the odd OR phases (shift and complement) the LSD of 
rA is 9. During the even OR phases (complement and shift) 
the LSD of rA is 0. 



4-189. The LSD complementer gate of rA is alerted by the 

OR output of the OR FF. At tlB the gate samples the X4D 

output of rX which is the SBW position. Only the X4D bit 

is necessary to determine whether a nine digit or a zero 

digit is stored in rX. If the SBW of rX is zero, it is 

complemented to a nine in the LSD of rA; if the SBW of rX 

is nine, it is complemented to a zero in the LSD of rA. 

4-190. JAM MQC. At tllB of each OR phase the OR signal 
makes gate 1 permissive, jamming ones into MQC FF f s 1, 2, 
and 4. This action stores a ten combination in MQC to allow 
countdown during the OR phase. 

4-191. INITIATE OR PHASE. At the end of the OR phase a 
tllB+ high signaj^ restores the OR FF to an output of 0R+, 
initiating the OR phase. 

4-192. OR PHASE. During the OR phase (figure 4-14) the 
divisor from rL and the dividend from rA go to the quinary 
and binary adder circuits where the two quantities are 
added. The MQC countdown circuit monitors the number of 
additions. The sum of the divisor-to-dividend additions 
returns to rA for temporary storage. 



4-193. ADDITION. The divisor, already placed 
previous instruction, is recirculating within r 
signal 66 and the OR FF output, 0R+, which is 1 
time, make the rL output gates permissive. The 
of rL continues to recirculate but also reads o 
lines to the M buffer and the M lines. The M 1 
the quinary and binary adders. Function signal 
recirculation of rA, and the dividend reads int 
buffers and the S lines. The S4 bits of the di 
the S lines read into the binary adder circuit, 
lowest-order bits read into the quinary adder c 
in the addition process (paragraph 4-94). Func 
50 alerts the quinary and binary adders to the 
The divisor and dividend are added and the sum 
the lines. With each addition, the MQC count 



in rL by a 
L. Function 
ow at this 

contents 
nto the L 
ines go to 

55+ blocks 
o the S 
vidend on 

The three 
ircuit, as 
tion signal 
M and S inputs, 
emerges on 
down gates. 



4-62 



alerted by FS 61, reduce_i.he number stored in the MQC FF*s 
by one every tlB of the OR phase. When decimal carry occurs, 
the remainder is still on the lines and the MQC contains 
the number of additions performed. Function signal 31 alerts 
gate 10 of the OR FF throughout the D2 step to sample the OF, 
A, C, S3, and S4 signals. The A and C signals at tllB in- 
dicate that the addition of the plO digit has produced a 
decimal carry to the pll digit. The S3 and S4 signals (1100=9) 
indicate that the pll digit is a nine. If a decimal carry 
is added to the final digit to be added, a nine, a carry con- 
dition, will occur. The OF FF is restored during the add 
phases, generating low OF. If present, these signals set 
the flip-flop to the OR phase by generating the OR, ORA+, 
and IER-OR control signals. 

4-194. END OF D2 STEP. During every OR phase of D2 , the 
division sentinel advances toward the MSD position of rX. 
At t9B of the tenth OR cycle the sentinel sampling gate 27 
examines the XI bit of rX which, if present, indicates the 
sentinel in the MSB position of rX. If the gate is alerted 
by OR, indicating that the last addition has ended, the OF FF 
is set, generating OF. Th e OF signal makes it possible to 
step to D3, if the last OR phase is complete. 

4-195. D3 STEP. In the D3 Step (figure 4-15) the contents 
of rA and rX are interchanged placing the final quotient in 
rA and the remainder (carry) in rX. The sign of the quotient 
also is computed during D3 and the instruction is ended, 

4-196. INTERCHANGING rA AND rX. Function signal 31 alerts 
input gate 001 of the D3 FF (figure A-2) throughout the D2 
step. When the following signals are present on the gate, 
the D3 FF is set, initiating the third step of division, D3: 

(1) OF, indicating that the sentinel is the MSD of rX. 

(2) A and C, which indicate that a carry or remainder 
is present. 

(3) S3 and S4, which indicate the presence of the 
digit 9 in the SBW of rA. 

(4) STR8 which indicates that improper division has 
not occurred. (Improper division generates EP, 
which clears all STR FF f s to zero.) 



4-63 



I 

•fit 



OF- 



SIGNALS INDICATING 
COMPLETION OF 
FINAL OR PHASE 



Q_ 



D3 
FLIP-FLOP 



MS) 



^32A) » 



-KB 



FUNCTION 
ENCODER 



— ® 



♦{56^ 



-® 



SIGN 


Divisor 


rA 
SIGN FF 




OF rL 
SIGN 


Dividend 


SIGN OF 
QUOTIENT 


OF rX 







Jam to Undecodable 
Combination 



«, STATIC 



REGISTER 



32 





($> 




| Remainder 




S Lines 


Q 






Jam 










OR 
FLIP-FLOP 












RECIRCULATION 
GATES 








RECIRCULATION 
GATES 






IER-OR 






















MULTIPLIER 
QUOTIENT 
COUNTER 










S 
BUFFERS 


REMAINDER 
INPUT 
GATES 




1 » 


REGISTER X 1— * 


Quotient 




QUOTIENT 
INPUT 
GATES 






REGISTER A 










1 














i 


i 






I 




CLQ 


1 




© 






© 


CLEAR MQC 
CIRCUIT 




















^ 





Figure 4-15. D3 Step 



Because OF is low, OF is high, blocking gate 10 of the 
OR FF, so that the flip-flop remains restored . Coinci- 
dence of these signals at tllB of the 10th OR phase sets 
the D3 FF, which generates FS 32 at tOB. Function signal 
32A is generated at tlA. When the D3 FF is set, it also 
steps FF5 to a 1 output, resulting in a combination that 
cannot be decoded by the instruction decoder. As a result, 
no function signals are generated by the instruction de- 
coder since the D3 FF is now generating its own function 
signal. The flip-flop is restored every word time by the 
tllB+ signal* 

4-197. Function signal 32A drives the function encoder 
to generate FS 55+, 56+, 86, and 67. Function signal 55+ 
blocks recirculation of rA. The remainder, from rA, goes 
to the S buffer and the S lines. Function signal 32 alerts 
the remainder of rX input gates to the S inputs. (Function 
signal 56+ blocks recirculation in rX. Function signal 32 
also generates the IER-OR control signal which alerts the 
input gates of the MQC FF's to the X lines from rX. Function 
signal 32A clears the MQC FF's every pulse time by generating 
the CLQ clear signal at the clear MQC circuit.) 

4-198. As the quotient in rX is shifted through the one 
pulse time of delay supplied by the MQC FF*s, the remainder 
on the S lines reads into rX. The outputs of rX are read 
through the MQC FF f s. Function signal 32 alerts the quotient input 
gates of rA to the quotient on the Q lines. Thus the re- 
mainder is transferred into rX and the quotient is transferred 
into rA. Function signal 67 ends the instruction at tllB of 
the D3 step by generating the EP signal at t9B. 

4-199. SIGN OF THE QUOTIENT. During the D3 step the sign 
of the quotient is computed at gates 01 and 02 of the rA 
sign flip-flop. Function signal 86 alerts these gates to 
sample the sign of the divisor, which is stored in the rL 
sign flip-flop, and the sign of the dividend, which is stored 
in the rX sign flip-flop. The rA sign flip-flop already has 
been set to A-. If the X and L signs signify a minus sign 
for the quotient, the rA sign flip-flop remains set to A-. 
If the X and L outputs signify a plus sign, the flip-flop 
is restored to store an A+ for the sign of the quotient. 

4-200. ERROR CIRCUITS 

4-201. A constant check on system errors or abnormal con- 
ditions in the input-output devices is maintained by four 
flip-flops: the memory-read error flip-flop, the timing- 
error flip-flop, the cycling-unit error flip-flop, and the 

4-65 



I/O (input-output) abnormal-condition flip-flop. The 
signals produced by the setting of all of these flip-flops 
except the I/O abnormal-condition flip-flop, set the stop 
flip-flop. The signal generated by the stop flip-flop 
blocks the gates of the instruction decoder so that the 
next instruction staticized in the static register will 
not be executed until the cause of the condition is 
remedied and the operator restarts the computer. An error 
or abnormal condition which develops in one of the input- 
output devices sets the I/O abnormal-condition flip-flop. 

4-202. MEMORY-CHECK FLIP-FLOP 

4-203. When information is written into the main memory 
the check-bit computer (figure A19) ensures that an odd 
number of 1 bits is recorded on the drum for each digit. 
The check-bit computer performs the same check on informa- 
tion read from memory. If the digit read from memory con- 
tains an even number of 1 bits, a low CK signal is generated . 
If the digit contains an odd number of 1 bits, a low CIC sig- 
nal is generated. The CK and CK signals go to the memory 
check flip-flop to indicate whether a or a 1 check bit 
was necessary when written on the drum. The value of the 
check bit being read from the drum is indicated by the 
DM5 signal output of the read circuits. The check bit is 
found on the DM55 line when reading from fast memory. The 
memory-check flip-flop is set to a high MRE output (Memory 
Read Error) to indicate an error under two conditions: 

(1) If a checkbit is present, as indicated by the 
low CK signal, and there is a 1 check bit being 
read as indicated by the low DM5 signal, or 

(2) if a 1 check bit is present as indicated by a low 
CK signal and a check bit indicated by the low 
DM5 signal. 

4-204. The memory-check flip-flop can be set to a high MRE 
output only if the check-timing flip-flop is set. This 
check-timing flip-flop is set at tOB if the RD signal is 
present, indicating that the main memory read flip-flop is 
set. The low output of the check timing flip-flop alerts 
gates 53A and 53B of the memory-check flip-flop to sample 
for check bit error condition. 

4-205. The high MRE signal lights the MAIN STORAGE and 
PROCESSOR/OFF NORMAL indicators on the control panel and 
sets the stop flip-flop (figure A-5). The high SP output 
of the stop flip-flop goes to the instruction decoder 



4-66 



to block the generation of function signals for the ex- 
ecution of the next instruction until the error condition 
is remedied. The operator must press the start button 
generating a high ST (start) signal. This signal restores 
the memory read error flip-f lop to a low MRE output and 
the stop flip-flop to a low SP output. The low SP signal 
enables the instruction decoder to generate function signals 
which enable the processor to resume operations. 

4-206. TIMING-ERROR FLIP-FLOP 

4-207. The timing-error flip-flop (figure A-17) samples 
the output digits of the timing band read circuits. When 
originally recorded on the timing band of the drum, each 
permanent timing combination contains an odd number of 1 
bits. The timing error flip-flop maintains a constant 
check on the digit outputs of the timing-band read circuits 
to ensure that sach digit contains an odd number of 1 bits. 
Thus, the operation of the memory drum and reading circuits 
is constantly checked. 

4-208. Gates 2, 3, 4, and 5 of the timing error flip-flop 
test the TS1 , TS2, and TS3 outputs of the timing band read 
circuits. Gates 6 and 7 test the TS4 and TS5 outputs. 
An even combination of 1 bits alerts two of the gates, 
setting the flip-flop to a high TE (timing error) output. 
For example, gates 2 and 6 operate if the TS combination 
is 0000. This combination contains an even number (zero) 
of 1 bits; therefore an error exists. Gate 2 operates to 
send a high signal to buffer 14 and then a low signal to 
gate 9. Gate 6 operates to send a high signal to buffer 
16 and then a low signal to gate 9. Both inputs to gate 9 
are therefore low, setting the flip-flop to a high TE output. 

4-209. The timing-error flip-flop is set to a high TE 
output, indicating an error, under two conditions: 

(1) If each of the two groupings of gates receives 
an even combination, (even + even = even) or, 

(2) if each of the two groupings receives an odd 
combination (odd + odd = even). 



A normal-odd input combination in one grouping plus an 
even input combination in the other grouping (odd + even = odd) 
puts a high on both set gates and the timing error flip-flop 
output, TE, remains low. If an error exists the high TE 
signal lights the TIMING ERROR and PROCESSOR OFF NORMAL 
indicators on the control panel and sets the stop flip-flop 
(paragraph 4-202). 

4-67 



4-210. CYCLING-UNIT ERROR FLIP-FLOP 

4-211. The cycling unit error flip-flop (figure A-16) 
constantly checks the synchronization of the timing com- 
bination i 11 pu t to the cycling unit. This combination, 
TS4 t TS3, TS2 and TSl, must be present at t6B of every 
word time to properly synchronize processor and input- 
output operations. If this combination is absent at 
t6B, the cycling unit error flip-flop generates a signal 
that stops the processor and indicates the condition on 
the control panel for remedial action. 

4-212. Gate 3 of the flip-flop is blocked by the high 
t6B+ signal at t6B, which is the exact time that the timing 
combination should be present. At any time other than t6B, 
the t6B+ signal is low. Therefore, if the bits 
of the timing combination are low at the gate at any time 
other than t6B, the gate is permissive, setting the flip- 
flop. Gates 4, 5, 6, and 7 check the individual bits of 
the timing combination for synchronization. These gates 
are alerted by the t6B- si gna l at 1 6 B . A mal fun ction is 
present if any one of the TSl, TS2 , TS3 f and TS4 signals 
is low at t6B, since only the timing combination signals 
should be low at that time. If the input signal to one 
of these gates is low at t6B, the gate is permissive. 
This condition again sets the flip-flop to a high CUE 
output. The high CUE signal lights the CYCLING UNIT ERROR 
and PROCESSOR OFF NORMAL indicators on the control panel 
and sets the stop flip-flop. 

4-213. INPUT-OUTPUT 

4-214. Any abnormal operation of one of the three input- 
output devices produces a signal that goes to one of the 
three set gates of the master I/O abnormal-condition flip- 
flop (figure A-2). On the next card cycle or print in- 
struction, the flip-flop is set by the function signal 
generated by the instruction and the signal that indicates 
the abnormal condition. For example, abnormal operation 
of the printer causes a low AOP (Abnormal Operation Printer) 
signal to be generated. The next print instruction (16 or 
11) in the program generates FS 41, which alerts gate 100 
to the AOP indication. The permissive gate sets the I/O 
abnormal-condition flip-flop, generating high Jam I2A and 
Jam I2B signals. The Jam I2A signal sets FF 1, 2, and 6, 
to 1 outputs. The Jam I2B signal restores FF 5 and 8 to 
outputs. This staticizes the second step of a test in- 
struction. The abnormal condition signals, AOT and AOR, 



4-68 



from the read-punch and card-reader respectively, similarly 
affect the I/O abnormal-condition flip-flop when the in- 
struction involving these devices is staticized. These 
signals set the flip-flop, which in turn, jams the STR FF's 
to the second stage of a test instruction. 

4-215. This new reading generates function signals that 
transfer the unexecuted instruction still in rC to rA for 
storage. The second stage of a test instruction normally 
transfers the contents of rC to rA and also sets the CT FF 
so the next instruction is taken from m instead of c. (See 
112, under instruction 22, Analysis of UCT Instructions.) 
This setting of the CT FF is prevented by an inhibiting 
Jam I2B signal which blocks the gate. 

4-216. The contents of rC is transferred to rA for future 
use by the programmer. This transfer takes place without 
clearing rC. Jam I2A ensures that the next instruction is 
taken from c+1 address by setting the OF FF and restoring 
the CT FF. The assumption is made that the programmer has 
stored, in the c-fl address, a routine which brings the com- 
puter to a stop. 

4-217. MANUALLY-CONTROLLED OPERATIONS 

4-218, The computer can operate either on a continuous or 
a non-continuous basis. Although the computer normally 
functions in the continuous mode; facilities are provided, 
mainly for troubleshooting and testing procedures, to operate 
the computer in the non-continuous or step-by-step mode. 

4-219. The operator controls the mode of operation of the 
computer by depressing one of the six pushbutton lights on 
the control panel under OPERATION. These buttons light 
when pushed and are mechanically interlocked so that only 
one can be pushed at a time. When the CONTINUOUS button 
is pushed, the computer operates continuously until a pro- 
grammed stop instruction is staticized in the static register, 
until an error occurs, or until the operator stops computa- 
tion by pushing the STOP button. To place the computer in 
a non-continuous mode one of the five buttons marked ONE 
LINE PRINT, ONE CARD RPU t ONE CARD HSR, ONE INSTRUCTION, 
or COMPARISON STOP must be pushed. The logical operation 
of the non-continuous modes are described in paragraphs 4-220 
through 4-234. 

4-220. ONE-LINE PRINT 

4-221. When the operator depresses the ONE LINE PRINT 
button, the computer stops on the first step of the next 



4-69 



advance-and-print instruction. When this button is pushed 
an EPR signal is generated and sent to gate 25 of the stop 
flip-flop (figure A-5). The EPR signal remains at gate 25 
until the conditions indicating that an advance instruction 
has been staticized are present. Function signal 41 alerts 
the gate whe n the advance-and-print instruction is staticized 
and the STR4 signal signifies that an advance-and-print in- 
struction has been called for rather than the paper-advance 
instruction, both of which generate FS 41. The low ST signal 
indicates that the start flip-flop has been set. 

4-222. The one remaining signal necessary to make gate 25 
permissive is the low output of the IOS FF. Because this 
signal is necessary in all of the non-continuous operations, 
the explanation of the one-line-print operation applies also 
to the four other operations. 

4-223. When any one of the non-continuous pushbutton 
switches is energized, the NC (non-continuous) signal is 
generated. The NC signal is used to synchronize the 
control panel input signal with internal computer signals. 
It alerts gate 1 of the synchronizing flip-flop which is 
permissive at tOB if an EW signal is present (paragraph 3-194). 
Because the NC signal is generated by a manually-controlled 
switch, it may be a weak or partial signal at tOB. The syn- 
chronizing flip-flop stores the NC signal for two word times, 
during which the signal either dies out or builds up into a 
strongsignal. 

4-224. If the original NC signal dies out, the synchronizing 
flip-flop is restored and then set again with a strong signal 
when the next EW signal is available. At the end of the two 
word times, the signal goes to gate 9 of the IOS FF. Gate 9 
is alerted by the EW signal and is permissive at tOB if the 
input signal is low, setting the flip-flop. The IOS FF 
generates a signal (IOS) which is sent to set gates 19, 22, 
23, 24, and 25 of the st op flip-flop. The setting of the 
IOS FF generates a high IOS signal which restores the syn- 
chronizing flip-flop. 

4-225. When gate 25 is jnarmissive , it sets the stop flip- 
flop to low SP and high SP outputs. The SP signal blocks 
the instruction decoder so that no function signals are 
generated. When the operator pushes the START button a 
high ST signal is generated to restore the stop flip-flop. 



4-70 



4-226. ONE-CARD RPU 

4-227. When the ONE CARD RPU button is pushed the com- 
puter stops on the first step of the next card cycle in- 
struction involving the read-punch unit. When this button 
is pushed, a TECC signal is generated and sent to gate 19 
of the stop flip-flop. Gate 19 is alerted by FS 29 dur- 
ing the first step of the next card-cycle instruction for 
the read-punch unit. If the ST and IOS signals are pre- 
sent the gate operates to set the stop flip-flop (para- 
graphs 4-223 through 4-225.) 

4-228. ONE-CARD HSR 

4-229. When the ONE CARD HSR button is pushed the com- 
puter stops on the first step of the next card-cycle in- 
struction for the card reader. When this button is 
pushed, an RECC signal is generated and is sent to gate 
22 of the stop flip-flop. Gate 22 is alerted by FS 28 
only during the first st ep of the next card-reader card- 
cycle instruction. The ST signal makes the gate permissive, 
setting the stop flip-flop (paragraphs 4-223 through 4-225.) 

4-230. ONE INSTRUCTION 

4-231. When the ONE INSTRUCTION button is pressed, the 
computer stops after the next instruction is staticized. 
The operator uses this mode of operation to type informa- 
tion into the computer from the keyboard. When this 
button is pushed, a st at icize-every-minus (SZE-) signal 
is generated and sent to gate 23 of the stop flip-flop. 
Function signal 2 alerts gate 23 during the staticize step 
of the next instruction. When the gate is permissive the 
stop flip-flop is set (paragraphs 4-223 through 4-225.) 

4-232. COMPARISON STOP 

4-233. The fifth non-continuous button, COMPARISON STOP, 
differs from the other four in that it stops the computer 
after a Q or T instruction has been executed but before 
the computer searches for the next instruction. The 
function of both the Q and T instructions is to compare 
two quantities and, on the basis of this comparison, to 
determine whether the next instruction should be taken 
from the m or c address. Two illuminated pushbutton 
switches on the control panel indicate to the operator 
whether the next instruction to be searched for will be 



4-71 



in the m or c address. When the operator has depressed 
the COMPARISON STOP button, the computer stops after the 
comparison is made and the next address has been select- 
ed. If the operator wishes to override the address de- 
termined by the comparison the correct button is pushed. 
The m or c button changes the state of the CT FF and 
lights the lamp associated with the chosen address. The 
RUN button is then pushed and the computer searches for 
the next instruction, 

4-234. When the COMPARISON STOP button is pushed a QT 
Stop signal is generated and sent to gate 24 of the stop 
flip-flop. The STR signals that make gate 24 permissive 
are common only to the Q and T comparison instructions. 
If the inputs to gate 24 are low, the gate is permissive 
at tlOB, setting the stop flip-flop. The tlOB signal 
ensures that the comparison instruction will be completed 
before the stop flip-flop is set (paragraphs 4-223 through 
4-225.) 

4-235. KEYBOARD INPUT 

4-236. The control panel keyboard enables the operator 
to change the contents of the arithmetic registers (A, X t 
or L), by typing in new information. An instruction word 
also is typed into rC at the keyboard to load the program 
into the memory at the c address specified in the instruc- 
tion word. The keyboard consists of ten keys (0 through 
9), a KEYBOARD ALERT pushbutton to energize the keyboard, 
a KEYBOARD READY light, which indicates that the keyboard 
is ready for use, and two WORD RELEASE pushbuttons labeled 
+ and -. With the latter two pushbuttons, the sign of 
the word is inserted and the typed word is released from 
temporary storage into the selected register. 

4-237. MANUAL OPERATION 

4-238. At all times during computation, the contents of 
one of the four registers. A, C, X, or L t is displayed 
in lights on the control panel. Forty lights labelled 
REGISTER CONTENTS display the biquinary combinations of 
each of the 10 digits" contained in the register. Two sign 
lights (+ and -) directly below these 40 lights indicate 
the sign of the word in the register. The operator selects 
the register to be displayed by pushing one of four 
illuminated pushbuttons on the control panel labelled 
REGISTER SELECTOR. These four buttons, C t A, X, and L, 
light when depressed and are mechanically interlocked so 
that only one can be operated at a time, 

4-72 



4-239. To type either instruction or data information 
into the computer, the operator selects a register and 
stops the computer by pushing the STOP button. When the 
computer stops, the operator pushes the ONE INSTRUCTION 
and KEYBOARD ALERT buttons. After a delay of approximate- 
ly one second, the KEYBOARD READY lamp lights to signal 
the operator that the keyboard is ready for use. The 
operator can now type in the word, MSD first. When the 
complete word is typed, the operator pushes one of the 
word-release buttons, either + or -. The word is shifted 
into the selected register and its sign is placed in the 
proper sign flip-flop. The operator then pushes the 
CONTINUOUS button and the RUN button. 

4-240, If a typing error is made, the operator can push 
one of the word-release buttons to release the word into 
the register, push the KEYBOARD ALERT button once again, 
and retype the word, 

4-241, The operator can depress two keys at the same time 
to form bit combinations for characters not represented by 
keys on the keyboard. An alternate method is to type in 
two complete words. The operator then depresses one of 
the word-release buttons and the combination of the first 
and second shifts into the selected register. Here is a 
list of key combinations that the operator can use: 

Biquinary Code Key Combinations 

0101 1+4 

0110 2 + 4 

0111 3+4 
1101 9+1 

1110 9+2 

1111 4+8 

4-242, The word typed into the computer is stored temporar- 
ily in four shift registers — read-punch shift register, 
card-reader shift register, card-reader group counter, and 
read-punch group counter (figure 4-16.) Each shift register 
stores 10 bits of the typed 40-bit word. The LSD of the 
word reads out of the shift registers first t although the 
operator types in the MSD of the word first. A CLIA-signal, 
which clears all four shift registers, is generated when 
the (keyboard alert) button is pushed. Signals necessary 
to shift the word are generated every time a key is released. 
When the entire word is typed and stored in the shift registers, 
the operator pushes one of the two word-release keys to supply 
the sign of the word and open the path into the selected 
registers. 

4-73 



4-243. DEPRESSING A KEY 



4-244. 
one dig 
for the 
matrix 
are dis 
goes in 
to the 
card-re 
card-re 
flip-fl 
of the 
board k 



Each 
it in 

desi 
shown 
tr ibu 
to th 
read- 
ader 
ader 
op of 
keybo 
eys # 



t ime 
to the 
red di 

in f i 
ted on 
e read 
punch 
shift 
group 

each 
ard en 



the 

f ou 
git 
gure 
to f 
-pun 
grou 
regi 
coun 
regi 
code 



oper 
r sh 
is g 
A-5 
our 
ch s 
P co 
ster 
ter . 
ster 
r wh 



ator de 
ift reg 
ener ate 
. The 
output 
hift re 
unter t 
, and t 

Each 
. Tabl 
ich is 



press 
ister 
d by 
four 
lines 
giste 
the S 
he SC 
bit i 
e 4-4 
contr 



es a k 
s t the 
the ke 
bits o 
The 
r t the 
CI3 li 
14 lin 
s stor 
shows 
oiled 



ey to place 

four-bit code 
yboard encoder 
f each digit 

SCI1 line 

SCI2 line goes 
ne goes to the 
e goes to the 
ed in first 

the outputs 
by the key- 



Table 4-4. Keyboard Encoder 



Keyboard 
Key 


Card- 
Reader 
Group 
Counter 

SCI. 
4 


Card- 
Reader 
Shift 
Register 

sci 3 


Read- 
Punch 
Group 
Counter 

sci 2 


Read- 
Punch 
Shift 
Register 

sci L 


UCT 
Code 













0000 


1 








X 


0001 


2 






X 




0010 


3 






X 


X 


0011 


4 




X 






0100 


5 


X 








1000 


6 


X 






X 


1001 


7 


X 




X 




1010 


8 


X 




X 


X 


1011 


9 


X 


X 






1100 



4-74 



4-245. A high SCI+ signal is generated from the beginn- 
ing to the end of the keyboard input. The SCI+ signal 
goes to the card-reader group counter to block the sett- 
ing of the sample-pulse 1 flip-flop and to the read-punch 
group counter to block the stepping of the row counter, 

4-246. RELEASING A KEY 

4-247. Each time a key is released a sprocket signal is 
generated. This signal is synchronized with the timing 
of computer signals by the EW and t4B- signals which set 
the sprocket-synchronizing flip-flop. This flip-flop 
generates a low SPR signal. This SPR signal sets the 
keyboard input flip-flop (figure A-27) at t4B f gate 218 
when the EW signal is present. Three signals are gener- 
ated — a low SCISB t a high SCISA t and a high RSP. The 
SCISA signal is available for 9 pulse times (t6A to t3A) 
and in all four registers it shifts each bit of informa- 
tion 9 places to the right. The SCISB signal supplies 
a recirculation path to the two group counters. The 
other two shift registers are already recirculating. 
The RSP signal restores the sprocket synchronizing flip- 
flop. 

4-248. As a result of the operation of a key the four 
bits of the first digit stored in the four registers are 
shifted nine places to the right in all shift registers 
by the SCISA signal. This signal sends a high signal to 
the restore gates and a low to the set gates of the ten 
flip-flops of each register. Section 2-97 explains the 
operation of a shift register. As a result of this 
shifting, the four bits of the first digit are placed in 
the LSD position of the four registers. When the next 
key is depressed, the four bits of the next digit are 
stored in the first flip-flop of each register. When the 
key is released the SCISA signal again shifts the new 
bits nine places to the right and shifts the previously 
inserted bits the same number of places. The SCISB sig- 
nal, sent to the group counters, permits the first bit 
in each counter to recirculate and become the second 
lowest order bit of the register. All ten digits of a 
word are read into the registers and shifted in the same 
manner. As a result, all digits of the word are in 
position in the register to be read out LSD first. See 
table 4-4. 



4-75 



4-249. SIGNING AND RELEASING THE WORD 

3-250. After all ten digits of a word have been typed, 
the operator provides the word with a sign and releases 
the word into the previously selected register by de- 
pressing either of the two word-release buttons, labeled 
+ and -. If the plus button is depressed, a WR+ signal 
is generated. If the minus button is depressed, a WR- 
signal is generated. The WR+ or WR- signal is stored 
temporarily in the word-release initial storage flip- 
flop and then is synchronized with computer timing by 
the setting of the word-release synchronizing flip-flop. 
The synchronized signal generated from this flip-flop 
sets the word-release flip-flop. When set, this flip- 
flop generates two signals, a high WRA and a low WRB. 
The WRB signal generates function signals that will open 
up the path into the selected register on the M lines 
and gate the information stored in all four registers 
onto the M lines. The WRA signal supplies the shift 
pulses needed to shift information out of the four 
registers. 

4-251. The WRB signal alerts the DM gates 56A, 56B, 56C, 
and 56D (figure A-5) so the four output lines of shift 
registers read the contents onto the DM and M lines as 
follows: 

Register Output DM line M line 

Read-Punch shift register SR2 DM11 Ml 



Read-Punch group counter TG10 
Card-Reader shift register SRI 



Card-Reader group counter 



G10 



DM21 
DM31 
DM41 



M2 

M3 
M4 



The WRB signal also goes to the gener ate-instruct ion 
gates 57, 58, 59 and 60 (figure A-5), only one of which 
has been alerted. One of the RSC, RSA, RSL, or RSX 
signals alerts one of the gates, depending on which 
register has been selected by the operator. If the RSC 
signal has been generated, a gener ate-bet a signal is 
produced. If the RSX signal has been generated, a gener- 
ate-Y signal is produced. If the RSL signal has been 
generated, a generate-L signal is produced and if RSA 
signal has been generated, a generate-B signal is produced 



4-76 



































































1 

3H9 








_ 




REGISTER 
SELECTOR 
SWITCHES 


- 


, 


WR + 


+ 




i 


, 














" 


















GENERATE 

INSTRUCTION 

GATES 




WORD RELEASE 

INITIAL 

STORAGE 

FLIP-FLOP 




WORD RELEASE 

SYNCHRONIZER 

FLIP-FLOP 




WORD RELEASE 
FLIP-FLOP 


WRB 












WRA 




ISnin out or Registers; 






u 








i 














FUNCTION 
ENCODER 




i 








1 




1 






FUNCTION 

SIGNALS 

WHICH ENABLE 

TYPED DATA TO 

ENTER SELECTED 

REGISTER 




RECIRCULATION 
GATE 










H 










sen 






READ-PUNCH SHIFT REGISTER 


SR2 






' 


' Shift 










r\c I DUARU 








/~\ Keyboard 
^ Ready 














J 






* 


'©©(§ 
©(DO 


\ r\_ 


- " 






REGISTER SIGN 
FLIP-FLOPS(A,X or L) 


), o 


»» 


i •» 






RECIRCULATION 
GATE 














~~ H 






i v.'>r~ 
















1 w w ^ i 

1 (Q) i 








SCI2 








READ-PUNCH GROUP COUNTER 




TGIO 




Alert 


1 










i 


Shift 




SR1 






























i 








Key Operation 




KEYBOARD 
ENCODER 






DM 
GATES 
















DM Lines 


M 


M Lines 


SELECTED REGISTER 












J 












BUFFERS 




(A.C.Lor X) 


Key Release 












RECIRCULATION 
GATE 
























~u 
















CARD-READER SHIFT REGISTER 






SCI3 


■ 


Shift 








i 




G10 












1 








RECIRCULATION 
GATE 












~H 














CARD-READER GROUP COUNTER 






SCI4 


Alert 


Shift 








-i SCISB 


, 




Set 










MSB 






SPROCKET 

SYNCHRONIZING 

FLIP-FLOP 


SPR 


KEYBOARD 

INPUT 
FLIP-FLOP 


(Shift Through Registers) 






SCISA 




Restore 






















RSP 



































































Figure 4-16. Keyboard Input Operation 



4-77 



One of these four signals is sent to the instruction de- 
coder to generate function signals that perform the in- 
struction required to store the input data in the select- 
ed register. (Function signal 67, however, is not gener- 
ated because the static register is not involved.) The 
WRB signal also is sent to gate 15 on the static register 
to generate an ending pulse if FS 2 is present. 



on 
s. 



4-252. The WRA signal is sent to all four shift registers 
to place a high signal on the restore gates and a low o" 
the set gates to shift the contents out of the register 
The WRA signal also is sent to the keyboard input flip- 
flop to generate an RSP signal which restores the word- 
release initial-storage and word-release synchronizing 
flip-flops. 

4-253. The signal generated when an arithmetic register 
is selected (RSA V RSX f or RSL) is combined with either 
the WR+ or WR- signal to generate one of the following 
signals: WRA- t WRA+, WRX-, WRX+ t WRL- t WRL+. These 
signals go directly to the rA, rX v or rL sign flip-flops 
to store the correct sign in the correct flip-flops. 
If rC is selected to receive the word typed in, no sign 
is involved. 



4-79 



SECTION V 
TABLE OF CONTENTS 

Paragraph Title Page 

5-1 Introduction 5-1 

5-3 Outline of Section 5-1 

5-5 Other References 5-1 

5-6 Section IV 5-1 

5-7 Analysis of UCT Instructions 5-2 

5-8 Section III 5-2 

5-9 Notation 5-2 

5-11 Description of Instructions 5-2 

5-12 Input-Output Instructions 5-2 

5-14 Arithmetic Instructions 5-3 

5-16 Transfer Instructions 5-3 

5-18 The 60(H), 56(X), and 50(J) 

Instructions 5-3 
5-19 The 25(B), 05(Y), and 30(L) 

Instructions 5-3 
5-21 The 77(K) Instruction 5-4 
5-22 Translate Instructions 5-4 
5-24 The 12(G) Instruction 5-4 
5-28 The 17(R) Instruction 5-5 
5-29 Miscellaneous Instructions 5-5 
5-31 The 20(P) Superimpose Instruc- 
tion 5-5 
5-34 The 35(E) Extract Instruction 5-6 
5-38 The 34(N) Shift-Right Instruc- 
tion 5-7 
5-42 The 37(V) Shift-Left Instruc- 
tion 5-8 
5-45 The 62 (ZS) Zero-Suppress In- 
struction 5-8 
5-51 The 67 (STOP) Instruction 5-10 
5-53 Comparison Instructions 5-11 
5-56 The 82(Q) Instruction 5-11 
5-62 The 87(T) Instruction 5-13 
5-71 Test Instructions 5-15 
5-75 The 22(1 11) Instruction 5-16 
5-77 The 27(1 21) Instruction 5-17 
5-79 The 42(1 31) Instruction 5-17 



ILLUSTRATIONS 



Number Title Page 

5-1 The 25(B) Transfer Instruction 

( (m)—- >rA) 5-19 
5-2 The 12(G) Translate Instruction 

(Card Code to OCT Code) 5-19 
5-3 The 17(R) Translate Instruction 

(UCT Code to Card Code) 5-20 
5-4 The 20(P) Superimpose Instruction 5-20 
5-5 The 35(E) Extract Instruction 5-21 
5-6 The 32(N) Right-Shift Instruction 5-21 
5-7 The 37(V) Left-Shift Instruction 5-22 
5-8 The 62 (ZS 1) Zero-Suppress In- 
struction 5-23 
5-9 The 82(Q) Equality-Comparison In- 
struction 5-24 
5-10 The 87(T) Comparison Instructions 5-24 
5-11 Second Stage of 22(1 11), 27(1 21), 

and 42(1 31) Test Instructions 5-25 



TABLE 

Number Title Page 

5-1 State of Conditional-Transfer Flip- 

Flop After Comparison Operation 5-18 



SECTION V 
INSTRUCTIONS 

5-1. INTRODUCTION 

5-2. There are 32 instructions in the UCT repertoire. 
Eight are input-output instructions described in other 
manuals. The remaining instructions, concerned with 
operations internal to the processor, are described in 
this section and in section 4 of this manual. Appendix C 
lists all the instructions numerically. 

5-3. OUTLINE OF SECTION 

5-4. The descriptions of instructions in this section 
are arranged as follows: 

(1) Input-output instructions 

(2) Arithmetic instructions 

(3) Transfer instructions 

(4) Translate instructions 

(5) Miscellaneous instructions 

(6) Comparison instructions 

(7) Test instructions 

5-5. OTHER REFERENCES 

5-6. SECTION IV. Section TV of this manual. Theory of 
Operations, describes in detail the search and staticize 
instruction steps that are common to all instructions* 
Section 4 also explains the execution steps of the 60(H) 
instruction, transfer (rA) to m t and the arithmetic 
instructions: 70(A), add; 75(S), subtract; 85(M) t 
multiply; and 55(D), divide. A thorough knowledge of the 
five instructions and the basic search and staticize 
sequence should provide the reader with the necessary 
background for understanding the less detailed descriptions 
in this section. The execution sequence for the remain- 
ing six transfer instructions and the translation, compari- 
son, miscellaneous, and input-output test instructions are 
described in this section at a block diagram level. The 



5-1 



reader may assume that the initial search and staticize 
instruction steps have been completed and that both the 
text and the figures in this section refer to the exe- 
cution sequences* 

5-7. ANALYSIS OF UCT INSTRUCTIONS. To trace in detail 
the execution of the instructions described in this 
section, refer to Analysis of UCT Instructions, a manual 
which describes briefly the steps in each instruction 
and the effect of the control signals generated by the 
instructions* 

5-8. SECTION III. Section III of this manual, Description 
of Processor Components, gives a functional description 
of the logical circuits that are mentioned both in this 
section and in the manual Analysis of UCT Instructions. 

5-9. NOTATION 

5-10. Instructions are designated in this manual by both 
an alphabetic notation, used on the logical drawings, 
and a numeric notation, used chiefly in programming; for 
example, instructions are designated: 70(A), 85(M). 

5-11. DESCRIPTION OF INSTRUCTIONS 

5-12. INPUT-OUTPUT INSTRUCTIONS^ 

5-13. Input-output instructions are used to control the 
transfer of information to and from the input-output 
devices, as well as to control the movement of cards, 
the selection of output stackers, and so forth. Because 
a thorough understanding of these instructions requires 
knowledge of the input-output devices, each input-output 
instruction is described in detail in the separate 
manual for the device with which it is associated, as 
follows: 

Read-Punch Unit Manual 

46(W11) instruction 
57(Z1) instruction 
8KWZ1) instruction 

Card Reader Manual 

47(Z2) instruction 
72 (CO instruction 
96(W31) instruction 



5-2 



Printer Manual 

ll(PRl) instruction 
16(PF1) instruction 

For convenience, these instructions are listed numerical- 
ly in appendix C of thi* manual, 

5-14. ARITHMETIC INSTRUCTIONS 

5-15. The four arithmetic instructions, 70(A), 75(S) t 
85(M), and 55(D), are described in detail in section 4 
of this manual. 

5-16. TRANSFER INSTRUCTIONS 

5-17. There are seven UCT transfer instructions that are 
internal to the processor. They are the 60(H), 65(X) f 
50(J), 25(B), 05(Y), 30(L), and 77(K) instructions. 

5-18. THE 60(H), 65(X), AND 50(J) INSTRUCTIONS. These 
instructions transfer information from a register in the 
processor to a main memory location. The 60(H) instruc- 
tion, which transfers the contents of register A to a 
main memory location, is described in detail in section 4. 
The 65(X) and 50(J) instructions are similar to the 60(H) 
instruction except that they transfer the contents of 
register X and register L, respectively, to main memory 
locations. 

5-19. THE 25(B), 05(Y), AND 30(L) INSTRUCTIONS. These 
instructions transfer information from a main memory loca- 
tion to a register in the processor. The 25(B) instruc- 
tion, which transfers the contents of a main memory loca- 
tion to register A, is described in paragraph 5-20. The 
05(Y) and 30(L) instructions are similar to the 25(B) 
instruction except that they transfer the contents of a 
main memory location to register X and register L, 
respectively. 

5-20. During the execution step of the 25(B) order 
(figure 5-1), the recirculation gates of register A are 
blocked so that the new word from memory can enter the 
register. The word from memory is read by the read 
amplifiers, goes through the M buffers, and enters the 
register-A input gates. A blocking signal into the S 
buffers forces the S lines low so that the input gates 
are permissive to information on the M lines only. The 
sign of the word from memory enters the rA sign flip-flop 
as shown in figure 5-1. When the entire word from memory 
is in the register, the blocking signal on the recircula- 
tion gates is removed so that the word can recirculate 
in the register. 

5-3 



5-21. THE 77(K) INSTRUCTION. The 77(K) instruction 
transfers the contents of register A to register L and 
is the only register-to-register transfer instruction. 
Because this instruction does not involve a search for 
an operand, the m-address portion of the instruction is 
ignored. 

5-22. TRANSLATE INSTRUCTIONS 

5-23. There are two translate instructions. The 12(G) 
instruction translates one word from card code to UCT 
code, and the 17(R) instruction translates one word from 
UCT code to card code. The input-output devices operate 
with card code, while the processor performs arithmetic 
operations only with UCT code. See section I, Introduc- 
tion, for details about the codes. 

5-24. THE 12(G) INSTRUCTION. The 12(G) instruction 
translates the contents of registers A and X from card 
code to UCT code. If it is desired to perform arith- 
metic operations on information read by the card reader 
or read-punch device, the 12(G) instruction must first 
be given in order to translate the information from the 
card code used by the input-output devices to the UCT 
code used by the processor. 

5-25. Information read in card code from punched cards 
by the card read or read-punch device is eventually stored 
in main memory. Each word of information in the 6-bit 
card code must be divided into two parts, called the primed 
and unprimed parts, in order to store it on the memory 
drum, which normally stores the 4-bit UCT code. The un- 
primed part is stored in one location which normally sto 
a complete UCT-coded word, and the primed part is stored 
in another location. The division of each word in card 
code into primed and unprimed parts is accomplished auto- 
matically when the programmer transfers the information 
from the card-buffer band to main memory. This operation 
is described in detail in the Read-Punch Manual and in 
the Card Reader Manual. 

5-26. In order to translate a word from card code to UCT 
code, the programmer gives the appropriate transfer 
instructions to transfer the unprimed part of the word 
to be translated from its main memory location to register 
A and the primed part from its main memory location to 
register X. When a 12(G) instruction is given, the unprimed 
part of the word in register A is sent to the S buffer and 
then to the translation gates of rA; this information does 
not recirculate in rA because the recirculation gates are 
blocked. At the same time, the primed part of the word 



5-4 



res 



in rX is sent to the M buffers and then to the transla- 
tion gates of rA. The recirculation gates of rX are 
also blocked* See figure 5-2, 

5-27. After the complete card-coded word is translated 
into UCT code, the blocking signal on the recirculation 
gates of rA is removed to allow the newly formed UCT 
word to recirculate in rA. Register X remains cleared 
to all zeros. The sign of the UCT word in rA after 
translation is the sign of the unprimed part of the card- 
coded word that was in rA before translation. 

5-28. THE 17(R) INSTRUCTION. The 17(R) instruction 
translates the contents of register A from UCT code to 
card code. The programmer places the UCT-coded word 
which is to be translated in register A. When a 17(R) 
instruction is given, the word is sent to the S buffers 
and then to the translation gates of registers A and X 
(figure 5-3), but it does not recirculate in register A 
because the recirculation gates are blocked. The unprimed 
part of the translated word goes to register A; the primed 
part of the translated word goes to register X. After 
the complete word is translated, the blocking signals on 
the recirculation gates of both registers are removed 
so that the unprimed and primed parts of the word can 
circulate in rA and rX respectively. The programmer then 
transfers the primed and unprimed parts of the word to 
main memory by giving the appropriate transfer instruc- 
tions. During the translation process, both the rA and 
rX sign flip-flops are forced to a plus condition. 

5-29. MISCELLANEOUS INSTRUCTIONS 

5-30. Six instructions have been grouped in the miscella- 
neous category. These are: the 20(p) superimpose instruc- 
tion; the 35(E) extract instruction; the 32(N) shift-right 
instruction; the 37(V) shift-left instruction; the 62(ZS) 
zero-suppress instruction; and the 67(ST0P) instruction. 

5-31. THE 2(T(P) SUPERIMPOSE INSTRUCTION. The 20(P) 
instruction superimposes the 1-bits of the word in the 
m-address location on the word in register A. The result 
is a new word in register A containing a 1-bit where 
either the original word in rA or the word from memory 
had a 1-bit. The sign of the original word in rA is not 
changed. 



5-5 



5-32, This instruction is used when it is desired to 
combine the information in one word with the information 
in another word so that the new word contains the infor- 
mation of both. Often the information in one word must 
be combined with many other words, so that the informa- 
tion to be superimposed is placed in memory as a constant, 

5-33. As shown in the block diagram of the 20(P) in- 
struction (figure 5-4), the word of information in rA is 
allowed to circulate in register A through the recircula- 
tion gates. At the same time t the word from memory enters 
rA on the M lines from the M buffers through the input 
gates of rA. The S buffers are blocked so that the rA 
input gates are permissive to information on the M lines 
only. Thus, the 1-bits in register A are allowed to re- 
circulate into the register through the recirculation 
gates and the 1-bits in the word from memory are allowed 
to enter the register through the input gates. 

5-34. THE 35(E) EXTRACT INSTRUCTION,, The 35(E) instruc- 
tion changes 1-bits to binary zeros in each decimal digit 
of the word in register A whenever there is a binary zero 
in the corresponding bit position of the word in the main 
memory location designated by the m address. The sign 
of rA is not changed. 

5-35. This instruction is referred to as the extract 
instruction because it is used to extract certain digits 
from a word in rA. In the extract word placed in memory 
by the programmer, each bit of each digit contains a 1- 
bit where the corresponding digit in rA is to be unchanged, 
and a O-bit where it is to be changed to zero. 

5-36. For example, to extract the five most significant 
digits of the word in rA by changing the five least 
significant digits to zeros, the programmer places the 

extract word OOOOO in the memory. When an extract 

instruction that contains this extract word as the m 
address is given, the O-bits in each bit position of the 
five least significant digit positions change these digits 
to zeros in the word in rA, Since the UCT code for a 
period is 1111, or four 1-bits, there are no zero bits 
in the five most significant digit positions of the extract 
word, and the corresponding digits in the original word 
in rA remain unchanged. 



5-6 



5-37. As figure 5-5 shows, this instruction is similar 
to the 20(P) instruction. In the 35(E) instruction, 
however, the word in rA does not recirculate because the 
recirculation gates are blocked. Instead, it is sent to 
the S buffer, so that it is on the S lines at the same 
time that the extract word from memory is on the M lines. 
Corresponding digits of both words, therefore, are at the 
input gates of register A at the same time. (See section 
3-34.) The new word formed in rA as a result of this in- 
struction contains 1-bits only in the bit positions where 
the S and M lines had 1-bits in corresponding bit positions. 

5-38. THE 32(N) SHIFT-RIGHT INSTRUCTION. The 32(N) in- 
struction shifts the contents of register A to the right 
a designated number of places into rX and at the same time 
shifts the contents of rX to the right into register A. 
The number of places shifted can vary from zero through 
ten. A single digit in the p7 digit position of the m 
address of the instruction word indicates the number of 
places to be shifted. (The p7 position is the next to 
most significant digit of the m address.) The bit-code 
combination 1101 is used to indicate 10 in this instruction. 



5-39. During the staticize step of every instruction, 
the p7 digit of the m address is placed in the multiplier- 
quotient counter (MQC), so that it is available if the 
instruction is a shift instruction. 

5-40. There are two execution steps to the 32(N) instruc- 
tion: Nl and N2. During the Nl step (figure 5-6), the 
digit in MQC (the p7 digit of the m address) is examined. 
If the digit in MQC is a zero, an ending pulse clears the 
static register to all zeros so that there is a search for 
the next instruction. If the digit in MQC is not a zero, 
the static register is stepped to the N2 step of the 32(N) 
instruction. 

5-41. During the N2 step of this instruction, the contents 
of rA and rX are shifted to the right by blocking the normal 
recirculation gates of rA and rX, and circulating the con- 
tents of rA and rX through a shortened loop. During the N2 
stage the contents of rA and rX are circulated through the 
shortened loop the number of times indicated by the digit 
in MQC. During each circulation, the contents of both rA 
and rX are shifted one place to the right (figure 5-6). A 
circular shift operation also takes place: the least sig- 
nificant digit (LSD) of rA becomes the most significant 
digit (MSD) of rX and the LSD of rX becomes the MSD of rA. 



5-7 



During each shift operation the count-down gates of 
MQC count down one until the digit in MQC is zero. 
A zero in MQC generates an ending pulse. 

5-42. THE 37(V) SHIFT-LEFT INSTRUCTION. The 37(V) 
instruction shifts the contents of rA to the left a 
designated number of places. The most significant 
digits are lost and zeros are placed in the least sig- 
nificant digit places* The number of places shifted 
can vary from zero through ten. The code combination 
1101 is used to indicate 10 in this instruction. 

5-43. There are two steps to the 37(V) instruction: 
Vl and V2. During the VI step (figure 5-7), the digit 
in MQC is examined. The digit in MQC is the p7 digit 
of the m address, placed in MQC during every staticize 
instruction step. If the digit in MQC is a zero, an 
ending pulse clears the static register so that there 
is a search for the next instruction. If the digit in 
MQC is not a zero, the static register is stepped to 
the V2 step of the 37(V) instruction. 

5-44. During the V2 step, the normal recirculation 
gates of rA are blocked and the contents of rA is 
shifted to the left by circulating it through a lengthened 
loop. The contents of rA is delayed one pulse time in 
the loop before it reaches the left shift gates, so that 
the entire contents of rA shifts one place to the left 
each time it circulates. The binary bit of each digit 
is delayed by adding one pulse time in subregister 4 of 
rA. The quinary bits are delayed one pulse time by send- 
ing them through the S buffers and the complementing 
circuit, and then back into rA. (The bits are only de- 
layed in the complementing circuit, not complemented.) 
As a result of each left shift of one digit position, 
the most significant digit is lost and a zero appears 
in the least significant digit position. During each 
shift operation the count-down gates of MQC count down 
one until the digit in MQC is zero. A zero in MQC gen- 
erates an ending pulse. 

5-45. THE 62(ZS) ZERO-SUPPRESS INSTRUCTION. The 62(ZS) 
instruction suppresses all the card-coded punching or 
printing zeros and commas (and only zeros and commas) to 
the left of the most significant digit and replaces them 
with non-punching or non-printing zeros. The m portion 
of the instruction word is ignored because there is no 
search for an operand in this instruction. Suppressing 
means that a code combination which would cause a zero 



5-8 



or comma to be punched on a card or printed by the printer 
is changed so that the code combination causes a space on 
the card or the printed paper. 

5-46. All output information which is to be printed by the 
printer or punched by the read-punch device must be in card 
code. When information is translated from UCT code to card 
code before going to the input-output devices, all UCT- 
coded zeros are translated into card-coded punching or 
printing zeros. The card code for a punching or printing 
zero is 000001, (See paragraph 1-37 for explanation of 
the card code.) The combination 000001 causes a hole to 
be punched in the zero row of the card, or causes the printer 
to print a zero. The zero suppress instruction changes 
the binary one of the combination 000001 to zero, creating 
the non-printing and non-punching combination 000000. 

5-47. In addition to suppressing all zeros to the left of 
the most significant digit, the 62 (ZS) instruction suppresses 
all commas to the left of the most significant digit. The 
instruction changes 000011, the code combination for a comma* 
to 000000. Since a result may have a large number of digits, 
commas are often programmed into words. For example, 
75875875 is printed or punched as 75,875,875. However, 
if the number 00,000,875 is to be printed or punched, a zero 
suppress instruction removes the five zeros and two commas 
to the left of the most significant digit, and 875 is printed 
or punched. 

5-48. During a zero suppress instruction, the unprimed 
part of the word to be suppressed must be in register A. 
Since each digit of the unprimed part consists of the four 
lower order bits, the unprimed part of the word fills 
register A. However, each digit of the primed part consists 
only of the two higher order bits and these occupy subregisters 
1 and 2 of rX. Because subregister 3 is not used to circulate 
information, it is used temporarily as a special storage de- 
vice during the execution of the zero suppress instruction. 
Register X, therefore, should contain only the primed part 
of the word. 

5-49. Figure 5-8 shows the two steps of the zero-suppress 
instruction: ZS1 and ZS2. During ZSl, the unprimed part 
of the word in rA is sent through the zero-suppress and 
comma-suppress gates of rX. The gates, which are connected 
only to subregister 3 of rX, place a binary zero in sub- 
register 3 wherever there is a punching or printing zero 
(000001) or comma (000011) in the corresponding digit po- 
sition of rA. They place a binary one in subregister 3 

5-9 



for every character other than a zero or a comma. When 
the entire contents of rA has been examined, the static 
register is stepped to ZS2. 

5-50. During the 2S2 step, the word in rA recirculates 
through the normal recirculation gates. Subregister 3 
of rX is designed so that the outputs of each of the ten 
bits in the subregister are available in parallel. These 
ten outputs are inputs to the zero-suppress gate of rA. 
The output of the rA zero-suppress gate is an input to 
the normal recirculation gates of rA. As long as a 
binary one in subregister 3 of rX indicates that there 
are still significant digits to enter rA, the zero-suppress 
gate of rA is blocked so that the output of this gate 
keeps the normal recirculation of rA permissive to the 
recirculating digits. A blocking signal on the normal 
recirculation qate of subregister 3 of rX prevents the 
bits from reentering the subregister. When there are 
no longer any binary ones in the subregister, the zero- 
suppress gate of rA is made permissive and its output 
blocks the normal recirculation gates of rA so that all 
the 1-bits of the remaining digits of the word in rA 
(which are zeros or commas) are changed to 0-bits. That 
is, all remaining zeros and commas are suppressed. 

5-51. THE 67(ST0P) INSTRUCTION. The 67(ST0P) instruction 
stops the processor. When this instruction is in the 
static register, it generates a signal which sets the 
stop flip-flop and clears the static register to zeros. 
The stop flip-flop generates a signal which is sent to 
the instruction decoder and prevents the generation of 
any function signals. 

5-52. With the static register cleared to zeros and no 
function signals being generated, the 67 instruction word 
(which includes the m and c address) continues to circulate 
in register C. The processor is started again by pressing 
the RUN button, one of the two COMPUTATION buttons on the 
control panel. The next instruction is at the m address 
if the NEXT ADDRESS button for the m address is lit; at 
the c address if that NEXT ADDRESS button is lit. The 
operator may select the next address by pressing either 
NEXT ADDRESS button, however. The buttons control the 
conditional-transfer (CT) flip-flop. 



5-10 



5-53. COMPARISON INSTRUCTIONS 

5-54. There are two comparison instructions which com- 
pare the contents of register A and register L and, as 
a result of the comparison, direct the processor either 
to the m address or to the c address. The 82(Q) in- 
struction compares for the equality or inequality of the 
contents of registers A and L. The 87(T) instruction 
compares for greater-than and less-than conditions. 

5-55. The processor can be stopped after the execution 
of an 82(Q) or an 87(T) instruction by pressing the 
COMPARISON STOP button on the control panel. When this 
button is pressed, one of the NEXT ADDRESS pushbuttons 
lights to indicate whether the next instruction is to 
be taken from the main memory location indicated by the 
m address or the c address. The operator can change 
the address determined by the comparison* by pushing 
the other NEXT ADDRESS button. The comparison stop 
operation is explained in detail in paragraph 4.5.5. 

5-56. THE 82(Q) INSTRUCTION. The 82(Q) instruction 
compares the contents of register A with the contents 
of register L. If (rA) and (rL) are algebraically equal, 
the next instruction is in the memory location designated 
by the m address. If (rA) and (rL) are not algebraically 
equal, the next instruction is in the memory location 
designated by the c address. 

5-57. Figure 5-9 is a block diagram of the 82(Q) in- 
struction. The state of the conditional-transfer (CT) 
flip-flop determines which address is read from the 
memory. If the CT flip-flop is set, the m address is read 
from memory; if the CT flip-flop is restored, the c address 
is read from memory. At the beginning of the instruction, 
the CT flip-flop is set. If (rA) and (rL) are equal, the 
CT flip-flop remains set at the end of the comparison and 
the m address is read from memory. If, however, (rA) 
and (rL) are not equal, the CT flip-flop is restored and 
the c address is read from memory. 

5-58. As shown in figure 5-9, (rA) and (rL) are sent to 
the binary and quinary equality gates on the M and S lines, 
(rA) on the S lines and (rL) on the M lines. The binary 
equality gates sample for the equality of the binary bits 
of each digit on the M and S lines, while the quinary 
equality gates sample for equality of the quin?iry bits of 
each digit on the M and S lines. See paragraphs 3-82 and 
3-95 for a detailed explanation of these circuits. 

5-11 



5-59. In addition to the M and S lines, the binary 
and quinary equality circuits of the comparator 
have, as an input, the CP signal from the complement 
flip-flop. The complement flip-flop is set at the 
beginning of the comparison operation so that the 
CP signal alerts the binary and quinary equality 
gates during the word time that (rA) and (rL) are 
compared. 

5-60. The quinary equality gates also have the A 
and C signals as inputs. When the complement flip- 
flop is set at the beginning of the comparison 
operations, it generates a CP5 signal for one pulse 
time. The CP5 signal is sent to the initial force- 
decimal-carry circuit (paragraph 3-99), where it 
initially generates the A and C signals so that the 
quinary equality gates are permissive to the bits 
of the first digit to be compared for equality on 
the M and S lines. For example, suppose the words 
being compared are as follows: 

(rL) on M Lines 0000006917 

(rA) on S Lines 0000006917 

The initial generation of the A and C signals by 
the initial f orce-decimal-carry c ircui t makes the 
quinary equality gates permissive to the two sevens, 
the first two digits to be compared. Because they 
are equal, the comparison of the two seven digits 
results in the generation of the A and C signals 
again. Because all succeeding digits are equal, 
the A and C signals continue to be generated and 
are present at the end of the comparison. 

5-61. There are four gates which can restore the 
CT flip-flop during the 82(Q) instruction. (See 
Analysis of UCT Instructions for gate numbers.) The 
outputs of th£ binary and quinary equality circuits 
(the EQ and A* signals) are sent to two of the four 
restore gates, to restore the CT flip-flop if either 
the binary or the quinary part is not equal. Dur- 
ing this instruction, the other twc restore gates 
of the CT flip-flop have as inputs the outputs of 
the rA and rL sign flip-flops, to restore the CT 
flip-flop if the signs of (rL) and (rA) are not the 
same. 



5-12 



5-62. THE 87(T) INSTRUCTION. The 87(T) instruction 
compares the contents of registers A and L. If the 
contents of register A is algebraically greater 
than the contents of register L, the next instruction 
is in the memory location designated by the m ad- 
dress. If (rA) is algebraically less than or equal 
to (rL) t the next instruction is in the memory 
location designated by the c address. 



5-63 

inst 

term 

CT f 

memo 

dres 

the 

is g 

at t 

desi 

(rA) 

flop 

by t 



. F 

ruct 

ines 

lip- 

ry; 

sis 

begi 

reat 

he e 

gnat 

i s 

i s 
he c 



igur 
ion . 

whi 
flop 
if t 

rea 
nnin 
er t 
nd o 
ed b 
less 
rest 

add 



e 5- 

Th 

ch a 

i s 
he C 
d fr 
g of 
han 
f th 
y th 

tha 
ored 
ress 



10 is a block diagram 

e condition of the CT 

ddress is read from m 

set, the m address is 

T flip-flop is rest or 

om memory. The CT fli 

the comparison opera 

(rL) , the CT flip-flo 

e comparison and the 

e m address is read. 

n or equal to (rL) t t 

and the memory locat 

is read from memory. 



of the 37(T) 

flip-flop de- 
emory. If the 

read from 
ed, the c ad- 
p-flop is set at 
tion. If (rA) 
p remains set 
memory location 

If, however, 
he CT flip- 
ion designated 



5-64. 

ing t 

gates 

(para 

(para 

cui t 

to al 

the c 

lines 

Sever 

input 

ning 

which 

tion 



The 
he 87 

(par 
graph 
graph 
(para 
1 of 
on ten 

and 
al of 
. Si 
of th 

have 
on th 



con te 
(T) in 
agraph 

3-95) 

3-91) 
graph 
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e comp 

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3-82 
♦ the 

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. The M 
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ts have 
flip-flo 
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he circ 
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y gates 
gates 
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are inputs 
struct ion , 

on the S 
e M lines • 

as an 
he begin- 
ui ts 
o informa- 



5-65. The binary and quinary equality gates sample 
for the equality of digits on the M and S lines in 
this instruction as they do in the 82(Q) instruction. 
Gate 31 of the force-dec imal -carry circuit (figure 
A12) samples for whether the binary bit on the M 
line is greater than the binary bit on the S line. 
The part of the quinary circuit consisting of 
gates 33, 34, and 46 through 56 samples for whether 
the digit on the M lines is greater than the digit 
on the S lines. 



5-13 



5-66. Table 5-1 shows all conditions for comparing 
(rA) and (rL). Whether the CT flip-flop remains 
set or is restored depends upon whether the A and 
C signals are present at the completion of the com- 
parison. The restore gates of the CT flip-flop 
during the 87(T) instruction have as inputs the A 
and C signals (gate 13) or the C signal (gate 14) 
or the A signal (gate 15). (See Analysis of UCT 
Instructions*) Paragraph 3-107 explains which 
gate operates to restore the CT flip-flop under 
each of the conditions in table 5-1. 

5-67. As indicated in table 5-1, gate 32 of 
figure A12 initially generates the decimal-carry 
signals (A and C) if the sign of (rA) is plus. If 
(rA) is minus the A and C signals are not initially 
generated. The initial generation of the A and C 
signals when (rA) is plus but not when (rA) is 
minus affects the conditions under which the CT 
flip-flop remains set or is restored. 



5-68. As shown in table 5-1, there are two con- 
ditions under which the CT flip-flop is restored 
when rA is plus: when (rA) equals (rL) , and when 
(rA) is less than (rL) . If (rA) equals (rL), the 
binary and quinary equality gates continue to 
generate the A and C signals, which restore the CT 
flip-flop at the end of the comparison. 

5-69. If (rA) is less than (rL), the A and C 
signals are again present at the end of the com- 
parison, but they are generated by the gates which 
indicate (rA) is less than (rL) (paragraph 3-86). 
For example, suppose the two words being compared 
are as follows : 

(rL) on M lines 0000007809 

(rA) on S lines 0000007431 

When the nine and the one are compared, A and C 
signals are generated because rA is less than rL. 
When the next digits, the zero and the three, are 
compared, the A and C signals are lost because 
rA is greater than rL and there are no gates to 
generate A and C signals under this condition. 
When the two most significant non-equal digits, the 
8 and 4, are compared, A and C signals are again 
generated by the gates of the quinary-carry circuit 



5-14 



which indicate rA is less than rL. The A and C sig- 
nals thus generated make the quinary equality gates 
permissive so that the succeeding digits, which are 
all equal, continue to generate the A and C signals, 
which restore the CT flip-flop at the end of the 
compar i son . 

5-70. Table 5-1 shows that when (rA) is minus, 
there is only one condition for which the CT flip- 
flop remains set: when both (rA) and (rL) are minus, 
and (rA) is less than (rL). When (rA) is less than 
(rL) , the gates which indicate the contents of rA 
is less than the contents of rL generate the A and 
C signals and the CT flip-flop is not restored. 
For example, suppose the two words being compared 
are as follows: 

(rL) on M lines 0000005924 

(rA) on S lines 0000005384 

the A and C signals are not generated until the two 
most significant non-equal digits, the nine and the 
three, are compared, when the gates which indicate 
that rA is less than rL generate the signals. Be- 
cause the A and C signals are not initially gener- 
ated, the equality gates are blocked and the A and 
C signals are not generated when the two fours are 
compared. They are not generated when the eight 
and the two are compared, because there are no 
gates which indicate (rA) is greater than (rL). 
However, when the nine and the three generate the 
A and C signals, the biquinary equality gates are 
made permissive and the A and C signals continue to 
be generated because all remaining digits of this 
example are equal. 

5-71. TEST INSTRUCTIONS 

5-72. Three input-output test instructions are 
provided in the UCT, one for each of the three in- 
put-output devices. The programmer uses these in- 
structions to determine whether a particular input- 
output device is available or whether it is still 
processing a previous instruction. For example, 
the input-output test for the printer tests to de- 
termine if the printer is free to accept a print 
order or is still processing a previous print order. 
If the printer is not available to process a print 
order, the processor is free to continue the main 
program, instead of waiting until the printer is 
available. This is a saving in computing time. 

5-15 



The instructions are distributed throughout the pro- 
gram to test the availability of the input-output 
devices at convenient intervals* 

5-73. Each of the three input-output instructions 
has two stages. The first stage tests whether the 
device is available. If it is not available, an end- 
ing pulse is generated and the processor goes to the 
c address, the address of the next instruction. Be- 
cause each of the three instructions tests a different 
device, the first stage of each instruction is 
different. 

5-74. If the test performed during the first stage 
shows that the device is available, the static regis- 
ter is stepped to the second stage. The second stage 
of each test instruction is identical. (See figure 
5-11.) During this stage, the contents of register C 
is transferred to register A, and the next instruction 
is read from the m address. Register C contains the 
c address, the address of the next instruction of the 
main program. It is put in register A because the 
processor must return to it in order to continue to 
process the program. The m address to which the pro- 
cessor is directed can contain a subroutine which 
transfers the c address of the test instruction from 
register A to memory, gives one of the input-output 
instructions, and returns the processor to the main 
program. 

5-75. THE 22 (I 11) INSTRUCTION. The 22 (I 11) 
instruction tests to determine whether the card buf- 
fer band is loaded with information from the read- 
punch device. If the card buffer band is not load- 
ed from the read-punch device, the next instruction 
is in the memory location designated by the c ad- 
dress. If the card buffer band is loaded from the 
read-punch unit, the next instruction is in the memory 
location designated by the m address, and the con- 
tents of register C is transferred to register A. 

5-76. Item 1 of the instruction analysis for the 22 
(I 11) instruction lists the signals in the first 
stage, during which the test is made to determine 
whether or not the buffer is loaded from the read- 
punch device. If the buffer band is not loaded from 
the read-punch device, an ending pulse is generated. 
If the buffer band is loaded from the read-punch 
device, the static register is stepped to the second 



5-16 



stage of the instruction (items 2 through 9 of the 
instruction analysis). The second stage of this in- 
struction, which is common to all the input-output 
test instructions, is shown in block diagram form in 
figure 5-11. 

5-Tt. THE 21 (I 21) INSTRUCTION. The 27 (I 21) in- 
struction tests to determine whether the printer is 
printing or feeding paper. If the printer is print- 
ing or feeding paper, the next instruction is in the 
memory location designated by the c address. If the 
printer is not printing or feeding paper, the next 
instruction is in the memory location designated by 
the m address and the contents of register C is 
transferred to register A. 

5-76. Item 1 of the instruction analysis of the 
27 (I 21) instruction lists the signals in the first 
stage, during which the test is made to determine 
whether or not a printing or paper feeding operation 
is taking place. If the printer is occupied, an 
ending pulse is generated. If the printer is avail- 
able, the static register is stepped to the second 
stage of the instruction (items 2 through 9 of the 
instruction analysis). The second stage, which is 
common to all the input-output test instructions, 
is shown in block diagram form in figure 5-11. 

5-79. THE 42 (I 31) INSTRUCTION. The 42 (I 31) 
instruction tests to determine whether the card buf- 
fer is loaded with information read by the card 
reader. If the buffer band is not loaded from the 
card reader, the next instruction is in the memory 
location designated by the c address. If the card 
buffer band is loaded from the card reader, the next 
instruction is in the memory location designated by 
the m address and the contents of register C is trans 
ferred to register A. 

5-80. Item 1 of the instruction analysis lists the 
signals in the first stage, during which the test 
is made to determine whether or not the buffer band 
is loaded from the card reader. If the buffer band 
is not loaded from the card reader, an ending pulse 
is generated. If the card buffer band is loaded, 
the static register is stepped to the second stage 
of the instruction (items 2 through 9 of the in- 
struction analysis). The second stage, which is 
common to all the input-output instructions, is 
shown in block diagram form in figure 5-11. 

5-17 



table 5-1. State of Conditional-Transfer 
Flip-Flop After Comparison Operation 



When the flip-flop is set, the m address is read. 
When the flip-flop is restored, the c address 
is read. 



Sign* 


Absolute Value 


(rA) 


(rL) 


(rA) > (rL) 


(rA) = (rL) 


(rA) < (rL) 


+ 

+ 


+ 

+ 


set 

set 
restored 
restored 


restored 

set 
restored 
restored 


restored 

set 
restored 

set 



•When the sign of (rA) is plus, gate 32 generates 
initial decimal-carry signals. When the sign of 
(rA) is minus, no initial decimal-carry signals 
are generated . 



5-18 









; .. '....-- 




BLOCK 

I 










BLOCK 

\ 




»«? 










RECIRCULATION 
GATES 




S 
BUFFERS 


S Lines 
1 












l 




l 


REGISTER A 1 












i_ 




INPUT 
GATES 






















t 








MAIN 
MEMORY 




READ 
AMPLIFIERS 




M 
BUFFERS 


M Lines 


ALERT 


































rA 
SIGN FF 


— -♦A- 
»»A+ 
























t 

ALERT 







Figure 5-1. The 25(B) Transfer Instruction ((m) >rA) 





BLOCK 

1 




















RECIRCULATION 
GATES 


ALERT 


ALERT 










\ 






REGISTER X 


| Primed Port 


BUFFERS 








| 




BLOCK 
1 












1 




■VI LIMBS 

S Lines 




rA 

TRANSLATION 

GATES 
















RECIRCULATION 
GATES 






























REGISTER A 


■ Unprimed Part 


S 
BUFFERS 










| 










UCT C( 


DDE 
















3138 



Figure 5-2. The 12(G) Translate Instruction 
(Card Code to UCT Code) 



5-19 











.... 






S Lines 




ALERT 

1 


BLOCK 

1 






BLOCK 
1 




RECIRCULATION 
GATES 




JAM • 


rA 
SIGNFF 


»-A+ 












rX 

TRANSLATION 

GATES 






REGISTER X 1 




RECIRCULATION 
GATES 








Cord Code 






Primed Port 




X+ 


















ALERT 

1 


REGISTER A 


I UCT Code 


S 
BUFFERS 












1 




J 




rX h fc 

SIGN FF if"* 












AM » 


Card Code-Unprimed Port 


rA 

TRANSLATION 

GATES 






















;*,•■■,,.<=•' 

















Figure 5-3. The 17(R) Translate Instruction 
(UCT Code to Card Code) 













BLOCK 

1 








ALERT 

J 






S«40 






S Lines 


RECIRCULATION 
GATES 






S 
BUFFERS 






~"1 












1 






REGISTER A 1 














1 ». 


INPUT 
GATES 
















M Lines 








. :■ ■•% 




MEMORY 




READ 
AMPLIFIERS 




M 
BUFFERS 


1 








ALERT 






i", ' 


., .....j,,, -, , r . 




J 


X 













Figure 5-4. The 20(P) Superimpose Instruction 



5-20 



















3<41 






S Lines 




BLOCK 

1 










RECIRCULATION 
GATES 




S 

BUFFERS 










M Lines 








rrc-rrrA 1 














INPUT 
GATES 


































MAIN 
MEMORY 




READ 
AMPLIFIERS 




M 
BUFFERS 


1 

ALERT 































Figure 5-5. The 35(E) Extract Instruction 



N1 



N2 



p7 DIGIT 



BLOCK 



MULTIPLIER 
QUOTIENT 
COUNTER 






ENO 
INSTRUCTION 
















STATIC 
REGISTER 







N2 



BLOCK 



ALERT 





COUNT 
DOWN 
GATES 




MULTIPLIER 
QUOTIENT 
COUNTER 




. END 




" INSTRUCTION 





























RECIRCULATION 
GATES 




RECIRCULATION 
GATES 














USD LSD 












USD LSD 




RIGHT 
SHIFT 
GATES 




I » 


REGISTER A 1 i 






RIGHT 
SHIFT 
GATES 




1 » 


REGISTER X 1— -i 




■" 


1 












> 


' 




i 






I 

ALERT 






1 

ALERT 




























CIRCULAR 

SHIFT 
GATES (rA) 








CIRCULAR 

SHIFT 
GATES (rX) 




















1 

ALERT 
















I 

ALERT 













Figure 5-6. The 32(N) Right-Shift Instruction 



5-21 



VI 



p7 DIGIT 



MULTIPLIER 
QUOTIENT 
COUNTER 






END 
INSTRUCTION 






















STATIC 
REGISTER 







V2 



V2 



BLOCK 



ALERT 







RECIRCULATION 
GATES 




























i*IO LOU 


S 
BUFFERS 




COMPLEMENTING 
CIRCUIT 






LEFT 
SHIFT 
GATES 






REGISTER A 1 








| 




















' 






t 

ALERT 


Binary Bit 










Quinary Bits 







ALERT 





1 












COUNT 
DOWN 
GATES 




MULTIPLIER 
QUOTIENT 
COUNTER 


» 



























END 
INSTRUCTION 



JI4* 



Figure 5-7. The 37(V) Left-Shift Instruction 



5-22 



ZS1 



ALERT 



REGISTER A 



h- 





rX COMMA 

SUPPRESS 

GATES 






















rX 
(SUBREGISTER X3) 








rX ZERO 

SUPPRESS 

GATES 















ALERT 



ZS2 



ALERT 



STATIC 
REGISTER 



■ZS2 



BLOCK 



ALERT 



RECIRCULATION 
GATES 



rX 
(SUBREGISTER X3) 



RECIRCULATION 
GATES 



rA ZERO 

SUPPRESS 

GATES 



REGISTER A 



ALERT 



3144 



Figure 5-8. The 62CZS1) Zero-Suppress Instruction 



5-23 













ALERT 

1 






























CP 
FLIP-FLOP 




ALERT 




SET 
GATE 




















1 






1 
















DECIMAL 
CARRY 




SET 
GATE 








REGISTER A 


1 


S 
BUFFERS 






















1 






Alert 

1 




»• 


CT 
FLIP-FLOP 


► m ADDRESS 

►■ c ADDRESS 
















Alert 

1 


ALERT 






S Lines 




QUINARY 

AND 

BINARY 

EQUALITY 

GATES 










REGISTER L 


L_ 






I 










n 






RESTORE 
GATE 








H 






M Lines 






























UNLIKE 
SIGNS 


OUTPUT 
GATES 




M 

BUFFERS 














1 

ALERT 
































SMS 



Figure 5-9. The 82(Q ) Equality-Comparison Instruction 



ALERT 



FORCE 

DECIMAL CARRY 

CIRCUIT 



REGISTER A 



W 



S 
BUFFERS 



S Lines 



REGISTER L 



HM 
BUFFI 



BUFFERS 



Li 
P 



ALERT 

_1_ 



COMPARATOR 



M Lines 



i r 



ALERT 



SET 
GATE 



BINARY 
CARRY 
CIRCUIT 






'"L 



RESTORE 
GATE 



, r-M— — r 

— •» QUINARY C I I 

r ARRY ——» . 1 



CT 
FLIP-FLOP 



CARRY 
-H CIRCUIT 



ALERT 



ADDRESS 



ADDRESS 



Figure 5-10, The 87(T) Comparison Instructions 



5-24 

















BLOCK 

1 








BLOCK 

I 








HIT 








M 

BUFFERS 






RECIRCULATION 
GATES 






RECIRCULATION 
GATES 




















M Lines 








REGISTER C 


INPUT 
GATES 




REGISTER" A 


1 








* 










| 






1 








1 




a Lines 


t 

ALERT 






OUTPUT 
GATES 




S 
BUFFERS 




ALERT 

1 


OUTPUT 
GATES 


f 












t 

BLOCK 


I 

ALERT 




CT 

FLIP-FLOP 





























Figure 5-11. Second Stage of 22(1 11), 27(1 21), 
and 42(1 31) Test Instructions 



5-25 



APPENDIX C 
INSTRUCTION LIST 



APPENDIX C 
INSTRUCTION LIST 



C-l. This appendix contains a list of all the instruc- 
tions provided for UCT # These instructions are divided 
into seven groups: 



(1) Arithmetic Instructions 

(2) Transfer Instructions 

(3) Translating Instructions 

(4) Miscellaneous Instructions 

(5) Comparison instructions 

(6) Input-Output Test Instructions 

(7) Input-Output Instructions 

The four arithmetic instructions in group 1 and the 60 
instruction of group 2 are explained in detail in 
Section IV of this manual. The input-output instructions 
(group 7) are explained in detail in the separate manuals 
for the three input-output devices. All the remaining 
instructions are explained on the block diagram level in 
Section V of this manual, 

C-2. The letter m refers to the m address of the instruc- 
tion word, the letter c to the c address. A dotted line 
in place of the m address means that any digits in this 
part of the instruction word are ignored by the computer. 
The parenthesis enclosing letters means "contents of," 
For example, (rA) means contents of register A. 

C-3. The UCT instructions are: 



C-l 



Table C-l. UCT Instruction List 



INSTRUCTION 



70 m c 



75 m c 



85 m c 



55 m c 



DESCRIPTION 



TIMING 
(No. of word times for 
minimum latency) 



Arithmetic Instructions 



Add algebraically (m) to (rA) 
and put result into rA 

Subtract algebraically (m) 
from (rA) and put result 
into rA 

Multiply (rL) by (m) and 
put 20 digit product into 
rA (most significant half) 
and rX (least significant 
half) t each half having 
sign of product 

Divide (m) by (rL) and 
put unrounded result and 
sign of the quotient in 
rA and remainder in rX. 
Remainder has sign of 
dividend. If divisor = 
dividend or divisor = O t 
an overflow to c+1 will 
result 



5 plus the number of 
digits in the multiplier 
plus the sum of the 
multiplier digits. 



20 plus the sum of the 
odd digits of the 
quotient plus the sum 
of the tens complements 
of the even digits. 
MSD is #1 (odd) . 









Transfer 


Instructions 




25 m 


c 


Transfer 


(m) to rA 




4 


60 m 


c 


Transfer 


(rA) to m 




4 


05 m 


c 


Transfer 


(m) to rX 




4 


65 m 


c 


Transfer 


(rX) to m 




4 


30 m 


c 


Transfer 


(m) to rL 




4 


50 m 


c 


Transfer 


(rL) to m 




4 


77.., 


,c 


Transfer 


(rA) to rL 




3 



C-2 



Translation Instructions 



12. ..c 


Send (rA) and (rX) through 
the card code to UCT transla- 
tor and deposit result into 
rA and clear rX. [(rA) con- 
tained the unprimed word of 
the card image.] Sign of 
the result is the sign of 
the unprimed word in rA 


3 


17. ..c 


Send (rA) through the UCT- 
to-card code translator and 
deposit the two words in rA 
and rX . [(rA) contains the 
unprimed word and rX the 
primed.] Signs of results 
are positive. All UCT code 
zeros are translated to 
Remington Rand code punch- 
ing zeros 


3 



Miscellaneous Instructions 



20 m c 



35 m c 



32 n c 



Superimpose the 1 bits of 
(m) on to (rA) and leave 
the result in rA. Sign of 
rA is undisturbed 

Change the bits in each 
decimal digit of (rA) to 
binary zero wherever (m) 
has a binary zero in the 
corresponding bit posi- 
tion. Sign of rA is un- 
disturbed 

Shift (rA) to the right 
n places into rX which 
also is shifting to the 
right into rA. The sign 
positions are not in- 
volved in this shift, 
n can vary between and 
10 and is a single digit 
inserted in the next to 
most significant digit 
position of m 



3 + n 



C-3 



Table C-l. UCT Instruction List (cont) 



Miscellaneous Instructions (cont) 



37 n c 



62. ..c 



67. . .c 



Shift (rA) to the left n places 
losing the most significant 
digits and bringing in zeros 
in the least significant places 
on the right. n can vary from 
to 10 and is a single digit 
inserted in the next to most 
significant digit position of 
m. The sign digit is un- 
di sturbed 

"Zero Suppress" the word in 
rA. All Remington Rand punch- 
ing zeros and commas (and any 
other character containing a 
one in the least significant 
bit position) to the left of 
the most significant digit 
are replaced by non-punching 
zeros 

Stop the computer 



3 + n 



Indefinite 



Comparison Instructions 



82 m c 


If (rA) equals (rL) t the 
next instruction is in m; if 
not, the next instruction is 
in c 


3 


87 m c 


If (rA) is algebraically great- 
er than (rL) f the next instruc- 
tion is in m; if not, the next 
instruction is in c 


3 



Input-Output Test Instructions 



22 m c 



If the read-punch unit buffer 
is loaded, transfer (rC) to 
rA and go to m for the next 
instruction. If not, go to c 
for the next instruction 



C-4 



Input-Output Test Instructions (cont) 



42 m c 



27 m c 



If the high speed reader unit 
buffer is loaded, transfer (rC) 
to rA and go to m for the next 
instruction. If not, go to c 
for the next instruction 

If a print or advance opera- 
tion is in progress (print 
flip-flop or paper feed flip- 
flop is reset), go to c for 
the next instruction. If 
not, (i.e. print flip-flop 
and paper feed flip-flop are 
set), transfer (rC) to rA 
and go to m for the next 
instruction 



Input-Output Instructions 



81 m c 



46 m c 



57 m c 



Read-Punch Unit 

Transfer the output card images 
from the band designated by m 
to the buffer band. When the 
memory to buffer transfer is 
completed, the computer is 
free to operate on other 
instructions 

Wait until the buffer is load- 
ed, then transfer the input 
card images from the read- 
punch buffer to the input 
band designated by m (i.e. 
0000, 0200, 0400, etc.) 



Select output stacker. 
m = 0000, stacker *0 is 
selected, if m = 0100, 
stacker *1 is selected 



If 



203 



203 



C-5 



Table C-l. UCT Instruction List (cont). 



72. . .c 



96 m c 



47 m c 



16 m c 



lime 



Input-Output Instructions (cont) 



Card Reader 

Feed one card into the contin- 
uously moving rollers of the 
feed. The card will be read 
at each station in turn, and 
the data stored in the buffer 
band 

Wait until the card-reader 
buffer is loaded, then trans- 
fer this data from the buffer 
to the memory band designated 
by m (i.e. 0000, 0200, 0400, 
etc. ) 

Select output stacker. If 
m = 0000, stacker #0 is 
selected; if m = 0100, stack- 
er #1 is selected; if m = 
0200, stacker #2 is selected 

Printer 

Advance. Wait until the pre- 
vious advance or print oper- 
ation is completed, then move 
the paper "m" lines as indi- 
cated by the two least signi- 
ficant digits of m. Once the 
paper movement is started, the 
computer is free to operate 
on other instructions 

Advance and print* Wait un- 
til the previous advance 
(16) or print (11) operation 
is completed, then start to 
move paper "m" lines, as in- 
dicated by the two least 
significant digits of m. 
The two most significant 
digits of m indicate the 
print -interlace band 



203 



591 



C-6