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ic 

NAVSHIPS 0967-280-4010 

VOLUME I 

TECHNICAL MANUAL 
for 

DIGITAL DATA COMPUTER 

CP~642B/USQ-20(V) 

SECTIONS 1 THROUGH^ 



SYLVANIA ELECTRIC PRODUCTS, INC. 
SYLVANIA ELECTRONIC SYSTEMS 
NEEDHAM HEIGHTS, MASS. 



DEPARTMENT OF THE NAVY 
NAVAL SHIP SYSTEMS COMMAND 



* 

Contract: NObsr 93272 Approved 22 SEPT 1967 



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Errors found in this publication (other than obvious typographical 
errors) , which have not been corrected by means of Temporary 
Corrections or Permanent Changes should be reported. Such report 
should include the complete title of the publication and the publication 
number (short title) ; identify the page and line or figure and location 
of the error; and be forwarded to the Electronics Publications Section 
of the Bureau of Ships. 

All Navy request for NAVSHIPS electronics publications listed 
in the current issue of NAVSANDA Publication 2002 "Requisitioning 
Guide and Index of Forms and Publications", Cognizance Symbol I, 
or in a subsequent issue of the Electronics Information Bulletin 
should be directed to the appropriate Forms and Publications Supply 
Point. 



ii 



ORIGINAL 



FRONT MATTER 



NAl'SHIPS 0967-280-4010 



Correction Page 



RECORD OF CORRECTIONS MADE 



CHANGE NO. 


DATE 


FIELD CHANGE NO. 


SIGNATURE 



















































































































































































































ORIGINAL 



iii/iv 



FRONT MATTER 



NAVSHIPS 0967-280-4010 



List of Sections 



LIST OF SECTIONS 



SECTION VOLUME 



1 


GENERAL INFORMATION 


I 


2 


INSTALLATION 


I 


3 


OPERATOR'S SECTION 


I 


4 


PRINCIPLES OF OPERATION 


II 


5 


TROUBLESHOOTING 


III 


6 


REPAIR 


III 


7 


PARTS LIST 


III 


8 


FUNCTIONAL SCHEMATICS 


IV 


9 


WIRE TABULATIONS 


V 



ORIGINAL 



v 



Index 



NAVSHIPS 0967-280-4010 



FRONT MATTER 



INDEX OF ILLUSTRATIONS 
A 



Figure p afl e 

4-23. Abort Evaluation for Jump Instructions, Simplified Schematic . . . 4-57 

4-24. Abort Flip-Flop Timing Enables, Simplified Schematic 4-58 

4-11, Abort Sequence (Skip Next Instruction), Events Chart 4-31 

8-40. Abort; Y > X, Functional Schematic 8-79 

8-162. Active and Monitor Control, Functional Schematic 8-325 

8-163. Active and Monitor Control, Functional Schematic .... 8-327 

8-70. Adder Functions; R = B; Clock Overflow; 00100 and 00540 

Translations, Functional Schematic 8-139 

4-14. Af Sequence Abort for f = 17, 60-65, Timing Chart 4-37 

8-76. Af Sequence I, Functional Schematic 8-151 

8-77. Af Sequence II, Functional Schematic 8-153 

6-13. All Addresses Sense Output Waveforms 6-14 

6-31. Amplifier, Module Type 2011, Electrical Schematic 6-40 

6-49. Amplifier, Module Type 2100, Electrical Schematic 6-58 

6-51. Amplifier, Module Type 2110, Electrical Schematic 6-60 

6-53. Amplifier, Module Type 2120, Electrical Schematic 6-62 

6-55. Amplifier, Module Type 2130, Electrical Schematic 6-64 

6-57. Amplifier, Module Type 2140, Electrical Schematic 6-66 

6-59. Amplifier, Module Type 2150, Electrical Schematic 6-68 

8-2. A Register Bits 00-14, Functional Schematic 8-3 

8-3. A Register Bits 15-29, Functional Schematic 8-5 

8-41. A Register Control, Functional Schematic 8-81 

4-28. Arith Hold Function, Timing Chart 4-69 

8-39. Arithmetic Hold; B = 0; Bf Inhibit, Functional Schematic 8-77 

4-46. Arithmetic Section Block Diagram 4-110 

8-30. Arithmetic Subtractor, Borrow Enable, Functional Schematic .... 8-59 

8-25. Arithmetic Subtractor 00-05, Functional Schematic 8-49 

8-26. Arithmetic Subtractor 06-11 (Section 2), Functional Schematic . . 8-51 

8-27. Arithmetic Subtractor 12-17 (Section 3), Functional Schematic . . 8-53 

8-28, Arithmetic Subtractor 18-23 (Section 4), Functional Schematic , . 8-55 

8-29. Arithmetic Subtractor 24-29 (Section 5), Functional Schematic . . 8-57 

8-37. A = 0; A Negative; W L = 0, Functional Schematic 8-73 

B 

4-4. Basic Sequencing Time Chart 4-12 

4-115. Belt Buckle Containing a "0", Enlarged View 4-255 

4-116. Belt Buckle Containing a "1", Enlarged View 4-256 

4-114. Belt Buckle Drive and Sense Lines, Enlarged View 4-254 

8-78. Bf Sequence I, Functional Schematic 8-155 

8-79. Bf Sequence II, Functional Schematic 8-157 

4-12. Bi — >Bf Transfer With Op Step Shown, Simplified Schematic .... 4-34 

3-3. Block Transfer Subroutine Flow Chart 3-12 

6-20. Bootstrap Memory Plane 6-26 

8-53. B Register Bits 00-14, Functional Schematic 8-105 



ORIGINAL 



FRONT MATTER 



NAVSHIPS 0967-280-4010 



Index 



INDEX OF ILLUSTRATIONS (CONT.) 



Figure ^ Page 

6-153. Capacitor Assembly, Module Type 3180, Electrical Schematic .... 6-162 

4-37. Carry Input to a »2 Type Stage, Simplified Schematic 4-89 

4-36. Carry Input to a #3 Type Stage, Simplified Schematic 4-87 

8-171. Chassis A5, Chassis Map 8-243 

8-172. Chassis A6, Chassis Map 8-245 

8-173. Chassis A7 ( Chassis Map 8-247 

8-174. Chassis A8, Chassis Map 8-249 

2- 10. Chassis Removal Mechanisms 2-21 

6-16. Chassis Removal Mechanisms 6-18 

8-84 Clock Drivers, Chassis A5, Functional Schematic 8-167 

8-85 Clock Drivers, Chassis A6, Functional Schematic ... 8-169 

8-86. Clock Drivers, Chassis A6, Functional Schematic 8-171 

8-87. Clock Drivers, Chassis A7 and A8, Functional Schematic 8-173 

8-93. Command Enables B, U, S0, Functional Schematic 8-185 

8-92. Command Enables R, P, Functional Schematic 8-183 

8-94. Command Enables S, Z, Functional, Schematic 8-187 

3- 1. Computer Control Console . . . ^ 3_0 

-^4-44. Computer Console . 4-101 

4- 2. Computer, Detailed Block Diagram . . . , 4_5 

2-6. Computer Idealized Grounding Diagram 2-10 

2-1. Computer InstaTiatiwi and Dimensional Diagram 2-3 

2-5. Computer Internal Ptmer, Distribution Schematic 2-9 

4-48. Computer Multiplication, Simplified Example ..... 4-123 

2-4. Computer Power Connection Diagram ' 2-8 

4-1. Computer, Simplified Block Diagram 4_2 

4-52. Computer Square Root Extraction, Simplified Example 4-135 

1- 2. Computer with Doors and Console Open 1_3 

2- 9. Connector Shell, 90-Degree ( Detailed View . , 2-14 

8-89. Console Control I, Functional Schematic 8-177 

-8-90, Console Control II, Functional Schematic . . . 8-179 

8-91. Console Control III, Functional Schematic 8-181 

6-17. Console Switches, Program of Pin Orientation 6-21 

8-69. Control Adder IV, Carry Enable, Functional Schematic 8-137 

8-66. Control Adder I, 00-04, Functional Schematic 8-131 

8-67. Control Adder II, 05-04, Functional Schematic . . . 8-133 

8-68. Control Adder III, 10-14, Functional Schematic .* 8-135 

4-109, Control and Bootstrap Memories, Block Diagram \ 4-246 

4- 111. Control Memory, Block Diagram 4-249 

8-115. Control Memory Timing, Functional Schematic 8-131 

5- 5. Control Memory Words, Diagram of ' Bit Locations 5-20 

4-3, Control Section Block Diagram " " * 4_;q 

4-32. Control: Skip N.I. During A Replace Instruction, Timing Chart . *. 4-79 

6- 1. Core Memory Chassis 6 _ 2 

6-19. Core Stack Assembly, Detailed View \ 6-24 

1-5. CP-642B/USQ-20(V) Computer Block Diagram \ ^9 

1-1. CP-642B/USQ-20(V) Digital Data Computer \ \ \ \ \ 1-0 

4-105. CP-642B/USQ-20(V) t Thin-Film Stack, Jack Location Diagram' \ \ \ \ 4-240 

8-126. C Register Bits 00-14, Functional Schematic 8-253 



ORIGINAL 



vii 



Index 



NAVSHIPS 0967-280-4010 



FRONT MATTER 



INDEX OF ILLUSTRATIONS (CONT.J 

Figure 

8-127. C Register Bits 15-29, Functional Schematic 8-255 

8-80. C Sequence I, Functional Schematic 8-159 

8-81. C Sequence II, Functional Schematic 8-16 L 

4-22. C Sequence Timing Considerations for the Dual Comparison for 

j - 4 or 5, Timing and Events Chart 4-55 

6-67. Current Diverter, Module Type 2190, Electrical Schematic .... 6-76 

I) 

4-49. Decimal Square Root Extraction 4 " 1 '?^ 

4-50. Decimal Square Root Extraction, Simplified Example 4-132 

6-89! Delay Line Driver, Module Type 2430, Electrical Schematic .... 6-98 

6-9. Digit Current Waveform 6-13 

6-113. Digit Generator - A, Module Type 2550, Electrical Schematic . . . 6-122 

6-llfi! Digit Generator - B, Module Type 2560, Electrical Schematic . . . 6-124 
6-109. Digit Timing Amplifier - A, Module Type 2530, Electrical 

Schematic 6-118 

6-111. Digit Timing Amplifier - B, Module Type 2540, Electrical 

Schematic 6-120 

4-85. Diode Board, Top View 4-214 

4-54. DL Shift for Square Root, Simplified Diagram 4-137 

8-4. D Register Bits 00-09, Functional Schematic . 8-7 

8-5. D Register Bits 10-19, Functional Schematic 8-9 

8-6. D Register Bits 20-29, Functional Schematic 8-11 

8-42. D Register Control, Functional Schematic 8-83 

E 

8-147. EF Active-Monitor Flip-Flops and Interrupt Generator, 

Functional Schematic 9-93 

8-153. EF Active-Monitor Flip-Flops and Monitor Generator, Functional 

Schematic 8-307 

8-155. EF Request and Special Priority Scan, Functional Schematic . . , 8-311 

8-150. EI Request Monitor, Active and Request FF's 8-301 

3- 13. Example of Bioctal Paper Tape 3-47 

4- 68. External Interrupt Flow Diagram 4-189 

4-67 External Interrupt Request and Acknowledge, Timing and Events 

Chart 4-185 

4-69. Fault and Monitor Interrupts, Timing and Events Chart 4-193 

2-8. Female Connector, 90-Pin, Detailed View 2-13 

4-110. Film Memory, Word Drive Line Routing Diagram 4-247 

4-107. Film Spot, Magnetic Vector Rotation Diagram 4-243 

4-108, Film Spot, Switching Diagram 4-244 

4-55. Final D'Rl — > Q Transmission for Square Root, Simplified 

Diagram 4-137 

6-29. Flip-Flop, Module Type 2000, Electrical Schematic 6-38 

6-33. Flip-Flop, Module Type 2020, Electrical Schematic 6-42 

6-105. Flip-Flop, Module Type 2510, Electrical Schematic 6-114 

4-56. Formation of Logical Product, Simplified Schematic and Truth 

Table 4-141 



viii 



ORIGINAL 



FRONT MATTER 



NAVSHIPS 0967-280-4010 



Index 



INDEX OF ILLUSTRATIONS ( CONT . ) 



Figure 

4-47. 
8-56. 
8-57. 
8-58. 
8-59. 
8-60. 
8-61. 
8-62. 
8-63. 
4-30. 
4-25. 

4-20. 
4-21. 
8-38. 



4-9. 



4-61. 



8-151, 

8-152. 

6-85. 

6-2. 

8-105, 

8-106. 

6-71. 

8-158. 

8-128. 

8-129. 

8-130. 

8-131. 

8-132. 

4-65. 

4-66. 

2- 3. 

3- 5, 

4- 62. 
4-5. 

2- 2. 
8-32. 
6-135. 

3- 11. 



Four Typical Subtractor Stages, Simplified Schematic . . . . 

f Translator I, Functional Schematic 

f Translator II, Functional Schematic 

f Translator III, Functional Schematic 

f Translator IV, Functional Schematic 

f Translator V, Functional Schematic 

f Translator VI, Functional Schematic 

f Translator VII, Functional Schematic 

f Translator VIII, Functional Schematic 

f = 00, 77, 66, 67, Abort Skip, Timing Chart 

f = 00, 77, 66, 67, and f = Jump Abort, Timing and Events 

Chart 

f = 04, Evaluation of Y — >X, Simplified Schematic 

f = 04, Final Skip Evaluation, Simplified Schematic . . . . 
f = 60-65 Abort Check, Functional Schematic 

G 

Generalized j Translator 

H 

High-Speed Interface Timing Chart 

I 

ID Active-Monitor Flip-Flops and ID Interrupt Generators, 

Functional Schematic 

ID/EI Request Gates and One-Shots, Functional Schematic . . 
Impedance Matching, Module Type 2410, Electrical Schematic . 

Inhibit Current Waveform 

Inhibit Selection, Functional Schematic 

Inhibit Selection, Functional Schematic 

Inhibit Switch, Module Type 2210, Electrical Schematic . . . 

Input Data Acknowledge, Timing and Requests 

Input Data Gates 00-05, Functional Schematic 

Input Data Gates 06-11, Functional Schematic 

Input Data Gates 12-17, Functional Schematic 

Input Data Gates 18-23, Functional Schematic 

Input Data Gates 24-29, Functional Schematic 

Input Data Mode Flow Diagram .- • . . 

Input Data Request and Acknowledge, Timing and Events Chart 
Input/Output Connectors (Top of Computer) Jack Orientation 

Diagram 

Input/Output Instruction Word Format 

Input/Output Section, Block Diagram . 

Instruction Word Format 

In terassembly Plug Rack, Diagrams of Plug Orientation . . , 

Interchange AQ, CPl, and CP2, Functional Schematic 

Intercomputer Channel Selector, Module Type 2660, Electrical 

Schematic 

Inter-Computer Bootstrap Program 



Page 

4-113 
8-111 
8-113 
8-115 
8-117 
8-119 
8-121. 
8-123 
8-125 
4-75 

4-63 
4-51 
4-52 
8-77 



4-22 



4-153 



8-303 
8-305 

6-94 
6-5 
8-209 
8-210 

6-80 
8-317 
8-257 
8-259 
8-261 
8-263 
8-265 
4-177 
4-179 

2-7 

3- 16 
4-162 

4- 13 

2-4 

8-63 

6-144 
3-44 



ORIGINAL 



IX 



Index 



NAVSHIPS 0967-280-4010 



FRONT MATTER 



INDEX OF ILLUSTRATIONS (CONT.) 



Figure Page 

3-12. Inter-Computer Bootstrap Program Flow Chart 3-45 

3- 10. Inter-Computer Bootstrap Program Record Format 3-43 

4- 59. Interface Cabling 4-148 

6-121. Interface Inverter, Module Type 2590, Electrical Schematic .... 6-130 

4-15. Interrupt Considerations for Return to Main Program, Events Chart . . 4-42 

4-38. Intersection Carry Input Stage for Section III, Simplified 

Schematic 4-90 

6-35. Inverter, Module Type 2030, Electrical Schematic 6-44 

6-37. Inverter, Module Type 2040, Electrical Schematic 6-46 

6-39. Inverter, Module Type 2050, Electrical Schematic . . 6-48 

6-41. Inverter, Module Type 2060, Electrical Schematic 6-50 

6-43. Inverter, Module Type 2070, Electrical Schematic 6-52 

6-45. Inverter, Module Type 2080, Electrical Schematic 6-54 

6-47. Inverter, Module Type 2090, Electrical Schematic 6-56 

6-61. Inverter, Module Type 2160, Electrical Schematic 6-70 

6-107. Inverter, Module Type 2520, Electrical Schematic 6-116 

8-137. I/O Control I, Functional Schematic 8-275 

8-138. I/O Control II, Functional Schematic 8-277 

8-139. I/O Control III, Functional Schematic 8-279 

8-140. I/O Control IV, Functional Schematic 8r28l 

8-141. I/O Translator, Section 1, Functional Schematic 8-283 

8-142. I/O Translator, Section 2, Functional Schematic 8-285 

8-143. I/O Translator Group Drivers I, Channels 0, 4, 10, 14, 

Functional Schematic 8-287 



8-144. I/O Translator Group Drivers II, Channels 1, 5, 11, 15, 
Functional Schematic 

8-145. I/O Translator Group Drivers III, Channels 2, 6, 17, 16, 
Functional Schematic 

8-146. I/O Translator Group Drivers IV, Channels 3, 7, 13, 17, 
Functional Schematic « 



J 

8-64. j Designator and Translator, Functional Schematic 8-131 

K 

8-65. k Designator and Translator, Functional Schematic 8-133 

8-16. Kl and K2 Register K Adder, Functional Schematic 8-131 

8-17. K3 Register, Functional Schematic 8 ~33 

L 

6-139. Line Capacitance Charger - A, Module Type 2740, Electrical 

Schematic . 6 ~ 148 

6-141. Line Capacitance Charger - B, Module Type 2750, Electrical 

Schematic ••••« • * 6—150 

4-117. Logic Chassis AS, Location of Program i/Program II Toggle Switch . . . 4-257 

8-1. Logic Symbology ♦ 

4-6. Lowest Level Function Code Translation 4-lt> 

4-60. Low-Speed Interface Timing Chart . 4-151 



x 



ORIGINAL 



FRONT MATTER 



NAVSHIPS 0967-280-4010 



Index 



INDEX OF ILLUSTRATIONS (CONT.) 

Pa^e 

4-45. Low-Speed Oscillator, Simplified Schematic 4-108 

6-21. Low-Speed Variable Oscillator, Module Type 0210, Electrical 

Schematic , 6-30 

M 

4-91. Magnetic Core Plane (16 x 16 Array), Simplified Diagram 4-221 

4- 76. Magnetic Cores, Intersection of Lines 4-206 

3-8. Magnetic Tape Bootstrap Program 3-38 

3-9. Magnetic Tape Bootstrap Program Flow Chart . . 3-39 

3- 7. Magnetic Tape Bootstrap Program Record Format 3-37 

5- 4. Main Memory, Abnormal Waveforms . P \ t 5-19 

4- 72. Main Memory Block Diagram 4-201 

5- 3. Main Memory, Typical Waveforms 5-17 

4-10. Main Timing and Sequence Control, Timing Relationship Chart . . [ 4-30 

8-75. Main Timing, Final, Functional Schematic 8-149 

8-72. Main Timing, Initial I, Functional Schematic ] 8-143 

8-73. Main Timing, Initial II, Functional Schematic 8-145 

8-74. Main Timing, Initial III, Functional Schematic \ 8-147 

6- 18. Main Power Supply 6-23 

8-177. Main Power Supply, Functional Schematic 8-355 

8-136. Main Priority II (Channel Translation), Functional Schematic . . \ 8-273 

8-135. Main Priority I, Functional Schematic 8-271 

2-7. Male Connector, 90-Pin, Detailed View \ \ \ \ 2-12 

4-42. Master Clock Fast Speed Connections, Simplified Schematic .... 4-97 

8-83. Master Clock, Functional Schematic 8-165 

4-41. Master Clock, Normal Connections, Simplified Schematic 4-96 

4-40. Master Clock Outputs, Idealized Waveforms 4-95 

4-43. Master Clock, Simplified Timing Chart 4-98 

4-94. Memory Address Translation Block Diagram \ \ 4-224 

4-77. Memory Board, Wiring Layout Diagram \ 4-206 

4-84. Memory Center Board, Bottom View * * 4-212 

4-83. Memory Center Board, Top View \ \ \ 4-211 

8-175. Memory Chassis, Chassis Map \ 3.35! 

8-108. Memory Control, Functional Schematic 8-215 

4-86. Memory Core Stack 4-215 

4-74 . Memory Core Stack Diagram . 4-204 

4-75. Memory Core Stack, Upper Level, Exploded View ] \ \ . \ 4-205 

4-101. Memory Diverter Circuit, Simplified Schematic 4-234 

4-100. Memory Inhibit Translation (S12, S13, S14) , Simplified 

Schematic „ 4-232 

4-78. Memory Plane Quadrant Designations 4-207 

4-93 c Memory Plane (128 x 128 Array), Bottom View 4^223 

4-92. Memory Plane (128 x 128 Array), Top View 4-222 

4-80. Memory Quadrant (64 x 64 Array), Bottom View 4-209 

4-79. Memory Quadrant (64 x 64 Array), Top View 4-208 

4-97. Memory Secondary Selection, Simplified Schematic 4-228 

4- 73. Memory Section e 4-202 

5- 2. Memory Timing Cycle, Idealized Timing Waveform 5-7 

5- 1. Module Extender Schematic . 5.2 

6- 22. Module Type 0210 Component Layout 6-31 

6-24. Module Type 1110 Component Layout 6-33 



ORIGINAL 



xi 



Index NAVSHIPS 0967-280-4010 FRONT MATTER 



INDEX OF ILLUSTRATIONS (CONTJ 

Figure Page 

6-26. Module Type 1120 Component Layout 6-35 

6-28. Module Type 1200 Component Layout 6-37 

6-30. Module Type 2000 Component Layout 6-39 

6-32. Module Type 2011 Component Layout 6-41 

6-34. Module Type 2020 Component Layout 6-43 

6-36. Module Type 2030 Component Layout 6-45 

6-38. Module Type 2040 Component Layout 6-47 

6-40 . Module Type 2050 Component Layout 6-49 

6-42. Module Type 2060 Component Layout 6-51 

6-44. Module Type 2070 Component Layout 6-53 

6-46. Module Type 2080 Component Layout 6-55 

6-48. Module Type 2090 Component Layout 6-57 

6-50. Module Type 2100 Component Layout 6-59 

6-52. Module Type 2110 Component Layout 6-61 

6-54. Module Type 2120 Component Layout 6-63 

6-56. Module Type 2130 Component Layout 6-65 

6-58. Module Type 2140 Component Layout 6-67 

6-60. Module Type 2150 Component Layout 6-69 

6-62. Module Type 2160 Component Layout 6-71 

6-64. Module Type 2170 Component Layout 6-73 

6-66. Module Type 2180 Component Layout 6-75 

6-68. Module Type 2190 Component Layout 6-77 

6-70. Module Type 2200 Component Layout 6-79 

6-72. Module Type 2210 Component Layout 6-81 

6-74. Module Type 2350 Component Layout 6-83 

6-76. Module Type 2360 Component Layout 6-85 

6-78. Module Type 2370 Component Layout 6-87 

6-80. Module Type 2380 Component Layout 6-89 

6-82. Module Type 2390 Component Layout 6-91 

6-84. Module Type 2400 Component Layout 6-93 

6-86, Module Type 2410 Component Layout 6-95 

6-88. Module Type 2420 Component Layout 6-97 

6-90. Module Type 2430 Component Layout 6-99 

6-92, Module Type 2440 Component Layout 6-101 

6-94. Module Type 2450 Component Layout 6-103 

6-96. Module Type 2460 Component Layout 6-105 

6-98. Module Type 2470 Component Layout 6-107 

6-100. Module Type 2480 Component Layout 6-109 

6-102. Module Type 2490 Component Layout 6-111 

6-104. Module Type 2500 Component Layout 6-113 

6-106. Module Type 2510 Component Layout 6-115 

6-108. Module Type 2520 Component Layout 6-117 

6-110. Module Type 2530 Component Layout 6-119 

6-112. Module Type 2540 Component Layout 6-121 

6-114. Module Type 2550 Component Layout 6-123 

6-116. Module Type 2560 Component Layout 6-125 

6-118. Module Type 2570 Component Layout 6-127 

6-120. Module Type 2580 Component Layout 6-129 

6-122. Module Type 2590 Component Layout 6-131 

6-124. Module Type 2600 Component Layout 6-133 

6-126. Module Type 2610 Component Layout 6-135 

xii ORIGINAL 



FRONT MATTER 



NAVSHIPS 0967-280-4010 



Index 



INDEX OF ILLUSTRATIONS (CONT.) 



Figure 
6-128. 



Page 



~ mv/wwj.^ ijjjc jyj ^uinpunuiiL Layout ...... A iAi 

6-154. Module Type 3180 Component Layout .... a ia/* 

5-6. MROT Test Setup, Cabling Diagram WWW'' 5-23 

8-35. Multiply/Divide/Square Root I, Functional Schematic' WWW 8-69 

8-36. Multiply/Divide/Square Root II , Functional Schematic 8-71 



N 

6-63. Negative Switch, Module Type 2170, Electrical Schematic . 6-72 
4-26. Normal Abort, Skip Next Instruction, Timing and Events Chart ' ' 4-65 

4-51. Normal Binary Square Root Extraction, Simplified Example . . . 4-133 
6-133. Normal Channel Selector, Module Type 2650, Electrical 

Schematic 6-142 

3-4. Normal Instruction Word Format . \ . Z K 
8-170, M 1 T • - • -- d-lb 



~ Normal I/O Chassis, Chassis Map 8-341 

8-165. Normal I/O Chassis Clock Drivers, Functional Schematic WWW 8-331 

8-168. Normal I/O Chassis Clock Drivers, Functional Schematic . ' ' 8-335 
6-137. Normal Speed I/O Selector, Module Type 2720, Electrical 

Schematic 6-146 

4-29. Normal Use of Di/Df, Timing Chart* ."!!!!!!!!!!!!!;.' 4-73 



8-148. OD Active-Monitor Flip-Flops and Interrupt Generator, 

Functional Schematic 8-297 

8-154. OD Active-Monitor Flip-Flops and Monitor Generator, 

Functional Schematic 8-305 

8-149. OD/EF One Shots, Request and Subpriority Gates' Functional' 

Schematic 8-299 

8-156. OD Requests and Resume, Functional Schematic ..."!*!!!** 8-313 

8-157. OD Requests, Functional Schematic '*!!"!' 8-315 

8-159. Output Data Acknowledge Timing and Requests, Functional 

Schematic 8-317 

4-64. Output Data and External Function Request and Acknowledge 

(Ready) , Timing and Events Chart 4-169 

4-63. Output Data and External Function Mode Flow Diagram WWW. \ \ 4-167 



ORIGINAL 



xiii 



Index 



NAVSHIPS 0967-280-4010 



FRONT MATTER 



INDEX OF ILLUSTRATIONS (CONT.) 

Figure Page 

P 

3-15. Paper Tape Bootstrap Program 3-49 

3- 14. Paper Tape Bootstrap Program Flow Chart 3-48 

4- 57. Parity Formation, Simplified Diagram 4-143 

8-31. Parity, Functional Schematic . . 8-61 

4-58. Parity Input Stage, Simplified Schematic 4-143 

4-8. Partial j Translation (j = 10 or 7), Simplified Schematic .... 4-21 
6-65. Positive and Negative Switch, Module 2180, Electrical 

Schematic 6-74 

8-176. Power Control, Functional Schematic 8-353 

8-54. P Register Bits 00-14, Functional Schematic 8-107 

1-3. Printed Circuit Module Front and Rear Views 1-5 

3- 6. Programming Symbols 3-29 

6-79, Pulse Delay - A, Module Type 2380, Electrical Schematic 6-88 

6-77. Pulse Delay - B , Module Type 2370, Electrical Schematic 6-86 

6-75. Pulse Delay Network - 1 usee, Module Type 2360, Electrical 

Schematic 6-84 

6-73. Pulse Delay Network - 3 usee, Module Type 2350, Electrical 

Schematic 6-82 

6-87. Pulse Reset Amplifier, Module Type 2420, Electrical 

Schematic 6-96 

fl 

8-14. Q Register Bits 00-14, Functional Schematic 8-27 

8-15. Q Register Bits 15-29, Functional Schematic 8-29 

8-45. Q Register Control, Functional Schematic 8-89 

R 

8-82. r Designator, Functional Schematic 8-163 

4- 88. Read/Restore a "0", Hysteresis Loop of Core 4-217 

4-87. Read/Restore a "l", Hysteresis Loop of Core 4-216 

6-69. Read-Write Switch, Module Type 2200, Electrical Schematic .... 6-78 

8-33. Read Y and Store Y Subsequences, Functional Schematic 8-65 

4-16. Read Y Considerations for f = 10-13, 20-27, 40-46, 50-52, 

54, 56, 60-67, 72-76; Timing and Events Chart 4-43 

4-17. Read Y Considerations for f = 30-35, 53, 57; Timing and 

Events Chart ..... 4-44 

4-18. Read Y Considerations for f = 71 ; Timing and Events Chart .... 4-45 
8-161. Ready/OD Acknowledge, Timing and Control, Functional 

Schematic 8-323 

6-143. Real-Time Clock Oscillator, Module Type 2760, Electrical 

Schematic 6-152 

4-71. Real-Time Clock Request Flow Diagram 4-197 

4- 70. Real-Time Clock Request, Timing and Events Chart 4-195 

5- 8. Regulated Primary Power Distribution Diagram 5-40 

4-33. Repeat Mode, Timing Chart 4_ j3l 

8-114. Reset, Functional Schematic 8-229 



xiv 



ORIGINAL 



FRONT MATTER NAVSHIPS 0967-280-4010 Index 

INDEX OF ILLUSTRATIONS (CONT.) 



6-23. Resistor Assembly #6, Module Type 1110, Electrical 

Schematic 6-32 

6-25. Resistor Assembly #7, Module Type 1120, Electrical 

Schematic 6-34 

8-164. Resume Sequence, Buffer Terminate Time-Out Monitor and 

Fault FF's, Functional Schematic 8-329 

8-65. R Register Bits 00-14, Functional Schematic 8-109 

S 

6-27. Select Fast/Normal Clock Switch Unit, Module Type 1200, 

Electrical Schematic 6-36 

8-18. Selector SI (SI Sel) 00-09, Functional Schematic* 8-35 

8-19. Selector SI (SI Sel) 10-19, Functional Schematic 8-37 

8-20. Selector SI (SI Sel) 20-29, Functional Schematic 8-39 

8-21. Selector S2 (S2 Sel) 00-09, Functional Schematic 8-41 

8-22. Selector S2 (S2 Sel) 10-19, Functional Schematic 8-43 

8-23. Selector S2 (S2 Sel) 20-29, Functional Schematic 8-45 

8-24. Selector 1 and 2 (Misc), Functional Schematic 8-47 

6-117. Sense Amplifier - A, Module Type 2570, Electrical 

Schematic 6-126 

6-119. Sense Amplifier - B, Module Type 2580, Electrical 

Schematic 6-128 

6-147. Sense Amplifier, Module Type 2850, Electrical Schematic . . . 1 ] 6-156 

8-107. Sense Amplifier Outputs, Functional Schematic 8-213 

6-6. Sense Amplifier Outputs Waveform 6-7 

6-15. Sense Amplifier Reset and Sense Output Waveforms 6-15 

8-71. Sequence Control, Functional Schematic 8-141 

4-13. Sequence Control, Main Timing and Af Bf and C Sequences, 

Timing Chart 4-36 

8-34. Shift Control, Functional Schematic 8-67 

4-27. Short Read or Store, Timing Chart 4-67 

4-34. Simplified Adder Operation (Six Bits), Typical Example 4-84 

6-12, Single Address Sense Output Waveforms 6-14 

4-31. Skip Next Instruction, Timing Chart 4-77 

8-169 Special I/O Chassis, Chassis Map 8-339 

8-166. Special I/O Chassis Clock Drivers, Functional Schematic 8-333 

8-167. Special I/O Chassis Clock Drivers, Functional Schematic 8-335 

4-53. Square Root Extraction, Simplfied Timing Chart 4-136 

6-14. Strobe and Sense Output Waveforms 6-15 

8-113. Strobe, Functional Schematic 8-225 

6-91. Strobe Pulse Amplifier, Module Type 2440, Electrical 

Schematic 6-100 

6-5. Strobe Pulse and "l" Output Timing Waveform 6-6 

• 6-95. Strobe Pulse Shaper - A, Module Type 2460, Electrical 

Schematic 6-104 

6-97. Strobe Pulse Shaper - B, Module Type 2470, Electrical 

Schematic . . . c 6-106 

8-97. S Register Bits 00-05, Functional Schematic 8-193 

8-98. S Register Bits 06-11, Functional Schematic 8-195 

8-99. S Register Bits 12-14, Functional Schematic 8-197 

ORIGINAL xv 



Index 



NAVSHIPS 0967-280-4010 



FRONT MATTER 



INDEX OF ILLUSTRATIONS (CONT.) 

Figure Page 

8-133. Subpriority I, Functional Schematic 8-267 

8-134. Subpriority II, Functional Schematic 8-269 

8-109. S0 Register (Bits 0-2) Word Transformer Selection, 

Functional Schematic 8-217 

8-110. S0 Register (Bits 3-6) Word Current Selection, 

Functional Schematic 8-219 

8-121. S0 Selector, Functional Schematic . . . . 8-243 

8-46. SI Selector Control, Functional Schematic 8-91 

8-47. S2 Selector Control, Functional Schematic 8-93 

i 

4-106. Thin-Film Plane, Exploded View 4-241 

4-103. Thin-Film Stack, Bottom View . 4-238 

4-102. Thin-Film Stack, Top View 4-237 

4-104. Thin-Film Stack with Unifluxor Plane, Exploded View 4-239 

6-125. Transformer Assembly &l f Module Type 2610, Electrical 

Schematic 6-134 

6-127. Transformer Assembly #2, Module Type 2620, Electrical 

Schematic 6-136 

6-129. Transformer Assembly #3, Module Type 2630, Electrical 

Schematic 6-138 

4-96. Transformer Selection, Simplified Schematic 4-227 

6-81. Transformer Selector - A, Module Type 2390 t Electrical 

Schematic 6-90 

6-83. Transformer Selector - B, Module Type 2400, Electrical 

Schematic 6 " 92 

4-95. Translation of X Primary Selector S14, S13, Simplified 

Schematic 4-226 

6-145. Tuning Fork Unit, 1.024 KC, Module Type 2770, Electrical 

Schematic 6-154 

4-39. Typical Adder Output Stage, Simplified Schematic 4-91 

4-35. Typical Adder Stages, Simplified Schematic 4-85 

1-4. Typical Input/Output Chassis 1-6 

4-7, Typical j Translation (j = 6 or 7) , Simplified Schematic .... 4-20 

4-81. Typical Magnetic Core, Inhibit Line X Oriented 4-210 

4-82. Typical Magnetic Core, Inhibit Line Y Oriented 4-210 

U 

4- 113. Unifluxor Plane, Exploded View 4-253 

3-2. U Register Bits for Manual Reading and Writing 3-11 

8-48. U Register Bits 00-09, Functional Schematic 8-95 

8-49. U Register Bits 10-14, Functional Schematic 8-97 

8-50. U Register Bits 15-19, Functional Schematic 8-99, 

8-51. U Register Bits 20-24, Functional Schematic 8-101 

8-52. U Register Bits 25-29, Functional Schematic 8-103 

5- 7. Unregulated Primary Power Distribution Diagram 5-39 



ORIGINAL 



FRONT MATTER NAVSHIPS 0967-280-4010 INDEX 

INDEX OF ILLUSTRATIONS (CONT.) 
Figure page 

V 

6-131. Voltage Regulator, +10V, Module Type 2640 t Electrical 

Schematic 6-140 

6-123. Voltage Regulator, -7V, Module Type 2600, Electrical 

Schematic 6-132 

6-149. Voltage Sensor, +15V and -15V, Module Type 2880, 

Electrical Schematic 6-158 

6-151, Voltage Sensor, -4.5V and Switch, Module Type 2890, 

Electrical Schematic 6-160 

W 

6-11. Word and Digit Current Timing Waveforms 6-14 

6-10. Word and Digit Current Waveforms 4 6-14 

6-103. Word Current Diverter, Module Type 2500, Electrical 

Schematic 6-112 

6-99. Word Current Generator - A, Module Type 2480, Electrical 

Schematic 6-108 

6-101. Word Current Generator - B f Module Type 2490, Electrical 

Schematic 6-110 

6-93. Word Current Translator, Module Type 2450, Electrical 

Schematic 6-102 

6-8. Word Current Waveform 6-13 

8-112. Word Line Selector (Bootstrap), Functional Schematic 8-225 

8-111. Word Line Selectors and Drivers (Control Memory), 

Functional Schematic 8-221 

6-7. Word Transformer Selector Waveforms 6-12 

8-11. W Register Bits 00-09, Functional Schematic 8-21 

8-12. W Register Bits 10-19, Functional Schematic 8-23 

8-13. W Register Bits 20-29, Functional Schematic 8-25 

8-44. W Register Control, Functional Schematic 8-87 

4-89. Write to a "0" from a "1", Hysteresis Loop of Core 4-219 

4-90. Write to a "1" from a "0", Hysteresis Loop of Core 4-220 

X 

4-98. X Line Selector Translation (S09, S10, Sll), Simplified 

Schematic , 4-230 

6-3. X Read/Write Current Waveform 6-5 

8-7. X Register Bits 00-09, Functional Schematic 8-13 

8-8. X Register Bits 10-19, Functional Schematic 8-15 

8-9. X Register Bits 20-24, Functional Schematic 8-17 

8-10. X Register Bits 25-29, Functional Schematic 8-19 

8-43. X Register Control, Functional Schematic 8-85 

8-103. X Translation, Functional Schematic . . . 8-205 

Y 

6-4. Y Read/Write Current Waveform 6-6 

8-104. Y Translation, Functional Schematic 8-207 

ORIGINAL xvii 



Index NAVSHIPS 0967-280-4010 FRONT MATTER 



INDEX OF ILLUSTRATIONS (CONT.) 

Figure Page 

Z 

8-95. Z Register Bits 00-14, Functional Schematic 8-189 

8-96, Z Register Bits 15-29, Functional Schematic 8-191 

8-100. Z Register Gates 00-09, Functional Schematic 8-199 

8-101. Z Register Gates 10-19, Functional Schematic .... 8-201 

8-102. Z Register Gates 20-29 t Functional Schematic 8-203 

8-116. Z0 Register Bits 00-05 and Sense Amplifiers, Functional 

Schematic 8-223 

8-117. Z0 Register Bits 06-11 and Sense Amplifiers, Functional 

Schematic 8-235 

8-118. Z0 Register Bits 12-17 and Sense Amplifiers, Functional 

Schematic 8-237 

8-119. Z0 Register Bits 18-23 and Sense Amplifiers, Functional 

Schematic 8-239 

8-120. Z0 Register Bits 24-29 and Sense Amplifiers, Functional 

Schematic 8-241 

8-122. Z0 Selector 1 Bits 00-14, Functional Schematic 8-245 

8-123. Z0 Selector 1 Bits 15-29, Functional Schematic 8-247 

8-124. Z0 Selector 2 Bits 00-14, Functional Schematic 8-249 

8-125. Z0 Selector 2 Bits 15-29, Functional Schematic 8-251 



xviii 



ORIGINAL 



FRONT MATTER NAVSHIPS 0967-280-4010 Tables 

LIST OF TABLES 
SECTION 1 
GENERAL INFORMATION 

Table Page 

1-1. Computer Operational Characteristics 1-2 

1-2. Quick Reference Data 1-13 

1-3. Equipment Supplied 1-15 

1-4. Equipment and Publications Required But Not Supplied 1-15 

1-5, Equipment Similarities 1-17 

1- 6. Module Complement 1-18 

SECTION 2 
INSTALLATION 

2- 1. Cabinet Input/Output Connectors 2-1 

2-2. Input/Output Cable Characteristics 2-6 

2-3. Connector Pin Assignments 2-15 

2- 4. Wire Assignment for Digital Data Cable 2-18 

SECTION 3 
OPERATOR'S SECTION 

3- 1. Summary of Operator Control Functions 3-2 

3-2. Summary of Functions of the START-STEP RESTART Switch 3-8 

3-3. Block Transfer Subroutine 3-13 

3-4. Instruction Repertory and Instruction Execution Time 3-33 

3- 5. Inter-Computer Request-Reply Logic 3-42 

SECTION 4 
PRINCIPLES OF OPERATION 

4- 1. Summary of Main Timing and Sequence Functions 4-14 

4-2. Summary of j Circuits and j Translations . 4-19 

4-3 f Summary of Conditions Affecting Sequence Control Flip-Flops .... 4-33 

4-4. Initiation Times of Read Y Sequence 4-47 

4-5. Interchange AQ Initiation Times ... 4-48 

4-6. Commands Generated by the AQ Interchange Subsequence 4-48 

4-7. Summary of the Y < (A) or Y > (A) Evaluation for f = 04 4-51 

4-8. Timing Enables to Set the Abort Flip-Flop 4-60 

4-9. Instruction Execution Times . 4-71 

4-10. Summary of Control Adder Functions 4-82 

4-11. HA Information by 30R-- 4-84 

4-12. Summary of Intersection Carry Enable Logic 4-91 

4-13. Summary of Adder Output Stage 4-91 

4-14. Typical Adder Problem, Circuit Outputs 4-94 

4-15. Summary of Timing Inputs to the Start Flip-Flop 4-103 

4-16. Summary of Start-Step/Restart Functions * * 4-105 

4-17. Subtractor Input Combinations and HS Results 4-111 

ORIGINAL xix 



Tables 



NAVSHIPS 0967-280-4010 



FRONT MATTER 



LIST OF TABLES (CONTJ 

Table Page 

4-18. Summary of Subtractor Borrow Status Signals 4-115 

4-19. Summary of Subtractor Section Borrow Enable Circuits 4-116 

4-20 . Summary of Arithmetic Subtractor Circuit Functions 4-118 

4-21. Summary of Subtractor Circuit Outputs 4-119 

4-22. Multiply Sequence, Initial Sign Correction Timing 4-122 

4-23. Multiply Step Timing if Multiplier Bit = 4-124 

4-24. Multiply Step Timing if Multiplier Bit = 1 4-125 

4-25. Multiply Termination Timing 4-126 

4-26. Divide Step, Summary of Timed Operations 4-129 

4-27. Final Sign Correction Timing for Division 4-130 

4-28. Summary of Shift Counts Versus Shift Operations 4-139 

4-29. Truth Tables for Input Stage of Parity Checker 4-142 

4-30. Computer Memory Assignment 4-146 

4-31. I/O Functional Areas 4-160 

4-32. Functional Schematic "g" Translation ... 4-163 

4-33. Input/Output Timing and Control-Scan 4-165 

4-34. Input/Output Timing and Control-External Function or Output 

Mode . 4-166 

4-35. Input/Output Timing and Control-Input Mode 4-175 

4-36. Input/Output Timing and Control-External Interrupt Mode .... 4-176 
4-37. Input/Output Timing and Control-Monitor Interrupts and Fault 

Monitor 4-191 

4-38. Input/Output Timing and Control - Real-Time Clock Request .... 4-192 

4- 39. Film Spot Output Polarity of Control Memory 4-248 

SECTION 5 
TROUBLESHOOTING 

5- 1. Test Equipment and Special Tools 5-3 

5-2. Bit Associated Circuits and Circuits Locations 5-9 

5-3. Master Clock Delay Module FAST/NORMAL Locations 5-32 

5-4. Main Power Supply Characteristics 5-37 

5- 5. Console Power Supply Characteristics 5-38 

SECTION 6 
REPAIR 

6- 1. Nominal Memory Current Values 6-3 

6-2. Memory Test Points 6-4 

6-3. Word Current Test Points 6-10 

6-4. Strobe and Sense Output Pin Numbers 6-11 

6-5. Wire Wrapping Information 6-28B 

6-6. Core Stack Wiring Terminations 6-25 



xx 



ORIGINAL 



FRONT MATTER 



NAVSHIPS 0967-280-4010 



Tables 



LIST OF TABLES (CONT.) 
SECTION 7 
PARTS LIST 

Table Page 

7-1. Digital Data Computer CP-642B/USQ-20(V) Maintenance 

Parts List 7-2 

7-2. Digital Data Computer CP-642B/USQ-20(V) Module 

Parts List 7-156 

7-3. Digital Data Computer CP-642B/USQ 20(V) List of Manufacturers . . 7-231 

SECTION 9 
WIRE TABULATIONS 

9-1. Mating Connectors Cross Reference 9-10 

9-2, Input and Output Connector, Jl through J32, Pin Assignments . . . 9-11 

9-3. Normal I/O Chassis : Card Jack to Card Jack 9-14 

9-4. Normal I/O Chassis: Intassy' Jack to Card Jack . 9-63 

9-5. Normal I/O Chassis: Test Block to Card Jack . 9-87 

9-6. Special I/O Chassis: Card Jack to Card Jack 9-116 

9-7. Special I/O Chassis: Intassy Jack to Card Jack . . 9-170 

9-8. Special I/O Chassis: Test Block to Card Jack 9-194 

9-9. I/O Chassis: Power 9-227 

9-10. A5: Card Jack to Card Jack 9-229 

9-11. A5: Intassy Jack to Card Jack .................. 9-297 

9-12. A5: Test Block to Card Jack „ . . . . . 9-327 

9-13. A6: Card Jack to Card Jack ................... 9-364 

9-14. A6: Intassy Jack to Card Jack .................. 9-434 

9-15. A6: Test Block to Card Jack 9-465 

9-16. A7: Card Jack to Card Jack 9-506 

9-17. A7: Intassy Jack to Card Jack 9-578 

9-18. A7: Test Block to Card Jack 9-597 

9-19. Chassis A5 f A6.A7 Power. 9-628 

9-20. A8: Card Jack to Card Jack 9-630 

9-21. A8: Intassy Jack to Card Jack 9-666 

9-22. A8: Test Block to Card Jack 9-685 

9-23. A8: Power 9-699 

9-24. Film Stack 9-705 

9-25. A9-A13: Card Jack to Card Jack 9-718 

9-26. A9-A13: Text Block to Card Jack , 9-736 

9-27. A9-A13: Intassy Jack to Card Jack . . . 9-739 

9-28. A9-A13: Power 9-740 

9-29. Core Stack 9-742 

9-30. Console: Power 9-753 

9-31. Console: Intassy Jack to Indicators ....... 9-773 

9-32. Console: C Reg Intassy Jack to Indicators , . . 9-793 

9-33. Console: Power Supply ....... .... 9-799 

9-34. Console: Intassy Jacks to Operating Controls ...... 9-801 

9-35. C Switches and Connectors 9-804 

9-36. Left Side 9-808 

9-37. Right Side . . 9-900 

9-38. Plenum .............................. 9-970 

9-39. Power Supply ........................... 9-971 

ORIGINAL xxi/xxii 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 Contents 
GENERAL INFORMATION 

SECTION 1 
GENERAL INFORMATION 
TABLE OF CONTENTS 

Paragraph Page 

1-1. Scope 1-1 

1-2. General Description 1-1 

1-3. Functional Description .... 1-4 

.a. Instructions 1-4 

Functional Analysis 1-7 

(1) Control Section 1-7 

(2) Arithmetic Section 1-8 

(3) Memory Section 1-10 

(4) Input/Output Section 1-10 

(5) Timing Control 1-11 

£. Maintenance and Control Console 1-11 

1-4. Quick Reference Data 1-12 

1-5. Equipment Supplied 1-12 

1-6. Equipment and Publications Required But Not Supplied 1-12 

1-7. Factory or Field Changes 1-12 

1-8. Equipment Similarities 1-12 

1-9. Shipping Data 1-12 

1-10. Module Complement 1-12 

LIST OF ILLUSTRATIONS 

Figure Page 

1-1. CP-642B/USQ-20CV) Digital Data Computer 1-0 

1-2. Computer, Doors and Console Open 1-3 

1-3. Printed Circuit Module, Front and Rear Views 1-5 

1-4. Typical Input/Output Chassis 1-6 

1-5. CP-642B/USQ-20(V) Computer Block Diagram 1-9 

LIST OF TABLES 

Table Page 

1-1. Computer Operational Characteristics 1-2 

1-2. Quick Reference Data. 1-13 

1-3. Equipment Supplied 1-15 

1-4. Equipment and Publications Required But Not Supplied 1-15 

1-5. Equipment Similarities 1-17 

1-6. Module Complement 1-18 



Original ^ 



Figure 
1-1 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

GENERAL INFORMATION 




Figure 1-1. CP-642B/USQ-20CV) Digital Data Computer 

ORIGINAL 1 



CP-642B/USQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
GENERAL INFORMATION 



Paragraph 
1-1 



SECTION 1 
GENERAL INFORMATION 

1-1. SCOPE 

This Technical Manual is in effect upon receipt. Extracts from this publication 
may be made to facilitate the preparation of other Department of Defense publications. 

1-2. GENERAL DESCRIPTION 

This manual describes the Digital Data Computer, CP-642B/USQ-20(V) (figure 1-1). 
The computer is a general purpose, stored program, real-time, digital computer 
capable of processing a large quantity of complex data where heavy input/output 
communication is required. Major operational characteristics of the computer are 
listed in table 1-1. 

The computer is suitable for such real-time applications as missile guidance, 
range safety, process monitoring, and tactical control and display. It may be con- 
nected simultaneously to a variety of military-qualified or commercial peripheral 
equipments. These include: 

Teletypewriter units 

Magnetic tape units 

High-speed printer units 

Card read/punch units 

Display and display interface equipment 

Radar and radar adaption interfaces 

Paper tape units 

Manual entry devices 

The computer is also capable of communicating with a wide variety of other manu- 
facturers' asynchronous external devices in real-time applications. In addition to 
the peripheral equipment listed, other compatible peripheral equipment include: 
video processors, various types of displays, digital-to-analog converters, analog- 
to-digital converters, X-Y plotters, and high-speed radio transmission links. 

The computer is housed in a single cabinet, 37 inches deep, 38.5 inches wide, and 
72 inches high. Thirteen chassis trays, seven logic, one control memory, and five 
main memory are horizontally mounted within the cabinet (figure 1-2). 

Interconnections between computer chassis are by jacks mounted on the chassis and 
by movable plug racks. Connections between the computer and other equipment are by 
jacks mounted on the top of the computer. 

Logic modules (figure 1-3) are encapsulated printed circuit modules which plug into 
the chassis trays (figure 1-4). Maintenance test points are located at the front of 
the trays. 

Computer cabinet doors, closed during normal operation, can be opened for mainten- 
ance. The maintenance and control panel, built into the upper part of the cabinet, 
contains register indicators, set and clear pushbuttons, and operating switches. 



ORIGINAL 



1-1 



Table 
1-1 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

GENERAL INFORMATION 



TABLE 1-1. COMPUTER OPERATIONAL CHARACTERISTICS 



ITEM 


CHARACTERISTICS 


Word Length 
Programs 


30 bits or 15-bit half-words 
internally stored and data parity 
checking 


Instruction 


62 single address instructions with 
provisions for address modification 
via seven index registers 


Arithmetic 


Parallel ones complement, subtractive 


Input/Output 


4, 8 t 12 or 16 input/output channels 
with provision for Highspeed or 
Lowspeed Interface (Lowspeed supplied) 


Memories 
Main 


Four microsecond cycle time storage of 
32,672 30-bit words 


Control 


Thin film magnetic with a cycle time 
of 667 microseconds and capacity of 
64 words 


NDRO 


Two Unifluxor* memories with a cycle 

L.HHC ui uui JidiiUocOUiiUa ailu a dapdClLy 

of 32 words 


Real-Time Clock 


Internal seven day with provisions 
for an external real time clock 



*Trademark of the Western Electric Company 



1-2 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER 
GENERAL INFORMATION 



NAVSHIPS 0967-280-4010 



Figure 
1-2 



CONSOLE 



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MAIN POWER SUPPLY 



ORIGINAL 



Figure 1-2. Computer, Doors and Console Open 



1-3 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(v) COMPUTER 

GENERAL INFORMATION 

The computer requires 400 cycle, three-phase, 115 volt regulated power for the 
logic circuits and 400 cycle, three-phase unregulated power for the blower motors. 

The computer is equipped with a water-cooled heat exchanger and plenum assembly 
where ambient air is drawn over the heat exchanger fins and then cools the logic 
drawers. Inter equipment cabling enters the computer at the top of the cabinet and 
may be run either overhead or through floor ducts. 

The computer is designed and constructed to withstand severe shock and vibration. 
It may be installed aboard ship or in a trailer without modification. 

1-3. FUNCTIONAL DESCRIPTION 

a.. INSTRUCTIONS. - A large repertory of instructions (table 3-4) provides the 
means for directing the computer to perform the mathematical operations involved 
in solving problems in real-time. Single address instructions are employed, most 
of which have an execution time of 8 - 12 microseconds. The computer can also be 
instructed to perform the data processing necessary for initiating and maintaining 
communications between, or control of, compatible external equipment. 

The instructions are assembled into a routine (program) which is entered into the 
computer for storage in its memory section. These instructions are usually stored 
at sequential memory addresses. Short routines can be manually entered into the 
computer by operating the appropriate console controls. Lengthy routines are enter- 
ed into the computer via a peripheral device such as a punched paper tape reader or 
a magnetic tape unit. 

The internal storage of the computer consists of a 32,672-word, ferrite-core main 
memory. A complete cycle for storage of a 30-bit word requires four microseconds. 
An additional storage area, designated as control memory, provides 64^ addressable 
locations with a read/restore cycle time of 667 nanoseconds. Fifty-six of these 
locations are special purpose to provide storage for input buffer control words, 
output command buffer control words, the real-time clock, and seven index registers. 
The other eight memory locations are used for data storage. Instructions cannot be 
run from the control memory; however, input/output transfers can take place to or 
from this memory, and any operand reference can be accomplished. 

The instructions contained in the program provide the computer with constants, 
decision-making capabilities, and an input/output capability. During operation, 
the program instructions are usually obtained from memory and performed in a 
sequential manner. However, a program decision may direct the computer to either 
skip an instruction or to exit from the present routine and enter a subroutine. 
The routine is terminated when either a predetermined event or conclusion is reached, 
or when all the instructions have been performed. At this point of the routine, the 
results of the computer operations are made available to the appropriate external 
equipment . 

Arithmetic and logical operations are performed in the parallel binary mode. For 
most operations, the result appears in a 30-bit accumulator register. Arithmetic is 
one's complement, subtractive, with a modulus (2 30 -l). Computer operation is cop- 
trolled by a stored program capable of self-modification. Each program instruction 
contains a function code (six bits), an instruction operand designator (15 bits), 
and three execution modifiers (two, three or four bits). Execution modifiers provide 
for address incrementation, operand interpretation, branch condition designation, 



Paragraph 
1-2 



1-4 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
GENERAL INFORMATION 



Figure 
1-3 




Figure 1-3. Printed Circuit Module, Front and Rear Views 

ORIGINAL 



1-5 



Figure 1 
1-4 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

GENERAL INFORMATION 




1-6 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
GENERAL INFORMATION 

input/output channel or minor function. The operand designator may be increased by 
the amount contained in any one of seven index (B) registers. The operand specified 
by the execution address may be interpreted as a 30-bit quantity, or as a 15-bit 
half-word with or without sign extension. The next sequential program step may be 
skipped when the branch condition designator places it under control of the contents 
of either the accumulator or the Q register. 

Communication between the computer and its associated external equipment is 
normally accomplished by a buffered transfer of data, with timing under control of 
the external device. Operating asynchronously with the main computer program, such 
transfers of data have independent access to storage. The number of data words 
transferred is under program control by specifying the first and last memory address 
in the buffer. 

A communication path is established by a sequence of request and response signals 
between external equipment and computer. The request signal may originate in either 
the computer or the external device. External request signals interrupt the main 
computer program and cause the computer to establish a communications channel. Once 
the communication link has been created, the computer returns to the main program 
sequence, and transfer of input or output data proceeds without program reference 
until completed. 

Sixteen input and 16 output channels are provided in the computer; each channel 
consists of 30 parallel data lines plus control lines. Two different interface 
options are available; the computer is provided with two each Type I and Type II 
I/O chassis. A group of four channels (one I/O chassis) may be converted from 
Type I to Type II and vice versa by simply changing plug-in logic modules within 
the channel circuitry. The Type I input/output chassis (normal) is capable of 
communicating with peripheral equipment only. The Type II input/output chassis 
(special) is capable of communicating with either another computer, or by changing 
plug-in logic modules, with peripheral equipment. The input/output plug-in logic 
modules provided with the computer provide a low speed interface for the low speed 
30-bit parallel mode. Plug-in logic modules are available for the input/output 
channel circuitry to modify it for a high speed mode. 

In addition to data words, output channels carry external function words to the 
external equipment. These words specify the function that the external device is 
to perform. Control of the external function signal is accomplished in block 
transfers. This feature allows the computer to continue engaging an external 
device after the completion of each function. 

Transfers of input and output data are controlled by priority and access control 
logic. This circuitry assigns access to control and core memory. If two or more 
requests for access to memory are received simultaneously, the priority and access 
circuitry evaluates the requests and assigns function priority according to an 
established sequence. 

b. FUNCTIONAL ANALYSIS. - An analysis of computer operation is facilitated by 

grouping the various logic circuits into broad functional sections. The block 

diagram (figure 1-5) identifies the main circuits associated with each of the four 
functional sections within the computer. The timing control circuits are common to 
all four functional sections. 

(1) CONTROL SECTION. - The control section consists of the registers and cir- 
cuits necessary to procure, modify, and execute the instructions of the program. 



Paragraph 
l-3a 



ORIGINAL 



1-7 



Paragraph 
l-3b.U) 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20(V) COMPUTER 
GENERAL INFORMATION 



The U register (30 bits) is the program control register. It holds the instruct- 
ion word during execution of an instruction. The function code and the various 
execution modifiers are translated from appropriate sections of the register* The 
lower order 15 bits of the U register have additional properties, modulus 2** -1. 

The 15-bit B registers, Bl through B7, store the quantities used for Ul modifica- 
tion. These B registers, also called index registers, occupy the lower 15 bits of 
the control memory addresses. 

The R register (15 bits) has counting properties to increase the contents of a 
selected B register. The output of this register is made available to the control 
adder for modifying the lower 15 bits of the U register. 

The B register (15 bits) is a nonaddressable control communications register. It 
holds the quantity added to the lower order 15 bits of the U register during address 
modification (i.e., the contents of the selected B register). 

The P register (15 bits) holds the memory address of a computer instruction word, 
that of the current instruction, or a new instruction, as a result of a jump condi- 
tion. 

The S register (15 bits) holds the storage address during memory references. At 
the beginning of a memory cycle period, the address is transferred to the S register. 
The contents of the S register are then translated to activate the storage selection 
system. 

The S0 register (seven bits) acts in the same manner as the S register except that 
it holds the address for control memory and NDRO memory during the memory cycle time. 

The Z register (30 bits) is the core memory buffer register through which all 
information to and from a core location must pass. Because of the optional use of 
15-bit half-words, Z is split into two 15-bit sections termed Z upper (Zu) and 
Z lower (ZD. The Z0 register (30 bits) is the memory buffer register for the 
control and Unifluxor memories. All information read from these memories must pass 
through this register. All information stored in the control memory locations must 
pass through this register. No storage is possible directly to Unifluxor locations. 

Although the S, S0, Z, and Z0 registers are shown in the control section they are 
closely allied with the memory section. 

(2) ARITHMETIC SECTION. - The arithmetic section performs numeric and logical 
calculations. 

The A register (30 bits) may be thought of, for programming purposes, as a conven- 
tional accumulator. Because of the logic employed, however, the A register is 
actually only the main rank of the accumulator; the D register serves as a second 
rank. The add operation is typical of the relationship between the A and D regis- 
ters: the augend and addend are initially contained in the A and D registers. Before 
the addition is performed, the contents of the A register are transmitted to the X 
register. The values of X and D are combined by the add network to form the sum of 
the two numbers in a parallel manner and placed in the A register. 

The Q register (30 bits) is used principally during multiply and divide operations. 
The contents of both A and Q may be shifted left or right, either individually or as 
one double-length, 60-bit word. 



1-8 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER 
GENERAL INFORMATION 



NAVSHIPS 0967-280-4010 



Figure 
1-5 



MEMORY SECTION 



BOOTSTRAP MEMORY 
64 -WORD NDRO 



CONTROL MEMORY 
64 -WORD THIN- FILM 
667 NANOSECONDS 




Figure 1-5. CP-642B/USQ-20(V) Computer Block Diagram 

ORIGINAL 



1-9 



Paragraph 
l-3b(2) 



NAVSHIPS 0967-280-4010 



CP-64 2B/USQ-20 ( V) COMPUTER 
GENERAL INFORMATION 



The X t D, and W registers are 30-bit, nonaddressable registers. These registers 
are used primarily for the exchange of data within the arithmetic section and for 
communicating with the remaining sections of the computer. The W register is not 
displayed on the control panel of the computer; the A t Q, X t and D registers have 
indicators which allow the operator to inspect the contents of these registers 
during debugging and maintenance operations. The A and Q registers are addressable 
arithmetic registers. 

The K registers (Kl, K2 f and K3) function as a shift counter for all arithmetic 
operations that involve shifts. Other instructions employing the K registers are 
multiply, divide, and square root. 

(3) MEMORY SECTION. - The memory section consists of three basic memories: 
main memory, control memory, and Bootstrap memory. 

The main memory, constructed of modular arrays of ferrite cores, has a capacity 
of 32,672 words of 30 bits. It is coincident-current driven and is addressed via 
the address translator. The memory operates in the destructive readout mode. 
Time required for the read/ restore cycle is four microseconds. 

The control memory, constructed from magnetic thin film elements, can store 64 
words of 30 bits. This memory stores the seven B-indexing registers, the control 
words for the input/output section, and the real-time clock. Address locations of 
the control memory are numbered from 00100 to 00177 and may be used for both read 
and store operations. No instruction can be run directly from control memory; 
if this is attempted, the computer will fault. 

The storage media of the magnetic thin-film memory consists of spots of a 
Permalloy ferromagnetic material, deposited upon a thin glass substrate. The 
Permalloy spots are 50 mils in diameter and 1,000 angstroms thick. The geometry 
of these spots permits the magnetic state of a spot to be switched in billionths of 
a second with only a small amount of power applied. Since these spots have only 
two stable states of magnetization, they can readily store binary information. 
Cycle time for read/ restore of data in the control storage is 667 nanoseconds (2/3 
microsecond) . 

The Unifluxor storage is a nondestructive readout (NDRO) type of memory used in 
the computer for automatic program recovery or bootstrap programs. This storage 
area is capable of reading 64 words with a read cycle time of 2/3 microsecond per 
word. Either one of the two 32-word bootstrap programs in the Unifluxor storage 
may be selected by a switch. The Unifluxor memory may be entered from any point in 
a program, and the exit from this memory area requires no special instruction. 

(4) INPUT/OUTPUT SECTION. - Communication with peripheral equipment is carried 
on in a 30-bit parallel mode through the input/output channels. The computer is 
equipped with 16 channels, numbered decimally through 15. These channels are 
assembled on four chassis, each of which contains four identical input/output 
channels. Two different types of chassis can be used with the computer: Type I 
(normal chassis) communicates with peripheral equipment, and Type II (special 
chassis) communicates either with peripheral equipment or with another computer. 
The conversion from a peripheral equipment channel to an intercomputer channel on 
Type II chassis involves the changing of one plug-in jumper logic module per 
channel. Either of the two types of chassis can be provided with a high or a low 
speed interface. The low speed interface provides communications transfer rates 



1-10 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER 
GENERAL INFORMATION 



NAVSHIPS 0967-280-4010 



Paragraph 
l-3b(4) 



of up to a nominal 40 kc per channel. The high speed interface will provide trans- 
fer rates of up to 125 kc per channel. 

In the computer, the transfer of input and output data words is asynchronous with 
the computer program, but the program maintains synchronous control over the 
issuance of external function words. Transmission of external function words is 
handled the same as data transmission. The peripheral equipment sets a line indi- 
cating it is capable of accepting a control word from the computer; therefore, the 
transmission of the word is not synchronous with the computer program. Provision 
has been made, however, to achieve synchronization of program and I/O control to be 
compatible with existing peripheral equipment. 

The four C registers (CI, C2 f C3 and C4) hold information for peripheral equip- 
ment during output data or external function transfers. Each is 30 bits in length 
and acts as a buffer register for four output channels. Groups of four channels 
may be adapted to Type I or Type II communication. 

(5) TIMING CONTROL. - Timing control of the computer operations is provided 
by internal master clock and real-time clock circuits. 

(a,) MASTER CLOCK. - The master clock consists of a delay line oscil- 
lator developing a four-phase output with a cycle time of approximately 680 
nanoseconds. The duration of each clock pulse is approximately 130, plus or minus 
15, nanoseconds. 

(b) INTERNAL REAL-TIME CLOCK. - The internal real-time clock consists of a 
tuning fork-controlled oscillator circuit operating at a frequency of 1024 cycles 
per second. The real-time clock is used to advance the count in memory address 
00160 and is accurate to plus or minus two cycles in 10,240 cycles. 

(c) EXTERNAL REAL-TIME CLOCK. - Provision is made for connecting an external 
real-time clock to the computer. The connection is made through a three-conductor 
connector located on the input/output connector panel. In order to use the external 
timing device, a logic module located on chassis A5 must be relocated at a different 
coordinate on the chassis. (See Section 5.) 

c. MAINTENANCE AND CONTROL CONSOLE. - The maintenance and control console (see 

figure 3-1) located on the upper front of the computer, includes indicator lamps 

which display a detailed report of the internal status of the computer and controls 

to permit manual initiation of various operations. It Is not necessary during 

normal operations, however, to monitor the console. 

Each register is represented on the console by a row of indicator-switch modules 
each of which can be used to enter a "one" manually into the corresponding bit 
position. A clear switch is associated with each register and is used to enter 
"zeros" manually into all bit positions of the register. Many of the registers are 
involved only in the mechanics of executing instructions and are not directly acces- 
sible to the program. 

The maintenance and control console provides manual controls for selecting the 
following special modes of operation: 



ORIGINAL 



1-11 



Paragraph 
l-3c 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

GENERAL INFORMATION 



Execution of one program instruction for each depression of a switch 

Execution of consecutive program instructions at a low controllable rate 

Execution of one master clock phase each time a switch is pressed 

Execution of consecutive master clock phases at a low, controllable rate 

Operation that is normal except that the computer does not stop for a programmed 
STOP instruction. (Such operation is called abnormal high-speed operation.) 

The console also provides manual controls that may be used either to disable the 
real-time clock, to inhibit the decrementing of the B7 register, or to inhibit in- 
crementing of the program address (P) register. These options enable the operator 
to suspend normal operation temporarily without affecting subsequent operation. 
Such suspensions could include stopping the computer or operating temporarily in one 
of the special modes. 

1-4. QUICK REFERENCE DATA. 

Quick reference data for the computer is summarized in table 1-2. 

1-5. EQUIPMENT SUPPLIED, 

The equipment normally supplied under a computer contract is tabulated in 
table 1-3. 

1-6. EQUIPMENT AND PUBLICATIONS REQUIRED BUT NOT SUPPLIED, 

Equipment, test equipment, tools, and publications required but not normally 
supplied with the computer are tabulated in table 1-4. 

1-7. FACTORY OR FIELD CHANGES. 

This manual includes all factory and field changes to the CP-642B/USQ-20(V) 
computer up to the publication date of this manual. 

1-8. EQUIPMENT SIMILARITIES. 

The CP-642B/USQ-20CV) computer, covered in this manual, is similar to the 
CP-642B computer and is an improved model of the CP-642/USQ-20(V) and CP-642A/ 
USQ-20(V) computers. The similarities and differences of these units are tabulated 
in table 1-5. 

1-9. SHIPPING DATA. 

Information pertinent to shipping may be extracted from table 1-2. 

1-10. MODULE COMPLEMENT. 

(See figure 1-3.) The basic building unit of the computer is a printed-circuit 
module containing the necessary transistors, resistors, diodes, etc., to perform 
logic functions. Several different types of these modules are used in the computer. 
These module types and quantities are tabulated in table -16. 

x _ 12 ORIGINAL 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
GENERAL INFORMATION 

TABLE 1-2, QUICK REFERENCE DATA 



ITEM 


CHARACTERISTICS 


POWER INPUT 

LOGIC (DC SUPPLIES) 
VOLTS 
FREQUENCY 
PHASES 
WATTS 
PROTECTION 

BLOWER 

VOLTS 

FREQUENCY 

PHASES 

WATTS 

PROTECTION 


115 (+2%) VAC (Line to line) 

400 (+5%) cps 

3 

2500 

15 Ampere fuse each line 

115 (+10%) VAC (Line to line) 

400 (+5%) cps 

3 

2000 

15 Ampere fuse each line 


OPERATING TEMPERATURE RANGE 
COOLING 

WATER TEMPERATURE 
WATER RATE 

VE RTEMPE RATU RE FEATURES 

OVERTEMP WARNING 
OVERTEMP SHUTDOWN 


0° - 50°C (320 - 1040F) 

21.1° + 2.8°C (70° + 5°F) 
6.3 GPM 

Alarm Horn and Light at 46°C (115°F) 
Shutdown at 60°C ( 140°F) 


SIGNAL CHARACTERISTICS 
INTERNAL 

"0" 
I/O LINES 

"0" 


-4.5 VDC 
VDC 

LOW SPEED INTERFACE HIGH SPEED INTERFACE 
VDC VDC 
-13.5 VDC -3 VDC 


INPUT/OUTPUT CHANNELS 

PERIPHERAL I/O 
INTERCOMPUTER I/O 
OPERATION 


0, 4 ( 8, 12, or 16 
t 4, 8 t 12, or 16 
30 bit, parallel mode 


INTERNAL FEATURES 

MATN MFMORY 

CAPACITY 
CYCLE TIME 

CONTROL MEMORY 

CAPACITY 
CYCLE TIME 


32,672 thirty-bit words 
four microseconds 

Thin Film devices 
64 thirty-bit words 
667 nanoseconds 



ORIGINAL 



1-13 



Table 
1-2 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

GENERAL INFORMATION 



TABLE 1-2. -QUICK REFERENCE DATA (CONT.) 



ITEM 


CHARACTERISTICS 


BOOTSTRAP 




Unifluxor devices 




CAPACITY 




64 thirty-bit words 




CYCLE TIME 


667 nanoseconds 




INSTRUCTION REPERTOIRE 


64 Function Codes 








(two of which are invalid) 


MAIN POWER SUPPLY CHARACTERISTICS 


DC OUTPUT 


VOLTAGE RANGE 


RIPPLE VOLTS (MAX. P. TO P.) 


FUSE (AMPS) 


-15 Volts 


-13.5 to -16.5 


0.20 


VARIES 


+15 Volts 


+13.5 to +16.5 


0.20 


BY 


+10 Volts** 


Adjustable from 




CHASSIS 




+9 to +11 


0.10 




-4.5 Volts 


-4 to -5 


0.20 




+18 Volts 


+16.2 to +19.8 


0.10 






CONSOLE POWER 


SUPPLY CHARACTERISTICS 




-90.5 Volts 


-80 to -100 




*1 


(single 


(peak-to-peak) 






phase half- 








wave 








rectified) 








-54 Volts 


-48 to -60 




*1 


-15 Volts 


-13.5 to -16.5 






-26.5 Volts 


-23.8 to -29.2 




1 



Fused together in power supply primary 

Output from voltage regulator module located at J37E 
on each memory chassis (A9 thru A13) 



1-14 



ORIGINAL 



CP-642B/USQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
GENERAL INFORMATION 



Table 
1-3 



TABLE 1-3. EQUIPMENT SUPPLIED 



OflANTTTY 

PER 
EQUIPMENT 


NOMENCLATURE 


OVER-ALL DIMENSIONS* 


TECHNICAL 
MANUAL 


NAME 


DESIGNATION 


HEIGHT 


WIDTH 


DEPTH 


VOLUME 


WEIGHT 


1 


Digital 
Data 

Computer 


CP-642B 
/USQ-20(V) 


72 


38.5 


37 


102,564 


2 T 150 


NAVSHIPS 



^Dimensions in inches, cubic inches, and pounds. 



TABLE 1-4. EQUIPMENT AND PUBLICATIONS REQUIRED BUT NOT SUPPLIED 



QUANTITY 

PER 
EQUIPMENT 


NOMENCLATURE 




REQUIRED 
CHARACTERISTICS 


NAME 


DESIGNATION 


REQUIRED USE 


1 


Analyzer 


Multimeter AN/PSM- 
4C or equivalent 


Measure AC and DC 
voltages and 
measure resistances 


Provide facilities 
for checking pri- 
mary power, and 
for general 
troubleshooting 


1 


Oscillo- 
scope 


Tektronix 545 or 
equivalent with CA 
dual trace plug-in 
preamplifier, or 
equivalent 


Check voltage 
waveforms 


Provide facilities 
for adjustments 
and for general 
troubleshooting 


1 


Tool Set 


Test-Tool Set 
AN/USM-3 or 
equivalent 


General purpose 




1 


Hand 

Stripper 


Ideal Industries 
No. 45-171 


Strip insulation 
from wire 




I 


Hand 
Crimper 


Aircraft Marine 

Products 

No. 47566 


Crimp wire in taper 
pins 


Provide facilities 
for making taper 
pin connections 
if necessary 



ORIGINAL 



1-15 



Table 
1-4 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20( V) COMPUTER 

GENERAL INFORMATION 



TABLE 1-4. EQUIPMENT AND PUBLICATIONS REQUIRED BUT NOT SUPPLIED (CONT. ) 



QUANTITY 

PER 
EQUIPMENT 



NOMENCLATURE 



NAME 



1 ea. 



1 ea. 



DESIGNATION 



Hand In- 
sertion 
Tool 



Wrapping 
Tool 

Power 
Pack 

Unwrap- 
ping 
Tool 

Dual for 
30 ga. 
Dual for 
20-26 ga. 

Bits for 
30 ga.Sq. 
Pin 

30 ga. 
Rect.Pin 
24 or 
26 ga. 

Sleeves 
for 
30 ga. 
Sq. Pin » 
30 ga. 
Rect.Pin 
24 or 
26 ga. 



Aircraft Marine 
Products No. 
380306 with 
No. 394042 in- 
sertion tip 

14R2 (8130-132) 



503885 (8130-151) 



505084 
A31478 



504221 ) 
505561(8130-144) 
26263 (8130-121) 



505350 

17611-2 (8130-129) 
18840 (8130-128) 



REQUIRED USE 



Insert taper pins 
in connectors 



Make wire wrap 
connections 

Battery for 
wrapping tool 



Unwrap wire-wrap 
Connections 



Adapts wire wrap- 
ping tool to various 
wire sizes 



Adapts wire wrap- 
ping tool to various 
wire sizes 



REQUIRED 
CHARACTERISTICS 



Unwraps left or 
right. 

Hand wrapped con- 
nec ti ons 



1-16 



ORIGINAL 



CP-642B/USQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
GENERAL INFORMATION 



TABLE 1-5. EQUIPMENT SIMILARITIES 



ITEM 


CP-642B or 
CP-642B/USQ-20(V) 


CP-642A/USQ-20(V) 


CP-642/USQ-20(V) 


DIMENSIONS 
HEIGHT 
WIDTH 
DEPTH 
WEIGHT 
VOLUME 

MOUNTING 


72 

38.5 

37 

2,315 
95,536 
Shock Mounted 


72 

37-3/8 
36-7/8 
2320 
95 , 536 
Shock Mounted 


65-1/2 
37-3/8 
36-7/8 
2320 
85,700 
Shock Mounted 


POWER 
LOGIC 

BLOWER 


115 (±2%) VAC, 

<J ^Jii d o c 

400 (+5%) cps, 
2500 watts 
115 (±10%) VAC, 
3 phase 

400 (±5%) cops 
2000 watts 


115 (±2%) VAC 

400 (+5%) cps, 
2500 watts 
115 (±10%) VAC 
3 phase 
400 (±5%) cps, 
2000 watts 


115 (±2%) VAC 

400 (±5%) cps, 

2500 watts 

115 (±10%) VAC, 

3 phase 

400 (±5%) ,;ps t 

2000 watts 


COOLING 


Recirculating air, 
water cooled 


Recirculating air, 
water cooled 


Recirculating air, 
water cooled 


OVERTEMPERATU RE 
WARNING 
onUlUUWIM 


46°C (115°F) 

^nOc { i /iaoc*\ 
ol) u U tl40 u t< ) 


46°C (115°F) 
oO u C (140 U F) 


46°C (115°F) 
60"C (1400F) 


SIGNAL CHAR- 
ACTERISTICS 
INTERNAL 
"1" 
"0" 


-4.5 VDC 

VDC 


-3 VDC 
VDC 


-3 VDC 
VDC 


I/O LINES 

t.QM 


VDC VDC 
-13.5 VDC -3 VDC 


VDC 
-13.5 VDC 


VDC 
-13.5 VDC 


STORAGE 

MAIN MEMORY 
CAPACITY 


Ferrite Cores 

32 , 672 30-bit words 


Ferrite Cores 

32 , 768 30-bit words 


Ferrite Cores 

32 t 768 30-bit words 


CYCLE TIME 


four microseconds 


eight microseconds 


eight microceconds 


CONTROL MEMORY 
CAPACITY 
CYCLE TIME 

BOOTSTRAP MEMORY 
CAPACITY 
CYCLE TIME 


thin film 
64 30-bit words 
667 nanoseconds 
Unifluxor devices 
64 30-bit words 
667 nanoseconds 


Wired jumper plugs 
16 30-bit words 
eight microseconds 


Wired jumper plugs 
16 30-bit words 
eight microseconds 



ORIGINAL 



1-17 



Table 
1-5 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

GENERAL INFORMATION 



TABLE 1-5. EQUIPMENT SIMILARITIES (CONT.) 



ITEM 


Lr-o4<dD or 
CP-642B/USQ-20(V) 


CP-642A/USQ-20(V) 


CP-642/USQ-20(V) 


INPUT/OUTPUT 
CHANNELS 

PERIPHERAL I/O 
INTERCOMPUTER I/O 


16 

CP-642BCP-642B/USQ- 

-20(V) 
16 Max. 14 
16 Max. 2 


14 

12 
2 


14 

12 
2 


MASTER CLOCK 
PHASE 

CYCLE TIME 
CLOCK PULSE 
DURATION 


4 

680 nanoseconds 
150 nanoseconds 
(+10 nsec) 


4 

1.6 microseconds 
0.4 microseconds 


4 

1.6 microseconds 
0.4 microseconds 


CONSOLE LOCATION 


Top of cabinet 


Top of cabinet 


Inside of doors 


REPERTORY OF 
INSTRUCTIONS 


64 10 


64 10 


64 10 



TABLE 1-6. MODULE COMPLEMENT 



MODULE 
TYPE 


CHASSIS 


TOTALS 


REMARKS 


1 


2 


3 


4 


5 


6 


7 


8 


*9-l3 


**0210 
























1110 
























1120 
























1200 
























**2000 










60 


2 


150 


45 




257 




2011 


21 


21 


24 


24 


32 


39 


41 


24 


1 


231 




2020 


106 


106 


117 


117 


58 


107 






6 


641 




2030 


35 


35 


37 


37 


22 


23 


1 






190 




2040 


3 


3 


5 


5 


25 


35 


86 






162 




2050 






1 


1 


48 


45 


73 






168 




2060 


3 


3 


15 


15 


56 


90 




6 


2 


198 




2070 


13 


13 


15 


15 


35 


39 


27 


11 


1 


173 




2080 


4 


4 


4 


4 


4 


9 


10 






39 




2090 


68 


68 


68 


68 


16 










288 




2100 










5 










5 




2110 










2 








1 


7 




2120 










1 








1 


6 




2130 


16 


16 


16 


16 












64 




2140 


30 


30 


30 


30 












120 




2150 


23 


23 


23 


23 


32 


33 


40 


15 




212 




2160 


















6 


30 




2170 


















8 


40 




2180 


















16 


80 




2191 


















10 


50 





1-18 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 Table 
GENERAL INFORMATION 1-6 



TABLE 1-6. MODULE COMPLEMENT (CONT.) 



MODULE 
TYPE 


CHASSIS 




REMARKS 


1 


2 


3 


4 


5 6 


7 
i 


ft 




TOTALS 


2200 
















4 


20 




2210 
















lO 


Oft 




2350 
















1 
1 


5 




2360 










4 








4 




2370 














1 




1 




2380 














5 




5 




2390 














ft 




Q 
O 




2400 














ft 




8 




2410 


















2 




2420 














4 




4 




2430 














1 




1 




2440 














o 




o 
d 




2450 














ft 




8 




2460 














o 
o 




8 




2470 














8 




8 




2480 














2 




2 




2490 














o 








**2500 


















4 




2510 














OV 




39 




2520 














12 




12 




2530 














2 




2 


















4 




4 




2550 














15 




15 




2560 














32 




32 




2570 


















30 




2580 














30 




30 




2590 














8 




8 




2600 














1 




i 
i 




5000 
















8 






2620 
















16 






2631 
















16 


80 




2640 
















1 


5 




2650 






4 


4 










8 




2660 






4 


4 










8 




2720 


1 


1 


1 


1 










4 




2740 














1 




1 




2750 














1 




1 





ORIGINAL 



Table NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

1-6 GENERAL INFORMATION 

TABLE 1-6. MODULE COMPLEMENT (CONT.) 



MODULE 
TYPE 


CHASSIS 


TTiT Arc 

lOlALo 


REMARKS 


1 


2 


3 


4 


5 6 


7 


8 


•9-13 


<£7oO 










1 








1 

I 




d.1 (0 










1 








1 




Od en 
















24 






<£OOU 










1 








i 
i 




2890 










1 








1 




3180 
















13 


65 




5000 










1 








1 




250210 






















251110 


















9 


Mounted on Console 


251120 


















1 


Mounted on Console 


251200 










1 








1 




TOTALS 


323 


323 


364 


364 


406 422 


428 


339 


151 


3724 





* Quantity for one chassis; multiply by five for memory total. 
** For complete module type, prefix each number with 25 for gold- 
plated connector or 700 for solder plated connector. 
*** For complete module type, prefix each type number with 422 for gold- 
plated connectors or 700 for solder plated connectors 



1-20 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
INSTALLATION 



Contents 



SECTION 2 
INSTALLATION 
TABLE OF CONTENTS 

Paragraph Page 

2-1. Unpacking and Handling 2-1 

2-2. Site Selection 2-1 

2-3. Power Requirements and Distribution 2-1 

2-4. Installation Layout 2-1 

2-5. Installation Requirements 2-2 

a. . Floor and Space Requirements 2-2 

b. Cooling Requirements 2-2 

c. . Dimensions and Weight 2-2 

d. . Interconnecting Diagrams 2-2 

e. . Grounding 2-6 

(1) General 2-6 

(2) Cabinet Ground 2-6 

(3) Intercabinet Ground 2-6 

j\ Cable Assembly 2-6 

(1) Construction and Materials 2-11 

(2) Connector Pin and Wire Assignments 2-11 

(3) Connectors 2-11 

(4) Connector Shells 2-11 

2-6. Inspection and Adjustment 2-20 

a, . Physical Inspection 2-20 

(1) Computer Doors 2-20 

(2) Chassis 2-20 

b. Initial Turn On Procedure 2-22 

_c. Nonlogic Checks 2-22 

d, . Logic Checks 2-22 

e. . Adjustments 2-22 

2-7. Interference Reduction 2-22 

2-8, Preparation for Reshipment 2-22 



ORIGINAL 2-i 



Contents 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

INSTALLATION 



LIST OF ILLUSTRATIONS 

Figure Paae, 

2-1. Computer Installation and Dimensional Diagram 2-3 

2-2. Interassembly Plug Rack, Diagrams of Plug Orientation 2-4 

2-3. Input/Output Connectors (Top of Computer) Jack Orientation 

Diagram 2-7 

2-4. Computer Power Connection Diagram 2-8 

2-5. Computer Internal Power, Distribution Schematic 2-9 

2-6. Computer Idealized Grounding Diagram 2-10 

2-7. Male Connector, 90-Pin, Detailed View 2-12 

2-8. Female Connector, 90-Pin, Detailed View 2-13 

2-9. Connector Shell, 90-Degree, Detailed View 2-14 

2-10. Chassis Removal Mechanisms 2-21 



LIST OF TABLES 

T able PM£ 

2-1. Cabinet Input/Output Connectors 2-5 

2-2. Input/Output Cable Characteristics 2-6 

2-3. Connector Pin Assignments 2-15 

2-4. Wire Assignment for Digital Data Cable 2-18 



2-ii ORIGINAL 



CP-642B/USQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
INSTALLATION 



Paragraph 
2-1 



SECTION 2 
INSTALLATION 



2-1. UNPACKING AND HANDLING. 

The computer will arrive at the site completely assembled. If shipped by truck, 
the computer requires no crating. When it is shipped by other means of trans- 
poration, the computer requires the protection of a standard crate. In either 
case, a skid bolted to the bottom of the computer permits the use of a forklift 
truck when handling the computer. To uncrate the unit, complete the following 
steps . 

NOTE 

Omit steps 1, 2 and 3 if the computer arrives uncrated. 

STEP 1. Remove the fasteners from the top of the shipping crate. 

STEP 2. Remove the top section of the crate. 

STEP 3. Pull away the four sides of the crate to expose the equipment. 

STEP 4. Move the computer to the desired area. 

STEP 5. Remove the bolts which hold the equipment to the skid. 

STEP 6. Lift or slide the computer from the skid. 

STEP 7. Place the computer in the area as shown by the installation plans. 

STEP 8. Perform a brief visual inspection of the equipment; note and report 
any damage. 

2-2. SITE SELECTION. 

The placement of the computer is optional and is dependent upon the installation 
site. Conditions must be suitable to protect the computer from damage. The equip- 
ment is self-contained but requires floor and wall supporting structures. There 
must be sufficient area around the back of the cabinet to allow access to the 
electrical and coolant connectors and to facilitate maintenance and repair pro- 
cedures. 

2-3. POWER REQUIREMENTS AND DISTRIBUTION. 

The total power dissipation of the computer circuits and the centrifugal blower 
is 4,500 watts. The computer logic circuits require 2,500 watts of 3-phase power 
at 115 volts (+1 percent) and 400 cps (+5 percent) with a current requirement of 
14 amperes. The centrifugal fan requires 2,000 watts of 3-phase power at 115 
volts (+10 percent) and 400 cps (+5 percent) with a current requirement of 25 am- 
peres starting and 9 amperes running. 

2-4. INSTALLATION LAYOUT. 

The installation layout for the computer and peripheral equipment is a function 
of the installing activity. When planning the installation layout, it must be. 



ORIGINAL 



2-1 



Paragraph 
2-4 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20CV) COMPUTER 

INSTALLATION 



remembered that the maximum distances between the computer and peripheral units are 
limited by the type of interconnecting cables and the interface speeds (high speed 
or low speed interface) which are used. Refer to paragraph 2-5 for recommended 
cables. 

2-5. INSTALLATION REQUIREMENTS 

a. . FLOOR AND SPACE REQUIREMENTS (See figure 2-1). - The floor area upon which the 
computer is to be mounted must be flat within 0.03 inch and unobstructed. There 
must be at least 17 inches clearance between the computer sides and walls or other 
equipment to allow space for the doors to be opened. There must be at least 23 
inches clearance between the front of the computer and the wall or other equipment 
to allow space for removing the chassis. There must be at least seven inches head 
room to allow adequate air circulation and work space. There must be at least four 
inches clearance between the rear of the computer and the wall to allow space for 
cables. 

b. COOLING REQUIREMENTS. - The cooling coil on the back of the computer requires 
6.3 gallons-per-minute of water at approximately 21°C (70°F). The water supply in- 
let is a 3/4-inch NPT fitting located near the back on the right side of the plenum 
section. When the computer is installed, the inlet is approximately 33 inches from 
the floor and approximately 5-1/2 inches from the wall behind the computer. The 
water return outlet from the computer is a similar pipe fitting located 4-1/2 inches 
directly above the inlet. Flexible lines should be used to allow variation of 
0.5-inch movement in any direction after installation. 

c. . DIMENSIONS AND WEIGHT. (Approximate, uncrated.) - The computer is 72 inches 
high (including shock mounts), 38.5 inches wide, and 37 inches deep. Cubic content 
(volume enclosed by over-all dimensions) is approximately 102,564 cubic inches. 
The total weight of the computer is 2150 pounds. This includes the weight of the 
cabinet, one power supply, heat exchanger, base and shock mounts totaling 1189 
pounds, and weight of the seven chassis, Al through A7, 588 pounds (each chassis 
84 pounds); chassis A8, 73 pounds; chassis A9 through A13, 300 pounds (each chassis 
60 pounds) . 

NOTE 

The computer is provided with four eyebolts to facilitate lifting during 
installation. The eyebolts are located on top of the chassis frame and 
are accessible only when the top cover is removed. 

d. INTERCONNECTING DIAGRAMS. - Connections between the chassis of the computer 
are made via movable plug-racks on the computer's sides and jacks mounted on the 
chassis. Figure 2-2 shows these plug designations. Connections between the com- 
puter and external equipment are via the jacks located on the top of the computer 
(see figure 2-3). Functions of these jacks are listed in table 2-1. Power con- 
nections to the computer are shown in figure 2-4. Power connections internal to 
the computer are shown in figure 2-5. 

NOTE 

Interconnecting cable types and the conductor grouping may vary among 
installations. Refer to the applicable ship or station plans to de- 
termine the correct cabling for any installation. 



2-2 



ORIGINAL 



CP-642B/USQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
INSTALLATION 



Figure 
2-1 




3 



ORIGINAL 



2-3 



Figure NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

2-2 INSTALLATION 





OUTSIDE LEFT VIEW 



OUTSIDE RIGHT VIEW 



Figure 2-2. Interassembly Plug Rack, Diagrams of Plug Location 

ORIGINAL 



CP-642B/USQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
INSTALLATION 



Table 
2-1 



TABLE 2-1. CABINET INPUT/OUTPUT CONNECTORS 



PAD TMPT 


r" AM M CTTAD 


FUNCTION 


INPUT 


OUTPUT 




DATA 


DATA 




Jl 


J17 


Channel 


32 


J18 


Channel 1 


J3 


J19 


2 


J4 


J 20 


3 


J5 


J21 


4 


J6 


J22 


5 


J7 


J23 


6 


J8 


J24 


7 


J9 


J25 




J10 


J26 


^ // 


Jll 


J27 


N 1Q ^ 


J12 


J28 


Id t$ 


J13 


J29 




J14 


J 30 




J15 


J31 


14 id 


J16 


J32 




J53 




Regulated 400 cps Power 


J54 




Unregulated 400 cps Power 


J42 




External Real-Time Clock 



ORIGINAL 



2-5 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

2 - INSTALLATION 
e. GROUNDING. 

(1) GENERAL, - The method of grounding the computer assumes extreme importance 
for two reasons: first, the safety of operating and maintenance personnel; and f 
secondly, a DC system is used for input/output communications. When large distances 
separate various pieces of equipment, a difference of potential may exist between 
the ground points. Such a difference of ground potential has a direct effect on 

the equipment's ability to distinguish between a logical " 1" or a logical "0" on 
the input/output lines. 

(2) CABINET GROUND. - The computer cabinet is grounded to the system ground 
bus through a branch cable. The branch cable should be of minimum practical length. 
Its size is determined by its length and is dependent upon the requirements of 

the system. (See table 2-2.) 

(3) INTERCABINET GROUND. - The ground bus, which has a very low impedance at 
low frequencies, has a relatively high impedance at the signal frequencies used. 
Because of its low inductance, the ground return wire of each signal-twisted pair 
will carry virtually all the signal return current. Recommended connections for 
ground return lines are shown in figure 2-6. Ideally, a twisted pair is carried 
from an output circuit in one cabinet to an input circuit in another cabinet. If 
necessary, a common ground return may be used exclusively on the output circuit 
end of the cable. This is required since the current supplied by an output cir- 
cuit during transition from "zero" to "one" state, or vice versa, includes the 
line charging current, which is much greater than the DC steady state current 
received by the input circuit. 

Figure 2-6 shows that the cable shield connects to pins 45 and 69 of the con- 
nector; these in turn are grounded at both ends to equipment cabinets. This ar- 
rangement allows the shield ground to be disconnected at one end if later desired. 
The aluminum braid armor is primarily for mechanical protection, serving no direct 
function in the grounding system, although some protection from radiation is 
realized. Circuit ground is shown connected to an internal bus which is isolated 
from cabinet ground. Provision is made for strapping circuit ground to cabinet 
ground at a point near the ground lug. This is an idealized case and provides 
maximum flexibility. Internal circuit considerations, however, determine the type 
of internal circuit grounding for specific cabinets. 

1. CABLE ASSEMBLY. - This paragraph provides a general, description of the 
service-type input/output cables suggested for use with the computer. The computer 
will operate with the cables (or equivalent) and the corresponding cable lengths 
and interface speeds specified in table 2-2 when the mating connectors [see para- 
graph 2-51(3)1 are connected to the cable ends. *~ 



TABLE 2-2. INPUT/OUTPUT CABLE CHARACTERISTICS 



CABLE TYPE IN 
ACCORDANCE WITH - 


MAXIMUM CABLE LENGTH (FEET) 


HIGH SPEED INTERFACE 


LOW SPEED INTERFACE 


*DS 5177 


200 


300 


*DS 5192 


150 


90 


•*SCD 7956068 


200 


300 


•*SCD 7956091 


200 


300 



* Manufacturer's Design Specification 
^Manufacturer* s Specification Control Drawing 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
INSTALLATION 



Figure 
2-3 



CVJ 



CVJ 



m n 

-> 0_ 



O 
—> 









—) 














J41 


CM 
CL- 


CD 










—> 













O 








CJ> 


OD 




a. 


—> 







CD 



O 
CM 



ro 




ro 
ro 



in 

CO 



-5 



r 












—> 


CO 


0> 




ro 


00 




—> 





2 
O 



ro 




in 






—> 










00 




ro 


CO 




-» 


0- 



CM 



fO 

eg 



OvJ 



N 



00 



o 

ro 
-5 



ro 







ro 


00 


-> 


0- 




ID 


u> 


ro 


CO 


—> 





ro 



ORIGINAL 



2-7 



Figure 
2-4 



NAVSHIPS 0967-280-4010 
UNREGULATED 1 15 VAC (±10%) 115 VAC (±2%) 



CP-642B/USQ-20CV) COMPUTER 
INSTALLATION 



SOURCE 



400 CPS (+5%) 
3 PHASE 





400 CPS (±5%) 

3 PHASE 

4 WIRE 




J54 



J53 



CP-642B/USQ-20(V) 
COMPUTER 



REGULATED 
SOURCE 



NOTES 

I. REGULATED SOURCE POWER CABLE -USE A FOUR- 
CONDUCTOR {14 AWG) CABLE AND A 
MS-3I06A24-22SW CONNECTOR TO MATE 
WITH J53. CONNECT AS FOLLOWS: 



FROM PWR 
SOURCE 


TO CONN. 
PIN 


FUNCTION 


01 


A 


115 VAC 01 400 CPS REG. 


02 


B 


115 VAC 02 400 CPS REG, 


03 


C 


115 VAC 03 400 CPS REG. 


GND 


D 


SAFETY GROUND 



2. UNREGULATED SOURCE POWER CABLE-USE A FOUR- 
CONDUCTOR (14 AWG) CABLE AND A 
MS-3I06A24-22S CONNECTOR TO MATE 
WITH J54. CONNECT AS FOLLOWS: 



FROM PWR 
SOURCE 


TO CONN. 
PIN 


FUNCTION 


1 


A 


115 VAC 01 400 CPS UNREG. 


02 


B 


115 VAC 02 400 CPS UNREG. 


03 


C 


115 VAC 03 400 CPS UNREG. 


GND 


CLAMP 


SAFETY GROUND 



2-8 



Figure 2-4. Computer Power Connection Diagram 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER 
INSTALLATION 



NAVSHIPS 0967-280-4010 



Figure 
2-5 



1 15V + 10% 
400 CPS +5% 
3 PHASE 



1 15V ±2% 
400 CPS + 5% 
3 PHASE, 4 WIRE 




J 54 




J 53 



Kl 



} 



TO CONSOLE POWER 
SUPPLfES AND 
POWER CONTROLS 



ABC 



V A B C 1 P98 



J 56 



-Wl 



ABC P99 



ABC 



J 57 




K2 




TBI TBI TBI 
I8/2B 3B/*»B 5B/6B 

TO O.C. POWER SUPPLIES 



P97 



J55 



Figure 2-5. Computer Internal Power Distribution Schematic 



ORIGINAL 



2-9 



Figure 
2-7 



NAVSHIPS 0967-260-4010 



CP-642B/USQ-20CV) COMPUTER 
INSTALLATION 



CABLE SHIELD 
CONNECTED TO 
PINS 45 AND 69 



SIGNAL WIRE 



INSULATING SHEATH 
'OVER SHIELD 



r ALUMINUM BRAID ARMOR 



GROUND 
RETURN 
WIRE 



GROUND 
RETURN 
WIRE 



LOGIC 
MODULE 




CABINET 
GROUND LUG 
3/8 INCH 
DIAMETER 



MAIN INSULATED GROUND 
BUS- LARGE CROSS- 
SECTIONAL AREA 



BONDEO AT ONE POINT 



2-10 



Figure 2-6. Computer Idealized Grounding Diagram 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 Paraqraph 
INSTALLATION 2-5f(l) 

(1) CONSTRUCTION AND MATERIALS. - Individual conductors are composed of 
strands of tinned, soft-annealed copper. Primary insulation is extruded, high- 
moleculaT weight polyethylene with an average thickness among all conductors no 
less than 0.025 inch. This primary insulation is covered with a sheath of ex- 
truded nylon. 

Conductor color coding conforms to Military Standard MIL-STD-104. Conductors 
are twisted into pairs, and cabled with the necessary fillers to form a core of 
circular cross-section. Cabling sequence conforms to Military Specification 
MIL-C-915 for twisted pair telephone cable. 

A shield of braided, tinned, soft-annealed copper is applied over the binder to 
provide a minimum of 88 percent coverage. A black polyvinyl chloride sheath is 
extruded over the shield. The sheath is covered with an armor braid of aluminum 
alloy wire, containing not more than 0.2 percent copper and not less than 92.5 
percent aluminum. The complete cable is painted, by the immersion process, with 
aluminum paint. 

(2) CONNECTOR PIN AND WIRE ASSIGNMENTS. - Tables 2-3 and 2-4 provide the 
connector pin and wire assignments. The male connector pin arrangement is illus- 
trated in figure 2-7, the female connector pin arrangement in figure 2-8. Com- 
paring the tables with the pin arrangement of the figure reveals that, for a 
signal carried by a pin in a particular horizontal row, the associated ground 
return is carried by a pin in the row beneath and slightly to the right. For ex- 
ample, a control signal is assigned to pin 1; ground return for that signal is 
assigned to pin 11. Thus, a row of signal pins alternate with a row of ground 
return pins. Note the distinction between spare pins (wires connected but 
carrying no intelligence) and unused pins (no wires connected). The cable shield 
connects to pins 45 and 69, outside pins. 

(3) CONNECTORS. - Cable connectors are of the rectangular, 90-pin type, 
featuring solderless taper-pin wire connections. Contacts are gold-plated, assur- 
ing continued low resistance over extended periods in corrosive atmospheres. Male 
connectors are cabinet-mounted; female connectors are attached to both ends of 
interconnecting cables. This arrangement minimizes the possibility of damage to 
male pins when installing or removing cable connectors. Exposed male pins present 
no safety hazard since only relatively low voltages are present. 

(a.) MALE CONNECTOR. - The physical configuration of the 90-pin male con- 
nector is illustrated in figure 2-7. 

(b) FEMALE CONNECTOR. - The physical configuration of the 90-pin connector 
is illustrated in figure 2-8, 

(4) CONNECTOR SHELLS. - The fittings on the female connector are termed a 
connector shell. Three connector shell variations allow for various angles of 
cable entry, zero degrees (cable axis parallel to connector pins), 90 degrees, and 
135 degrees. Thus, flexibility is provided in connector panel positioning, relative 
to the direction of cable entry. Figure 2-9 illustrates a 90-degree connector 
shell. 

A clamp, shown in the figure 2-9, functions as a locking device to secure the 
connector. The metal strap slips over a notch on the connector shell and a locking 
screw holds the connector in place. 



ORIGINAL 



2-11 



Figure 
2-7 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20CV) COMPUTER 

INSTALLATION 



3 3/8 



© o © 




° o° o° o- 

fofoO°o^ 05 

6 o o°o° 
5°o°o°o? 
o9o°o°o° 
ogogogog 

o°o o°o 
os" o r..o u 




o 



11/16" 




310 MIN. 
ENLARGED VIEW 



2-12 



Figure 2-7, Male Connector, 90-Pin, Detailed View 

ORIGINAL 



CP-642B/USQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
INSTALLATION 



Figure 
2-8 



® o © 




3 3/8 



^o u ooo 

°o°o°o°o 
o o o o 

o o o 00 

o n 

=o wC W 




o 



11/16 



2 23/64 



V- 

t 

j— 



i r 



1 



052 PI A. 



T 




.061 TAPER 
PER INCH ON 
DIAMETER 



ENLARGED VIEW 



Figure 2-8. Female Connector, 90 Pin t Detailed View 
ORIGINAL 2-13 



Figure 
2-9 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20( V) COMPUTER 

INSTALLATION 




2-14 



Figure 2-9. Connector Shell. 90-Degree t Detailed View 

ORIGINAL 



CP-642B/USQ-2CKV) COMPUTER NAVSHIPS 0967-280-4010 
INSTALLATION 



Table 
2-3 



TABLE 2-3. CONNECTOR PIN ASSIGNMENTS 



CONNECTOR 
NUMBER 


PERIPHERAL 

FTfMT TPMPMT 
Ciyu IrivJCiN 1 

INPUT CHANNEL 


INTERCOMPUTER 

TM DI1T 

UNrU 1 

CHANNEL 


PERIPHERAL 

EQUIPMENT 
OUTPUT CHANNEL 


INTERCOMPUTER 
OUTPUT 
CHANNEL 


1 


Input Data 
Request 


Input Data 
Request 


Output Data 
Acknowledge 


Ready 


2 


Input Data 
Acknowledge 


Input Data 
Acknowledge 


Output Data 
Request 


Resume 


3 


External 

111 Lcif Upi 


External 
in terrupt 


External 
Function 


External 
Function 


A 


external 

Interrupt 

Request 


External 

Interrupt 

Request 


External 
Function 
Request 


External 
Function 
Request 


5 


Spare 


Spare 


Spare 


Spare 


6 


Spare 


Spare 


Spare 


Spare 


7 


Spare 


Spare 


Spare 


Spare 


8 


Spare 


Spare 


Spare 


Spare 


Q 

7 


uata tsit c 


Data Bit 2y 


Data Bit 2 U 


Data Bit 2° 


10 


Data Bit 2 1 


Data Bit 2 1 


Data Bit 2 1 


Data Bit 2 1 


11 


Input Data 
Request r 


Input Data 
Request r 


Output Data 
Acknowledge r 


Ready r 


12 


Input Data 
Acknowledge r 


Input Data 
Acknowledge r 


Output Data 
Request r 


Resume r 


13 


External 
j-iitcrrupi, r 


External 
Interrupt r 


External 
Function r 


External 
Function r 


14 


externa i 
Interrupt 
Request r 


External 
Interrupt 
Request r 


External 
Function 
Request r 


External 
Function 
Request r 


15 


Spare 


Spare 


Spare 


Spare 


16 


Spare 


Spare 


Spare 


Spare 


17 


Spare 


Spare 


Spare 


Spare 


18 


Spare 


Spare 


Spare 


Spare 


19 


Data Bit 2°r 


Data Bit 2° r 


Data Bit 2° r 


Data Bit 2° r 


20 


Data Bit 2 1 r 


Data Bit 2 1 r 


Data Bit 2 1 r 


Data Bit 2 1 r 


21 


Unused 


Unused 


Unused 


Unused 


22 


Data Bit 2 2 


Data Bit 2 2 


Data Bit 2 2 


Data Bit 2 2 


23 


Data Bit 2 3 


Data Bit 2 3 


Data Bit 2 3 


Data Bit 2 3 


24 


Data Bit 2 4 


Data Bit 2 4 


Data Bit 2 4 


Data Bit 2 4 


25 


Data Bit 2 5 


Data Bit 2 5 


Data Bit 2 5 


Data Bit 2 5 


26 


Data bit 2 6 


Data Bit 2 6 


Data Bit 2 6 


Data Bit 2 6 



ORIGINAL 



2-15 



Table NAVSHIPS 0967-280-4010 CP-642B/USQ-20( V) COMPUTER 

2 " 3 INSTALLATION 
TABLE 2-3. CONNECTOR PIN ASSIGNMENTS (CONT.) 



CONNECTOR 
PIN 
NUMBER 


PERIPHERAL 
EQUIPMENT 
INPUT CHANNEL 


INTERCOMPUTER 
INPUT 
CHANNEL 


PERIPHERAL 
EQUIPMENT 
OUTPUT CHANNEL 


INTERCOMPUTER 
OUTPUT 
CHANNEL 


27 


Data 


Bit 


2 7 


Data 


Bit 


2 7 


Data 


Bit 


2 7 


na t a 

Ud Ld 


Ri t 
Dl L 


2 7 


28 


Data 


Bit 


2 8 


Data 


Bit 


2 8 


Data 

L/d Ls U 


Bit 

LJ X V 


2 8 


Da t a 


Ri t 
Dl L 


2 8 


29 


Data 


Bit 


2 9 


Data 

L/d L> CI 


Bit 

u x u 


2 9 


Da t a 


Ri t 


2 9 


Ha t a 


Oil 


2 9 


30 


Data 


Bit 


2 10 


Dat a 


Bit 

LJ ± U 


2 10 


Da t a 


Ri t 

LJ J. L 


2 10 


Ud Ld 


Rit 


2 io 


31 


Dat a 


Bit 


2 11 


Data 


Bit 


2 11 


Da t a 


Ri t 

LJ X L 


2 11 


Ud Ld 


Rit 
D 1 L 


2 11 


32 


Data 


Bit 


2 12 


Da ta 


Bit 


2 12 


Da ta 


Bit 


2 12 


Da t a 
Ud Ld 


Ri t 


2 12 


33 


Data 


Bit 


2 2 r 


Data 


Bit 


2 2 r 


Data 


Bit 


2 2 r 


Da t a 


Rit 

LJ X Li 


2 2 r 


34 


Data 


Bit 


2 3 r 


Data 


Bit 


2 3 r 


Data 

i-/d w d 


Bit 


2 3 r 


Da ta 


Rit 

Dl L 


2 3 r 


35 


Data 


Bit 


2 4 r 


Data 

Cd L* d 


Bit 


2 4 r 

Ld J- 


Data 


Bit 


2 4 r 


Da ta 

Ud Ld 


Rit 

Dl L 


2 4 r 


36 


Data 


Bit 


2 5 r 


Data 


Bit 


2 5 r 


Data 


Bit 


2 5 r 


Data 

ua l- a 


Bit 


2 5 r 


37 


Data 


Bit 


2 6 r 


Data 


Bit 


2 6 r 


Data 


Bit 


2 6 r 


Data 


Bit 


2 6 r 


38 


Data 


Bit 


2 7 r 


Data 


Bit 


2 7 r 


Data 


Bit 


2 7 r 


Data 


Bit 


2 7 r 


39 


Data 


Bit 


2 8 r 


Data 


Bit 


2 8 r 


Data 


Bit 


2 8 r 


Data 


Bit 


2 8 r 


40 


Data 


Bit 


2 9 r 


Data 


Bit 


2 9 r 


Data 


Bit 


2 9 r 


Data 


Bit 


2 9 r 


41 


Data 


Bit 


2 10 r 


Data 


Bit 


2 io r 


Data 


Bit 


2 10 r 


Data 


Bit 


2 io r 


42 


Data 


Bit 


2 U r 


Data 


Bit 


2 11 r 


Data 


Bit 


2 U r 


Data 


Bit 


2 11 r 


43 


Data 


Bit 


2 12 r 


Data 


Bit 


2 12 r 


Data 


Bit 


2 12 r 


Data 


Bit 


2 12 r 


44 


Unused 




Unused 




Unused 




Unused 




45 


Cable Shield 


Cable Shield 


Cable Shield 


Cable Shield 


46 


Unused 


2 13 


Unused 


2 13 


Unused 


2 13 


Unused 


2 13 


47 


Data 


Bit 


Data 


Bit 


Data 


Bit 


Data 


Bit 


48 


Data 


Bit 


2 14 


Data 


Bit 


2 14 


Data 


Bit 


2 14 


Data 


Bit 


2 14 


49 


Data 


Bit 


2 15 


Data 


Bit 


2 15 


Data 


Bit 


2 15 


Data 


Bit 


2 15 


50 


Data 


Bit 


2 16 


Data 


Bit 


2 16 


Data 


Bit 


2 16 


Data 


Bit 


2 16 


51 


Data 


Bit 


2 17 


Data 


Bit 


2 17 


Data 


Bit 


2 17 


Data 


Bit 


2 17 


52 


Data 


Bit 


2 18 


Data 


Bit 


2 18 


Data 


Bit 


2 18 


Data 


Bit 


2 18 


53 


Data 


Bit 


2 19 


Data 


Bit 


2 19 


Data 


Bit 


2 19 


Data 


Bit 


2 19 


54 


Data 


Bit 


2 20 


Data 


Bit 


2 20 


Data 


Bit 


2 20 


Data 


Bit 


2 20 


55 


Data 


Bit 


2 21 


Data 


Bit 


2 21 


Data 


Bit 


2 21 


Data 


Bit 


2 21 


56 


Data 


Bit 


2 22 


Data 


Bit 


2 22 


Data 


Bit 


2 22 


Data 


Bit 


2 22 


57 


Data 


Bit 


2 23 


Data 


Bit 


2 23 


Data 


Bit 


2 23 


Data 


Bit 


2 23 


58 


Data 


Bit 


2 13 r 


Data 


Bit 


2 13 r 


Data 


Bit 


2 13 r 


Data 


Bit 


2 13 r 



2-16 



ORIGINAL 



CP-642B/USQ-20(V) COMPUTER 
INSTALLATION 



NAVSHIPS 0967-280-4010 



Table 
2-3 



TABLE 2-3. CONNECTOR PIN ASSIGNMENTS (CONT.) 



CONNECTOR 
PIN 
NUMBER 



PERIPHERAL 
EQUIPMENT 
INPUT CHANNEL 



INTERCOMPUTER 
INPUT 
CHANNEL 



PERIPHERAL 
EQUIPMENT 
OUTPUT CHANNEL 



INTERCOMPUTER 
OUTPUT 
CHANNEL 



59 
60 
61 
62 
63 
64 
65 
66 
67 
68 
69 
70 
71 
72 
73 
74 
75 
76 
77 
78 
79 
80 
81 
82 
83 
84 
85 
86 
87 
88 
89 
90 



14 

Data Bit 2 r 
Data Bit 2 15 r 
Data Bit 2 16 r 
Data Bit 2 17 r 

■I Q 

Data Bit 2 r 
19 

Data Bit 2 r 
20 

Data Bit 2 r 
21 

Data Bit 2 r 
22 

Data Bit 2 r 

23 

Data Bit 2 r 

Cable Shield 
24 

Data Bit 2 



25 
26 
27 
28 
29 



Data Bit 2 
Data Bit 2 
Data Bit 2 
Data Bit 2 
Data Bit 2 
Spare 
Spare 
Unused 
Unused 

24 

Data Bit 2 r 

Data Bit 2 25 r 

Data Bit 2 r 
27 

Data Bit 2 r 

QQ 

Data Bit 2 r 
29 

Data Bit 2 r 

Spare 

Spare 

Unused 

Unused 

Unused 



14 

Data Bit 2 r 

Data Bit 2 15 r 

Data Bit 2 16 r 

Data Bit 2 17 r 

Data Bit 2 i8 r 
19 

Data Bit 2 r 
20 

Data Bit 2 r 
21 

Data Bit 2 r 
22 

Data Bit 2 r 

23 

Data Bit 2 r 

Cable Shield 
24 

Data Bit 2 



25 
26 
27 
28 
29 



Data Bit 2 
Data Bit 2 
Data Bit 2 
Data Bit 2 
Data Bit 2 
Spare 
Spare 
Unused 
Unused 

24 

Data Bit 2 r 

25 

Data Bit 2 r 

Data Bit 2 r 
27 

Data Bit 2 r 

Data Bit 2 28 r 
29 

Data Bit 2 r 

Spare 

Spare 

Unused 

Unused 

Unused 



Data Bit 2 14 r 
Data Bit 2 15 r 
Data Bit 2 16 r 
Data Bit 2 17 r 

1 o 

Data Bit 2 r 
19 

Data Bit 2 r 

20 

Data Bit 2 r 
21 

Data Bit 2 r 
22 

Data Bit 2 r 

23 

Data Bit 2 r 

Cable Shield 
24 

Data Bit 2 

Data Bit 2 25 

Data Bit 2 26 

Data Bit 2 27 

Data Bit 2 28 
29 

Data Bit 2 

Spare 

Spare 

Unused 

Unused 

24 

Data Bit 2 r 

25 

Data Bit 2 r 
Data Bit 2 26 r 
Data Bit 2 27 r 

Data Bit 2 28 r 

29 

Data Bit 2 r 

Spare 

Spare 

Unused 

Unused 

Unused 



14 

Data Bit 2 r 

Data Bit 2 15 r 

Data Bit 2 16 r 

Data Bit 2 17 r 

Data Bit 2 18 r 
19 

Data Bit 2 r 
20 

Data Bit 2 r 
21 

Data Bit 2 r 
22 

Data Bit 2 r 

23 

Data Bit 2 r 

Cable Shield 
24 

Data Bit 2 



25 
26 
27 
28 
29 



Data Bit 2 
Data Bit 2 
Data Bit 2 
Data Bit 2 
Data Bit 2 
Spare 
Spare 
Unused 
Unused 

24 

Data Bit 2 r 

Data Bit 2 25 r 

Data Bit 2 r 
27 

Data Bit 2 r 

Data Bit 2 28 r 
29 

Data Bit 2 r 

Spare 

Spare 

Unused 

Unused 

Unused 



NOTE: "r" denotes ground return side of twisted pair. 
ORIGINAL 



2-17 



Table 
2-4 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

INSTALLATION 



TABLE 2-4. WIRE ASSIGNMENT FOR DIGITAL DATA CABLE 



COLOR 


PIN 


PAIR 


Black 
White 


28 
39 


1 


Black 
Red 


49 
60 


2 


Black 
Green 


52 
63 


3 


Black 
Orange 


53 
64 


4 


Black 
Blue 


oO 
41 


5 


Black 
Brown 


29 
40 


6 


Black 
Gray 


27 
38 


7 


Black 
Yellow 


50 
61 


8 


Black 
Purple 


51 
62 


9 


Black 
Tan 


54 

65 


10 


Black 
Pink 


55 
66 


11 


White 
Red 


56 
67 


12 


White 
Green 


31 
42 


13 


White 
Orange 


10 
20 


14 


White 
Blue 


9 

19 


15 


White 
Brown 


7 

17 


16 


White 
Gray 


5 

15 


17 


White 
Yellow 


25 
36 


18 


White 
Purple 


26 
37 


19 


White 
Tan 


24 
35 


20 



2-18 



ORIGINAL 



CP-642B/USQ-2CKV) COMPUTER NAVSHIPS 0967-280-4010 Table 
INSTALLATION 2-4 



TABLE 2-4. WIRE ASSIGNMENT FOR DIGITAL DATA CABLE (CONT.) 



COLOR 


PIN 


PAIR 


White 


23 


21 


Pink 


34 


Red 


48 


22 


Green 


59 


Red 


72 


23 


Orange 


82 


Red 


22 




Blue 


33 


24 


Red 


47 


25 


Brown 


58 


Red 


70 


26 


Gray 


80 


Red 


71 


27 


Ye 1 1 ow 


81 


Red 


73 


28 


Purple 


83 


Red 


74 




lan 


84 


29 


Red 


75 


30 


rink 


85 


Green 


76 


31 


urange 


86 


Green 


77 


32 


tsiue 


87 


Green 


57 


33 


Brown 


68 


Green 


32 


14 
tji 


Gray 


43 


Green 


8 


35 


Yellow 


18 


Green 


6 


36 


Diiv.nl a 

r urp j.e 


16 


Green 


4 






1 A 

14 


37 


Green 


3 


38 


Pink 


13 


Orange 


2 


39 


Blue 


12 


Orange 


1 


40 


Brown 


11 



ORIGINAL 



2-19 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20CV) COMPUTER 

2-6 INSTALLATION 



TABLE 2-4. WIRE ASSIGNMENT FOR DIGITAL DATA CABLE (CONT.) 



rnr or 


PIN 


PA TR 














21 








44 








46 




UNUSED 




78 






< 


79 








88 








89 








90 












Cable Shield 


45 






69 





2-6. INSPECTION AND ADJUSTMENT. 

a,. PHYSICAL INSPECTION. - Make certain that all power is disconnected at the 
main power panel before making any inspection. Check the tightness of the bolts 
on the base of the computer to insure that the base is well secured. Remove the 
top cover and the side panels of the computer. Make a thorough visual check for 
loose or broken taper pins t broken or bared wires, and possible broken or damaged 
connectors. Be sure that all connectors are set firmly in place on every chassis 
because there is no interlock system. 

The following checkout procedure is used to check the mechanical operation of the 
doors and the chassis. 

(1) COMPUTER DOORS. - Release the five door locks by turning locks in a 
counterclockwise direction. Open the doors and check for binding, dents, con- 
dition of gaskets, etc. When the computer doors are open, they are held in either 
of two positions by a detent mechanism (locking mechanism) on the door guides. 
Once the doors are locked in position, the detent must be released manually. Do 
not attempt to force a door out of a detent position. When a chassis is to be 
removed from the computer, the doors must be locked in their outermost detent. 

(2) CHASSIS. - The chassis are normally shipped installed in the computer. 
Each chassis should be removed and given a thorough visual inspection before power 
is applied. Check for any damage to jacks, printed circuit modules, or wiring. 

Using the special wrench provided, turn, to OPEN, the plug assembly lock-release 
mechanism on each side of a chassis (see figure 2-10). Turn only far enough so 
that the assembly clears the side of the chassis. This disengages the plug as- 
sembly from the jacks on the side of the chassis. Manually release the chassis 
locks on each side of a chassis. Hook the two provided chassis pullers over the 
locks; the chassis should slide forward easily. When the chassis is stopped by 
the chassis stops, push the release rods on each side of th,e chassis and remove 
the chassis. 

WARNING 

Do not attempt to remove a chassis alone. Get assistance. Personnel dis- 
regarding this warning could very easily receive a serious injury. 

o_on ORIGINAL 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
INSTALLATION 



Figure 
2-10 




SPARE FUSE 
HOLDER 



PLUG RACE 
DRIVE SHAFT 



CHASSIS LOCK 




ORIGINAL 



Figure 2-10. Chassis Removal Mechanisms 



2-21 



Paragraph 
2-6a(2) 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20(V) COMPUTER 
INSTALLATION 



When all chassis have been removed, inspect the inside of the computer. Pay 
particular attention to the alignment of each plug assembly and the condition of 
the nylon rollers. Unless alignment is required, do not turn a plug assembly 
drive shaft when a chassis is removed from the computer. 



Chassis A8 contains switches exposed on the front face of the chassis. Do 
not "stand" chassis AS on its front edge. 

If alignment of the plug assembly is necessary, remove the chassis. Turn the 
lock-release mechanism in the locking direction until the assembly is disengaged 
from the drive gears. Reposition the assembly and feed it evenly back into the 
drive gears while turning the mechanism in the RELEASE direction. 

To install a chassis in the computer, reverse the removal procedure described 
in paragraph 2-6a(2). 

b. INITIAL TURN 0N~ PROCEDURE. - Energize the computer in the following manner: 

STEP 1. Operate the BLOWER POWER ON-OFF switch up to ON (indicator glows 
green). 

STEP 2. Operate the COMPUTER POWER ON-OFF switch up to ON (indicator glows 
green) . 

STEP 3. Press the PHASE STEP MODE and OP STEP MODE indicator-switches and 
then the MASTER CLEAR pushbutton. 

The computer power on sequence is completed, 

c. . NONLOGIC CHECKS. - Perform all nonlogic checks listed in paragraph 5-4. 

d. . LOGIC CHECKS, - Perform all logic checks listed in paragraph 5-3. 

e. . ADJUSTMENTS. - Perform all adjustments as required in accordance with the 
adjustment and timing procedures in paragraph 6-2. b. 

2-7. INTERFERENCE REDUCTION. 

If properly installed no interference by or to other equipment is possible. 
2-8. PREPARATION FOR RESHIPMENT. 

To prepare the equipment for reshipment, perform the following steps. 

STEP 1. Disconnect all cables attached to the equipment. 

STEP 2. Ensure that all chassis are secured in the cabinet and the doors are 
shut. 

STEP 3. Reverse the procedure given in paragraph 2-1. Include the applicable 
technical manuals with the computer and mark the box "TECHNICAL MANUALS INSIDE". 



CAUTION 



2-22 



ORIGINAL 



CP-642B/ISQ-2CKV) COMPUTER NAVSHIPS 0967-280-4010 Contents 
OPERATOR'S SECTION 

SECTION 3 
OPERATOR'S SECTION 
TABLE OF CONTENTS 

Paragraph Page 

3-1. Functional Operation 3-1 

a. . Operating Concept 3-1 

b. Operating Characteristics 3-1 

3-2. Preparation For Use 3-1 

3-3. Operating Procedures 3-1 

a. . Controls and Indicators 3-1 

(1) Blower Power ON /OFF 3-1 

(2) Computer Power ON /OFF 3-1 

(3) Mode Switches 3-1 

(4) Start-Step/Restart 3-7 

(5) Restart Speed Control 3-7 

(6) Stop 3-7 

(7) Phase Repeat 3-7 

(8) Automatic Recovery 3-7 

(9) Master Clear 3-7 

(10) Run 3-7 

(11) Program I and II 3-7 

(12) Program Selector Switch 3-7 

(13) Fault 3-7 

(14) Marginal Check 3-8 

(15) Local Control 3-8 

(16) Clock Phase 3-8 

(17) Overtemp Warning 3-8 

(18) Computer On Time 3-8 

(19) C1-C2-C3-C4 3-8 

(20) Disconnect 3-9 

(21) Jump (Selective) 3-9 

(22) Stop (Selective) 3-9 

(23) Bit Indicators 3-9 

(24) Operator Control Function 3-9 

b. Turn On Procedure . 3-9 

_c. Turn Off Procedure 3-9 

d. Modes Of Operation 3-10 

e> Manual Functions 3-10 

(1) Manual Reading 3-10 

(2) Manual Writing 3-11 

(3) Block Transfer - 3-H 

3-4. Summary of Operating Procedures , . . 3-13 

a. . Turn On 3-13 

b. Turn Off 3-13 

c. . Bootstrap Load 3-13 

d. High Speed Operations 3-13 

e. . Phase Step Operations 3-14 

_f. Operation Step 3-14 

SL- Stop 3-!4 

h.. Phase Repeat 3-14 

ORIGINAL 3_i 



Contents 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

OPERATOR'S SECTION 



TABLE OF CONTENTS (CONTj 

Paragraph Faae 

i.. Clear Fault Indicator 3-14 

j. Silence Overt emperatu re Alarm Horn 3-15 

3-5. Emergency Operation 3-15 

3-6, Test Procedures 3-15 

3-7. Operator's Maintenance 3-15 

3-8. Programming 3-15 

ja. Programming Concepts 3-15 

(1) Flow Diagrams 3-15 

(2) Basic Procedures 3-15 

b. Instruction Word 3-16 

(1) Function Code Designator 3-16 

(2) Branch Condition Designator 3-16 

(3) Operand Interpretation Designator 3-17 

(4) Index Designator 3-18 

c. Programming Symbols 3-19 

(1) Lines Of Flow 3-19 

(2) Operation Symbols 3-19 

(3) Decision Symbols 3-19 

(4) Connectors and Remote Connectors 3-19 

3-9. Repertory Of Instructions 3-21 

3-10. Bootstrap Programs • . „ 3-34 

a. Description 3-34 

(1) General 3-34 

(2) Physical 3-35 

b. Bootstrap Operation 3-35 

_c. Bootstrap Programs and Operating Procedures . . 3-35 

(1) Magnetic Tape Bootstrap 3-35 

(2) Inter-Computer Bootstrap 3-36 

(3) Paper Tape Bootstrap 3-40 



3-ii ORIGINAL 



CP-642B/USQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Illustrations 



LIST OF ILLUSTRATIONS 

Figure Page 

3-1 Computer Control Console 3-0 

3-2. U Register Bits for Manual Reading and Writing 3-11 

3-3. Block Transfer Subroutine Flow Chart 3-12 

3-4. Normal Instruction Word Format 3-16 

3-5. Input/Output Instruction Word Format . . . . 3-16 

3-6. Programming Symbols 3-20 

3-7. Magnetic Tape Bootstrap Program Record Format . 3-37 

3-8. Magnetic Tape Bootstrap Program 3-38 

3-9. Magnetic Tape Bootstrap Program Flow Chart 3-39 

3-10. Inter-Computer Bootstrap Program Record Format 3-43 

3-11. Inter-Computer Bootstrap Program 3-44 

3-12. Inter-Computer Bootstrap Program Flow Chart 3-45 

3-13. Example of Bi octal Paper Tape 3-47 

3-14. Paper Tape Bootstrap Program Flow Chart 3-48 

3-15. Paper Tape Bootstrap Program 3-49 



LIST OF TABLES 

Table Page 

3-1. Summary of Operator Control Functions 3-2 

3-2. Summary of Functions of the START-STEP RESTART Switch .... 3-8 

3-3. Block Transfer Subroutine 3-13 

3-4. Instruction Repertory and Instruction Execution Time 3-23 

3-5„ Inter-Computer Request-Reply Logic 3-42 



ORIGINAL 



3-iii 



Figure 
3-1 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20(V) COMPUTER 
OPERATOR'S SECTION 




3-0 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Paragraph 
3-1 



SECTION 3 
OPERATOR'S SECTION 



3-1. FUNCTIONAL OPERATION. 

The CP-642B/USQ-20(V) computer is a program-controlled device designed to process 
data and disperse the resulting information. Once initiated, it performs all task 
requirements with a minimum of supervision or assistance, 

a. . OPERATING CONCEPT. - Since the computer is automatic, the operator need 
only have limited experience in its operation. After initial starting, the com- 
puter operates automatically until the program has completed the tasks assigned 
or until the computer is stopped through manual intervention. 

b. OPERATING CHARACTERISTICS. - Prior to any operation of the computer and its 
program, preliminary selections must be made in a prescribed sequence. Before 
the computer is actually started, it must be powered and the desired mod of 
operation selected. Once defined by mode selection, the computer will run in that 
mode until otherwise directed by different selections. 

3-2. PREPARATION FOR USE. 

The computer, when installed, inspected, and adjusted according to procedures 
in Section 2, requires no further preparation for use. 

3-3. OPERATING PROCEDURES. 

Although the computer is basically automatic, there are provisions for manual 
control. There are switches which are used to affect the entire computer oper- 
ation, control parts of the computer operations, provide certain jump or stop 
conditions, and govern speed of operation. There are also indicator-switches 
by which a single stage can be set and switches which clear an entire register. 
The various controls are covered in this manual by first describing the function 
performed and then the procedure the operator must follow for correct operation. 

a,. CONTROLS AND INDICATORS. - (See figure 3-1 and table 3-1.) 

(1) BLOWER POWER ON/OFF. ~ Operating the BLOWER switch to the ON position 
energizes a contactor which provides power to the blowers and lights the green 
indicator adjacent to the switch. 

(2) COMPUTER POWER ON /OFF. - Operating the COMPUTER POWER switch to the ON 
position energizes a contactor which provides power to the logic circuits and 
lights the green indicator. An interlocking device prevents computer primary 
power distribution when a temperature or blower fault condition occurs. 

(3) MODE SWITCHES. - The computer is operative in one of several modes. The 
indicator-switch controls (LOAD MODE, PHASE STEP MODE, OP STEP MODE, and RUN MODE) 
allow the operator to select a specific computer operating mode. Pressing the 
LOAD MODE control locks out all interrupts, enables the AF sequence, and enables 

a jump to address 00540. Pressing the PHASE STEP MODE indicator-switch allows 
the computer to operate on a one-clock-phase-at-a-time basis. Pressing the OP 



ORIGINAL 



3-1 



Table 
3-1 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20(V) COMPUTER 
OPERATOR'S SECTION 



T5 
01 

O 
O 



u 
o 

H-> 

CO 

o 

•iH 

TJ 



s: 
o 

CD 

z 

VI 

CD 
+J 
cd 
o 

•iH 

•o 
c 



S J "H 
# ^ W J 























































O 


CLi 


















































z 






















































OS 


















































Cxi 


o 


_,[ 


























































/— N 












/— s 
















/ N 








/ — \ 




OS 


CO 


r— t 






CM 






CO 






CO 






CO 






CO 


















<c 


1 








— ' 












^ — ' 






\s 






^ — ' 


^ — ' 


~- — ' 




^ — ' 




^ ^ 




□s 


cu 


CO 




















































































CO 




















































1 H-> 


I — 1 


CO 






CD 










































rH M 


cd 


CO 






TJ 












H 


M 




H 








H 










CO 






co cd 


r-* 

C 


cd 






O 












CO 


<D 




CD 


CO 






CO 




o 


CD 




1 o 






CX 


rH CD 






c 


E 












S M 




O 










+^ 






+-> 




o 






O CO 


O T3 


CX 




o 




•H 










O CD 


o 


•rH 


o 


o 






3 




CD 






t— ■ 
B 








£ O 






•rH 


CX 












Oh 5 


cx 


tn 


Om 


CX 


CO 


o 


CX 




"O 


CX 










*H H 


E 






H-i 


CD 


CD 










o 




O 










E 




o 


E 




CX 






O CD 




o 


CO 


O 


+■> 


T5 










CD f—t 


CD 


rH 


CD SO 


CD 


•H 


CD 


o 




E 


o 




CD 


c 




H-> 


cd ss 


O TJ 


=1 


CO 


O 










<— I -Q 


r— t 




rH +-) 


1 — 1 




TJ 


o 






o 




H— 5 


CD 




CD 3 




i — i 


o 


rH 




E 










O 


o 


*D 


O tH 


O 


O 


o 






CX 






CO 




to 


T3 CX 


Lh OS 


o 


E 


■M 


CX 














>-> 




>-> 3 




rH 


E 






CD 


c 








H-> 


O E 


CO 






CO 


o 


TJ 










o cd 


o 


cd 


o o 


o 


•H 




CD 




■M 


CD 




CD 




rH 


E s? 


+■> c 


CO 


CX 


C 




cd 




















o 








U~) 


j=; 






C 


cc 


o 




c 


CO 


•H 


c 


o 










o =s 


o 


rH 


o 


o 




ed 












cd 


o 


H-> 


c 


CX 


o 


hJ 




•H 












o <w 


o 


CO 


O o 


o 


o 


o 






CX 








•rH 


CO 


^ d 


5 V 




CO 


CD 
























•H 




c 




o 


c 




a, 






OS CO 


O CD 


CO 




e 




CO 














o 










o 






o 






CD 


H 




O CD 


CD 


CO 


o 


© 


CO 


TJ 








CO H-> 


co 


1— ( 


CO 'rH 


00 


o 


Wl 


♦rH 




CO 


•rH 




to 


fH 


CD 


CO g 


CX 


+■> 


CO 




•iH 


+J 


CD 






z 


CD C 


CD 






CO 








w 


+^ 


H-> 


w 


+^ 


CO 




H-* 


CO CO 


CO 


CO 


CO 




CO 


H- 3 






o 


■H CD 


> 




•rH O 


> 




•rH 


ed 




•l-t 


cd 




•rH 


CX 




•rH C 


+-> , 


rH 


x: 






•rH 


o 






l-H 


l-H O 


O 


S 


rH rH 


o 


E 


E 


r^ 


U 


E 


rH 


rH 


E 


o 


CX 


E o 




CO 


Cu 


o 


o 


+-> 


CD 






H 


CI, 


E 


o 


Oh 


E 


o 


f-i 


CD 


cd 




CD 


ed 






E 


rH *rH 


cd tT) 


c 




rH 


CD 


•iH 


r— ( 






o 


CX o 


CD 


rH 


CX O 


CO 


rH 


CD 


a +-> 


CD 


CX -M 


CD 




o 


CD H- 1 


+-> 'rH 


CD 


ri 
>-( 


rH 


X 


c 


CD 






< 




03 




< 


OS 




Cu 


o 


CO 


CU 


O 




CU 


o 


o 


CU CO 






•l-t 


<c 


CD 


f—t 


CO 








































^ 1 


















5 

l-H 


/ x 

s 


s 




s 


s 
























S rCJ 


/■— 
















IT 


* — ' 


" — > 






u, 
























SS < 

5 H 


CU 

u 
























z 


























o en 


H 
















ss 


s 


o 




o 


o 
























a w 


CO 
















cu 




















































NO 


TJ 


TJ 




-o 


tj 
























TJ 


















l-H 


CD 


CD 




CD 


CD 




T3 




















CD 


















RAT 


rat 


rat 




rat 


rat 




sse 






sse 






sse 






sse 


rat 


















w 


CD 


CD 




CD 


<D 




CD 






CD 






CO 






CO 


CD 


















cu 


CX 


CX 




CX 


CX 




U 






U 






u 






u 


CX 


















o 


o 


O 




O 


o 










Cm 






CU 






Cu 


o 


















OS 




























































































































































< 






















































c 






C 






u 






U 






rH 






rH 




















1— 1 


CD 






CD 






CD 






CD 






CD 






CD 




















Q 


CD 






CD 
























-Q 




















Z 


U 






U 


















i 






s 




















h- ( 














< 






< 






< 






< 


















TON 


















































u 


H 


















































cu 




















































>H 


CQ 


l-H 
































* 
















H 


PUSH 


MS 


















































os 


X 






































































































> 


M 


# 






# 


























# 
















Cd 3 


















































_J 


CO 
















































































































OS 


















Q 




















































O 




























OWER 






POW 






Cx] 






MODE 






s 

cu 




























cu 






OS 






a 












B 






W 


B 


















uJ 














o 






cu 






CO 






Q 




















o 




















TE 












O 


f a 




















Ex] bu 




























S 


H < 


















H 


BLOW 
ON-0 






CU o 

o z 






Q 






C75 














03 H 


















ON 
















CU 






HA 


























o 






u o 












O 






Cu 





















3-2 



ORIGIINJAL 



CP-642B/ISQ-20CV) COMPUTER 
OPERATOR'S SECTION 



NAVSHIPS 0967-280-4010 



Table 
3-1 



cc 
a, 
< 
as 
O 

SCO 
CO 

a, co 



in 



to 



CO 



CO 



o 

CO 



o 



o 

OS 
H 

5 

O 

a: 
o 

OS 

u 

CU 

o 
o 

>H 

as 



d 
co 



CO 

-a 

4-> 03 

CO i-H 

1 — I 

« o 

« e 
-C o 

a. o 
a> 

o 

o to 

rH rH 

c 

« o 

03 -rH 
+-> H-> 
CO "H 

rH +-> 

E CX 

a> o 



I 



a> 
•o 

rH O 

-pH E 

o 

« a, 

a> 
h-* 

■o CO 
03 

a> a> 

CX to 

W CO 

1 JZ 
«£ Cu 

o 

— t c 



>> CO 
X3 p-4 



-a 
I a) 

• rH i—( 
+-> — t 
•rt O 

e h 
c 

e o 
o o 

•rH 

+3 0) 

o s 

3 — < 

U +J 
+-> 

in co 
CO 

co 

3 E 

o o 

i— ( «rH 

rH 

< CO 



I 

I— I 

•rH 03 

O 73 
W O 
o E 

-D CX 
03 03 
0) +J 

a, co 
t a. 

8° 

—i e 

*rH 
■C rH 

+J o 

H-> 

>» CO 



S 
o 

c 
3 

rH OS 

03 

> c 

o *rH 

o 

03 <W 

rH *H 

I 

H CX 
43 O 

to 

0) 
T3 

•rH 
> 
O 
U 

CU 



CO 

E 

u 

D> 03 
O T3 
U O 
CX E 



I 

3 
O 



O 
>» 

o 
e 

03 J-t 

3 O 

cr h-j 

03 CO 

rH rH 

<*H rH 
•iH 

in o 

03 t/1 

10 O 
CO 

03 *D 

rH 03 

O 03 

e a, 

rH (0 



I 

3 
o 



o 

o 
e 

03 U 

3 O 

cr -m 

03 CO 

rH rH 

<H rH 
•rH 

W O 

03 CO 

W O 
CO 

0) T3 

rH 03 

O 03 

03 CL 



cx 
o 

to 
C 

o 

■rH 

CO 
rH 

03 
CX, 
O 

rH 

03 
*-> 
3 
CX 
£ 
o 
o 



J* 

I O co 

-C O 'rH 

t» rH 

•rH O 03 

•o o 

H-> 03 E 
CO 

w o CX 

0) 0) 

e rH HJ 
O 03 

•rH CO 

+^ 03 

•H 4) « 

•rJ C CO 

03 O J5 

cx a, 

03 Vh 

rH O *H 
•rH 

03 TJ 03 > 

O 4) W'H 

!m 03 CO 

o ax; o 

tz* to CX CO 



I 

o 

rH 

CX 

o 

rH H-» 

03 

+-> E 

<4H O 

a) *ih 
+-> 

rH *rH 
03 "O 

■M E 
3 O 
CX O 
E 

O -M 

O rH 

3 

CO CO 

-M "HH 
O 

03 E 

»-i CO 

•rH rH 
Q CD 



o 
o 

CQ 



O 

iO 
O 

o 

to 
w 

03 
U 

•a 
-o 
co 

o 

cx 

CX CO 

E rH 

3 ■»-> 

•r-J W 



CX 
3 

rH 
rH 
03 
+-> 

E 



H-> 

3 
O 



O 
O 



I 

o 

rH 

CX 

O 
U 4-> 

03 

H-> E 

VH O 

CO «rH 

rH -H 

03 *D 
E 

3 O 

CX O 
E 

O h-J 

O rH 

3 

W CO 

o 

03 E 

rH CO 
•rH f-i 

£21 tn 



to 

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O r^ 

O rH 

O 03 

o +^ 

E 

C0 >H 

co 

QJ rH 
rH 

CO 



CO 



3 

o 



Ui 

CX^rJ 
E C 
3 O 

•r-J J 



0) 



H-> 
O 

z 



C/3 

o 

CU 



H 
OS 

^ < 

w co 



Oi 

•rH 

OS 



03 



ON 


T3 


HH 


03 


EH 


H-> 


<c 


CO 


OS 


H 


w 


03 


CU 


CX 


o 


O 



T3 
03 

*-> 
CO 

H-> 

o 

OS 



as 
o 

H 

< 



CX 



cx 



CO 

r^ ^ 
H-> _J 

3 ^ 

03 



E 
3 
o 
a 



03 

H-> 

cc 

rH 
03 
CX 

o 



03 
+J 
CO 
rH 
03 

CX 

o 



03 
+-> 
CO 

rH 

03 
CX 
O 



T3 

03 
H-> 

CO 

rH 

03 
CX 

o 









I— ( 

1 




o 


CO 




^ g 




CU 


O E-f 






CO rH 




H 


X 3= 


CQ 




CO CO 








g 




CU 



33 
OS O 

> rH 

J CO 



U 
CO 

o 

OS 



o 

OS 

H 



H 

as 

s 

CO 



CO OS 



o 
as 
H 



CO w 

S55 







< 




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CU 


u 




t-t 

H OS 


w 


< tx3 
S > 


HAS 


O O 
H O 
S Ex] 


CU 


< OS 



ORIGINAL 



3-3 



Table 
3-1 



NAVSHIPS 0967-280-4010 



C?-642B/USQ-20(V) COMPUTER 
OPERATOR'S SECTION 



W 33 

O CU 

z < 

w os 

a: a, 



1 








-o 


1 












o 


CO 








CD 






rH 


o 








a. 








X3 






o 






















a, c 


CD 


*o 




"O 




a 


as 


•iH 




CD 


4-> 


0) 




o 






4-> 


rH 


rH 


0) 




rH 


+j 


T3 




CD 


3 


Oh 




<H 


w 


CD 


W 


■P 


co 


</J 




I 


H-> 


*h 


a> 


E 




1 




Cl, 


o 


CD 


+-> 


CD 




si 




•iH 


o 




co 




S 


Cn 




r-H 




c 


o 


s 


CO 


•H 








CU 


•iH 


CO 


*h 








CD 




73 


rH 


OJ 






c 




CD 


E 




O 


CO 






+-> 




*rH 


© 


rH 


CD 




OS 








>h 


a. 


■P 








O 


rH 


o. 




re 


to 


VI 


+-> 


+-> 


o 




Cn 


o 


e 




o 






CU 


c 


•H 


o 


CO 


CD 


E 


CD 


CO 


•H 




•rH 


CD 


p— i 


CO 


T3 


u 


rH 


c 


+-> 


rH 


cd 


rH 


O 


■P 




h- 1 


CD 


O 


CO 




E 


CO 





CO 



co 



TP 



in 



co 



H 
O 



3 
CJ 
rH 
•H 
O 

u 

CD 
3 

Qh 

E 

O CD 

o 

r— ' E 

i— f 

CO c 
3 

W 03 
M 

CO w 

CD -P 

i— I (D 

O CO 



CO 

E 
to 

rH 

CP 
O 

u 

Cu 

w e 

cu o 

•P *H 
CO 4-1 
O -<H 
•rH 73 
XJ E 

E O 

rH O 



CO 
"H 

O 
U <D 

cu j=; 

4-1 o 
3 

a c 

E -H 

O ©> 

O rH 
CO 

CD E 
4-1 



rH 

WOE 

CD £ o 

4-1 CD -r-l 

CO E 4-1 

O -H 
H COD 
E 

E E O 
— t 'i-f O 



rH E 

CD 'rH 

T3 4-> 

E CO 

3 U 

CD 

CO CU 

•rH O 

rH E 

a> £ 
o 

3 

Cu co 

E 4^ 

O *ri 

o 

<4H 

tfl o 

CD 

4-> 

CO O 

t> u 

•rH 4-> 

-O E 

c o 

I— I o 



rH 
O 

► I 

CO CD 

- U 

CM 

* CD 

>■ — ' 

O 

T3 4-> 
CD 

4-> CD 

O CO 

CD CO 

CD Cu 
CO 

co o 

CD O 

rH rH 

XJ o 
co 

E 

tiJ TT 



4-1 

CO 
CD 

a. 

CD 

as 

CD 
co 
CO 

-c 

0-t 

CP 

c 

•rH 
rH 

3 

*u 
-a 

CD • 

•P <D 

CO T3 

CD O 
Q- E 



o 




u 










1— ( 




CD 






rH 




o 




dm 


re 




te 




rH 




CD 


3 




3 


T3 


CO 




4-1 


4-> 




a. 


CD 


rH 


CD 




CO 




s 


•rH 


3 


3 


CD 


Jh 




o 


rH 


O 


w 


> ^ 


CD 




o 


a. 


•rH 




•rH 


Ou 






a. 


4-1 


•r-t 


w o 


E 






CO 


rH 




W LO 


CD 




i 




CO 


cn 


CD rH 


4-> 




•rH 


CO 


CU 


in 


O — H 

X w 


er 




4-> 


•iH 


CO 


CD 


CD 


> 




CD 


rH 






o 


© 


E 




CD 


co 




CO O 




u 


+-> 




CD 


Vi 


CD sO 


in 


o 




o 


4-> 


•rH 


4-> ^ 


CD 




w 


CU 


CO 




CO 


o 




*o 




o 


CD 


O CD 


E 




rH 


o 


•r-t 


w 


*"H rH 


CD 




o 


•H 


T3 


CO 


T3 3 


rH 


CO 


o 


cn 


E 




E 4-> 


•r-t 


rH 


CD 


o 


hH 


a. 


rH CO 


c/) 


CO 


OS 


i — p 



o 

hH 

H 

hH 

S3 







o 




1— 1 


•a- 




CD 




in 


OS 


Wl 




CD 




rH 




CU 



CD 
CO 

w 

rH 
Dh 



CD 

W3 
CO 

CD 

rH 
Oh 



T3 
CD 
W 
w 
CD 

rH 

CU 



T3 
0) 

w 

00 

CD 

fH 
Qh 



Cu 

>H 

H 



E 

CD 
CD 

rH 



E 

CD 
CD 
U 

o 



CD 
05 



T5 
CD 
OS 



X5 
CD 
OS 



•rH 



CM 

* 



TP 



33 
OS O 

bJ CO 



o 

OS 
H 
z 
o 



OS 

< 

•— ] 

o 

OS 

s 



OS 



E 
CO 



OS 

OS 
Cu 





U 








< 














< 




Cju 





o 

OS 

H 



sa 

33 
Cu 

8 

O 

uJ 

O 



Qu 

OS 

> 
o 



t— I 
H 



OS 

cu 

8 



3-4 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER 
OPERATOR'S SECTION 



NAVSHIPS 0967-280-4010 



Table 
3-1 



02 Qu 



CO 

I 

CO 



o 

CM 



o 

CM 



o 

CM 



o 

CM 



CM 



CM 



CM 



CM 



CM 
CM 



O 

o 



en 



H 
O 

O 
H 



02 
O 
H 
< 
02 
LJ 
CU 
O 

o 
>H 
< 



I 

CO 

3 



o 



CO 

<L> U 
<D O 
■P £} +J 
cd 

<M O O 
O +-> -H 

CO ?H 

+J CD t-i 

C P 

ID W 

-p «h j=; 

C tttJ 

O CD 

O fn C 

o 

CD O 

CD >> 

5 W — i 

O <D Q. 

r- 1 i— I to 

i— i <D *<■■• 



CD 

+-> 

CD 

o > 
CO 

CD X 

rH 

O CO 

E CD 

fn o 

O P 

CD £ CD 

c w 

O CO 

p > 

co O ■<-< 

CD CD P 

+j c o 

cc c 

o o 
o 

-o 

S3 

H T3 ^5 



OS 

CD 

<w 
O 

fn 

+j CD 
C -P 
CD (A 

s 

o> 



Cn 

•rH 
P 

1 

CD 
U 

o 

c ■ 



CO 



CO CD 
CD 



CD 
U 

J* 

o 
o 



CD 
E 



CD CD 

-C <D 

P »H 

CO CU 

-P 

•rH CD 

,Q ^ 

•rH +-> 

c «w 

i— i o 



Co I 
E CD 
•iH 02 
■P 

C C 

CD *Hi 

e 

CD J-< 

f-i CD 

O P 

CD W 

Cn 
CD CD 
Xj >h 
+-> 

h- CD 
CO QQ 
P ' O 
CD E 

x: 

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XI CO 
C ^ CD 
MOO, 



<4H 

o 

CD 
?h 
O 
E 

U 
o 

CD 
C 

o 



CD 
> 
CO 

x: 

to 
CD 

x: 
o 
p 

•rH 

C/l 
CO 

CD 0- 

P S 

CO G 
O 
•i— I 

"C CD 

c x: 

HH -P 



CD 

-p 

CO 

> 



T3 - 

CD lO 

•rH sO 
V-t 

-H fn 

o o 

0) 

CL, i— l 

to 

2 11 

E fH 

3 o 

CO to 

-P to 

•r-l CD 

E *h 

fn T3 

CD 

Qu CO 



T3 ► 

<D UO 

•fH vO 
•rH f-l 

o o 

CD 

CL —i 
w sO 

S 11 

G, 

E ^ 
3 o 

W 00 
•iH CD CO 

E H 

fH ^ II 

CD XJ 
O-i CO — 2 



<D lO 

sO 

•r-l H 

O O 

CD 

Cl t— i 

S" 

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3 O 

V) to 

■p to 

•H 1) CO 

S n 

CU CO ••— ; 



O 

0) 
S-i 

o 
E 

w 

rH CD 

o x: 

o 

CD T3 



CD 
> 
CO 



to 

CD Cm 

■P O 

CO H 

O CO 



CD 

to O 
CD 



CD 
to 



CD CD 
C JS CD 
H +J £ 



o 



o 

Qu 



a. 



a. 



a. 



13 



< 
02 
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ORIGINAL 



3-5 



Table 
3-1 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20(V) COMPUTER 
OPERATOR'S SECTION 



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3-6 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER 
OPERATOR'S SECTION 



NAVSHIPS 0967-280-4010 



Paragraph 
3-3a(3) 



STEP MODE indicator-switch allows the computer to execute one instruction at a 
time. Pressing the RUN MODE indicator-switch allows the computer to operate at 
normal high-speed. When pressed, each amber MODE indicator switch glows. 

(4) START- STEP/ RESTART . - Once a mode selection has been made, the computer is 
started by operating the START-STEP/RESTART switch. The function of the computer 
is dependent on the mode selected and the initiation of the START-STEP/RESTART 
switch. Table 3-2 summarizes the action performed by the various selections. 

(5) RESTART SPEED CONTROL. - Operating the RESTART SPEED CONTROL varies the 
frequency of the low-speed oscillator. Its functions are noted in table 3-1. The 
low-speed oscillator frequency varies between two and 200 cycles per second. 

(6) STOP. - The STOP switch, when operated, disables the high-speed operation 
of the computer. It extinguishes the RUN indicator [see paragraph 3-3a.( 10 )] and 
discontinues the operations of the run circuits. 

(7) PHASE REPEAT. - The operation of the PHASE REPEAT switch forces the 
repetition of the selected clock phase [see paragraph 3-3a.(16)]at a high-speed 
operation rate. The PHASE REPEAT switch is active only if the phase step mode is 
active . 

(8) AUTOMATIC RECOVERY. - The AUTOMATIC RECOVERY switch, when selected, gives 
direction to the computers activity after a program fault condition arises. 
Positioning the switch in the up position causes all interrupts to be locked out 
and initiates a jump to address 00540 (if a program fault occurs) and the automatic 
execution of the Bootstrap program. With the switch in the center position, a 
jump to 00000 and action appropriate to the program at that address occur after 

a program fault. For additional information, refer to paragraphs 3-3a,(l2) and 3-10. 

(9) MASTER CLEAR. - Pressing the MASTER CLEAR pushbutton clears all registers 
and timing sequences and results in the setting of the RUN MODE indicator and its 
associated circuitry (if the computer is not in high-speed operation). Operating 
the pushbutton during high-speed operations clears only the FAULT indicator. 

(10) RUN. - The green RUN indicator-switch glows when the computer is in high- 
speed operation. Operating the STOP switch during high-speed running disables 

the operation and extinguishes the RUN indicator. 

(11) PROGRAM I AND II. - The operation of the PROGRAM I or II indicator-switch 
indicates the Bootstrap program (see paragraph 3-10) that will be performed when 
the program is manually initiated under load mode. It also indicates the bootstrap 
utilized when the program is referenced by means of the AUTOMATIC RECOVERY switch 
[see paragraph 3-3a.(8)]. The corresponding green PROGRAM I or II indicator glows 
when selected. For additional information refer to paragraph 3-3a,(l2). 

(12) PROGRAM SELECTOR SWITCH (PROGRAM i/ll). - The program selector switch 
provides manual selection of the program that is referenced when in the automatic 
recovery mode. The switch is located on logic module J35A on chassis A5. Refer 
also to paragraphs 3-3a,(8) and (11). 

(13) FAULT. - The red FAULT indicator glows whenever the computer encounters 
a program fault condition. Function codes 00 and 77 are fault conditions which, 
if executed, cause a fault interrupt within the computer. The FAULT indicator 
glows during this condition and can be extinguished only by operating the MASTER 
CLEAR pushbutton. 



ORIGINAL 



3-7 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20( V) COMPUTER 

3-3^(14) OPERATOR'S SECTION 



TABLE 3-2. SUMMARY OF' FUNCTIONS OF THE START-STEP/RESTART SWITCH 



SELECTION 


MODE 


COMPUTER ACTION 


START-STEP 


RUN 


Initiates hicrh— sDeed oDeration 


RESTART 


RUN 


Allows self-recovery from program 
stops . 


START-STEP 


OP STEP 


Allows the execution of one in- 
struction each time the switch is 
operated. 


RESTART 


OP STEP 


Allows initiation of instructions at 
a repetition rate controlled by the 
RESTART SPEED CONTROL and low-speed 

o s ft i 1 latnr 


START-STEP 


PHASE STEP 


Generates one clock phase each time 
the switch is operated. 


RESTART 


PHASE STEP 


Generates clock phases at a rate 
controlled by the RESTART SPEED 
CONTROL and low-speed oscillator. 


START-STEP 


LOAD 


Initiates high-speed operation 
starting at address 00540 (executes 
bootstrap) . 


RESTART 


LOAD 


Not used. 



(14) MARGINAL CHECK. - The amber MARGINAL CHECK indicator glows when a memory 
chassis is in the marginal check condition. 

(15) LOCAL CONTROL. - When the computer is under the control of its own oper- 
ating console the amber LOCAL CONTROL indicator glows. 

(16) CLOCK PHASE. - The CLOCK PHASE indicator-switch indicates generation of 
the corresponding Master Clock phase. Pressing the switches in conjunction with 
phase repeat mode [see paragraph 3-3jj.(7)] allows the repetition of the selected 
clock phase at a high-speed rate of operation. 

(17) OVERTEMP WARNING. - The computer' s temperature sensing circuits cause the 
alarm horn to sound and the red OVERTEMP WARNING indicator-switch to glow whenever 
the internal cabinet temperature exceeds 46°C (115°F). Automatic shutdown occurs 
at 60°C (140°F). Pressing the OVERTEMP WARNING indicator-switch silences the alarm 
horn, 

(18) COMPUTER ON TIME. - The COMPUTER ON TIME meter cumulatively records the 
time that power is on for distribution to the computer logic circuits. The meter 
ranges from to 9999.9 hours and cannot be reset. 

(19) CI - C2 - C3 - C4, - The two C register rotary switches allow switching 
between the four C register and the C register indicator-switches. Operating the 



3-8 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 

switches to the appropriate setting allows the selected register to be displayed. 
The setting of a specific stage (or stages) can then be accomplished if desired. 
The left switch permits the upper 15 bits to enter the indicator display and the 
right switch allows the lower 15 bits to enter the display. 

(20) DISCONNECT. - The operation of the disconnect circuit involves an indi- 
cator and three switches. Selecting (operating to the up position) any of the three 
switches (RTC, ADV P, or B7) causes the red DISCONNECT indicator to glow. Select- 
ing the B7 switch inhibits the decrementing of the B7 register during the repeat 
mode of operation. Selecting the ADV P switch inhibits the incrementing of the P 
register. Selecting the RTC switch inhibits the incrementing of the real-time 
clock register. 

(21) JUMP (SELECTIVE). - The red JUMP indicator glows when any or all of the 
three Selective Jump switches (1, 2 f or 3) are selected (operated to the up po- 
sition). Selecting the switches allows manual selection or omission of pre- 
determined program sections in conjunction with the 61 or 65 instructions, 

(22) STOP (SELECTIVE). - The red STOP indicator glows when any or all of the 
Selective Stop switches (5, 6, or 7) are selected (operated to the up position). 
Selecting the switches allows program monitoring when used in conjunction with 
appropriate 61 and 65 instructions. The red STOP 5, 6, or 7 indicators glow when 
a corresponding switch is selected, and another indicator glows when the program 
stop occurs. 

(23) BIT INDICATORS. - The remaining arrays of indicator-switches and clear 
switches are associated with the registers, designators, and sequences of the 
computer. Pressing any register indicator-switch sets that stage and lights the 
associated neon indicator. The entire register is cleared by operating the associ- 
ated clear switch. The operation of the designator and sequence indicator-switches 
and the clear switches is identical to those of the various registers. 

(24) OPERATOR CONTROL FUNCTION, - All controls, indicators, indicator-switches, 
and switches have prescribed functions to follow to obtain correct indications and 
maintain control over the computer. 

b. TURN ON PROCEDURE. - To supply power to the computer operate the BLOWER POWER 
switch to the ON position. Power from the external source energizes a contactor 
which provides voltage to the centrifugal blower. This selection lights the green 
indicator adjacent to the switch. Protection against short circuits is provided 

by 15 ampere fuses. Once blower power is supplied, operate the COMPUTER POWER 
switch to the ON position. Power from the external source energizes a contactor 
which applies power to the computer logic circuits. This selection lights the 
green indicator adjacent to the switch. The computer power also has short circuit 
protection provided by 15 ampere fuses. 

Releasing the BLOWER POWER or the COMPUTER POrfER switch allows the switch to re- 
turn to the neutral position. During the operation of the computer, a temperature 
or blower fault will remove regulated power. A temperature or blower fault during 
the initial turn on procedure prevents the application of regulated power to the 
computer. 

c, . TURN OFF PROCEDURE. - To remove power from the computer, operate the BLOWER 
POWER switch to the OFF position. This removes power from the interlocking relays. 
The relays open and remove all power from the computer. 



Paragraph 
3-3a(l9) 



ORIGINAL 



3-9 



Paragraph 
3- 3d 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20( V) COMPUTER 

OPERATOR'S SECTION 



d. . MODES OF OPERATION. - To initiate a mode of operation for the computer, the 
prescribed routine must be followed. 

To operate the computer in run mode, following power application, press the 
PHASE STEP MODE, OP STEP MODE and the MASTER CLEAR switches in order. The computer 
is cleared, and the amber RUN MODE indicator-switch glows, indicating that the run 
mode is enabled. If a starting address other than 00000 is desired, it must be set 
in the P register. Operate the START- STEP/ RESTART switch to the START-STEP position, 
and the computer starts. 

To initiate the run mode after another mode (op step, phase step, or load) has 
been selected, press the RUN MODE indicator-switch. This allows the computer to 
initiate high-speed operation when started and permits the execution of the former 
program, starting from the address at which it stopped, or a new program, by setting 
a different address in P. Operate the START-STEP switch down and the computer 
starts. This lights the green RUN indicator. 

To operate the computer in the op step (Operation Step) mode, press the MASTER 
CLEAR switch and the OP STEP indicator-switch. Operating the START-STEP/RESTART 
switch down initiates the execution of one instruction. Operating the START-STEP/ 
RESTART switch up (locked) causes the computer to initiate the instructions under 
control of the restart speed control circuits. 

To operate the computer in the phase step mode and accomplish the issuance of one 
clock phase pulse, press the MASTER CLEAR switch, and the PHASE STEP MODE indicator- 
switch. Operate the START-STEP/RESTART switch to the START-STEP position, and 
computer operation is initiated. The computer then issues progressively (1, 2, 3, 
and 4) one clock phase each time the START-STEP/RESTART switch is operated to the 
START-STEP position. To generate progressive clock phases at a rate controlled 
by the restart speed control circuits, operate the START-STEP/RESTART switch up to 
RESTART (locked) position. 

To operate the computer in the load mode, press the MASTER CLEAR and LOAD MODE 
switches, and operate the START-STEP/ RE START switch down to the START-STEP position. 
The computer automatically starts the program at address 00540^ (bootstrap). Im- 
mediately upon starting, the LOAD MODE indicator-switch will extinguish and the 
green RUN and amber RUN MODE indicators will glow, signifying high-speed operation. 

e, . MANUAL FUNCTIONS. - The following procedures for manually reading and writing 
can be used in performing operations used in testing and debugging programs and in 
maintenance of the computer. In the following paragraphs, the Q register is 
utilized. Similar operations are accomplished using the A register and related 
instruction references. 

(1) MANUAL READING. - To transfer information from one memory address location 
to the Q register, master clear the computer; press the Af En (Af Enable) indicator- 
switch to allow the generation of the proper command signals when the computer is 
started; press the appropriate indicator-switches in the U register for enter Q 
instruction (f = 10, j = 0, k = 3 and b = 0). The y portion of the U register is 
loaded with the memory address from which the information is to be extracted. 
(See figure 3-2,a . ) Once the U register is properly set, press the OP STEP MODE 
indicator-switch. Operate the START-STEP/RESTART switch to the START-STEP position. 
The computer operates, the word from memory is located in the Q register, and the 
computer stops. 



3-10 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Paragraph 
3-3e(T) 



a. 


001 000 

f 


000 

j 


Oil 
k 


000 
b 


15 BITS (DESIRED ADDRESS) 

y 






b. 


001 100 

f 


000 

j 


Oil 
k 


000 
b 


15 BITS (DESIRED ADDRESS) 

y 



Figure 3~2 # U Register Bits for Manual Reading and Writing 



Information can be transferred from consecutive addresses to Q by setting up the 
repeat mode for enter Q. Master clear the computer and press Af En. Manually set 
the U register to 70100 00003. Operate the DISCONNECT B7 switch to the up position 
Press the OP STEP MODE indicator-switch and then operate the START-STEP/RESTART 
switch to the START-STEP position. The repeat mode is now active. Clear U and 
manually set Uu to 10030 with UL equal to the address of the first desired memory 
reference. Repeated operations of the START-STEP/RESTART switch to the START-STEP 
position enter the contents of consecutive addresses in Q for inspection. 

(2) MANUAL WRITING. - To write from the Q register into one of the storage 
locations, master clear the computer; press the Af En (Af Enable) indicator-switch 
to allow the generation of the proper command signals when the computer is started; 
press the appropriate indicator-switches in the U register for a store Q instruc- 
tion (f = 14, j =0, k= 3, and b = 0). The y portion of the U register is loaded 
with the memory address that is the destination of the word in Q (see figure 3-2b). 
Set the word to be stored in the Q register. Press the OP STEP MODE indicator- 
switch. Operate the START-STEP/RESTART switch to the START-STEP position. The 
computer operates and stops, and the desired word is located at the selected memory 
location. 

Information can be stored in consecutive addresses from Q by setting up the re- 
peat mode for the store Q instruction. Master clear and press the Af En indicator- 
switch. Set the U register to 70100 00003 t operate the DISCONNECT B7 switch to the 
up position, press the OP STEP MODE indicator-switch, and then operate the START- 
STEP/RESTART switch to the START-STEP position. The repeat mode is now active 
Clear U and enter Uu with 14030 and UL with the lowest address of the desired 
storage locations. Enter Q with the information to be stored. Operate the START- 
STEP/RESTART ^ switch to the START-STEP position. The word in Q is stored in the 
address specified by UL. Load Q with new information and operate the START-STEP/ 
RESTART switch to the START-STEP position. Consecutive addresses can be referenced 
for storage in this manner. The same word or different words can be stored. 

(3) BLOCK TRANSFER. - Block transfer utilizes a small routine which must first 
be entered m computer memory. This routine can be loaded into the computer man- 
ually or via other input devices if the proper loading routine is stored in memory 
(see figure 3-3). The block transfer subroutine is shown in table 3-3. 

When the block transfer has been loaded, perform the following sequence of manual 
operations: Master clear the computer. Set the P register equal to the initial 
address of the subroutine (see ml of table 3-3). This permits the computer, when 
started, to perform the instruction contained at that location. Operate the START- 
STEP/RESTART switch to the START-STEP position; this starts operations at normal 
high-speed. When the transfer is completed, the computer will stop with the red 
STOP 4 indicator lighted. 



ORIGINAL 



3-11 



Figure 
3-3 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20C V) COMPUTER 

OPERATOR'S SECTION 




Example: 

Transfer words in addresses 01520 - 01525 to addresses 01630 - 01635. 

1st cycle - Transfer word from y x (01520) + N(5) to y 2 (01630) + 
N(5) and Bl - 1 (N = 4). 

2nd cycle - Transfer word from (01520) + N(4) to y 2 (01630) + 
N(4) and Bl - 1 (N = 3) . 

3rd cycle - Transfer 01523 to 01633 and Bl - 1 (N = 2). 

4th cycle - Transfer 01522 to 01632 and Bl - 1 (N = 1). 

5th cycle - Transfer 01521 to 01631 and Bl - l (N = 0). 

6th cycle - Transfer 01520 to 01630 and jump (Bl = 0) and STOP 4. 



3-12 



Figure 3-3. Block Transfer Routine Flow Chart 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER 
OPERATOR'S SECTION 



NAVSHIPS 0967-280-4010 
TABLE 3-3. BLOCK TRANSFER SUBROUTINE 



Paragraph 
3-4 



RELATIVE 
ADDRESS 


INSTRUCTION 


FUNCTION 


ml 


12100 N 


Enter Bl with number of words to be 
transferred, less one (N) . 


m2 


10031 yl 


(yl equals lowest address of block to 
be transferred.) Enters word from 
highest address to be transferred. 


m3 


14031 y2 


(y2 equals lowest address of new 
storage location.) Stores word at 
highest address of new location. 


m4 


72100 m2 


If Bl = 0, read ,NI; if Bl ^ 0, Bl - 1 
and jump to m2. (This operation stops 
transfer when all words have been 
transferred. ) 


m5 


61400 ml 


Jump to beginning of routine and 
STOP 4. 



3-4. SUMMARY OF OPERATING PROCEDURES. 

The following step-by-step procedures are those to be followed for the listed 
operations . 

a. TURN ON. 

STEP 1. BLOWER POWER switch to ON. 
STEP 2, COMPUTER POWER switch to ON. 

th ST S«™ rflll the ™ SE STEP M0DE and 0P STEP MODE indicator switches, and 
the MASTER CLEAR pushbutton switch. 

b. TURN OFF. 

STEP 1. BLOWER POWER switch to OFF. 

c. BOOTSTRAP LOAD. 

STEP 1. Master clear the computer. 

STEP 2. Press LOAD MODE. 

STEP 3. Press PROGRAM I or II. 

STEP 4. Operate the START-STEP/RESTART switch to START-STEP. 

d. HIGH SPEED OPERATIONS. 

STEP l. Master clear the computer. 

STEP 2. Set starting address in P register. 

STEP 3. Operate the START-STEP/RESTART switch to START-STEP. 



ORIGINAL 



3-13 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

3 ~ 4 £ OPERATOR'S SECTION 

e. PHASE STEP OPERATIONS. 

STEP 1. Master clear the computer. 

STEP 2. Press PHASE STEP MODE. 

STEP 3. Set the instruction in the U register. 

STEP 4. Operate the START-STEP/ RESTART switch to START-STEP (for one clock 
phase) . 

STEP 5. Operate the START-STEP/ RESTART switch to START-STEP (for each additional 
clock phase desired) . 

or 

STEP 1. Repeat steps 1 thru 3. 

STEP 2. Operate START-STEP/ RESTART switch to RESTART. 

STEP 3. Rotate RESTART SPEED CONTROL switch to the desired rate of clock phase 
control . 

STEP 4. Operate the START-STEP/ RESTART switch to neutral to stop. 

f. OPERATION STEP. 

STEP 1. Master clear the computer. 

STEP 2. Press OP STEP MODE. 

STEP 3. Set starting address in P register. 

STEP 4. Operate the START-STEP/ RESTART switch to START-STEP (for one in- 
struction execution. 

STEP 5. Operate the START-STEP/RESTART switch to START-STEP (for each ad- 
ditional instruction execution desired). 

or 

STEP 1. Repeat steps 1 thru 3. 

STEP 2. Operate the START-STOP/ RESTART switch to RESTART. 

STEP 3. Rotate RESTART SPEED CONTROL switch to the desired rate of instruction 
execution. 

STEP 4. Operate the START-STEP/RESTART switch to neutral to stop. 
£. STOP. - Operate STOP switch down at any time to stop operation, 
h. PHASE REPEAT. 

STEP 1. Master clear the computer. 
STEP 2. Press PHASE STEP MODE. 
STEP 3. Press desired CLOCK PHASE. 

STEP 4. Operate the PHASE REPEAT switch to the up position. To advance the 
clock it is necessary to press the phase indicators in order. 

STEP 5. Operate the PHASE REPEAT switch to neutral to stop, 
j,. CLEAR FAULT INDICATOR. - Press MASTER CLEAR. 



3-14 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 

L SILENCE OVERTEMPERATURE ALARM HORN . - Press the OVERTEMP WARNING indicator. 
3-5. EMERGENCY OPERATION. 

There are no emergency, operat ion procedures for the computer, 
3-6. TEST PROCEDURES. 

No test procedures are to be performed by the operator. See Section 5 for 
troubleshooting and test procedures. 

3-7. OPERATOR'S MAINTENANCE . 

See Section 5 for operator maintenance routines. 

3-8. PROGRAMMING. 

a.. PROGRAMMING CONCEPTS . - Once the program is written and coded in an acceptabl 
form, it is entered into the storage section of the computer. From this point, the 
computer, upon proper initiation, executes the instructions of the program. The 
instructions of the program are stored in the memory (storage) section of the com- 
puter in a sequential manner. The computer will first execute the instruction 
located at the lowest address of the program and proceed to the highest address. 
From its storage location, the instruction is moved to the control section, where 
the computer analyzes the instruction to determine the method of execution! (The 
instruction in its original form is not altered in memory due to this process.) 
Normally, the next instruction to be executed is located at the address that is, in 
value, one greater than the address of the previous instruction. 

Any problem that can be solved by mathematical procedures can be solved by the 
computer. If it is determined that the problem can be best solved by the computer, 
it is then necessary to formulate the problem in the language of the computer. A 
program of instructions and the data needed for the solution of the problem must 
be devised. 

(1) FLOW DIAGRAMS. - A flow diagram is helpful in facilitating the coding or 
programming of the problem. A flow diagram or flow chart indicates the flow, or 
series of steps, in the computation that leads to the solution of a particular 
problem. A basic flow diagram usually lists the series of simple arithmetic steps 
that are to be performed by the computer. It is imperative that the coder be 
familiar with the overall operations and the peculiarities of each computer in- 
struction so that he can construct the outline with regard to the capabilities of 
the computer. 

(2) BASIC PROCEDURES. - Usually, more than one flow diagram is formed for more 
complicated problems. The first flow outline may be equations in mathematical 
language written in the sequence in which they will be computed, together with 
brief explanations of the steps involved. The second flow chart formulates the 
flow of computation as the problem will be computed in the computer. This chart 
contains the instructions necessary for the data input, the instructions that 
operate on the input data to obtain the solutions, and the necessary instructions 
for the output of the results. Many problems are such that the second type of flow 
diagram will consist of many charts and/or diagrams, each a more detailed pre- 
sentation of the preceding chart. 



Paragraph 
3-4i 



ORIGINAL 



3-15 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20CV) COMPUTER 

3 ~ 8 £ OPERATOR'S SECTION 

b. INSTRUCTION WORD. - The instruction word is placed in the U register and its 
outputs are applied to translator circuits which interpret the bits. The instruc- 
tion word bits are illustrated in figures 3-4 and 3-5. Further simplification of 
the word is attained by using the octal numbering system because of the ease of 
conversion. The binary notation of an instruction could be as follows: 

001 100 010 Oil 101 000 010 001 111 110 

Octal notation of the same instruction would be 14 2 3 5 02176. The desig- 
nators can be stated as f = 14, j = 2, k = 3, b = 5, and y = 02176. The transla- 
tion of these designators determines the exact method of executing the instruction, 

(1) FUNCTION CODE DESIGNATION. - The f designator appears in bit positions 29 
through 24 of the U register or an instruction and designates the function to be 
performed by that instruction. All values of f other than 00 and 77 are defined 
in the instruction repertoire (see table 3-4). Codes 00 and 77 are program fault 
conditions; if executed, they cause a fault interrupt and a jump to address 00000, 
the fault entrance register, or address 00540 of memory, depending on the AUTOMATIC 
RECOVERY switch setting. 

(2) BRANCH CONDITION DESIGNATOR. - The j designator appears in bit positions 
23, 22, and 21 of the U register or an instruction; it is used in a majority of 
the instructions. The three primary uses of j are for jump and skip determination, 
for B register specification, and for repeat status interpretation. Appropriate 
interpretations of the j designator are listed either below or under the descrip- 
tions of the individual instructions. 

For those instructions in which the j designator has no special interpretation, 
it specifies the condition under which the next sequential instruction in the 
program will be skipped. This permits branching from a sequence without executing 
a jump instruction, as would normally occur if a skip condition were not satisfied. 



f 


j 


k 


b 


y 


29 




24 


23 - 21 




20 - 18 


17 


- 15 




14 




00 






Figure 3-4. 


Normal Instruction 


Word 


Format 






f 


t 


\ 


b 


y 


29 




24 


23 - 20 




19 - 18 


17 


- 15 




14 




00 



Figure 3-5. Input/Output Instruction Word Format 

NOTE: j = C n Input/Output Channel 



3-16 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Paragraph 
3-8b(2) 



A skip of the next sequential instruction is determined by the following rules 
in all instructions except 04, 12, 13, 16, 17, 26, 27, 60-67, and 70-76: 



0: 


Do not skip the next instruction. 






1: 


Skip 


the 


next 


instruction. 










2: 


Skip 


the 


next 


instruction 


if 


(0) 


is 


positive. 


3: 


Skip 


the 


next 


instruct ion 


if 


(0) 


is 


negative . 


4: 


Skip 


the 


next 


instruction 


if 


(A) 


is 


zero (positive zero) 


5: 


Skip 


the 


next 


instruction 


if 


(A) 


is 


nonzero . 


6: 


Skip 


the 


next 


instruction 


if 


(A) 


is 


positive. 


7: 


Skip 


the 


next 


instruction 


if 


(A) 


is 


negative. 



When the branch condition involves the sign of the quantity in A or Q, the evalu- 
ation examines the sign bit of these quantities; hence, positive zero (all zeros) 
is considered a positive quantity, and negative zero (all ones) is considered a 
negative quantity. 

For input/output instructions, the j designator appears in bit positions 23, 22, 
21, and 20 of the U register or an input/output instruction and specifies the chan- 
nel for the instruction. Bit 23 assumes a value of eight, bit 22 a value of four, 
bit 21 a value of two, and bit 20 a value of one; thus, the j designator provides 
accessibility to the sixteen (decimal) input/output channels (numbered 0-17s). In- 
structions 13, 17, 62, 63, 66, 67, 73, 74, 75, and 76 use the j designator con- 
figuration . 



(3) OPERAND INTERPRETATION DESIGNATOR. - The k designator (three bits^ appears 
in bit positions 20, 19, and 18 of the U register or an instruction. The k desig- 
nator appears only in bit positions 19 and 18 since bit 20 is a portion of the j 
designator. Instructions 13, 17, 62, 63, 66, 67, and 73 through 76 use the k 
designator configuration since they perform input/output activities and require a 
j designator for channel specification. The k designator controls operand and 
instruction interpretation for the input/output instructions as noted in the 
description of the applicable instruction [see paragraph 3-8M2)] . 

The k designator controls operand interpretation. Those instructions that read 
an operand but do not replace it after the arithmetic is performed are designated 
Read instructions. Those instructions that do not read an operand but store it 
are designated Store instructions. Instructions which both read and store operands 
are classified as Replace instructions. 

The various values of k affect the operand except where noted otherwise under 
individual instruction description as follows: 

Read instructions (01-12, 20-23, 26, 27, 30, 31, 40-43, 50-53, 60-65, 70-72): 



k = 





Yu = 


O's; 


YL = 


Y 


k = 


1 


• Yu = 


O's; 


YL = 


(Y)L 


k = 


2 


Yu = 


O's; 


YL = 


(Y)u 


k = 


3 


Y = 


(Y) 






k = 


4 


Yu = 


same 


bits 


as Y14; YL = Y 



ORIGINAL 



3-17 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20CV) COMPUTER 

3-8b(2) OPERATOR'S SECTION 

k = 5: Yu = same bits as Y14 ; YL = (Y)L 
k 6: Yu = same bits as Y29; YL = (Y)u 
k = 7: Y = (A) 

For instructions 22, 52, and 53, k = 7 is not used. 
Store instructions (14-16, 32, 33, 47): 
k = 0: Store operand in Q.* 

k = 1: Store operand L in YL, leaving (Y)u undisturbed, 
k = 2: Store operand L in Yu , leaving (Y)L undisturbed, 
k = 3: Store operand in Y. 
k = 4: Store operand in A.** 

k = 5: Store complement of operand L in YL, leaving (Y)u undisturbed. 

k = 6: Store the complement of operand L in Yu , leaving (Y)L undisturbed. 

k = 7: Store the complement of operand in Y (storing the complement of Bj 
is the same complement as for a 30-bit register). 

Replace instructions (24, 25, 34-37, 44-46, 54-57): 

k = 0: Not used, 
k = 1 : Read portion 

Store portion 
k = 2: Read portion 

Store portion 
k = 3: Read portion 

Store portion 
k = 4: Not used, 
k = 5: Read portion 

Store portion 
k = 6: Read portion 

Store portion 
k = 7: Not used. 

Repeat instructions require special interpretation when followed by a replace 
instruction. 

(4) INDEX DESIGNATOR. - The b designator appears in bit positions 17, 16, and 
15 of the U register or an instruction; it specifies which of the B-index regis- 
ters, if any, will be used to modify the operand address designator, y t to form 



* A 1400000000 instruction complements (Q) 
**A 1504000000 instruction complements (A) 



- Yu = 0* s; YL = ( Y)L. 

- Stores operand L in YL leaving (Y)u undisturbed. 

- Yu = 0' s; YL = ( Y)u 

- stores operand L in Yu leaving (Y)L undisturbed. 

- Y = (YL 

- Stores operand in Y. 

- Yu = same bits as Y14: YL = (Y)L 

- Stores operand L in YL leaving (Y)u undisturbed. 

- Yu = same bits as Y29; YL = (Y)u 

- Stores operand L in Yu leaving (Y)L undisturbed. 



3-18 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 Paragraph 
OPERATOR'S SECTION 3-8M4) 

Y = y + (Bb). This operation employs an additive accumulator; hence, a quantity 
consisting of all zeros cannot result unless the bits of both the operand desig- 
nator, y f and (Bb) are all zeros. Use of a B-index register to modify y to form 

Y = y + (Bb) causes the higher-order 15 bits of the B register memory address to 
be made zero. 



The effect of the various values of the b designator is as follows: 



b 
b 
b 
b 
b 
b 
b 
b 



Do not modify y. 

Add (Bl) to y. 

Add (B2) to y. 

Add (B3) to y. 

Add (B4) to y. 

Add (B5) to y. 

Add (B6) to y. 

Add (B7) to y. 



(5) OPERAND DESIGNATOR. - The y designator appears in bit positions 14 through 
00 of an instruction. The operand or address of an operand Y is relative to y 
since Y = y + (Bb) . 



c. PROGRAMMING SYMBOLS. - To make it easier to formulate and understand flow 
diagrams, certain symbols are used. The following list of symbols gives the coder 
an example of the basic symbols used in drawing the second type of flow chart 
(see figure 3-6). 

(1) LINES OF FLOW. - A solid line with an arrow touching the next element of 
the flow diagram usually is used to indicate the path to be followed by the com- 
puter, or, more precisely, the path to be followed by the coder who is formulating 
the computer instructions from the flow diagrams. 

(2) OPERATION SYMBOLS. - The rectangular box usually contains a statement about 
a computer or mathematical operation. The content of the box may be a simple state- 
ment or a mathematical expression. 

(3) DECISION SYMBOLS. - An oval is used to indicate a two-way decision. This 
symbol is sometimes written as: 




*Yes 



T 

No 



The function code, 04, designates the use of the Compare instruction to make an 
evaluation in the computer. 

(4) CONNECTORS AND REMOTE CONNECTORS. - To eliminate crossing flow lines on a 
diagram, remote connectors are used to indicate a destination not easily reached 
in the diagram. Thus, the flow can be broken at a convenient point by terminating 
it in an arbitrary symbol which can be used to initiate the flow in another region 
of the diagram. 



ORIGINAL 



3-19 



Figure 
3-6 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20( V) COMPUTER 

OPERATOR'S SECTION 




OPERATION SYMBOL 



("777") 



DECISION SYMBOL 



RRINT * SUBROUTINE SYMBOL 




ENTRANCE OR EXIT SYMBOL 



STOP SYMBOL 



LINES OF FLOW 

< 




REMOTE CONNECTORS 
(Discontinuity symbol) 



JUNCTION SYMBOL 
(Used if there is more than 
one input to a symbol) 



3-20 



Figure 3-6. Programming Symbols 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 

3-9. REPERTORY OF INSTRUCTIONS. - (See table 3-4.) 

The CP-642B/USQ-20(V) computer is specified as a self-modifying, single-address 
computer. Although this means that one reference or address is provided for the 
execution of instruction, this reference can be modified automatically during a 
programmed sequence. The references are modified by using the B registers which 
contain any previously stored constants. In order to modify the address, the 
content of a selected B register is added to the operand address designator, y. 
A programmed address is coded using octal notation with each octal digit denoting 
three binary digits. The instructions are read sequentially from memory storage 
except after satisfied jump or skip instructions. Every instruction executed by 
the computer is transmitted from memory to the Z register and then to the U 
register. While the instruction is in the U register, its components are trans- 
lated to determine the exact method of executing the instruction. The instruc- 
tions and explanations of their common usage are listed below. Instruction 
execution times are tabulated in table 3-4, 

01 - Right Shift . _ Shifts (Q) to the right Y bit-positions.* The higher-order 
bits are replaced with the original sign bit as the word is shifted. Only the 
lower-order six bits of Y are recognized for this instruction. The higher-order 
24 bits are ignored. 



Example of two executions of right shift in Q : _Y = 1 



Content of Q 


Content of Q 


(Q). (positive) = 0101 
First shift 0010 
Second shift 0001 


(Q). (negative) = 1010 
First shift 1101 
Second shift 1110 



02 - Right Shift A . - Shift (A) to the right Y bit positions.* The higher- 
order bits are replaced with the original sign bit as the word is shifted. Only 
the lower-order six bits of Y are recognized for this instruction. The higher- 
order 24 bits are ignored. The over-all operation is analogous to the example 
given in instruction 01. 



03 - Right Shift AO . - Shift (A) and (Q) as one 60-bit register. The shift is 
to the right Y bit positions* with the lower bits of A shifting into the higher bit 
positions of Q. The higher-order bits of A are replaced with the original sign bit 
as the word is shifted. Only the lower-order six bits of _Y are recognized for this 
instruction. The higher-order 24 bits are ignored. 



Example of two executions of right shift in AQ: 1=1 



Content of AQ 


Content of AQ 


(AQ) j (positive) = 01010011 
First shift 00101001 
Second shift 00010100 


(AQ)i (negative) = 10001010 
First shift 11000101 
Second shift 11100010 



Paragraph 
3-9 



* The maximum shift count shall be 63 decimal (D) places. 
ORIGINAL 



3-21 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

3 ~ 9 OPERATOR'S SECTION 

04 - Compare - Compare the signed value of _Y with the signed value of (A) and 
(Q) or the value of either. It does not alter either (A) and (Q) . The branch 
condition designator, j, is interpreted for this instruction as listed below: 

j = 0: Do not skip the next instruction, 

j = 1: Skip the next instruction. 

j = 2: Skip the next instruction if _Y is less than or equal to (Q). 

j = 3: Skip the next instruction if _Y is greater than (Q). 

j = 4: Skip the next instruction if (Q) is greater than, or equal to Y ( and 
_Y is greater than (A). 

j = 5: Skip the next instruction if Y is greater than (Q), or if Jf is less 
than, or equal to (A). 

j = 6: Skip the next instruction if Y is less than, or equal to (A). 

j = 7: Skip the next instruction if _Y is greater than (A), 

05 - Left Shift . - Shift (Q) circularly to the left Y bit positions.* The 
lower-order bits are replaced with the higher-order bits as the word is shifted. 
Only the lower-order six bits of X a re recognized for this instruction; the 
higher-order 24 bits are ignored. 



Example of two executions of left circular shift in Q: Y = 1 



Content of Q 


Content of Q 


(Q). (positive) = 0011 
First shift 0110 
Second shift 1100 


(Q). (negative) = 1100 
First shift 1001 
Second shift 0011 



06 - Left Shift A . - Shift (A) circularly to the left Y bit positions.* The 
lower-order bits are replaced with the higher-order bits as the word is shifted. 
Only the lower-order six bits of Y are recognized for this instruction; the higher- 
order 24 bits are ignored. The over-all operation is analogous to the example 
given in instruction 05. 

07 - Left Shift AQ. - Shift (A) and (Q) as one 60-bit register. The shift is 
circular to the left Y bit positions.* The lower bits of A are replaced with the 
higher bits of Q and the lower bits of Q are replaced with the higher bits of A. 
Only the lower-order six bits of Y are recognized by this instruction; the higher- 
order 24 bits are ignored. 



Example of left shift in AQ: Y = 1 



Content of AQ 


Content of AQ 


(AQ). (positive) = 01010011 
First shift 10100110 
Second shift 01001 101 


(AQ). (negative) - 10001011 
First shift 00010111 
Second shift 00101110 



* The maximum shift count shall be 63 decimal (D) places. 

3-22 ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER 
OPERATOR'S SECTION 



NAVSHIPS 0967-280-4010 



Table 
3-4 



OCTAL 
CODE 



00 
01 
02 
03 



TABLE 3-4. INSTRUCTION REPERTORY AND INSTRUCTION EXECUTION TIME 



INSTRUCTION 



(Fault interrupt) 
RIGHT SHIFT Q 
RIGHT SHIFT A 
RIGHT SHIFT AQ 



EXECU- 
TION* 



8-12 
8-12 
8-12 



ABORT* 



4 
4 
4 



REPEAT* 



4-8 
4-8 
4-8 



SPECIAL CONSIDERATIONS 



0-3, 8-11, 16-19, or 

24-27 place shifts- 

8 [j,sec 
4-7, 12-15, 20-23, 

28-63 place shifts- 

12 jisec 



04 
05 
06 
07 



COMPARE 
LEFT SHIFT Q 
LEFT SHIFT A 
LEFT SHIFT AQ 



8-12 
8-12 
8-12 



4 
4 
4 
4 



4 
4-8 
4-8 
4-8 



0-3, 8-11, 16-19, or 

24-27 place shifts- 

8 (j,sec 
4-7, 12-15, 20-23, 

28-63 place shifts- 

12 jisec 



10 
11 
12 
13 



ENTER 
ENTER A 
ENTER Bj 
EXTERNAL FUNC- 
TION on Cj 



8 
8 
8 
8 



4 
4 



4 
4 
4 



13 k = 3-max of 36 jisec 
13 1c = 0,1,2 - 8 ^isec 



14 
15 
16 
17 



STORE 
STORE A 
STORE B? 
STORE Cj 
EFB 



or TEST 



8 
8 
8 

8-12 



4 

4 



4 
4 
4 



17 1c 
17 * 
17 \ 



2- max of 36 (j,sec 
0, 1-8 jisec 

3- 12 jxsec 



20 
21 
22 
23 



ADD A 
SUBTRACT A 
MULTIPLY 
DIVIDE 



8 
8 

32-52 
52 



4 
4 
4 
4 



4 
4 

32-52 
32 



k = 7 Square Root Execu- 
tion time = 52 ^sec 



24 
25 
26 
27 
30 



31 
32 
33 
34 
35 



REPLACE A + 
REPLACE A - 
ADD 
SUBTRACT Q 
ENTER Y + Q 



12 
12 
8 
8 
8 





4 
4 
4 



8 
8 
4 
4 
4 



ENTER Y - 
STORE A + 
STORE A - 
REPLACE Y + 
REPLACE Y - Q 



8 
12 
12 
12 
12 



4 







4 
8 
8 
8 
8 



* Time in microseconds 



ORIGINAL 



3-23 



Table NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

3-4 OPERATOR'S SECTION 



TABLE 3-4. INSTRUCTION REPERTORY AND INSTRUCTION EXECUTION TIME (CONT.) 



OCTAL 




EXECU- 








CODE 


INSTRUCTION 


TION* 


ABORT* 


REPEAT* 


SPECIAL CONSIDERATIONS 


36 


REPLACE Y + 1 


12 





8 




37 


REPLACE Y - 1 


12 





8 




40 


ENTER LOGICAL PRODUCT 


8 


4 


4 




41 


ADD LOCIGAL PRODUCT 


8 


4 


4 




AO 


SflRTRAfT T OftTCAr PRODUCT 


ft 


4 


4 




43 


COMPARE MASK 


8 


4 


4 




44 


REPLACE LOGICAL PRODUCT 


12 





8 




45 


REPLACE A + LOGICAL PRODUCT 


12 





8 




46 


REPLACE A - LOGICAL rKULHJLl 


id. 


U 


Q 

o 




47 


STORE LOGICAL PRODUCT 


8 


4 


4 




50 


SELECTIVE SET 


8 


4 


4 




51 


SELECTIVE COMPLEMENT 


8 


A 

4 


4 




52 


SELECTIVE CLEAR 


8 


A 

4 


4 




53 


SELECTIVE SUBSTITUTE 


8 


4 


4 




o4 


nrnr Art? CCT UfTTtfTT CCT 


1 9 
Id 


u 


ft 




55 


REPLACE SELECTIVE COMPLEMENT 


12 





8 




56 


REPLACE SELECTIVE CLEAR 


12 





8 




57 


REPLACE SELECTIVE SUBSTITUTE 


12 





8 




60 


JUMP (Arithmetic) 


8 


- 


- 


If jump condition is 


61 


JUMP (Manual) 


8 


- 


- 


not satisfied, exe- 












cution time is 4 ^sec 


62 


JUMP ON Cj ACTIVE INPUT 


8 


— 


— 






RUFFFR 












JUMP ON ct ACTIVE OUTPUT 


8 










BUFFER 

UUI 1 Mil 








If rptnvn inmn p.nn- 


64 


RETURN JUMP CAr i thmet ic ) 


12 


o 





dition is not satis— 


65 


RETURN JUMP (Manual) 


12 






fied. execution time 












is 4 [xsec 


66 


TERMINATE Cj INPUT BUFFER OR 


4 


— 


_ 






ENABLE, DISABLE INTERRUPTS 










67 


TERMINATE Cj OUTPUT BUFFER, 


4 


— 


- 






ALL BUFFERS, OR TERMINATE 












Cj EXTERNAL FUNCTION BUFFER 










70 


REPEAT 


8 


— 


— 




71 


B SKIP ON Bj 


8 





- 




72 


B JUMP ON Bj 


8 


— 


- 




f o 


TNPT1T RT1FFFR ON f!^ 


8 


_ 


_ 






(without monitor mode) 










74 


OUTPUT BUFFER ON Cj 


8 


- 


- 






without monitor mode) 










75 


INPUT BUFFER ON Cj 


8 










(with MONITOR mode) 










76 


OUTPUT BUFFER ON Cj 


8 










(with MONITOR mode) 










77 


(Fault interrupt) 











3-24 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 

10 - Enter . - Enter Y in Q. 

11 - Enter A . - Enter Y in A. 

12 - Enter B j . - Enter Y, in B register specified by j. The branch condition 
designator, j, is used to specify the selected B register for this instruction and 
is not available for its normal function. 

13 - External function on Cj . - Establish a one word external function buffer 
via the output buffer channel j from storage address Y. The buffered word address 
is maintained in the lower order 15 bits of storage address 00140 plus j . 

This instruction is implemented as follows: For all % values, store Y in the 
upper- and lower-order half of storage location 00140 plus j . The \ values modify 
the instructions as follows: 

k = 0: Establish a one word external function buffer with monitor and proceed 
to the next instruction. A monitor interrupt follows the comoletion of 
the buffering ooeration. Subsequent to this instruction the individual 
transfer shall be accomplished when requested by the external device. 

k = 1: Establish a one word external function buffer with monitor and with 

force. The force considerations for 1c = 3 apply. A monitor interruot 
follows the completion of the buffering operation. 

k = 2: Initiate a one word external function buffer and proceed to the next 
instruction. Subsequent to this instruction the transfer shall be 
accomplished when requested by the external device. 

k - 3: Establish a one word external function buffer with force (with force 

the instruction ignores the external function request from the external 
device). The program will hold until the external function word is 
transmitted. If the external devices cannot accept external functions 
executed consecutively, restrictions must be made in the programming 
of external function instructions to this equipment. 

14 - Store Q. - Store (Q) at storage address Y as directed by the operand 
interpretation designator, k. If k = 0, complement (Q) . If k = 4, store in A. 

15 - Store A. - Store (A) at storage address Y as directed by the operand 
interpretation designator, k. If k = 4, complement (A). If k = 0, store in Q. 

16 - Store Bj . - Store a 30-bit quantity whose lower order 15 bits correspond 
to the content of B register soecified by j and whose higher order 15 bits are 
zero at storage address Y as directed by the ooerand interpretation designator, k. 
The branch condition designator, j is used to specify the selected B register for 
this instruction and is not available for its normal function. 

17 - Store Cj or Test EFB . - Performs a storage or jump function as specified 
below: 

k = 1 or 0: Clear the program-address register P ( and enter a new address in 
P for certain external-function buffer conditions on the channel 
designated by j . If the buffer is active, the jump condition is 



Paragraph 
3-9 



ORIGINAL 



3-25 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20( V) COMPUTER 

3-9 OPERATOR'S SECTION 

satisfied; then if k = 1, Y L; or if k = 0, _Y becomes the address of 
the next instruction. If the buffer is inactive, the jump condition 
is not satisfied. The next sequential instruction in the current 
sequence shall be executed in the normal manner. 

k = 2: Store the contents of the C channel specified by j at storage address Y a 
An input data acknowledge with force signal is then sent on the C chan- 
nel. The program will hold until the word is read. 

k = 3: Store the contents of storage address 00520 plus j at storage address Y. 
The external-interrupt-request line is reset on channel Cj . 

20 - Add A. - Add _Y to the previous content of A. 



21 - Subtract A . - Subtract Y from the previous content of A. 

22 - Multiply . - Multiply (Q) times Y t leaving a double-length product in AQ. 
If the factors are considered as integers, the product is an integer in AQ. 

The branch condition designator, j t is interpreted prior to end correction 
permitting sensing of a product with (A)f =0. If j = 4, a skip of the next 
instruction is made when (A)f = 0. (A)f ^ + 0, a double-length product has been 
formed with significant bit(s) in the A register. However, if a skip does occur 
for j = 4, the multiply instruction can be re-executed with the same operand and 
with j = 2 or 3 to determine if Q29 contains a significant bit (a one) of the 
product. 



In this instruction, k = 7 is not used. 



23 - Divide . - Perform a divide or square root operation as specified by the k 
designator. If k ^ 7, divide (AQ) by Y leaving the quotient in the Q register and 
the remainder in the A register. The remainder bears the same sign as the dividend. 
If k = 7, take the square root of (Q) leaving the root in the Q register and the 
remainder in the A register. The remainder a = n-(QxQ). 



NOTE 



If a divide overflow condition exists, no maintenance console indication is 
given. However, by coding each divide instruction with j = 3, a program 
test for the divide overflow is automatic. With this selection of j t a 
skip of the next instruction occurs if a divide overflow exists. The skip 
should be made to a jump instruction which provides a remedial means of 
noting the error or of correcting it. Therefore, the instruction which 
follows the divide instruction should have its j = 1 in order to preclude 
the jump instruction whenever the divide sequence culminates in a correct 
answer. 



A divide overflow can be detected also if the divide instruction is executed 
with j = 2. In this case, a correct answer is indicated when a skip occurs. 

24 - Replace A + Y . - Add Y to (A) and store the results in Y and A. 

25 - Replace A - Y . - Subtract Y from (A) and store the results in Y and A. 
In this instruction k = and k = 7 are not used. 



3-26 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 Paragraph 
OPERATORS SECTION 3 "9 

26 - Add . - Add Y to (Q) and store the results in Q, The branch condition 
designator, j, has special meaning in this instruction as specified in instruction 
27. 

27 - Subtract Q. - Subtracts Y from (Q) and stores the results in Q. 

In instructions 26 and 27 t the branch condition designator, j, has the following 
meaning : 



j = 


0: 


Do not skip the next instruction. 






j = 


1: 


Skip 


the 


next 


instruction 










j = 


2: 


Skip 


the 


next 


instruction 


if 


(A) 


is 


positive. 


j = 


3: 


Skip 


the 


next 


instruction 


if 


(A) 


is 


negative. 


j = 


4: 


Skip 


the 


next 


instruction 


if 


(0) 


is 


zero. 


j = 


5: 


Skip 


the 


next 


instruction 


if 


(Q) 


is 


nonzero. 


j = 


6' 


Skip 


the 


next 


instruction 


if 


(0) 


is 


positive. 


j = 


7- 


Skip 


the 


next 


instruction 


if 


(0) 


is 


negative. 


30 - 


- Enter Y 


+ 9 


. - Add (Q) to Y 


and 


enter 


the results 



31 - Enter Y - . - Subtract (Q) from Y and enter the results in A. 

32 - Store A + . - Add (Q) to (A) and store the results at A and Y as directed 
by the operand interpretation designator, k. 

33 - Store A - . - Subtract (Q) from (A) and store the results in A and Y as 
directed by the operand interpretation designator, k. 

34 - Replace Y + . - Add (Q) to Y and store the results in Y and A. In this 
instruction k = and k = 7 are not used. 

35 - Replace Y - . - Subtract (Q) from _Y and store the results in Y and A. 
In this instruction k = and k = 7 are not used. 

36 - Replace Y + 1 . - Add 1 to Y and store the results in Y and A. In this 
instruction k = and k = 7 are not used. 

37 - Replace Y - 1 . - Subtract 1 from Y and store the results in Y and A. In 
this instruction k=0 and k=7 are not used. 

40 - Enter Logical Product . - Enter the bit-by-bit logical product of Y and (Q) 
in A. 

In this instruction, the j designator is interpreted in a special way for the 
values j = 2 or 3. If j = 2, skip if the parity of (A)f is even. If j = 3, 
skip if the parity of (A)f is odd. 

NOTE 

Even parity - an even number of "ones" in the A register. Odd parity - an 
odd number of "ones" in the A register. 

41 - Add Logical Product . - Add to (A) the bit-by-bit product of Y and (Q). 



ORIGINAL 



3-27 



Paragraph 
3-9 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

OPERATOR'S SECTION 



42 - Subtract Logical Product . - Subtract from (A) the bit-by-bit product of Y 
and (Q). 

43 - Compare Mask , - Subtract from (A) the bit-by-bit product of Y and (Q), and 
perform the branch point evaluation for skip of next sequential instruction as 
directed by the branch condition designator, j. 

This instruction results in no net change in the content of any operational 
register. It provides, through the branch condition designator, j, a comparison 
of a portion of Y with (A). 

44 - Replace Logical Product . - Enter in A the bit-by-bit product of Y_ and (Q). 
Then store (A) at storage address Y. 

In this instruction, the j designator is interpreted in a special way for the 
values j = 2 or 3. If j = 2, skip if the parity of (A)f is even. If j = 3, skip 
if the parity of (A)f is odd. In this instruction k = and k = 7 are not used. 

45 - Replace A + Logical Product . - Add to (A) the bit-by-bit product of Y and 
(Q) and enter the sum at storage address Y. In this instruction k = and k = 7 
are not used. 

46 - Replace A - Logical Product . - Subtract from (A) the bit-by-bit product of 
Y and (Q) and enter the difference at storage address Y. In this instruction 

k =0 and k = 7 are not used. 

47 - Store Logical Product . - Store in address Y the bit-by-bit product of (A) 
and (Q) as directed by the operand interpretation designator, k„ 

50 - Selective Set . - Set the individual bits of A to "ones" corresponding to 
"ones" in Y leaving the remaining bits of A unaltered. 

51 - Selective Complement . - Complement the individual bits of A corresponding 
to "ones" in Y leaving the remaining bits of A unaltered. If k = 4, this instruc- 
tion shall enter A T in A when Y is 77777. 

52 - Selective Clear . - Clear the individual bits of A corresponding to "ones" 
in Y leaving the remaining bits of A unaltered. In this instruction k = 7 is not 
used. 

53 - Selective Substitute . - Substitute the individual bits of A with bits of Y 
corresponding to "ones" in leaving the remaining bits of A unaltered. In this 
instruction k = 7 is not used. 

54 - Replace Selective Set . - Set the individual bits of A to "one" corresponding 
to "ones" in Y leaving the remaining bits of A unaltered and then store (A) at a 
storage address Y. In this instruction k = and k = 7 are not used. 

55 - Replace Selective Complement . - Complement the individual bits of A 
corresponding to "ones" in Y leaving the remaining bits of A unaltered and then 
store (A) at storage address Y. In this instruction k = and k = 7 are not used. 

56 - Replace Selective Clear . - Clear the individual bits of A corresponding to 
"ones" in _Y leaving the remaining bits of A unaltered and then store (A) at storage 
address Y. In this instruction k = and k = 7 are not used. 



3-28 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Paragraph 
3-9 



57 - Replace Selective Substitute . - Substitute the individual bits of A with 
bits of I corresponding to "ones" in Q leaving the remaining bits of A unaltered 
and then store (A) at storage address Y. In this instruction k = and k = 7 are 
not used. 



60 - Jump (Arithmetic) . - Clear the program address register, P f and enter a new 
program address in P for certain conditions of either the A or Q register content. 
The branch condition designator, j, is interpreted in a special way for this in- 
struction and thus determines the conditions under which a jump in program address 
occurs. If the jump condition is not satisfied, the next sequential instruction 
in the current sequence is executed in a normal manner. If the jump condition is 
satisfied, as listed below, then Y becomes the address of the next instruction 
and the beginning of a new program sequence. 



J 



J = 



= 0: 



= 1: 



No jump. Set interrupt enable to remove interrupt lockout, thus 
clearing bootstrap and interrupt modes. Continue with current program 
sequence . 

Execute jump. Set interrupt enable to remove interrupt lockout, thus 
clearing bootstrap and interrupt modes. 

Execute jump if (Q) is positive. 

Execute jump if (Q) is negative. 

Execute jump if (A) is zero. 

Execute jump if (A) is nonzero. 

Execute jump if (A) is positive. 

Execute jump if (A) is negative. 



61 - Jump (Manual) . - Clear the program address register, P t and enter a new 
program address in P for certain conditions of manual JUMP key selections. The 
branch condition designator, j, is interpreted in a special way for this instruc- 
tion and thus determines the conditions under which a jump in program address 
occurs. If the jump condition is not satisfied, the next sequential instruction 
of the current sequence is executed in a normal manner. If the jump condition is 
satisfied, as listed below, then Y becomes the address of the next instruction 
and the beginning of a new program sequence. 

Program execution may be stopped by certain STOP selections on execution of 
this instruction. The branch condition designator, j, specifies which key 
selections are effective. 



J ~ 



Execute jump regardless of key selections. 
Execute jump if JUMP 1 is selected. 
Execute jump if JUMP 2 is selected. 
Execute jump if JUMP 3 is selected. 
Execute jump. Stop computation. 

Execute jump. Stop computation if STOP 5 is selected. 
Execute jump. Stop computation if STOP 6 is selected. 
Execute jump. Stop computation if STOP 7 is selected. 



ORIGINAL 



3-29 



Paragraph 
3-9 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20CV) COMPUTER 
OPERATOR'S SECTION 



62 - Jump On Cn Active Input Buffer . - Clear the program address register, P, 
and enter a new program address in P for certain input buffer conditions on the 
channel designated by j. If the buffer is active, the jump condition is satisfied; 
then Y becomes the address of the next instruction. If the buffer is inactive, the 
jump condition is not satisfied. The next sequential instruction in the current 
sequence is executed in normal manner. 1c = 0, 1, 2, or 3 permitted. 

63 - Jump on ct Active Output Buffer . - Clear the program address register, P, 
and enter a new address in P for certain output buffer conditions on the channel 
designated by j. If the buffer is active, the jump condition is satisfied; then 
Y becomes the address of the next instruction. If the buffer is inactive, the 
jump condition is not satisfied. The next sequential instruction in the current 
sequence is executed in the normal manner, k = 0, 1, 2, or 3 permitted, 

64 - Return Jump (Arithmetic) . - Execute a return-jump sequence for certain 
conditions of either the A or Q register content. The branch condition designator, 
j, is interpreted in a special way for this instruction and determines the con- 
ditions under which the return jump sequence is executed. If the return jump 
condition is not satisfied, then the next sequential instruction in the current 
sequence is executed in a normal manner. If the return jump condition is satis- 
fied, as listed below, then the following sequence is performed: 

Store (P) + 1 in the lower half of memory address Y. Then jump to Y + 1. 



j 




0: 


No action. Continue 


with 


the 


current p 


j 




1: 


Execute 


return jump. 










j 




2: 


Execute 


return jump 


if 


(0) 


is 


positive. 


j 




3: 


Execute 


return jump 


if 


(0) 


is 


negative. 


j 




4: 


Execute 


return jump 


if 


(A) 


is 


zero. 


j 




5: 


Execute 


return jump 


if 


(A) 


is 


nonzero . 


j 




6: 


Execute 


return jump 


if 


(A) 


is 


positive. 


j 




7: 


Execute 


return jump 


if 


(A) 


is 


negative. 



65 - Return Jump (Manual) . - Execute a return jump sequence for certain conditions 
of manual key selections. The branch condition designator, j, is interpreted in 
a special way for this instruction and determines the conditions under which the 
return jump sequence is executed. If the return jump condition is not satisfied, 
the next sequential instruction in the current sequence is executed in a normal 
manner. If the return jump condition is satisfied, as listed below, then the 
following sequence is performed. 

Store (P) + 1 in the lower half of memory address Y. Then jump to Y + 1. 

j = 0: Execute return jump regardless of key selections. 

j = 1: Execute return jump if JUMP 1 is selected. 

j = 2: Execute return jump if JUMP 2 is selected. 

j = 3: Execute return jump if JUMP 3 is selected. 

j = 4: Execute return jump. Then stop computation. 

j = 5: Execute return jump. Stop computation if STOP 5 is selected. 



3-30 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER NAVSHIPS O967-280-4OIO Paraqraoh 
OPERATOR'S SECTION 3-9 

j = 6: Execute return jump. Stop computation if STOP 6 is selected, 
j = 7: Execute return jump. Stop computation if STOP 7 is selected. 

66 - Terminate Cj Input Buffer or Enable, Disable Interrupts . - This instruction 
is variable, depending upon the 1c designator and b designator selections. 

1c = 0: Terminate the input buffer on channel j 
Enable all interrupts 
Disable all interrupts 
Enable all external interrupts 

Disable all external interrupts (The external interrupt request 
is removed from all channels) 



1c = l & b = 

ft = 1 & b 4 

ft = 2 & b = 

ft = 2 & b 4 



ft - 3 & b - 0: Enable external interrupt on channel j 

ft = 3 & b ^ 0: Disable external interrupt on channel j (The external interrupt 
request signal is removed from the channel specified by J) 

The operand address designator, y, bits are not translated for this instruction. 

The enable, disable interrupts, f = 66, ft = 1, b = o, b f o, do not affect the 
state of the external interrupt lock out flip-flops. Therefore, if all interrupts 
are disabled and subsequently enabled, the status of the external interrupt lock 
out flip-flODS shall be identical to the status before the lock out all interrupts 
instruction was executed. Only the instructions pertaining to the external 
interrupts shall have any effect on the state of the external interrupt lock out 
flip-flops, that is f = 66, ft = 2 or 3. 

67 - Terminate C.f Output Buffer or all Buffers . - This instruction is variable, 
depending upon the ft designator and J designator selections. 

k = 0: Terminate the output buffer on channel 

k = 1: Terminate the external function buffer on channel If the channel 

specified by j is involved with the use of an output register of an inter- 
computer group, a resume signal is simulated and sent to the register. 

k - 2: Terminate all buffers, if an output register is being used for inter- 
computer communications, a resume signal is simulated and sent to this 
register. 

For all values of ft no output buffer monitor interrupt shall occur. The index 
designator, b, and the operand address designator, y, bits are not translated for 
this instruction. 



70 - Repeat. - Initiate the repeat mode or if YL is zero, skip the next in- 
struction. The repeat mode executes the instruction immediately following the 
repeat instruction YL times. B7 contains the number of executions remaining 
throughout the repeat mode. 

If no skip condition is met for the repeated instruction, the repeat mode 
terminates and the instruction following the repeated instruction is executed. 
If the skip condition for the repeated instruction is met, the repeat mode 



ORIGINAL 



3-31 



Paragraph 
3-9 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20CV) COMPUTER 

OPERATOR'S SECTION 



terminates and the instruction following the repeated instruction is skipped. 
Following the repeat mode termination, the count remains in B7. 

In no way does the repeat mode alter a repeated instruction as stored in memory. 

The three low order bits of the r designator (from j of instruction 70) affects 
the operand indexing as follows: 

r = 0: Do not modify the operand address of the repeated instruction after each 
individual execution. 

r = 1: Increase the operand address of the repeated instruction by one after 
each execution of the repeated instruction. 

r = 2: Decrease the operand address of the repeated instruction by one after 
each execution of the repeated instruction. 

r = 3: Repeat the initial B register modification of the repeated instruction 
before each execution. 

r = 4: Do not modify the operand address of the repeated instruction after each 
individual execution. If the repeated instruction is a replace in- 
struction the operand address is incremented by (B6) for the store portion 
of the replace instruction. 

r = 5: Increase the operand address of the repeated instruction by one after 

each execution of the repeated instruction. If the repeated instruction 
is a replace instruction the operand address is incremented by (B6) for 
the store portion of the replace instruction. 

r = 6: Decrease the operand address of the repeated instruction by one after 

each execution of the repeated instruction. If the repeated instruction 
is a replace instruction the operand address is incremented by (B6) for 
the store portion of the replace instruction. 

r = 7: Repeat the initial B register modification of the repeated instruction 
before each execution. If the repeated instruction is a replace 
instruction the operand address is incremented by (B6) for the store 
portion of the replace instruction. 

NOTE 

Instruction 70 j designator establishes the repeat mode r designator since j 
is transmitted to r. 

71 - B Skip On Bi . - Selectively skip the next instruction depending upon a 
comparison of B register j and YL. If the content of B register j is equal to VL, 
skip the next instruction in the current sequence and proceed to the following 
instruction. Clear B register j. 

If the content of B register j is not equal to YL, proceed to the next instruc- 
tion in the sequence in a normal manner. Increase the content of B register j by 
one. 

The branch condition designator, j, is used to designate the selected B register 
in this instruction and is not available for its normal function. Only the lower 
order 15 bits of Y are used in these comparisons. 



3-32 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 Paragraph 
OPERATOR'S SECTION 3-9 

72 - B Jump on Bj . - Selectively execute a program jump to address Y depending 
upon the value of B register j. If the content of B register j is nonzero, execute 
a jump in program address to address Y. Reduce the content of B register j by one. 

If the content of the B register j is zero, proceed to the next instruction in 
a normal manner. Do not alter the content of B register j. 

The branch condition designator, j, is used to designate the selected B register 
in this instruction and is not available for its normal function. 

73 - Input Buffer o n Cj (without monitor mode). - Establish an input buffer via 
input buffer channel j f to storage with an initial storage address Y. Subsequent 
to this instruction individual transfers wil 1 be executed at a rate determined by 
an external device. The storage address initially established by this instruction 
will be advanced by one preceding each individual transfer. The next current 
address will be maintained throughout the buffer process in the lower order 15 bits 
of control register 00100 plus j. This mode will continue until it is superseded 
by a subsequent initiation or termination of an input buffer via the same input 
channel or until the higher order half and the lower order half of control register 
00100 plus j contain equal quantities, whichever occurs first. 

Store Y in the lower order half of storage location 00100 plus j 
leaving the higher order half undisturbed. 

Store the lower order 15 bits of Y in the lower order half of storage 
location 00100 + j leaving the higher order half undisturbed. 

Not permitted. 

Store Y in storage location 00100 + j. 



k = 


0: 


k - 


1: 


k = 


2: 


k = 


3: 


74 - 


- 



til k ? 2, output data buffer; if k = 2 external function buffer) via output buffer 
channel j from initial storage address Y. Subsequent to this instruction the 
individual transfers will be executed at a rate determined by an external device 
The storage address initially established by this instruction will be advanced 
by one preceding each individual transfer. The next current address will be main- 

o hF ^ 9 on Ut the buffe A P rocess in the lower order 15 bits of control register, 
if * * 2, 00120 plus j; if % = 2, 00140 plus J. This mode will continue until it 
is superseded by a subsequent initiation or termination of an output buffer via 
the same output channel or until the higher order half and the lower order half of 
control register (if k 4 2, 00120 plus J; if \ = 2 t 00140 plus f) contain equal 
quantities, whichever occurs first. 

k = 0: Store Y in the lower order half of storage location 00120 + j 
leaving the higher order half undisturbed. 



k = l: 



Store the lower order 15 bits of Y in the lower order half of storage 
location 00120 + j leaving the higher order half undisturbed. 



k - 2: Store Y in storage location 00140 + j. 
k = 3: Store Y in storage location 00120 + j\ 

, 75 Buffer on , c t (with monitor mode) . - Establish an input buffer, via 

mputbuffer channel j, to storage with an initial storage address Y. Subsequent 
to this instruction, the individual transfers will be executed at a rate determined 
by an external device. The storage address initially established by this 



ORIGINAL 



3-33 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

3-9 OPERATOR'S SECTION 

instruction will be advanced by one, preceding each individual transfer. The next 
current address will be maintained throughout the buffer process in the lower order 
15 bits of control register 00100 plus j. This mode will continue until it is 
superseded by a subsequent initiation or termination of an input buffer via the 
same input channel or until the higher order half and the lower order half of the 
control register contain equal quantities, whichever occurs first. The initiation 
of this input buffer selects the input channel j and establishes a buffer monitor 
on input channel j. A monitor interrupt to address 00040 + j shall follow com- 
pletion of the buffering operation. 



\ = 


0: 


Store Y in the lower order half of storage location 00100 + j. 


% = 


1: 


Store the lower order 15 bits of Y in the lower order half of storage 
location 00100 + j leaving the higher order half undisturbed. 


\ = 


2: 


Not permitted. 


n = 


3: 


Store Y in storage location 00100 + j . 



76 - Output Buffer on C\ (with monitor mode) . - Establish an output buffer (if 
1c 4 2 t output data buffer; if \ = 2, external function buffer) via output buffer 
channel j from initial storage address Y. Subsequent to this instruction the 
individual transfers will be executed at a rate determined by an external device. 
The storage address initially established by this instruction will be advanced 
by one preceding each individual transfer. The next current address will be 
maintained throughout the buffer process in the lower order 15 bits of control 
register, if i 4 2, 00120 plus J; if 1c = 2, 00140 plus j. This mode will con- 
tinue until it is superseded by a subsequent initiation or termination of an 
output buffer via the same output channel or until the higher order half and the 
lower order half of the control register contain equal quantities, whichever 
occurs first. The initiation of this output buf fer^selects the output channel j 
and establishes a buffer monitor on output channel j. A monitor interrupt (if 
£ 4 2 to address 00060 + j ; if 1c = 2 to address 00500 + J) follows the completion 
of the buffering operation. 



t = 


0: 


Store Y in the lower order half of storage location 00120 + j 
the higher order half undisturbed. 


leaving 


4 = 


1: 


Store the lower order 15 bits of Y in the lower order half of 
location 00120 + j leaving the higher order half undisturbed. 


storage 


4 = 


2: 


Store Y in storage location 00140 + j. 




\ = 


3; 


Store Y in storage location 00120 + §> 





3-10. BOOTSTRAP PROGRAMS 
a. DESCRIPTION. 

(1) GENERAL. - The bootstrap program is a sequence of 32 computer instructions 
fabricated as a permanent part of the computer memory. These instructions can be 
executed by the computer but cannot be altered by it in any way. The purpose of 
the bootstrap is to provide automatic loading of other programs into the computer. 
Programs to be loaded may originate from three different sources: 

Magnetic Tape 

Another CP-642B/USQ-20(V) Computer 
Paper Tape 



3-34 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 

A separate and different bootstrap program is required for each of these 
sources. 

The bootstrap programs, being limited to 32 instructions, require that the 
programs to be loaded follow a definite format. In addition, there are a number 
of restrictions pertaining to the use of certain memory addresses in the computer. 
Programs to be loaded by the bootstraps should not in general occupy memory addresses 
between 00000 and 00617. These memory addresses are normally permanently assigned 
for such special purposes as buffer control, B-register storage, bootstrap program 
storage, and interrupt entrance and status word storage. 

(2) PHYSICAL. - Each computer contains two bootstrap programs. These are 
located in the Non Destructive Read-Out (NDRO) memory and are assigned addresses 
00540 through 00577. Although both bootstrap programs are assigned these same 
32 addresses, only one bootstrap can be used at a time. The particular bootstrap 
program from the NDRO memory is determined by the position of manually operated 
switches on the computer. These switches are the PROGRAM I and PROGRAM II push 
button indicator switches located on the computer control console, and the program 
selector switch located on logic module J35A on chassis A5. 

Program I is the magnetic tape bootstrap and is selected by depressing the 
PROGRAM I indicator switch or by placing the program selector toggle switch in the 
down position. Program II is either the inter-computer bootstrap or the paper tape 
bootstrap* (See paragraph 3-10c(2) & (3).) Program II is selected by depressing the 
PROGRAM II indicator switch or by placing the program selector toggle switch in the 
up position. 

b. BOOTSTRAP OPERATION. - Bootstrap operation normally occurs in one of two ways. 
The first and most common is inititated when initially loading the computer. The 
second method is the automatic recovery operation initiated when the computer exper- 
iences a fault condition(fault condition is when the computer tries to execute an 
instruction having an 00 or 77 function code) during the execution of a program. 

jc. BOOTSTRAP PROGRAMS AND OPERATING PROCEDURES 

(1) MAGNETIC TAPE BOOTSTRAP , 

(a.) PROGRAM. - This bootstrap program will load in the computer memory the 
first record (properly formatted)from transport 1 of an RD-243 magnetic tape unit. 
It will checksum the record loaded to ensure correct transmission and then jump to 
the new program. Summarizing, the magnetic tape bootstrap issues the following 
commands : 

Disable all external interrupts and terminate all buffers. Take con- 
trol of magnetic tape. Store a Release-Interrupt -Lockout (RIL) instruc- 
tion in all external interrupt addresses. Store a jump to the magnetic 
tape interrupt routine in the external interrupt address applicable to 
the RD-243 magnetic tape unit, Set the return address in Bl . Send a 
rewind command to transport 1 of the RD-243 magnetic tape unit. Enable 
the external interrupt applicable to the RD-243 magnetic tape unit. Upon 
receipt cf the external interrupt from the RD-243 magnetic tape unit in- 
dicating that transport 1 is rewinding, initiate an input buffer and send 
a read command to transport 1 of the RD-243 magnetic tape unit. Set the 
return address in Bl. Upon receipt of the external interrupt from the 
RD-243 magnetic tape unit indicating that the first record on tape 



Paragraph 
3-i0a(l) 



ORIGINAL 



3-35 



Paragraph NAVSHIPS 0967-280-4010 CP-642B/USQ-20CV) COMPUTER 

3-lOc(l)(a) OPERATOR'S SECTION 

transport 1 has been read, the record loaded is checked against the checksum 
to ascertain correct transmission. If a checksum error is found, the boot- 
strap is re-executed. If the checksum is correct, jump to the program 
entrance address. Each external interrupt from the RD-243 magnetic tape 
unit is checked. If the interrupt indicates an error has occurred, the 
bootstrap is re-executed. 

(b) OPERATING PROCEDURES , - The magnetic tape to be read into memory must be 
manually positioned on transport number 1 of the magnetic tape unit. 

MANUAL INITIATION 

The computer must be operating in the stop condition. 

Step 1. - Depress the PROGRAM I push button indicator switch. 

Step 2. - Depress the LOAD MODE push button indicator switch. 

Step 3. - Operate the START-STEP/ RESTART switch to the START-STEP position. 

The computer will immediately begin reading the magnetic tape and, upon completion, 
will jump to the program just loaded. 

AUTOMATIC INITIATION 

Step 1. - Place the AUTOMATIC RECOVERY toggle switch in the up position. 

Step 2. - Place the program selector switch, located on logic module J35A on 
chassis A5, to the down position. 

If the computer attempts to execute a 00 or 77 function code the bootstrap opera- 
tion will be initiated. 

The proper format for the RD-243 magnetic tape unit is shown in figure 3-7. The 
program is listed in figure 3-8 and flow-charted in figure 3-9. The program as listed 
is for use on channel 11 (octal). It may be used on any channel by changing the 
operators TAPE and CHAN appropriately. The bootstrap requires the following memory 
locations which are outside the loaded programs: 

ADDRESS PURPOSE 

00020-00037 Interrupt Preset 

00107 Storage for program entrance address 

and first address 
00110 Storage for checksum 

(2) INTER-COMPUTER BOOTSTRAP 

(a) PROGRAM. - This bootstrap program will load a program into memory from 
one of three other computers via an inter-computer channel. It will checksum the 
proqram to ensure correct transmission and, upon completion, it will jump to the 
program entrance address. The use of the inter-computer bootstrap program pre- 
supposes that the other computer contains a program capable of communicating with 
the bootstrap program. Summarizing, the inter-computer bootstrap issues the 
following commands: 

ORIGINAL 

3-36 



CP-642B/ISQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Figure 
3-7 



TAPE 



Entrance Address = a+ j 


First Address = a 


Checksum ( Note 1 ) 


Final Address= a+ n 


First Address = a 


PROGRAM 


i 


i 




t 

PROGRAM 



Note 1: Checksum is (00107) + (a-H) 



Read into 

00107 

00110 

00111 
a 



a + j 



a +n 



1=0 



Figure 3-7. Magnetic Tape Bootstrap Program Record Format 



ORIGINAL 



3-37 



Figure 
3-8 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20CV) COMPUTER 
OPERATOR'S SECTION 



ADDRESS 



00540 

00541 
00542 
00543 
00544 
00545 
00546 
00547 



00550 
00551 
00552 
00553 
00554 
00555 
00556 
00557 

00560 
00561 
00562 
00563 
00564 
00565 
00566 
00567 

00570 

00571 
00572 
00573 
00574 
00575 
00576 
00577 



INSTRUCTION 
WORD 



66027 00013 



67020 
13570 
10000 
70100 
14020 
10030 
14030 



10100 
00540 
60000 
00020 
00020 
00574 
0003$ 



12100 
13f70 
66?70 
60100 
73470 
13470 
12100 
61000 

12110 
11030 
21030 
21031 
71120 
61000 
60500 
61020 

11760 

52400 
61000 
60101 
61000 
00000 
00000 
00000 



00554 
00541 
14420 
00553 
00560 
00552 
00560 
00557 



OOi 
001 1& 
OOK&T 
00000 

oo id. 

00563 
00572 
OOWf 

0053? 

00777 
00540 
00000 
00570 
00000 
00000 
00000 



CODE 



NOTE : TAPE 
CHAN 



SIL-EX«ALL 
TERM • ALL 

EX-FCT *TAPE • W( 540) 

ENT-Q -60000 

RPT-20*ADV 

STR-Q-U(20) 

ENT*Q-W(574) 

STR«Q.W(204€HAN) 



ENT»B1'554 

EX-FCT -TAPE -W( 541) 

RIL-EX-TAPE 

RILJP.553 

IN-TAPE-W(560) 

EX-FClSTAPE.W(552) 

ENT'B1'560 

JP-557 

ENT*Bl.L(lOO+CHAN-2) 

ENT*A-W(100+CHAN-1) 

SUB-A*W(l00+CHAN-2) 

SUB*A«W(B1) 

BSK'B1-U(100+CHAN) 

JP.563 

JP.572.AN0T 

JP-UQOO+CHAN-2) 

ENT • A • UX ( 520+CHAN )• ANEG 

SEL.CI < .777.AZER0 

JP-540 

RILJP-B1 

JP°570 

0-0 

0*0 

0-0 



FUNCTION 



LOCKOUT EXTERNAL INTERRUPTS, 

CONSTANT 
TERMINATES ALL BUFFERS , CONSTANT 
TAKE CONTROL OF TAPE UNIT 
STORE RIL INSTRUCTION IN 

ALL EXTERNAL INTERRUPT 

ENTRANCE ADDRESSES 

SET UP TAPE EXTERNAL INTERRUPT 
ADDRESS 

SET UP INTERRUPT RETURN ADDRESS 

SEND REWIND COMMAND 

ENABLE TAPE INTERRUPT .CONSTANT 

WAIT FOR INTERRUPT 

INITIATE 'INPUT BUFFER 

SEND READ COMMAND 

SET UP INTERRUPT RETURN ADDRESS 

WAIT FOR INTERRUPT 

FIRST ADDRESS TO Bl 
CHECKSUM TO A 

SUBTRACT ENTRANCE ADDRESS WORD 
SUBTRACT PROGRAM WORD 
IS CHECK SUMMING COMPLETED 
NO, CONTINUE 

YES, JUMP IF CHECKSUM ERROR 
JUMP TO PROGRAM ENTRANCE ADDRESS 

STATUS TO A AND -TEST FOR 

IMPROPER 
TEST STATUS FOR READ ERROR 
ERROR, START OVER 
STATUS GOOD, RETURN TO Bl 
TAPE INTERRUPT INSTRUCTION 
SPARE 
SPARE 
SPARE 



MEANS-C11 
EQUALS* 11 



$0 



o 



/ o t 



Figure 3-8. Magnetic Tape Bootstrap Program 



3-38 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Figure 
3-9 



CP-642B/USQ-20CV) 
Mag Tape 
Bootstrap 




Lockout all 
Interrupts and 
Terminate all 
Buffers 



Preset all 
Interrupt 
Entrance 
Arklres ses 



Preset !U and 
Send Rewind 
Command 



Enable 
Interrupt 
From Tape 




Interrupt Received 



NO 




Initiate 
Buffer and 
Send Read 
Command 



Preset Bl 




Interrupt Received 



( 





YES 


Compute Checksum 






r- 






YES 



NO 



To Program Entrance 



ay Type Interrupt 




iad Condition 



C X (520 + CHAN) ^ 



c 



.) <} 



MO 



To Bl Address 



3 



YES 



Figure 3-9. Magnetic Tape Bootstrap Program Flow Chart 



ORIGINAL 



3-39 



Paragraph 
3-l0c(2)(a) 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20CV) COMPUTER 
OPERATOR'S SECTION 



Disable all interrupts and terminate all buffers. Store a Release-Interrupt - 
Lockout (RID instruction in all interrupt addresses. Send an external function 
on the three inter-computer channels requesting any computer that is on-line to 
reply. Monitor the interrupt word storage address to ascertain if any computer 
replied. Terminate all buffers and clear upper fifteen bits of B7. Send an ex- 
ternal function on the three inter-computer channels requesting program transfer 
from the computer that replied first. Initiate an input buffer on the three inter- 
computer channels. When the input buffer terminates for the computer from which 
program transfer was requested, the loading is complete. Terminate all buffers. 
The program loaded is checked against the checksum to ascertain correct trans- 
mission. If a checksum error is found, the bootstrap is re-executed. If the 
checksum is correct, jump to the program entrance address. 

(b) OPERATING PROCEDURES. 

MANUAL INITIATION 

The computer must be operating in the stop condition. 

Step 1. - Depress the PROGRAM II push button indicator switch,, 

Step 2. - Depress the LOAD MODE push button indicator switch. 

Step 3. - Operate the START-STEP/ RESTART switch to the START-STEP position. 

The bootstrap computer will request and accept a program from another computer 
and jump to that program. 

AUTOMATIC INITIATION 

Step 1. - Place the AUTOMATIC RECOVERY toggle switch in the up position. 

Step 2. - Place the program selector switch, located on logic module J35A on 
chassis A5, in the up position. 

If the computer attempts to execute a 00 or 77 function code the bootstrap opera- 
tion will be initiated. 

The inter-computer request-reply logic is summarized in table 3-5. The format of 
the inter-computer program record is shown in figure 3-10. The real-time clock must 
be enabled in the bootstrap computer. The program as listed is for use on channels 
O t 1, and 2, but it may be used on any three consecutive inter-computer channels 
provided the operators BC, ICO, IC1 and IC2 are changed appropriately. The boot- 
strap requires the following memory locations which are outside the loaded program; 



The inter-computer bootstrap program is listed in figure 3-11 and flow-charted in 
figure 3-12. 

(3) PAPER TAPE BOOTSTRAP. 

(a) PROGRAM - This bootstrap will load into memory a program from a manually 
positioned paper tape of the proper format and, upon completion, jump to that program 

3-40 ORIGINAL 



ADDRESS 



PURPOSE 



00020-00617 



Interrupt Preset 



CP-642B/ISQ-2CHV) COMPUTER NAVSHIPS 0967-280-4010 

OPERATOR'S SECTION Paragraph 

3-10c(3)(a) 

with a STOP 7 option. The paper tape bootstrap is installed in the computer as 
Program II (instead of the inter-computer bootstrap). The paper tape bootstrap is 
only for diagnostic testing during the installation and checkout of a new data pro- 
cessing system. When the installation is complete and the system is operating 
properly this bootstrap is removed and the inter-computer bootstrap is installed in 
its place. The paper tape bootstrap issues the following commands: 

Disable all interrupts and terminate all buffers. Enable the paper tape reader. 
Store a Release-Interrupt -Lockout (RIL) instruction in all external and internal 
monitor interrupt addresses. Look for the beginning of information on the paper 
tape. Read the first and last address from the paper tape. Read each program 
data word from the paper tape and store it in memory as defined by the first and 
last address. When all program data words and the two checksums have been loaded 
into memory, the loading is complete. Display the first and last address in the 
Q register and jump to the first address. Stop of STOP 7 toggle switch is in the 
up position. 

(b) OPERATING PROCEDURES. - The paper tape to be read into memory must be 
manually positioned on the paper tape reader. 

MANUAL INITIATION 

The computer must be operating in the stop condition. 

Step 1. - Depress the PROGRAM II push button indicator switch. 

Step 2 t - Depress the LOAD MODE push button indicator switch. 

Step 3 t - Operate the START -STEP/RE START switch to the START-STEP position. 

The computer will immediately begin reading the paper tape. If the STOP 7 toggle 
switch is in the down position the computer will jump to the input program upon 
completion of the loading operation. If the STOP 7 switch is in the up position 
the computer will stop when the program is loaded. Operating the STABT-STEP/RESTART 
switch to the START-STEP position will cause the computer to jump to the input 
program. 

AUTOMATIC INITIATION 

StepJL. - Place the AUTOMATIC RECOVERY toggle switch in the up position. 

Ste P 2 t " Place the program selector switch, located on logic module J35A on 
chassis A5 ( in the up position. 

If the computer attempts to execute a 00 or 77 function code the bootstrap opera- 
tion will be initiated. As above, the position of the STOP 7 switch will determine 
whether the computer stops or transfers to the input program upon completion of the 
loading operation. 

The proper format for the paper tape is the normal bioctal format consisting of 
leader, bioctal tape identifier (76), first address, last address, contents of all 
address (from first to last address), checksum of all upper half words, checksum of 
all lower half words and trailer (see figure 3-13). Note that the bioctal tape 
identifier must be the first non-zero frame on the tape or the tape must be so 
positioned. The last address should not exceed 77775 because two locations beyond 

ORIGINAL 3 _ 41 



Table NAVSHIPS 0967-280-4010 CP-642B/USQ-20(V) COMPUTER 

3-5 OPERATOR'S SECTION 



TABLE 3-5. INTER-COMPUTER REQUEST-REPLY LOGIC 



WORD FORMAT 


SENT BY 


RECEIVED BY 


MEANING 




Duotsi/rdp ounipu tci 


A1 1 f.fimnut pits 


Please reDlv if vou 
are there 


00000. XXXXX 


All Computers cap- 
able of replying 


Bootstrap 
Computer 


I am here 


00000.00000 


Bootstrap Computer 


All computers 


Will the computer 
connected to the 
Bootstrap computers 
Channel please send 
program. 


or 

00000.00001 


Bootstrap Computer 


All computers 


Will the computer 
connected to the 
Bootstrap computers 
Channel 1 please send 
program. 


or 

00000.00002 


Bootstrap Computer 


All computers 


Will the computer 
connected to the 
Bootstrap computers 
Channel 2 please send 
program. 



3-42 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER 
OPERATOR'S SECTION 



NAVSHIPS 0967-280-4010 



Figure 
3-10 



INCOMING 



Entrance AddressE a + j 


First AddressE a 


Checksum (Note 1) 


Final Address = a + n 


First Address E a 


PROGRAM 







Read into 
ChO Chi Ch2 

00076 00077 00100 

00077 00100 00101 
00100 00101 00102 

at a a 



a+j a + j a +j 



t 

PROGRAM 



a+n a+n a+n 



n (00076) if Ch 

El or 

(a + i) + { (00077) if Ch 1 
l=o I or 

I (00100) if Ch2 

2- Entrance Address is the Program Start Address 

Figure 3-10. Inter-Computer Bootstrap Program Record Format 



ORIGINAL 



3-43 



Figure 
3-11 



NAVSHIPS 0967-280-4010 



CP-64 2B/USQ-20 ( V) COMPUTER 
OPER ATOR'S SECTION 



ADDRESS 



00540 
00541 
00542 
00543 
00544 
00545 
00546 
00547 

00550 
00551 
00552 
00553 
00554 

00555 

00556 
00557 

00560 
00561 
00562 
00563 
00564 

00565 

00566 
00567 



INSTRUCTION 
WORD 



66017 
67020 
10000 
70100 
14020 
66010 
13020 
13060 



00076 
00077 
60000 
00600 
00020 
00100 
00545 
00545 



13120 00545 
70200 00003 
11427 00517 
61000 00546 
67020 00000 

16020 00167 

13020 00167 
13060 00167 

13120 00167 
73030 00540 
73070 00541 
73130 00545 
11027 00100 

21717 00100 

61000 00564 
67020 00000 



CODE 



00570 


12617 00076 


00571 


11037 00077 


00572 


21037 00076 


00573 


21036 00000 


00574 


71627 00100 


00575 


61000 00573 


00576 


60500 00540 


00577 


61027 00076 



SIL'ALL 

TERM • ALL 

ENT-Q-60000 

RPT'600-ADV 

STR-Q4K20) 

RIL-ALL 

EX-C0M«IC0.W(545) 
EX-C0M-IC1.W(545) 

EX-C0M-IC2.W(545) 
RPT*3*BACK 

ENT-A*U(BC+517+B7) .AZERO 

JP-546 

TERM • ALL 

CL-U(167) 

EX-C0M-IC0-WC167) 
EX-C0M-IC1-WU67) 

EX-C0M-IC2.WC167) 

IN*IC0*W(540) 

IN*IC1-W(541) 

IN*IC2.W(545) 

ENT*A«U(100+B7) 

SUB'A-L(100+B7) -ANEG 

JP-564 
TERM -ALL 



ENT*B6»L(100+B7-2) 

ENT*A*W(100+B7-1) 

SUB-A-W(l00+B7-2) 

SUB-A-W(B6) 

BSK-B6.UU0O+-B7) 

JP-573 

JP*540.AN0T 

JP-U(100+B7-2) 



FUNCTION 



LOCKOUT ALL INTERRUPTS , CONSTANT 
TERMINATE ALL BUFFERS t CONSTANT 
STORE RIL INSTRUCTION 

IN ALL ADDRESSES 

FROM 00020 to 00617 
ENABLE ALL INTERRUPTS f CONSTANT 
INTERROGATE 

THE THREE SUCCESSIVE 

INTERCOMPUTER CHANNELS 
DID ANY 

COMPUTER REPLY 
NO t RE-INTERROGATE 
YES ,(B7) INDICATES REPLYING 

COMPUTER 
CLEAR UPPER HALF OF B7 STORAGE 

ADDRESS 
SEND PROGRAM REQUEST t (B7) f 

ON THE THREE SUCCESSIVE 

INTERCOMPUTER CHANNELS 
INITIATE INPUT BUFFER 

ON THE THREE SUCCESSIVE 

INTERCOMPUTER CHANNELS 
IS INPUT BUFFER ON REQUESTED 

CHANNEL 

TERMINATED (LOWER GREATER 
THAN UPPER) 
NO .CONTINUE TERMINATION CHECK 
YES .TERMINATE OTHER TWO INPUT 

BUFFERS 

FIRST ADDRESS TO B6 
CHECKSUM TO A 

SUBTRACT ENTRANCE ADDRESS WORD 
SUBTRACT PROGRAM WORD 
IS CHECK SUMMING COMPLETED 
NO, CONTINUE 

YES, JUMP IF CHECKSUM ERROR 
JUMP TO PROGRAM ENTRANCE 
ADDRESS 



NOTE: 



BC 
ICO 
IC1 
IC2 



EQUALS -0 
MEANS* CO 
MEANS -CI 
MEANS *C2 



Figure 3-11. Inter-Computer Bootstrap Program 



3-44 



ORIGINAL 



CP-642B/ISQ-20CV) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Figure 
3-12 




Lockout all 
Interrupts and 
Terminate all 
Buffers 



Preset all 
Interrupt 
Entrance 
Addresses 



Enable all 
Interrupts 



Interrogate 
Base and 2 
Successive 
IC Channels 






Terminate 
all 
Buffers 



Send Program 
Request (B7) 
on all 3 
Channels 



Initiate 
Buffers on all 
3 Channels 



Buffer Completed 



NO 



LU00+B7) 
U( 100+67) 



YES 



Terminate 
all 
Buffers 



Compute Checksum 



Checksum Correct 



NO 




C 



YES 



To Program Entrance 







Figure 3-12. Inter-Computer Bootstrap Program Flow Chart 



ORIGINAL 



3-45 



Paragraph 
3-lOc(3)(b) 



NAVSHIPS 0967-280-4010 



CP-642B/USQ-20 ( V) COMPUTER 
OPERATOR'S SECTION 



the last address will be used for storage of the checksums. The program loaded 
should ascertain proper loading by checking the checksum. The address limits to be 
checked are in the Q register when the program is entered; the first address in _ 
Q lower and the last in Q upper. The checksum words are stored in the two location 
beyond the last address as explained above. The program as listed is for Channel 4 
but the program can be used on any channel if the instructions which contain the 
operators PT and PTCHAN are changed appropriately. 

The paper tape bootstrap program is flow-charted in figure 3-14 and listed in 
figure 3-15, This bootstrap requires the following memory locations which are 
outside the loaded program. 



ADDRESS 



PURPOSE 



00104 
00124 

Last address +1 
Last address +2 



Input buffer control word and input store 
Storage for first and last address 
Storage for checksum of all upper half words 
Storage for checksum of all lower half words 



3-46 



ORIGINAL 



CP-642B/ISQ-20(V) COMPUTER NAVSHIPS 0967-280-4010 
OPERATOR'S SECTION 



Figure 
3-13 



BEGINNING 



TAPE 
MOTION 




LEADER 



BIOCTAL TAPE IDENTIFIER 
" FIRST ADDRESS (23574) 



> LAST ADDRESS (31677) 



ABSOLUTE INSTRUCTIONS 
FIVE FRAMES PER INSTRUCTION 



> CHECK SUM OF UPPER HALF WORDS 



j 



CHECK SUM OF LOWER HALF WORDS 



> TRAILER 



END 



Figure 3-13. Example of Bioctal Paper Tape 



ORIGINAL 



3-47 



Figure 
3-14 



NAVSHIPS 0967-280-4010 CP-642B/USQ-20CV) COMPUTER 

OPERATOR 1 S SECTION 



/ CP-642B/USQ-20(V) A 
Paper Tape Bootstrap I 



/ cp-e 

I Pap* 



Lockout all 
Interrupts and 
Terminate all 
Buffers 



Enable 

PT 
Reader 



Preset all 
Interrupt 
Entrance 
Addresses 





Read 
Five 
Frames 



567 



Store First 
and Last 
Addresses and 
Enter B3 with 
Last Address 



Increment B3 

by 2 
For Checksum 
Storage 



< 




Read Five Frames 



567 










Store 
Word 









Read-in Completed 



B4=B3 





YES 


First and Last 
Address to Q 
Register 







c 



Read Five Frames 



Clear A 
4 to B5 




Read 

one 

Frame 






Assemble 
in 

A Register 







NO 



5 Frames 
Read 



B5=0 



) c 



YES 



Exit to Bl 



3 



(To First Addr. ^ 
Stop Key 7 J 



Figure 3-14. Paper Tape Bootstrap Program Flow Chart 



3-48 



ORIGINAL 



CP-642B/ISQ~20(V) COMPUTER 
OPERATOR'S SECTION 



NAVSHIPS 0967-280-4010 



Figure 
3-15 



ADDRESS 



00540 
00541 
00542 
00543 
00544 
00545 
00546 
00547 

00550 
00551 
00552 
00553 
00554 
00555 
00556 

00557 

00560 
00561 
00562 
00563 
00564 
00565 
00566 

00567 

00570 
00571 
00572 
00573 
00574 
00575 
00576 
00577 



INSTRUCTION 
WORD 



66011 
67020 
13230 
10000 
70100 
14020 
73230 
62200 

11010 
60400 
12100 
61000 
15030 
12310 
1?303 



00040 
00000 
00540 
60000 
00060 
00020 
00577 
00547 

00104 
00546 
00554 
00567 
00124 
00124 
00002 



12420 00124 



12100 
61000 
15034 
71403 
61000 
10030 
61720 



00562 
00567 
00000 
00000 
00560 
00124 
00124 



12500 00004 



11000 
73230 
62200 
06000 
50010 
72500 
61001 
00104 



00000 
00577 
00572 
00006 
00104 
00571 
00000 
00104 



CODE 



SIL'ALL 

TERM • ALL 

EX-FCT-PT-W(540) 

ENT* 0*60000 

RPT • 60 . ADV 

STR-Q.U(20) 

IN-PT.W<577) 

JP • 547 • PT • ACTI VEIN 

ENT*A*L(100+PTCHAN) 
JP-546-AZER0 
ENT.BL554 
JP-567 

STR-A-W(120+PTCHAN> 

ENT-B3-LU20+PTCHAN) 

ENT.B3-2+B3 

ENT -B4 .U ( 120+PTCHAN) 

ENT.Bl-562 

JP'567 
STR.A-W(B4) 
BSK*B4*B3 
JP-560 

ENT-Q-WQ20+PTCHAN) 
JP-UC 120+PTCHAN) -STOP 7 

ENT-B5.4 
CL*A 

IN«PT.W(577) 

JP • 572 • PT • ACTI VEIN 

LSH'A*6 

SEL *SET°L( 100+PTCHAN ) 

BJP-B5.571 

JP.B1 

U-TAG* 100+PTCHAN • 100+ 

PTCHAN 



FUNCTION 



LOCKOUT ALL INTERRUPTS, CONSTANT 
TERMINATE ALL BUFFERS 
ENABLE READER 
STORE RIL INSTRUCTION 

IN ALL ADDRESSES 

FROM 00020 TO 00077 
INITIATE ONE FRAME INPUT BUFFER 
WAIT FOR BUFFER TO COMPLETE 

EXAMINE FRAME 

JUMP IF STILL ON LEADER 

SET UP RETURN ADDRESS 

READ AND ASSEMBLE 5 FRAMES 

SAVE FIRST AND LAST ADDRESS 

LAST ADDRESS TO B3 

LAST ADDRESS + 2 TO B3 

(CHECKSUM STORAGE) 
FIRST ADDRESS TO B4 

SET UP RETURN ADDRESS 
READ AND ASSEMBLE 5 FRAMES 
STORE ASSEMBLED WORD IN MEMORY 
IS READ-IN COMPLETED 
NO, CONTINUE 

YES, FIRST AND LAST ADDRESS TO Q 
JUMP TO FIRST ADDRESS, STOP IF 

KEY 7 SET 
SET UP TO READ 5 FRAMES 

CLEAR ASSEMBLY REGISTER 
INITIATE ONE FRAME INPUT BUFFER 
WAIT FOR BUFFER TO COMPLETE 
MAKE ROOM FOR FRAME RECEIVED 
SET FRAME IN ASSEMBLY REGISTER 
JUMP IF LESS THAN 5 FRAMES READ 
RETURN TO Bl 



NOTE: 



PT 

PTCHAN 



MEANS *C4 
EQUALS • 4 



Figure 3-15. Paper Tape Bootstrap Program 



ORIGINAL 



3-49/3-50 



*