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Report No. klk 



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THE DESIGN OF A DATA COMMUNICATIONS CONTROLLER 

by 
Kent Laurence Ulrich 



October 29, 1970 




THE LIBRARY 'QEIHB 

NOV 9 197? 

UNIVERSITY OF ILUNO'S 
AT URBANA-CHAMPAIGN 



DEPARTMENT OF COMPUTER SCIENCE 
UNIVERSITY OF ILLINOIS AT URBANA-CHAMP, 



Report No. klk 



THE DESIGN OF A DATA COMMUNICATIONS CONTROLLER 

by 

Kent Laurence Ulrich 



October 29, 1970 



Department of Computer Science 
University of Illinois at Urbana- Champaign 
Urbana, Illinois 6l801 



This work was submitted in partial fulfillment of the requirements for 
the degree of Master of Science in Electrical Engineering, October, 1970' 



iii 
ACKNOWLEDGMENT 

The author wishes to express his sincere gratitude 
and appreciation to Professor Don Secrest, Department of 
Chemistry and Chemical Engineering, under whose direct 
supervision the design described in this thesis was developed. 
Professor Secrest's extensive knowledge in the field of digital 
logic design has greatly influenced the author. 

The author also wishes to thank Professor Sylvian Ray, 
Department of Computer Science and Department of Electrical 
Engineering, and Mr. Clifford Carter, Resident Engineer, 
Department of Computer Science, for their helpful suggestions. 



iv 
TABLE OF CONTENTS 

CHAPTER Page 

I INTRODUCTION 1 

II SYSTEM ORGANIZATION 3 

III SCAN 10 

IV RECEIVE BUFFER AND RECEIVE CONTROL 17 

V TRANSMIT CONTROL 2k 

VI TRANSMITTER/RECEIVER 27 

VII CONSPECTUS 49 

REFERENCES 50 



CHAPTER I 
INTRODUCTION 

The Data Communications Controller, described in this 
thesis, is an interface between a digital computer and up to 
thirty-two teletypewriters. The Controller services the tele- 
typewriters in both the receive mode and the transmit mode. In 
the receive mode, characters arrive from the teletypewriters in 
serial form. The functions of the Controller in the receive 
mode are as follows: 

1. to convert the signals from teletypewriter 
current levels to digital voltage levels; 

2. to convert the characters from serial form to 
parallel form; 

3. to forward each character to the computer in the 
form of a fifteen bit word. The first five bits 
consist of a pre-assigned number corresponding to 
the originating teletypewriter; the next eight 
bits consist of the character in an eight bit 
code; the remaining two bits consist of an error 
message which is generated by the Controller. 

In the transmit mode, characters are sent to the 
Controller in parallel form from the computer. The functions of 
the Controller in the transmit mode are as follows: 

1. to convert the characters from parallel form to 
serial form; 



2 

2. to convert the signals from digital voltage 
levels to teletypewriter current levels; 

3. to forward each character to the proper 
teletypewriter. 

Newell has described the design of a similar type of 
interface which services thirty-two input devices in the receive 
mode only. His basic concept, which he refers to as "Search 
Sequencing," has been utilized and is referred to as "Scanning" 
in this thesis. 



CHAPTER II 
SYSTEM ORGANIZATION 

The System Block Diagram for the Controller is shown 
in Figure 1. The Controller is organized around a supervisory 
unit called Scan. Scan contains a five bit counter which 
always contains a number, in binary form, corresponding to one 
of the thirty-two teletypewriters. 

The Controller contains a Transmitter/Receiver (T/R) for 
each teletypewriter to which it is connected; the two lines from 
each teletypewriter are terminated at the corresponding 
Transmitter /Receiver. The Transmitter/Receiver converts data, 
received from the teletypewriter, from teletypewriter current 
levels to digital voltage levels and from serial form to parallel 
form. After receiving data from the teletypewriter, the Trans- 
mitter/Receiver informs Scan that it contains a word which is to 
be sent to the computer; the Transmitter/Receiver then holds the 
word until the word is gated into the Receiver Buffer on command 
from Scan. Similarly, the Transmitter/Receiver converts data, 
to be sent to its corresponding teletypewriter, from digital 
voltage levels to teletypewriter current levels and from 
parallel form to serial form; the Transmitter/Receiver then 
forwards the data to the teletypewriter. 

By use of its five bit counter, Scan queries the Trans- 
mitter/Receivers, one by one, until it finds a Transmitter/Receiver 







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5 

which has a word ready for transmission to the computer. After 
Scan finds a Transmitter/Receiver which has a word ready, Scan 
checks to determine if the Receive Buffer is empty. If the 
Receive Buffer contains a word waiting to be accepted by the 
computer, Scan halts its scanning procedure until the Receive 
Buffer has been emptied by the computer. After the Receive 
Buffer has been emptied (or if it was empty when first checked by 
Scan), Scan gates the number contained in the counter into the 
first five bit-positions of the Receive Buffer and gates the 
ten bit word, consisting of the eight bit character and the two 
bit error message, from the Transmitter/Receiver into the next 
ten bit-positions of the Receive Buffer, forming a fifteen bit word 
ready for transmission to the computer. Scan then resumes its 
scanning procedure. 

After the Receive Buffer has been filled, Receive Control 
informs the computer that the Receive Buffer contains a word 
which is ready for transmission. After the computer has received 
the word, Receive Control notifies Scan that the Receive Buffer 
is empty. 

When the computer has data to be transmitted to one of 
the teletypewriters, it gates the data on to its Output Data 
Channel in the form of a thirteen bit word. The first five bits 
consist of the binary number corresponding to the teletypewriter 
for which the data is intended, and the other eight bits contain 
the transmitted character in an eight bit code. 



In order for a Transmitter/Receiver to send data to its 
corresponding teletypewriter in serial form, a period of 110 
milliseconds is required after a word has been gated into a 
particular Transmitter/Receiver before the next word can be gated 
into the same Transmit ter /Receiver . If the Transmitter/Receiver, 
to which the computer is attempting to send data, is in the process 
of either transmitting data to its teletypewriter or receiving 
data from its teletypewriter, it will reject any new data until 
it is free. If the Transmitter/Receiver in question is not in 
the process of either transmitting data to its teletypewriter or 
receiving data from its teletypewriter, it will accept the data 
and will forward it in serial form to its teletypewriter. 

Whenever data is rejected by one of the Transmitter/ 
Receivers, the Controller sends an interrupt signal to the computer, 
thus informing the computer of the rejection. In order to fully 
utilize the transmit capabilities of the Controller, the computer 
software should be written in such a way, that if data is rejected 
by one of the Transmitter/Receivers and the computer has data 
ready to send to another teletypewriter, the computer will place 
the data, which it was unsuccessful in transmitting, "at the 
botton of the waiting list," and will attempt to send data to the 
next teletypewriter "at the top of the waiting list." 

The Controller contains a crystal clock which it uses in 
order to send pulses to the Transmitter/Receivers on the FAST 
CLOCK line. In each Transmitter/Receiver, the FAST CLOCK 



7 

frequency is divided by sixteen in order to provide SLOW CLOCK 
pulses which are used for gating serial transmissions. The 
FAST CLOCK frequency is determined by the speed at which the 
teletypewriters are operated; if more than one speed is used, 
then an additional clock must be provided for each additional 
speed. 

Some of the flip flops in the Controller are assigned 
specific initial states; these flip flops are connected to a line 
called INITIALIZE. When the Controller is first turned on, a 
monostable multivibrator is triggered, producing a five microsecond 
positive pulse on the INITIALIZE line. This pulse is used in 
order to place these flip flops in their specified initial states. 

Figures 2 and 3 show the symbols which are used in this 
thesis to represent two types of flip flops constructed from 
NOR gates. Figure 2 shows the symbol for a flip flop composed 
of cross-coupled NOR gates; Figure 3 shows the symbol for the 
same flip flop followed by inverters which are used as delay 
elements in order to insure that the flip flop has been 
sufficiently set or reset before decoding or state transition 
gating begins. 

In the logic circuits described in this thesis, the 
actual types of logic packages, which might be used to assemble 
the Controller, have not been specified. Since FAN-IN and FAN-OUT 
requirements vary from one type of logic package to another, 
manufacturer's literature should be consulted in order to determine 



8 




S _ 



Q 
Q 



Q 



FIGURE 2 FLIP FLOP COMPOSED OF CROSS-COUPLED NOR GATES 




— Q 

— Q 



FIGURE 3 FLIP FLOP COMPOSED OF CROSS-COUPLED NOR GATES 
FOLLOWED BY INVERTERS 



9 
the places in the logic circuits where buffer gates must be 
used. 

The indiridual units, which comprise the Controller, 
and the interconnections shown in Figure 1 are discussed in more 
detail in the following sections. 



10 

CHAPTER III 
SCAN 

Scan is realized as a four state sequential circuit. 
The Flow Chart, Logic Diagram and State Diagram for Scan are 
shown in Figures 4, 5 and 6, respectively. In Figure ^f, the 
number in the upper left-hand corners of the blocks corresponds 
to the status of the secondaries, Q and Q 2 , respectively. In 
Figure 6, the state transition functions are shown in parenthesis, 
and transition between two states occurs when the respective state 
transition function is equal to a logical "1." When there is no 
state transition function indicated for a transition between two 
states, the first state is unstable, and the transition occurs 
automatically, regardless of the values of the inputs. 

Flip Flops 3 through 7» which comprise a five bit counter, 
and Flip Flop 1 are JK flip flops; Flip Flop 2 is composed of 
cross-coupled NOR gates followed by inverters as shown in Figure 3» 
The counter is incremented when COUNT, the input to Flip Flop 3» 
changes from "1" to "0." Scan contains two monostable multi- 
vibrators; the inputs to the first and second monostable multi- 
vibrators are labeled SHOT 1 and SHOT 2, respectively. 

Scan is connected to each Transmitter/Receiver by two 
control lines; these control lines are: FLAG, which is controlled 
by the Transmitter/Receiver; and PROCEED, which is controlled by 
Scan. Scan is always connected to the control lines for the 
Transmitter/Receiver, which corresponds to the number contained in 



11 



INITIALIZE 




RESET COUNT 



5 /'sec. 



*7~^ 



#1 



10 



SET COUNT 




#2 



5 >*sec. | — I 



RESET PROCEED 




SET PROCEED 



FIGURE 4 FLOW CHART FOR SCAN 



12 




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1 ., + 


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Q x e COUNT • 
Q 2 * PROCEED m 1 


1 


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5 *sec. #1 


NITIALIZE'Qi ) 

+ 


Ql = 1 COUNT - 1 
Q 2 = PROCEED ■ 1 


(FLAG) 




■ p| 3 ^ sec • r 












(FLAG 'FILLED) 


Ql = 1 COUNT = 1 
Q 2 ■ ^ PROCEED = 




(FILLED) 


5 */ sec. #2 


1 


r 


Ql = COUNT - 1 
Q 2 = 1 PROCEED - 1 











FIGURE 6 STATE DIAGRAM FOR SCAN 



Ik 

the counter, by a decoding technique which is explained in detail 
in the chapter on the Transmitter/Receiver (Chapter VI), Scan is 
connected to Receive Control by a control line, called FILLED, which 
is controlled by Receive Control; PROCEED is also terminated at 
Receive Control. The outputs of the counter, bits A through E , 
and their complements are carried on a ten wire bus which is 
available to the Transmitter/Receivers. The manner in which each 
Transmitter/Receiver is connected to this bus is described in the 
chapter on the Transmitter/Receiver (Chapter VI). 

A normal Scan cycle begins when Scan enters state, Q Q p 
equal 00. When Scan enters this state, COUNT changes from "1" 
to "0, n and the counter is incremented. At the same time, the 
first monostable multivibrator is triggered as SHOT 1 changes 
from "0" to "1." The monostable multivibrator produces a five 
microsecond positive pulse; this pulse provides enough time to 
insure that the counter has been stabilized before there are any 
more state changes. The pulse's trailing edge triggers Flip 
Flop 1, thus placing Scan in state 10 and setting COUNT. 

Scan is now ready to examine FLAG from the Transmitter/ 
Receiver which corresponds to the number contained in the counter. 
If FLAG is "0," then the Transmitter /Receiver in question does not 
contain a word ready for transmission to the computer. If this is 
the case, the second monostable multivibrator is triggered, 
producing a five microsecond pulse, whose trailing edge triggers 
Flip Flop 1; this action returns Scan to state 00, and resets 



15 

COUNT, which increments the counter. Scan then continues its 
scanning procedure until it finds a Transmitter/Receiver for 
which FLAG is "1." 

If upon entering state 10, Scan determines that FLAQ is 
"1," this indicates to Scan that the Transmitter/Receiver, under 
consideration, contains a word which it is ready to transmit to 
the Receive Buffer. If FILLED is "1," this indicates that the 
Receive Buffer already contains a word which it is waiting for the 
computer to accept. In this case, Scan remains in state 10 until 
FILLED is reset. When FILLED is "0," this indicates that the 
Receive Buffer is empty and is ready to accept a word from one of 
the Transmitter/Receivers. 

After FILLED is reset (or if it was "0" when first checked 
by Scan), Scan enters state 11 and PROCEED is reset. After 
PROCEED is reset, the number contained in the counter is gated 
into the first five bit-positions of the Receive Buffer, and the 
ten bit word is gated from the Transmitter/Receiver into the next 
ten bit-positions of the Receive Buffer. 

When the Receive Buffer has received the word, it sets 
FILLED. When FILLED is set, the second monos table multivibrator 
is triggered, producing a five microsecond pulse, whose trailing 
edge triggers Flip Flop 1, thus sending Scan into state 01 and 
setting PROCEED, Scan automatically returns to state 00 from 
state 01. 

Initial conditions are established by the INITIALIZE 
pulse which resets Flip Flop 2 and triggers Flip Flop 1. Thus, 



16 

Scan initially enters either state 00 or state 10 depending on 
whether Q. is "1" or "0," respectively, at the time that the 
INITIALIZE pulse occurred. 



17 
CHAPTER IV 
RECEIVE BUFFER AND RECEIVE CONTROL 

The Receive Buffer, which is shown in Figure 7, is a 
buffer register composed of fifteen flip flops (cross-coupled 
NOR gates). Initially all fifteen flip flops are reset by the 
INITIALIZE pulse; after each transmission of the contents of 
the Receive Buffer to the computer, the flip flops are reset 
by a signal, called CLEAR, which is generated by Receive Control. 

The output gates for bits A through E of the counter 
are connected to the set leads of Flip Flops 1 through 5» and 
the output gates for bits F through of the Transmitter/ 
Receivers are connected in parallel (i.e., OR) to the set leads 
of Flip Flops 6 through 15, respectively. (The physical nature 
of this parallel connection is explained in the chapter on the 
Transmitter /Receiver, Chapter VI.) After Scan resets PROCEED, 
bits A to E are gated from the counter into Flip Flops 1 
through 5, respectively, and bits F through axe 
gated from the Transmitter/Receiver, corresponding to the 
number contained in the counter, into Flip Flops 6 through 15, 
respectively. 

Receive Control is realized as a four state sequential 
circuit. The Flow Chart, Logic Diagram and State Diagram for 
Receive Control are shown in Figures 8, 9 and 10, respectively. 
Flip Flop 1 is composed of cross-coupled NOR gates followed by 
inverters, and Flip Flop 2 is a JK Flip Flop; Receive Control 



18 






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19 



INITIALIZE 



00 



L-JL 



RESET CLEAR 
RESET FILLED 




YES 
| 700 /usee. I 



SET FILLED 

SET REQUEST 




RESET REQUEST 




SET CLEAR 



FIGURE 8 FLOW CHART FOR RECEIVE CONTROL 



20 




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w 

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M 

w 
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OS 

03 
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a 

o 

M 

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21 



INITIALIZE 






Ql ■ CLEAR ■ 




PILLED « 




Q 2 « REQUEST ■ 












( PROCEED ) 




3f 




700 a/ sec. 




A 






Q t = CLEAR = 




FILLED = 1 




Q 2 = 1 REQUEST = 1 






(SERVICE) 








Q t = 1 CLEAR = 




FILLED = 1 




Q 2 = 1 REQUEST = 












( SERVICE* PROC] 


2ED) 


1 


r 




5 *sec. 

1 






Q x = 1 CLEAR = 1 




FILLED = 1 




Q 2 = REQUEST = 











FIGURE 10 STATE DIAGRAM FOR RECEIVE CONTROL 



22 
also contains two monos table multivibrators. 

Receive Control is connected to the computer by two 
control lines; these control lines are: REQUEST, which is 
controlled by Receive Control; and SERVICE, which is controlled 
by the computer. 

When the Receive Buffer is empty and is ready to accept 
a word from one of the Transmitter/Receivers, Receive Control 
is in state, Q Q_ equal 00. Initially Receive Control is placed 
into this state by the INITIALIZE pulse. 

When Receive Control is in state 00, FILLED is M 0"; this 
indicates to Scan that the Receive Buffer is empty. Scan resets 
PROCEED in order to load the Receive Buffer. When PROCEED is 
reset, the 700 microsecond multivibrator is triggered, producing 
a 700 microsecond pulse. The five bits from the counter are 
loaded immediately after PROCEED is reset; however, the eight 
bits from the Transmitter/Receiver are not gated into the 
Receive Buffer until the first FAST CLOCK pulse occurs, following 
the changing of PROCEED from "1" to "0." (This is discussed in 
the chapter on the Transmitter/Receiver, Chapter VI.) Since the 
FAST CLOCK period is approximately 560 microseconds, this 700 
microsecond pulse provides more than enough time to insure that 
the Receive Buffer has been loaded before Receive Control 
changes states. 

The trailing edge of this pulse triggers Flip Flop 2, 
thus placing Receive Control in state 01 and setting FILLED and 



23 

REQUEST. FILLED indicates to Scan that the Receive Buffer 
contains a word, and REQUEST indicates the same fact to the 
computer. 

When the computer is ready to receive the word, it gates 
the word into its Input Data Channel by placing a positive pulse 
of approximately five microseconds duration on the SERVICE line. 
The leading edge of this SERVICE pulse sets Flip Flop 1, thus 
placing Receive Control into state 11 and resetting REQUEST. 
After SERVICE returns to "0" and PROCEED has been set, the five 
microsecond monostable multivibrator is triggered, producing a 
five microsecond pulse. This pulse's trailing edge triggers 
Flip Flop 2, thus placing Receive Control into state 10 and 
setting CLEAR, which resets all the flip flops in the Receive 
Buffer. Receive Control automatically returns to state 00, 
thus resetting CLEAR and FILLED; the resetting of FILLED indicates 
to Scan that the Receive Buffer is empty and is again ready to 
accept a word. 



2k 
CHAPTER V 
TRANSMIT CONTROL 

The first five bite of the thirteen bit Output Data 
Channel of the computer are labeled as bits A through E., 
respectively, and comprise the five bit binary number corresponding 
to the teletypewriter to which the computer is attempting to send 
data. Bits A. through E. and their complements are carried on a 
ten wire bus available to the Transmitter/Receivers. The remaining 
eight bits of the Output Data Channel are labeled as bits F 
through M , respectively, and comprise the eight bit character 
which is being transmitted. Bits F through M are connected to the 
corresponding input gates in each of the Transmitter/Receivers. 

Transmit Control is realized as a two state sequential 
circuit composed of one JK flip flop and a monostable multi- 
vibrator. The Logic Diagram and the State Diagram for Transmit 
Control are shown in Figures 11 and 12, respectively. Transmit 
Control is connected to each Transmitter /Receiver by a control 
line called DEMAND which is controlled by Transmit Control. In 
addition, there is a line, called REJECT, by which the Transmitter/ 
Receiver, which corresponds to the binary number contained in 
bits A through E , can send an interrupt signal to the computer. 
(The decoding technique by which the correct Transmitter/Receiver 
is connected to the computer is discussed in the chapter on the 
Transmitter/Receiver, Chapter VI.) There is a control line, 
called RESPONSE, from the computer to Transmit Control; RESPONSE 



25 



e 



RESPONSE 1 


T 










i 


if 5 //sec. 








DEMAND 



FIGURE 11 LOGIC DIAGRAM FOR TRANSMIT CONTROL 



Q « 1 


DEMAND ■ 


1 




A 


k 


(RESPONSE) 


5 /j sec. 


l-*0 






Q = 


DEMAND - 






FIGURE 12 STATE DIAGRAM FOR TRANSMIT CONTROL 



26 

is controlled by the computer. 

When the Controller is ready to attempt to relay data 
from the computer to one of the teletypewriters, Transmit Control 
is in state, Q equals "1," with DEMAND equal to "1." When the 
computer is ready to attempt to send data to one of the teletype- 
writers, it sends a positive pulse, of approximately five micro- 
seconds duration, on the RESPONSE line and simultaneously gates 
the thirteen bit word on to its Output Data Channel. The RESPONSE 
pulse's trailing edge triggers the flip flop, thus resetting 
DEMAND and triggering the monostable multivibrator. This produces 
a five microsecond negative pulse on the DEMAND line to the 
Transmitter/Receivers. If the Transmitter/Receiver in question 
is not in the process of either transmitting a word to its tele- 
typewriter or receiving a word from its teletypewriter, it will 
accept the data and will transmit it in serial form to its 
teletypewriter. If the Transmitter/Receiver in question is in 
the process of either transmitting a word to its teletypewriter 
or receiving a word from its teletypewriter, it will reject the 
data and will send an interrupt signal to the computer on the 
REJECT line. 

The computer is required to keep data on its Output Data 
Channel for a period of approximately ten microseconds. If the 
computer is capable of placing new data on to its Output Data 
Channel at a faster rate than once every ten microseconds, then 
DEMAND must be connected to the computer, and the computer must 
wait until DEMAND returns to "1" before it places new data on its 
Output Data Channel and sends the next RESPONSE pulse. 



27 

CHAPTER VI 
TRANSMITTER/RECEIVER 

The Controller contains one Transmitter /Receiver for 
each teletypewriter connected to it. The Transmitter /Receiver 
consists of two sub-units, called the Interface Sub-unit and 
the Register Sub-unit. In the Receive mode, data is sent from 
a teletypewriter to the Interface Sub-unit of the corresponding 
Transmitter/Receiver. The Interface Sub-unit converts the 
teletypewriter current levels of the incoming data to digital 
voltage levels and forwards the data, in serial form, to the 
Register Sub-unit over the IN line. Similarly, in the transmit 
mode, data is sent from the Register Sub-unit to the Interface 
Sub-unit, in serial form, over the OUT line. The Interface Sub- 
unit converts the digital voltage levels of the outgoing data to 
teletypewriter current levels and 6ends the data to the 
corresponding teletypewriter. 

The Circuit Diagram for the Interface Sub-unit is shown in 
Figure 13. The teletypewriters are connected to the Controller in 
a Half Duplex configuration; when a teletypewriter is connected in 
this configuration and there is no data being sent in either 
direction, OUT is "1," and the teletypewriter contacts are closed. 
Therefore, there is current flowing on the line; transistors Tl, 
T2 and T3 are "on," thus causing IN to be "1." Resistor Rl is a 
500 ohm variable resistor, which can be adjusted in order to set 
the line current at 20 ma. This condition in which there is 



28 




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29 
current on the line and IN is "1" is called a "Mark." 

The condition in which the loop is broken and there is no 
current on the line is called a "Space." The loop ia broken when 
either the teletypewriter contacts are opened or OUT is reset by 
the Transmitter/Receiver. When the loop is broken, transistors 
Tl, T2 and T3 are turned "off," and IN changes to "0." 

In order to prevent interference to the rest of the 
Controller, by noise generated by the switching of 50 volts, 
the components comprising the Interface Sub-unit, except for 
Transistor T3 and the resistor connected to its collector, are 
contained within a ground-shielded case; the wire to the base of 
transistor T3 and the twisted pair of wires to the teletypewriter 
are ground-shielded. 

A ten wire bus connected to the five bit counter in Scan 
is available to each Transmitter/Receiver; this bus carries the 
counter outputs, bits A to E and their complements. The 
Register Sub-unit of each Transmitter /Receiver has a NOR gate 
which is connected to the complements of the corresponding binary 
number as shown in Figure l*f. The output of this NOR gate is 
called GO, and it is "1" only for the particular Transmitter/ 
Receiver corresponding to the number contained at that time 
in the counter of Scan. In each Register Sub-unit, GO is 
connected along with the PROCEED line from Scan to a NOR gate 



whose output is PROCEED if the Transmitter/Receiver corresponds 
to the number contained at that time in the counter; for all 



30 




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W 



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o 

Q 

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ca 

o 



31 
other Transmitter/Receivers, the output of this gate is "0." 
Therefore, when Scan resets PROCEED, in order to gate a word 
from a Transmitter/Receiver into the Receive Buffer, only the 



Transmitter /Receiver under consideration receives the PROCEED 
signal. 

Figure 15 shows that the GO and the FLAG lines of each 
Transmitter/Receiver are connected to a NOR gate (in the 
Register Sub-unit) f the output of which is connected to a 
switching transistor, which is in the common emitter configuration. 
The collectors of the thirty-two transistors are connected in 
parallel to a line which is connected through a limiting resistor 



to a 3*6 volt power supply; this line is the FLAG input to Scan. 
Whenever FLAG for the Transmitter/Receiver, under consideration 
by Scan, is "1," this line is grounded through the corresponding 



transistor (which is "on"), and the FLAG input to Scan is "0." 
At all other times, the voltage on the line is 3*6 volts and the 



FLAG input to Scan is "1." 

There is also a ten wire bus which carries bits A through 
E and their complements from the computer's Output Data Channel. 
In each Transmitter/Receiver, the complements of the corresponding 
binary number are connected to a NOR gate as 6hown in Figure 16 in 
a similar manner as was described for the complements of the 
counter output bits. The output of this NOR gate is called OK and 
is "1" only for the particular Transmitter/Receiver corresponding 
to the number contained at that time in bits A through E . In 



32 



GO (1) 



FLAG (1) 



GO (2) 




FLAG (2) 



29 i 



GO (32) 



FLAG (32) 



2N3903 




2N3903 




2N3903 



6.8K 



FLAG (TO SCAN) 



FIGURE 15 FLAG CONNECTION 



DEMAND 
(FROM TRANSMIT CONTROL) 



At A t *t *t c t c t °t °t Et Et 





REJECT (1 ) 



OK (1) OK (1) 
BUSY (2)- 



CxPi> 



REJECT (2) 



OK (2) OK (2) 



29 i 



BUSY (32) 



REJECT (32) 



OK (32) OK (32) 



FIGURE 16 REJECT CIRCUITS 



33 

each Transmitter/Receiver, OK and the DEMAND line from Transmit 
Control are connected to a NOB gate along with a signal called 



BUST. (The generation of BUSY will be discussed later; if BUST 
is "1," this indicates that the Transmit ter/Receirer is either 
transmitting data to its teletypewriter or receiving data from 
its teletypewriter.) The output of this NOR gate is REJECT. 
Therefore, when the computer is attempting to transmit data to 
one of the teletypewriters and Transmit Control produces a 



DEMAND pulse, if the corresponding Transmitter/Receiver is 
presently either transmitting data to its teletypewriter or 
receiving data from its teletypewriter, the Transmitter/Receiver 
will reject the data and will produce a five microsecond REJECT 
pulse. If the Transmitter/Receiver in question is not either 
transmitting data to its teletypewriter or receiving data from its 



teletypewriter, then REJECT will remain equal to n f " since BUSY 
is "1," and the Transmitter/Receiver will accept the data. Also, 
REJECT is "0," for all Transmitter/Receivers not corresponding to 
bits A through E . 

As shown in Figure 17, the REJECT signals from the 
Transmitter/Receivers are connected in parallel in a similar 
arrangement as was described earlier for the outputs of the NOR 



gates to which FLAG and GO are connected. 

As stated earlier, when the teletypewriter is not sending 
data, there is a Mark ("1") on the IN line. When a character 
is sent by the teletypewriter, a Space ("0") bit, called the 



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35 
"start bit," is first sent, followed by an eight bit combination 
of Mark6 and Spaces representing the particular character, which 
is followed by two Mark bits ("1"), called the "stop bits." 
The same signal conditions apply when the Transmitter/Receiver 
sends data to the teletypewriter. 

Most of the logic of the Register Sub-unit is shown in 
Figure l8; the time relationship of the signals used in the 
receive mode is shown in Figure 19. A shift register, composed 
of Flip Flops 6 through lk (D flip flops) is used in both the 
transmit mode and the receive mode. Since in the receive mode, ' 
the "start bit" ("0") of a word can occur immediately following 
the two "stop bits" ("1") of the previous word, it is necessary 
to gate a word into a buffer register, composed of Flip Flops 
15 through 22 (cross-coupled NOR gates) during the period of 
time that the two "stop bits" are occurring. This buffer register 
then holds the word until after PROCEED has been reset by Scan. 

In the receive mode, the "start bit" ("0") of an incoming 
word sets Flip Flop 1 (cross-coupled NOR gates), thus setting R 
RELEASE which gates FAST CLOCK to the trigger of Flip Flop 2; 
however, if the Transmitter/Receiver is already in the transmit 
mode, T RELEASE (which will be discussed in detail later) is "1," 
thus preventing the "start bit" from setting Flip Flop 1. Flip 
Flops 2 through 5 («JK flip flops) comprise a divide-by-sixteen 
circuit which provides SLOW CLOCK pulses to trigger the shift 
register (Flip Flops 6 through Ik ) . (In Figure 19* only four 



36 




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38 
FAST CLOCK pulses are shown for each SLOW CLOCK pulse, but in 
the actual circuit, sixteen FAST CLOCK pulses occur for each 
SLOW CLOCK pulse.) The divide-by-sixteen circuit is preset to 
eight, so that the "trailing edge" of SLOW CLOCK occurs during 
the center of the "start bit" and during the center of each of 
the following bits until fi RELEASE is reset. 

Initially Flip Flops 6 through lk are set. The input 
data is shifted into the shift register until the "start bit" is 
shifted into Flip Flop 1^; the "start bit" resets Flip Flop 1^+ and 
A when the received word is contained in Flip Flops 6 through 13 # 

Figure 20 shows Flip Flops 27 and 28 (JK flip flops) which 
comprise a four state sequential circuit, called A Circuit, for 
which the State Diagram is shown in Figure 21. When A is "1," the 
circuit is in state, Q Q « equal 00. Since the shift register 
(Flip Flops 6 through lk) is used for both the receive mode and 
the transmit mode, A can change from "1" to "0" as a result of 
the shift register being used for either mode. If the change of 
A from "1" to "0" occurs while the Transmitter/Receiver is in 
the transmit mode, T RELEASE is "1," and the A Circuit does not 
change states. However, if the Transmitter/Receiver is not in 
the transmit mode when A goes from "1" to "0," then T RELEASE is 
"0," and on the next FAST CLOCK pulse, the A Circuit goes from 
state 00 to state 01, and a positive pulse occurs on the Z_ line. 
This Z pulse resets Flip Flops 15 through 22 (buffer register). 



FAST CLOCK 



39 




FIGURE 20 LOGIC DIAGRAM FOR A CIRCUIT 



(A + 

T RELEASE) 







1 






+ 


Q 2? = 

Q 28 = 


Z3 « 
Z|> = 


Z5 « 










(A*T 






RELEASE) 






Q 2? = 

028 = 1 


Z3 = 1 

Z4 * ° 


Z5 - 


















Q 2? = 1 

028 = 1 


Z3 B 
Z^ - 1 


Z5 = 








i 








Q 2? = 1 

028 ■ ° 


Z3 = 

Z4 - 


Zj-.l 

















FIGURE 21 STATE DIAGRAM FOR A CIRCUIT 



ko 

On the second FAST CLOCK pulse, the A Circuit goes to 
state 11, and a positive pulse occurs on the Z^ line. This Z. 
pulse provides the following functions: (a) it gates the word 
from Flip Flops 6 through 13 (shift register) into Flip Flops 15 
through 22 (buffer register); and (b) it signals the FLAG-R ERROR 
Circuit (Flip Flops 23 and 2*0 to set FLAG; this action informs 
Scan that the Transmitter/Receiver has a word ready for transmis- 
sion to the computer. (The FLAG-R ERROR Circuit will be 
discussed later.) 

On the third FAST CLOCK pulse, the circuit goes to state 
10, and a positive pulse occurs on the Z_ line. This Z c pulse 
provides the following functions: (a) it resets Flip Flop 1 and 
R RELEASE, thus disengaging SLOW CLOCK; (b) it resets Flip Flops 
2 through *f and sets Flip Flop 5, thus presetting the divide-by- 
sixteen circuit to eight; and (c) it sets Flip Flops 6 through 1^, 
thus placing all M l*s" in the shift register and setting A. 

On the fourth FAST CLOCK pulse, the circuit returns to 
state 00 with all outputs equal to "0." The circuit stays in 
this state until A again goes from "1" to "0." 

After FLAG has been set, and Scan is ready for the 
Transmitter/Receiver to transmit its word, Scan resets PROCEED. 
Figure 22 shows Flip Flops 29 and 30 (JK flip flops) which 
comprise a four state sequential circuit, called PROCEED Circuit, 
for which the State Diagram is shown in Figure 23. When PROCEED 
is "1," the circuit is in state Q Q Q equal 00, and both outputs 



kl 




PROCEED 



FIGURE 22 LOGIC DIAGRAM FOR PROCEED CIRCUIT 



(PROCEED) 



(PROCEED) 







* 






* x 




(PROCEED) 


r* 


Q 29 « 
Q 3 = ° 


z x = 
z 2 = 














(PROCEED) 




Q 29 - 

Q30 = 1 


z 2 = 














Q29 = 1 

Q30 - 1 


z t ■ 
z 2 = 1 














( PROCEED ) 




-n 


Q 29 - 1 
Q30 - ° 


z t = 

Z2 B 






(PROCEED) 









FIGURE 23 STATE DIAGRAM FOR PROCEED CIRCUIT 



are "0." On the first FAST CLOCK pulse following a change of 
PROCEED from "1" to "0," the circuit goes to state 01, and a 
positive pulse occurs on the Z. line. This Z.. pulse gates the 
outputs from the buffer register (Flip Flops 15 through 22) into 
the Receive Buffer (for transmission directly to the computer)* 

On the second FAST CLOCK pulse, the PROCEED Circuit goes 
to state 11, and a positive pulse occurs on the Z_ line. This 
Z pulse resets Flip Flop 25 and signals the FLAG-R ERROR Circuit 
(Flip Flops 2J> and 2k) to reset FLAG. Both Flip Flop 25 and the 
FLAG-R ERROR Circuit are used to generate error messages which 
will be discussed later. 

If on the third FAST CLOCK pulse, PROCEED is still equal 
to "0," the circuit goes to state 10 with both outputs equal to 
"0." It stays in this state until the first FAST CLOCK pulse 
following a change of PROCEED from "0" to "1," at which time 
it returns to state 00. 

The output gates for each bit (of the buffer registers) 

are connected in parallel in the same type of arrangement that 

was described earlier for FLAG. Figure 2k shows the connection 

for bit F . If bit F is "1" when the negative Z pulse (positive 

Z pulse) occurs, the corresponding transistor stays "off" and 

bit F is transmitted as "1," thus setting Flip Flop 6 of the 

Receive Buffer. If bit F is "0," then the negative Z n pulse 

r -L 

turns the corresponding transistor "on," and bit F is transmitted 
as "0." In this case, Flip Flop 6 of the Receive Buffer remains 



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reset. The other output gates are similarly connected. 

In addition to transmitting the eight bit character, 

the Transmitter /Receiver also transmits a two bit error message 

consisting of bits N and , which are transmitted to the Receive 

r r 

Buffer as the l^ftk and isu bits, respectively. These bits are 
gated into the Receive Buffer (for transmission to the computer) 
in the same manner and at the same time as the other eight bits by 
the Z.. pulse. Bit indicates an error caused by the simultaneous 
use of the Transmitter/Receiver for both the receive mode and the 

transmit mode; the generation of bit will be discussed later. 

r 

Bit N indicates an error caused when a word is loaded into the 
r 

buffer register (Flip Flops 15 through 22) while another word is 

still contained in the buffer register waiting to be gated into 

the Receive Buffer (for direct transmission to the computer). If 

both N and are "0," no error exists; if either N or is ,f l,' ! 
r r r r 

then the corresponding error has occurred. 

Flip Flops 23 and 2k (cross-coupled NOR gates with inverters) 
of Figure l8 comprise a three state sequential circuit, called 
FLAG-R ERROR Circuit, for which the State Diagram is shown in 
Figure 25. This circuit generates both FLAG and R ERROR, which is 

gated into the Receive Buffer as bit N . 

° r 

When the Transmitter/Receiver does not contain a receive 
mode word in either its shift register or its buffer register, 
the FLAG-R ERROR Circuit is in state, Q Q . equal 00, and both 
FLAG and R ERROR are "0." As a word is being gated from the shift 



<*5 



INITIALIZI 
1 


5 




Q 2 c « FLAG « 




$26 " ° R ERR0R = ° 












(2^) 




(Z^) 










Q 2 t = FLAG ■ 1 




Q 2 ^ =1 R ERROR ■ 












(z 3 ) 




(Z^) 










Q 2 r = 1 FLAG ■ 1 




Q 2 5 =1 R ERROR = 1 








(z 2 z^) 





FIGURE 25 STATE DIAGRAM FOR FLAG-R ERROR CIRCUIT 



46 
register into the buffer register and the Z, pulse occurs, the 
FLAG-R ERROR Circuit goes to state 01 with FLAG equal to "1" and 
R ERROR equal to "0." 

After the word has been shifted from the buffer register 
(Flip Flops 15 through 22) to the Receive Buffer, the Z ? pulse 
occurs, causing the circuit to change back to state 00 except 
for the case where the Z_ and Z. pulses occur simultaneously. In 
this case, no error has occurred, but the circuit remains in state 
01 with FLAG equal to "1," and R ERROR equal to "0." 

If a Z, pulse is followed by a Z_ pulse without a Z pulse 
occurring between them, an error has occurred, since the Z pulse 
has reset the flip flops of the buffer register while the previous 
word was still waiting in the buffer register for transfer to the 
Receive Buffer. This type of error is signified by R ERROR being 
equal to "1." Therefore, if a Z-. pulse occurs While the circuit 
is in state 01, the circuit changes to state 11 with both FLAG 
and R ERROR equal to "1." 

After the FLAG-R ERROR Circuit has entered state 11, it 
remains in this state until a Z pulse occurs, at which time the 
circuit returns to state 00, except in the case where the Z_ and 
Z. pulses occur simultaneously. In this case, the circuit goes to 
state 01 with FLAG equal to "1" and R ERROR equal to "0." 

As discussed earlier, when the computer wants to transmit 
data to one of the teletypewriters, Transmit Control produces a 



five microsecond DEMAND pulse. If the Transmitter/Receiver, to 



<*7 
which the computer is attempting to send data, is not presently 
either transmitting data to its teletypewriter or receiving data 
from its teletypewriter, REJECT will remain equal to "0," and 
the following actions will take place during the five microsecond 
DEMAND pulse: (a) bits F through M. will be gated into Flip 
Flops 6 through 13 respectively; (b) Flip Flop Ik will be reset, 
in order to provide a "start bit"; and (c) Flip Flops 2 through 
5 will be reset, thus presetting the divide-by-sixteen circuit to 



zero. At the end of the DEMAND pulse, a monostable multivibrator 

is triggered, producing a 110 millisecond T RELEASE pulse which 

engages SLOW CLOCK, thus shifting the data on to the OUT line, 

T RELEASE prevents the data from being shifted back into the 

shift register from the IN line. BUSY is "1," whenever either 

T RELEASE or R RELEASE is "1." 

When the Transmitter/Receiver is transmitting data to the 

teletypewriter, the IN and OUT lines are checked bit-by-bit by a 

three gate comparator circuit connected to the set lead of Flip 

Flop 26 (D flip flop). The check is made when SLOW CLOCK rises 

from "0" to "1," which occurs in the center of each bit on the 

OUT line since the bits are shifted on to the OUT line when SLOW 

CLOCK falls from "1" to "0." Whenever the IN and OUT bits are not 

identical in value at the time of the check, Flip Flop 26 is 

temporarily set, setting Flip Flop 25, thus also setting T ERROR. 

Flip Flop 25 remains set until after the error bit has been 

r 

gated into the computer. In order to insure that the computer is 



48 
notified of the error, FLAG is set whenever Flip Flop 25 is set, 
regardless of the state of the FLAG-R ERROR Circuit. 

The INITIALIZE line is connected to the Transmitter/ 
Receivers in order to establish initial conditions; the INITIALIZE 
pulse: (a) presets the dlvide-by-sixteen circuit to tight; 
(b) resets Flip Flop 1 and R RELEASE} (o) sets Flip Flops 6 
through Ik (shift register); (d) resets Flip Flops 23 and 2k % 
thus placing the FLAG-R ERROR Circuit in state 00; and (e) resets 
Flip Flop 25 and T ERROR. 



<*9 
CHAPTER VII 
CONSPECTUS 

The Data Communications Controller, which has been 
described in this thesis, is designed to serve as an interface 
between a digital computer and up to thirty-two teletypewriters or 
other input/output devices. Although the teletypewriter is the 
principal input/output device which the Controller is designed to 
service, other devices could be connected to the Controller, 
provided that a data rate of greater than ten characters per 
second is not required. When a device, other than a teletypewriter, 
is connected to the Controller, the corresponding Transmitter/ 
Receiver may have to be modified in order to provide the proper 
interface with the device. 

When a teletypewriter (or other device) is located at a 
relatively large distance from the Controller, it may be neces- 
sary to modify the comparator circuit in the corresponding 
Transmitter/Receiver. Under normal conditions with the teletype- 
writer located relatively close to the Controller, the line delay 
is negligible, and the IN and OUT lines can be compared at the 
same time. However, with large distances it may be necessary to 
determine the number, N,, of FAST CLOCK pulses occurring between 
the time that a bit is placed on the OUT line and the time that the 
same bit appears on the IN line. It would then be necessary to 
modify the comparator circuit so that it compares the OUT line at 
the leading edge of the SLOW CLOCK pulse with the IN line at 
"N d " number of FAST CLOCK pulses later. 



50 
REFERENCES 



Bain, M. "Linking On-line Data Acquisition to General Purpose 

Computers ," Control Engineering , April 196^f, PP« 92-95. 

Cooper, W. and Heckathorne, R. "Hardware for On-line," 

Transition to On-line Computing: Problems and Solutions , 
F. Qruenberger, Editor, Washington, D. C: Thompson 
Book Company, 1967, pp. 39-6*f. 

Corbato, F. J. and Fano, R. M. "Timesharing on Computers," 
Scientific American , September 1966, pp. 129-1^0. 

Korn, G. A. "Digital Computer Interface Systems," Simulation , 
December 1968, pp. 285-298. 

Newell, D. E. "The Design of an Input/Output Control Unit," 
Master's Thesis, Graduate College, University of 
Illinois, 1967. 

Yourdon, E. Real-time Systems Design , Cambridge, Massachusetts: 
Information and Systems Institute, Inc., 1967* 



% 



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ty e