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JAPIO 

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02771253 **Image available** 
MEMORY CONTROL SYSTEM 


Pub* No.: 01-068853 [JP 1068853 A ] 
Published: March 14, 1989 (19890314) 
Inventor: KANEKO TADASHI 
SUDO KlYOSHI 

Applicant: FUJITSU LTD [000522] (A Japanese Company or Corporation), JP (Japan) 
Application No.: 62-227020 [JP 87227020] 
Filed: September 10, 1987 (19870910) 
International Class: [ 4 ] G06F-012/06 

JAPIO Class: 45.2 (INFORMATION PROCESSING -- Memory Units) 

Journal: Section: P, Section No. 892, Vol. 13, No. 284, Pg. 19, June 29, 1989 (19890629) 

ABSTRACT 

PURPOSE: To shorten the queuing time of a CPU, by checking the start of write at every stage of 
interleave and starting the read data transfer report to the CPU and a read data holding means after 
confirming that the stage is idle. 

CONSTITUTION: An interleave control part 1 1 is provided with a read data holding means 13 
where read data from memory banks 1 -4 is held and a control means 12, and this control means 
checks the start of write it every stage of interleave and starts the read data transfer report to CPUs 5- 
8 and a read data holding means 1 3 after confirming that the stage is idle. Thus, when overlapping 
between transfer of read data and that of write data is forecasted, read data is held in the read data 
holding means 1 3 and its transfer can be delayed with one stage as the unit, and the queuing time of 
CPUs 5-8 is shortened as much as possible. 


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