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MANUAL 


PROGRAMMED DATA 
PROCESSOR - 4 
MANUAL 


DIGITAL EQUIPMENT CORPORATION +. MAYNARD, MASSACHUSETTS 


Foreword 


This manual is for programmers and users of the Programmed Data 
Processor-4, a high speed, stored program, digital computer manufac- 
tured by the Digital Equipment Corporation. Chapters 2 and 3 contain the 
detailed information necessary to make use of the machine. Chapter 1 
summarizes the machine's electrical and logical design. Chapter 4 pre- 
sents information helpful in making the electrical connections to input- 
output devices. Appendices provide detailed data which may be helpful 
in specific programming assignments. Although program examples are 
given in this document, no attempt has been made to teach programming 
techniques. However, Appendix 4 explains the meaning and use of special 
characters used in the programming examples. 


Copyright 1962 Digital Equipment Corporation 


Table Of Contents 


Page 
CHAPTER 1: SYSTEM DESCRIPTION  ............ mI sees 5 
CHAPTER 2: ARITHMETIC AND CONTROL ELEMENT  ........... ee 11 
Functions: osculo see uA a ee eee aad nlt 11 
Control States ss... seierer iists ir verir iernedtnrntasatedriredensretdnen: 15 
Instructions —..ccccccecccccccecccsceccscescectscscosencctcuecsceseuensnceeenesecedsueescuscueneesssenrenerennoes 16 


CHAPTER 3: INPUT-OUTPUT EQUIPMENT FUNCTIONS AND PROGRAMMING ..25 


Input-Output Commands eee ee eee 1 25 
Device Selector utes GSA: 25 
Information Collector ss regs 26 
Information Distributor... HH HH ee eeee eet een t ey 28 
Input-Output Skip Facility se 28 
Program Interrupt Control ........................................................................ 28 
Input-Output Status Instruction eerren erenn 29 
Clock/TImEr 13. 5040 amant a date MN Enter MR Res 29 

Input-Output Devices se 30 
Precision CRT Display, Type 30A ...........sssss He 30 
Light Pen, Type 32 ............... eee ee 32 
Precision CRT Display, Type 30D and Light Pen, Type 32 .............................… 33 
High Speed Analog-to-Digital Converter (Typical Input Dec. are 34 
Low Speed Analog-to-Digital Converter (Typical Input Device) 55.08 35 
Perforated-Tape Reader see 36 
Printer-Keyboard and Control, Type 65 ...................................................... 38 
Perforated-Tape Punch and Control, Type 75 .........1-. essere 42 
Card Reader and Control, Type 41-4 He 44 
Card Punch Control, Type 40-4 HH 46 
Automatic Line Printer and Control, Type 62 sese ee ees 49 

CHAPTER 4: THE INTERFACE ELECTRICAL CHARACTERISTICS .......................- 52 
Appendix 1 Instruction Lists ................. eect nett eer e renee teeter 57 
Appendix 2 Codes e eene eee eee eee EEE Ea 61 
Appendix 3 Read-In Mode Sequence ............................................................. 65 
Appendix 4 Assembly Program sss Mee renens 67 
Appendix 5 Multiply and Divide Subroutines ..................................................... 70 
Appendix 6 Programming Aids cece eee 73 
Appendix 7 Powers of 2 sss eee 75 







SA ERE 


EA ie 






123375 é g 


Typical PDP-4 System 


CHAPTER 1 
SYSTEM DESCRIPTION 


Summary 


The Digital Equipment Corporation Programmed Data Processor-4 (PDP-4) 
is designed to be the control element in an information processing system. 
PDP-4 is a single address, parallel, binary machine with an 18-bit word 
length using 1’s or 2's complement arithmetic. Standard features of the 
machine are stored program operation, a random access magnetic-core 
memory, a complete order code, and indirect addressing. 


Flexible, high-capacity input-output capabilities of the PDP-4 enable it to 
operate in conjunction with a variety of peripheral devices, such as per- 
forated-tape readers and punches, punched-card readers and punches, 
Teletype printer-keyboard, line printers, magnetic tape transports, and 
analog-to-digital converters. 


The machine is completely self-contained, requiring no special power 
sources, air conditioning, or floor bracing. From a single source of 115- 
volt, 60-cycle, single-phase power, PDP-4 produces circuit operating dc 
voltages of —15 volts (+1) and +10 volts (+1) which are varied for mar- 
ginal checking. Total power consumption is 900 watts. It is constructed 
with standard DEC 4000 series system modules and power supplies. 
solid-state components and built-in marginal checking facilities insure 
reliable machine operation. 


System Description 


The basic PDP-4 system is shown diagramatically in Figure 1. Three por- 
tions of the system are delineated according to function: the Arithmetic 
and Control Element, the Interface, and the Input-Output Equipmen: 
Information originates not only from peripheral devices but can be entered 
manually and modified at the Operator Console. 


armene [ EJ INTERNAL CORE I MOBILE 
ELEMENT CONSOLE PROCESSOR* MEMORY* | BE 


E de ed bn m REAL TME L 
i INTERFACE | Y. | | "| CONNECTION* 


E INT EU is — pa Le | = - ef a. — - — -— 
EQUIPA ENT. | =f 


PERFORATED- | PRINTER-KEYBOARD T one 
TAPE READER* AND CONTROL, TYPE 65 CONTROL. TYPE 75 


included ina 
Standard PDP-4 


Figure 1 — PDP-4 System with Real-Time Connection 


ARITHMETIC AND CONTROL ELEMENT 


The Operator Console, Internal Processor, and Core Memory constitute 
the Arithmetic and Control Element. The Internal Processor carries out 
the arithmetic and logical operations and controls the Real-Time Connec- 
tion and the Core Memory. Binary arithmetic with a fixed point is employed. 
The optional Extended Arithmetic Control Unit, Type 22, gives PDP-4 a 
multiply, divide, and arithmetic shifting capability without the use of sub- 
routines. 


The Console is used to observe and control the action of the program and 
the Internal Processor, and to alter the contents of Internal Processor 
registers. The contents of Core Memory can be examined or new infor- 
mation deposited. All Internal Processor registers are displayed 
continuously. 


Memory capacities of from 1,024 to 32,768 words are available for PDP-4. 
The cycle time (the time required to read information from memory and 
rewrite information back into memory) is 8 microseconds. The access 
time (the time required to read information from memory) is 2 micro- 
seconds. In the event of power failure, the contents of the Core Memory 
remain unaltered. See Chapter 2 for detailed functions of the Arithmetic 
and Control Element. 


INTERFACE 


The Real-Time Connection, furnished as standard equipment, provides 
communication between the Internal Processor and the Perforated-Tape 
Reader, the Perforated-Tape Punch and Control, Type 75, and the Printer- 


6 


Keyboard and Control, Type 65. The Real-Time Option, Type 25 gives the 
system the additional capability to operate efficiently over a wide range 
of information handling rates (from seconds per event to 125,000 words 
per second) and with a large variety of input-output devices (see Figure 2). 
The Real-Time Option consists of a Device Selector, an Information Col- 
lector, an Information Distributor, an Input-Output Skip connection, a 
Program Interrupt facility, a Data Interrupt facility, and a Clock/Timer. 
See Chapter 3 for details of functions. 


OPERATOR INTERNAL CORE mer | nilo d 
c ARITHMETIC CONSOLE* PROCESSOR* MEMORY* | | TYPE Er | MT 
AND CONTROL | | S 


ELEMENT 






INTERFACE — — REAL TIME 


TYPE 25 


INPUT- OUTPUT 


PRINTER-KEYBOARD FET TAPE PUNCH AND 
[===] AND CONTROL, TYPE 65 Le Gre CONTROL. TYPE 75 





F ProarammeD MAGNETIC |-- TILLER CARD PUNCH 
CARD READER LEE. TAPE CONTROL. ci CONTROL, 
AND CONTROL. Sod T. TYPE 54 edir TYPE 40-4 
S : COE A A AUTOMATIC LINE PRINTER) 
Ta ur Mi fem SE på STE AND CONTROL | 
——— nene TAPE fi: BI pee TYPE 62 
DES | | TRANSPORT. Le 


o X ms TYPE 50 JL: 
‘included ina À "RELAY BUFFER, 
neiuded in a 
Standard PDP-4 | TYPE 67- 4 
E Lid LIGHT PEN. PRECISION CRT å | 
Fe TT PESA DISPLAY, TYPE 30 e fio o 





Figure 2. — PDP. 4 System with «Real ime or 


THE DEVICE SELECTOR consists of decoding elements to select and 
establish the state of an external device when the program issues an 
input-output transfer instruction. The direction of information transfer 
(in or out of the Internal Processor) is controlled by signals produced 
by the Device Selector. Up to 64 input-output devices can be selected 
and these, in turn, may cause the selection of many more. The stand- 
ard Device Selector has provisions for twenty selector elements. 


THE INFORMATION COLLECTOR receives information from input 
devices (selected by the Device Selector) and transfers the informa- 
tion to the Internal Processor. Up to 18 bits of information can be 
collected simultaneously; 8 x 18 bits of information may be collected, 
broken into variable-sized words. 


7 





The Perforated-Tape Reader (top) and Printer-Keyboard (bottom). 


THE INFORMATION DISTRIBUTOR distributes information from the 
Internal Processor to all output devices. Only the output device se- 
lected (or addressed) by the Device Selector samples and reads in 
the information contained in the Information Distributor. Up to8 x 18 
bits may be distributed. | 


THE INPUT-OUTPUT SKIP CONNECTION provides a program skip 
instruction conditioned by the state of a given input-output device 
logic line. The instruction following the skip instruction will not be 
executed if the line is a 1. Eight skip conditions may be sampled. 


THE PROGRAM INTERRUPT permits one of 11 lines (conditions) or 
input-output devices to interrupt the program and initiate a sub- 
routine which may return to the original program when the cause for 
interruption has been processed. The machine state is preserved 
during a Program Interrupt. This type of interrupt is suited for in- 
formation or event rates in the range of 0 to 2,000 cycles per second. 


THE DATA INTERRUPT allows a device to automatically interrupt the 
program and deposit or extract data from the Core Memory at an 
address specified by the device. The Data Interrupt is suited for high 
speed information transfers; up to 125,000 18-bit words may be 
transferred per second. 


THE CLOCK/TIMER produces a signal which increments a Core Mem- 
ory register at a rate of 60 cycles per second. When the register over- 
flows, a Program Interrupt occurs. 


INPUT-OUTPUT DEVICES 


All of the input-output devices are optional except the Perforated-Tape 
Reader. 


THE PERFORATED-TAPE READER senses 5., 7-, or 8-hole perforated- 
tape at the rate of 300 lines per second. Either one line of tape (alpha- 
numeric) or 3 lines of tape (binary word) may be read. 


THE PERFORATED-TAPE PUNCH AND CONTROL, TYPE 75, per- 
forates 5-, 7-, or 8-hole paper tape at a rate of 63.3 lines per second. 


THE PRINTER-KEYBOARD AND CONTROL, TYPE 65, includes a 
Teletype Model KSR-28 Printer and Keyboard with an allowable input 
or printing rate of ten characters per second. Typed information may 
be monitored by a program. A program may print information. 


THE PRECISION CRT DISPLAY, TYPE 30, displays data on a 94" by 
94" area. Information is plotted point by point to form either graphical 


or tabular data. Operation of this device requires the Real-Time Option. 


THE LIGHT PEN, TYPE 32, is a photoelectric device which detects 
information displayed on the Type 30 Visual CRT Display. Upon signal 


9 


from the Light Pen, the computer carries out previously programmed 
instructions. Requires Real-Time Option. 


THE 18-BIT RELAY BUFFER, TYPE 67-4, provides contacts which 
operate devices of higher power rating. The relays have form “D” 
contacts, which open and close in approximately 3 milliseconds. 
Requires Real-Time Option. 


THE PROGRAMMED MAGNETIC TAPE CONTROL, TYPE 54, controls 
up to four Magnetic Tape Transports, Type 50. Information is read 
from or written on the tape. The format on the tape may be pro- 
grammed to be compatible with IBM tapes having a density of 200, 
6 + 1 bit characters per inch. Requires Real-Time Option. 


THE MAGNETIC TAPE TRANSPORTS, TYPE 50, are used with the 
Programmed Magnetic Tape Control, Type 54. 


THE AUTOMATIC LINE PRINTER AND CONTROL, TYPE 62, operates 
at up to 600 lines per minute, 120 columns per line. Each column 
may print one of 64 characters. Spacing format is controlled by a 
punched format tape in the Printer. Once a command to print or space 
is given, the Internal Processor is not required. Approximately one 
per cent of program running time is required to operate the Line 
Printer at a 600-line-per-minute rate. Requires Real-Time Option. 


THE CARD READER AND CONTROL, TYPE 41-4, operates at a rate of 
up to 200 cards per minute. Cards are read column by column. Column 
information may be read in alpha-numeric or binary mode. The alpha- 
numeric mode converts the 12-bit Hollerith Code of one column into 
the six-bit binary-coded decimal code with code validity checking. 
The binary mode reads a 12-bit column directly into the PDP-4. Ap- 
proximately one per cent of a Card Reader program running time is 
required to read the 80 columns of information at the 200 cards per 
minute rate. Requires Real-Time Option. 


THE CARD PUNCH CONTROL, TYPE 40-4, enables the operation of a 
standard IBM Type 523 Summary Punch with PDP-4. Cards are 
punched row by row at a rate of 100 cards per minute. Approximately 
0.3 per cent of program running time is required to operate the Card 
Punch at the 100-card-per-minute rate. Requires Real-Time Option. 


PROGRAMMING AIDS 


Several programs are supplied with each PDP-4 to assist the programmer 
in routine tasks. They include: The PDP-4 Assembly Program, the DDT-4 
debugging tape, double-precision floating point routines, maintenance 
routines, a tape reproducer, punch routines, an octal debugging routine, 
an algebraic compiler, and a floating point functions program which will 
enable various functions, such as double precision floating-point sine, to 
be computed. See Appendix 6. ! 


10 


CHAPTER 2 
ARITHMETIC AND CONTROL ELEMENT 


In this chapter the functions of the Arithmetic and Control Element are 
described in detail. The operations of the machine instructions are ex- 
plained and listed. 


Functions 


INTERNAL PROCESSOR 


The Internal Processor performs arithmetic operations, controls memory 
access, and handles information entering and leaving the machine. It 
consists of the Information Processor Control, which oversees all activities, 
and six registers: Accumulator, Link, Memory Buffer, Memory Address, 
Instruction, and Program Counter. The elements of the Internal Processor 
are shown within the broken line in Figure 3. 


Data Interrupt 

address and 

data lines to 
and from external. 
devices, under 

control of Real 
Time Option 


ADDRESS 
SWITCHES 13 
(of Operator 

Console) 





| ACCUMULATOR 

| SWITCHES 18 
(of Operator 
Console) 













MEMORY 
ADDRESS 


! PROGRAM - 

COUNTER 3 LL @ 

ml INSTRUCTION À y 
m REGISTER 4 iu | 





Normal data . === | | rt 
transfer dines | ACCUMULATOR 18 aag 
to and from ^C T — i 
externa! devices, th | À ee 
fooi f 






MEMORY 
BUFFER 
REGISTER 18 






Via the Real Time 
Option ör under 
. control of Real . 
Time Connection 









- Control. .- 






KEYS 
] (of Operator INTERNAL PROCESSOR seas | | PE" 
Console) enr toand ES | 
| I INTERNAL å mne e foma A 
| Processor or Wil me sd EN 


Figure 3 — Arithmetic and Control Element 


11 


REGISTER 13 |. 


ACCUMULATOR (AC): Arithmetic operations are performed in this 
18-bit register. The AC may be cleared and complemented. Its con- 
tents may be rotated right or left with the Link. The contents of the 
Memory Buffer may be added to the contents of the AC with the result 
left in the AC. The contents of both these registers may be combined 
by the logical operations AND and Exclusive OR, the result remaining 
in the AC. The Inclusive OR may be formed between the AC and the 
Accumulator Switches on the Operator Console (see below), and the 
result left in the AC. 


The Accumulator also acts as an input-output register. Under normal 
operation all information transfers between core memory and an 
external device must pass through the Accumulator. 


LINK (L): This is a one-bit register used to extend the arithmetic 
facility of the Accumulator. In 1’s complement arithmetic, the Link 
is an overflow indicator; in 2’s complement it functions as a carry 
register. The Link may be cleared and complemented and its state 
sensed independent of the AC. It is included with the AC in rotate 
operations. 


MEMORY BUFFER (MB): All information transferred between Core 
Memory and the AC, Instruction Register, or Program Counter passes 
through the MB. Information is read from a memory cell into the MB 
and rewritten into the cell in one cycle time (8 microseconds). In- 
structions are brought from memory into the MB to be decoded. The 
MB serves also as a buffer for information transferred between Core 
Memory and an external device in a Data Interrupt. The contents of 
the MB may be incremented by one. 


MEMORY ADDRESS REGISTER (MA): The address of the Core Memory 
cell currently being accessed is contained in the 13-bit MA. Informa- 
tion may enter the MA from the MB, Program Counter, or from an 
external device operating in a Data Interrupt. 


INSTRUCTION REGISTER (IR): This is a 4-bit register which contains 
the operation code of the instruction currently being performed by 
the computer. Information enters the IR from the MB. 


PROGRAM COUNTER (PO): The program sequence, that is, the order 
in which instructions are performed, is determined by the PC. This 
13-bit register contains the address of the memory cell from which 
the next instruction will be taken. Information may enter the PC from 
the MB, MA, or the Address Switches of the Operator Console. 


12 


MEMORY 


The memory contains stored information for processing, and the instruc- 
tions of the program being run. Memory capacities of from 1,024 to 32,768 
words are available in PDP-4. Standard models PDP-4A and PDP-4B come 
with 1024-word and 4096-word memories, respectively. The two models 
are identical in all other respects. The smaller memory has a 32 by 32 by 
18 core array, the larger a 64 by 64 by 18 core array. A Memory Module 
Type 17, containing a 64 by 64 by 18 core array may be added to PDP-4B 
to give it an 8192-word capacity. With the addition of the Magnetic Core 
Memory Extension Control Type 16, memory modules may be added to 
build a memory of 32,768 words. Further increase in storage capacity can 
be gained by adding the Magnetic Drum System Type 24, available in 
three capacities: 16,384, 32,768, and 65,536 words. 


OPERATOR CONSOLE 


The Operator Console contains all the switches and controls necessary to 
run the machine, and lights which indicate the current status of the In- 
ternal Processor. The functions of the lights and controls are described 
in the following tables. 





Figure 4 — Operator Console 


13 


Console Switches 


Function 








ADDRESS 


ACCUMULATOR 


POWER 


SINGLE STEP 


SINGLE INSTRUCTION 


REPEAT 


SPEED 


Console Light 





ACCUMULATOR 

MEMORY BUFFER 

LINK 

MEMORY ADDRESS 
INSTRUCTION 

PROGRAM COUNTER 

RUN 

FETCH, DEFER, EXECUTE, BREAK 


A group of 13 switches which establishes 
the memory address for the START, EX- 
AMINE, and DEPOSIT operations. 


A group of 18 switches, the setting of which 
determines the word to be placed in memory 
by the DEPOSIT and DEPOSIT NEXT opera- 
tions, or to be placed in the AC under 
program control. 


Controls the primary power to the computer 
and all external devices attached to it. 


Causes the computer to stop at the comple- 
tion of each memory cycle. Repeated opera- 
tion of CONTINUE while this switch is on 
will step the program one cycle at a time. 


Causes the computer to stop at the comple- 
tion of each instruction. Repeated operation 
of CONTINUE while this switch is on will 
step the program one instruction at a time. 
When both switches are on, SINGLE STEP 
takes precedence over SINGLE INSTRUC- 
TION. 


Causes the operations initiated by pressing 
CONTINUE, EXAMINE NEXT, or DEPOSIT 
NEXT, to be repeated as long as the key Is 
held on. The rate of repetition is controlled 
by the setting of the SPEED knobs. 


Two controls that vary the REPEAT interval 
from approximately 40 microseconds to 8 
seconds. The left knob is a five-position 
coarse control, the right knob a continuously 
variable fine control. For both knobs, slowest 
speed is obtained in extreme left position. 


Indication 


The contents of the AC. 

The contents of the MB. 

The contents of the Link. 

The contents of the MA register. 

The contents of the IR. 

The contents of the PC. 

The computer is executing instructions. 


The primary control state of the next mem- 
ory cycle. 


14 


Console Key 


START 


STOP 


CONTINUE 


EXAMINE 


EXAMINE NEXT 


DEPOSIT 


DEPOSIT NEXT 


Function 














Starts the processor. The first instruction is 
taken from memory cell specified by the 
setting of the ADDRESS: switches. The 
START operation clears the AC and Link, 
and turns off the Program Interrupt. 


Stops the processor at the completion of the 
memory cycle in progress at the time of key 
operation. 


Causes the computer to resume operation 
from the point at which it was stopped by 
the last previous operation of STOP or one 
of the EXAMINE or DEPOSIT keys. Besides 
the normal off and momentary on positions, 
CONTINUE has a latched on position ob- 
tained by ralsing the key instead of de- 
pressing it. 


Places the contents of the memory cell 
specified by the ADDRESS switches in the 
AC and MB. The contents of the ADDRESS 
switches appear in the MA. The PC contains 
the address of the next cell. 


Places the contents of the cell specified by 
the PC in the MB and AC. The C(PC) are 
incremented by one. The MA contains the 
address of the register examined. 


Deposits the contents of the AC switches in 
the memory cell specified by the ADDRESS 
switches. The C(AC switches) remain in the 
AC and MB. The contents of the ADDRESS 
switches appear in the MA. The PC contains 
the address of the next cell. 


Deposits the contents of the AC switches in 
the memory cell specified by the PC. The 
C(PC) are then incremented by one. The 
C(AC), C(MB), and C(MA) are the same as 
for DEPOSIT. 


Control States 


The PDP-4 operates in one of four primary control states during a memory 
cycle: Fetch, Defer, Execute, or Break. The next control state is established 
at the completion of the current one. All states except Break are deter- 
mined by the instructions themselves. 


FETCH: A new instruction is obtained when this state occurs. The 
contents of the memory cell specified by the PC are placed in the MB, 


15 


and the instruction part (bits 0-4) of this word are placed in the IR. 
The C(PC) are then incremented by. one. 


If a two-cycle instruction is fetched, the following control state will be 
either Defer or Execute. If a one-cycle instruction is fetched, the 
operations specified will be performed during the last part of the 
Fetch cycle. The next state will be Fetch. 


DEFER: When bit 4 of a memory reference instruction is a 1, the Defer 
state is entered to perform the indirect addressing. The process of 
indirect addressing is often referred to as deferring, in the sense that 
access to the operand is deferred once to another memory cell. This 
is why the primary control state in which this operation is performed 
is called Defer. Bit 4 of a memory reference instruction is referred to 
interchangeably as the Indirect or the Defer Bit. 


EXECUTE: This state is established only when a memory reference 
instruction is being performed. The contents of the memory cell 
addressed are brought into the MB, and the operation specified by 
the C(IR) is performed. 


BREAK: When this state is established, the sequence of instructions 
is broken for a Data Interrupt or a Program Interrupt. In both cases, 
the break occurs only at the completion of the current instruction. 


The Data Interrupt allows information to be transferred between 
memory and an external device; when this transfer has been com- 
pleted, the program sequence is resumed from the point of the break. 
The Program Interrupt causes the sequence to be altered. The C(PC) 
and the C(L) are stored in location 0000 and the program continues 
from location 0001, 


Instructions 


The instruction code is specified by bits 0-3 of a word. There are two types 
of instructions: Memory Reference and Augmented. 


MEMORY REFERENCE INSTRUCTIONS 


The bit assignment of the memory reference instruction is shown in Figure 
5. Bits 0-3 determine the operation to be performed. Bits 5-17 specify the 
address of the memory cell containing the operand. If bit 4 is a 1, then 
indirect addressing occurs. In the following discussion, i is the mnemanic 
symbol used to indicate indirect addressing. 


16 






CLEES Ie ieres 





Operation Indirect ^ Operand Address | 
Code Address .—— | ^ | | 
(Defer) 


Figure 5 — Memory reference instruction format 
INDIRECT ADDRESSING 


When indirect addressing is specified, the address part (bits 5-17) of a 
memory reference instruction is interpreted as the address of a cell con- 
taining not the operand, but the address of the operand. Consider the 
instruction add A. Normally, A is interpreted as the address of the cell 
containing the quantity be be added to the AC. Thus, if cell 100 contains 
the number 576, the instruction 


add 100 


will cause the quantity 576 to be added to the AC. Now suppose that cell 
576 contains the number 1135. The instruction 


add i 100 


(where i signifies indirect addressing) will cause the computer to take the 
number 576, which is in cell 100, as the effective address of the instruction, 
and the number in cell 576 as the operand. Hence this instruction will 
result in the quantity 1135 being added to the AC. 


If, when indirect addressing is indicated, the memory cell addressed by 
the instruction is one of those in locations 10-17, the contents of that cell 
are incremented by one and the result taken as the effective address. 
This feature is called auto-indexing. If memory cell 12 contains the number 
200, the instruction 


add i 12 
will cause the number in cell 200 + 1 to be added to the AC. 
1'S COMPLEMENT ARITHMETIC 


When two numbers are added together in 1’s complement arithmetic 
(see add instruction in following table), a 1 carried out of the high-order 
position will be added to the low-order digit, as follows: 


110101001100011 
011001010111101 


cl 001110100100000 
1 


001110100100001 


17 


Since bit O of a word is used for the sign of a number, the largest positive 
number that can be represented is 21” —1. If, in 1's complement addition, 
the addends are of like sign and the sign of the sum is different, overflow 
is said to have occurred and the Link is set to 1. 


2'S COMPLEMENT ARITHMETIC 


In 2's complement addition (see tad instruction), a carry out of the high- 
order bit is not added into the low order position. Instead, if a carry occurs, 
the Link is complemented. The signs of the addends and sum are not 
examined. Two’s complement addition is used primarily in multiple 
precision arithmetic. 


All memory reference instructions require an Execute cycle (see Control 
States above) to transfer data between Core Memory and the MB and 
execute the instruction. When indirect addressing is specified, an extra 
cycle is required to determine the effective address. The jmp instruction, 
while it requires an address, does not require an operand; an Execute 
cycle is thus not needed, and the instruction is performed in only one cycle. 


MEMORY REFERENCE INSTRUCTIONS 


Explanation of Special Terms 

















C(A) contents of A 4 | exclusive OR 
A => B | A replaces B V | inclusive OR 
Y1-4 bits 1-4 of Y A | AND 
Y; a given bit in Y A | 1’s complement of A 
OCTAL 
MNEMONIC CODE TIME 
SYMBOL (BITS 0-3) (usec) OPERATION 
lac Y 20 16 Load AC. The C(Y) are loaded into the AC. 


The previous C(AC) are lost. 
C(Y) => C(AC). 


dac Y 04 16 Deposit AC. The C(AC) are deposited in 
the memory cell at location Y. The previous 
C(Y) are lost; the C(AC) are unchanged. 


C(AC) => C(Y). 


dzm Y 14 16 Deposit Zero in Memory. Zero is deposited 
in memory cell Y. The original C(Y) are 
lost. The AC is unaffected by this operation. 


0 —» C(Y). 


add Y 30 16 Add (1’s complement). The C(Y) are adde 
to the C(AC) in 1's complement arithmetic. 
The result is left in the AC and the original 
C(AC) are lost. The C(Y) are unchanged. 
The Link is set to 1 on overflow. (See text). 


C(Y) + C(AC) => C(AC). 
18 


MNEMONIC 
SYMBOL 


tad Y 


xor Y 


and Y 


sad Y 


OCTAL 
CODE 
(BITS 0-3) 


34 


24 


50 


94 


TIME 
(usec) 


16 


16 


16 


16 






OPERATION I 
Two's complement Add. The C(Y) are 
added to the C(AC) in 2's complement 
arithmetic. The result is left in the AC and 
the original C(AC) are lost. The C(Y) are 
unchanged. A carry out of the Obit com- 
plements the Link. 


C(Y) + C(AC) => C(AC). 


Exclusive OR. The logical operation Ex- 
clusive OR is performed between the C(Y) 
and the C(AC). The result is left in the AC 
and the original C(AC) are lost. The C(Y) 
are unchanged. Corresponding bits are 
compared independently. 
C(Y;) V C(AC;) ^» C(AC ). 
Example 


C(AC); original C(AC); final 


— 00 
Orr © 


AND. The logical operation AND is per- 
formed between the C(Y) and the C(AC). 
The result is left in the AC, and the orig- 
inal C(AC) are lost. The C(Y) are un- 
changed. Corresponding bits are com- 
pared independently. 


C(Y;)) ^ C(AC;) => C(AC;) 


Example 






C(AC); original C(AC); final 


O O 
0 O 
1 O 
1 1 


Skip if AC is Different from Y. The C(Y) 
are compared with the C(AC). If the num- 
bers are the same, the computer proceeds 
to the next instruction. If the numbers 
are different, the next instruction is skip- 
ped. The C(AC) and the C(Y) are un- 
changed. | 


If C(AC) # C(Y) then C(PC) +1 => C(PC). 


19 


MNEMONIC 
SYMBOL 


isz Y 


jmp Y 


jms Y 


cal 


xct Y 


OCTAL 
CODE 
(BITS 0-3) 


44 


60 


10 


00 


40 


TIME 
(usec) 


16 


16 


16 


8 + time 
of in- 


OPERATION 


Index and Skip if Zero. The C(Y) are in- 
cremented by one in 2’s complement 
arithmetic. If the result is O, the next 
instruction is skipped. If not, the com- 
puter proceeds to the next instruction. 
The C(AC) are unaffected. 


C(Y) + 1 => C(Y). 

If result = 0, CCPC) + 1 => C(PC). 

Jump to Y. The next instruction to be 
executed is taken from memory cell Y. 

Y => C(PC). 

Jump to Subroutine. The C(PC) and the 


C(L) are deposited in memory cell Y. The 
next instruction is taken from cell Y + 1. 


C(L) => C(Yo). O => C(Y 1-4). 
C(PC) => C(Ys-a7). Y + 1 2» C(PC). 


Call Subroutine. The address portion of 
this instruction is ignored. The action is 
identical to jms 20. The instruction cal i is 
equivalent to jms i 20. 


Execute. The instruction in memory cell Y 
will be executed. The computer will act as 


struction if the instruction located in Y were in the 


being 
executed 


place of the xct. 


AUGMENTED INSTRUCTIONS 


None of the augmented instructions require a memory reference. Bits 
4-17 of an augmented instruction are used to specify operations, many 
of which may be combined in a single instruction. There are three classes 
of augmented instructions: 


a. Operate class: includes operations on the AC and Link, the skip 
group, and the halt instruction. 


b. The special instruction, law. 


c. Input-output transfer class: includes all the instructions which 
initiate transfers of information between the Internal Processor and 
an external device and those that sense the status of the devices. 


20 


OPERATE CLASS 


The instructions of the Operate class require one cycle for their execution. 
The octal code (bits 0-3) for this class is 74. The operations specified by 
bits 4-17 are called micro-instructions. The functions of each micro- 
instruction are described in the following table. The Event Time indicates 
when the operation is performed in the course of the cycle. Times 0, 1, 
and 2 occur in that order in the latter part of the cycle. 


Except for the restrictions indicated at the end of the table, micro- 
instructions may be combined in a single instruction. The bit assignment 
of the Operate class micro-instructions is shown in Figure 6. 


Opr-740000 


sx-1[sTsT7 Is Te DoDu Toe Te 7 


tittttttt 


Invert i 
Sense 


Of Skip 


lfbit8—1  Ifbit7—1 
szl sna spa rir rtl 


Wit 


tf 


cla cil 


Additional 


Rotate 





sn! sza sma hlt rar rak oas cml cma 


Figure 6 — Operate class instruction — bit assignment 














MNEMONIC OCTAL EVENT 
SYMBOL CODE TIME OPERATION 
opr 740000 Operate. Indicates the Operate class. When 
used alone, performs no operation; the 
computer proceeds to the next instruction. 
cla 750000 2 Clear AC. The AC is cleared to 0. 
O => C(AC). 
cma 740001 3 Complement AC. Each bit of the AC is com- 
plemented. 
C(AC) => C(AC). 
cll 744000 2 Clear Link. Link is set to O. 
O => C(L). 
cml 740002 3 Complement Link. C(L) => C(L). 


21 


MNEMONIC 
SYMBOL 


OCTAL 


CODE 


EVENT 
TIME 


OPERATION 





ral 


rti 


rar 


rtr 


oas 


sma 


spa 


Sza 


sna 


740010 


742010 


740020 


742020 


740004 


740100 


741100 


740200 


741200 


23 








Rotate AC Left. The C(AC) and the C(L) are 
rotated left one place. 


C(AC,) => C(AC;_1) 
C(AC,) => C(L). C(L) => C(ACi7) 


Rotate Two places Left. Equivalent to two 
successive ral’s. 


Rotate AC Right. The C(AC) and the C(L) are 
rotated one place right. 


C(AC;) => C(AC; 1) 
C(L) => C(ACo) 
C(ACiz) =>C(L) 


Rotate Two Places Right. Action taken is 
equivalent to two successive rar’s. 


OR AC Switches. The Inclusive OR of the 
C(AC) and the C(AC switches) is placed in the 
AC. A switch up is interpreted as a l. 


C(AC Switches) V C(AC) => C(AC). 


Example 






C(AC); original C(AC); final 


Ke © CE 
IM ee OC 


Skip if Minus AC. If the AC is negative, the 
next instruction is skipped. 


If ACy = 1, then CCPC) + 1 => C(PC). 

Skip if Plus AC. If the AC is positive, the next 
instruction is skipped. 

If AC, = O, then C(PC) + 1 => CCPC). 

Skip if Zero AC. If C(AC) are O, the next in- 
struction is skipped. 

if C(AC) = 0, then C(PC) + 1 => C(PC). 


Skip if Non-zero AC. 
If C(AC) 0, then C(PC) +1 => C(PO). 


22 


MNEMONIC OCTAL EVENT 
SYMBOL CODE TIME OPERATION č 








snl 740400 1 Skip if Non-zero Link. If C(L) is 1, the next 
instruction is skipped. 


If C(L) ¥ 0, then C(PC) +1 => C(PC). 


szi 741400 1 Skip if Zero Link. 
If C(L) = 0, then C(PC) + 1 => C(PC). 
hit 740040 immedi- Halit. Stops the computer. 
ately after 
the comple- 
tion of the 
cycle. 


If skips are combined in a single instruction, the Inclusive OR of the con- 
ditions to be met will determine the skip. For instance, if both sza and snl 
are indicated (octal code 740600), the next instruction will be skipped if 
either the AC is zero or the Link is non-zero, or both. 


If ral or rar is specified, cma, cml, oas may not be specified, and conversely. 
If rtl or rtr is specified, cma, cml, cla, cll, vas may not be specified, and 
conversely. 


THE INSTRUCTION, law 


The octal code for this instruction is 760000. Bits 5-17 are used to specify 
a quantity to be placed in the AC. The effect of the law instruction is to place 
itself in the AC. 


law Y 76 8 usec Load AC With law Y. 


INPUT-OUTPUT TRANSFER CLASS 


The instructions in this class are used to effect information transfers 
between the Internal Processor and external devices, via the Interface. 


iot 760000 | 8 usec Input-Output Transfer. Bits 4-13 of an iot 
instruction determine the device and sub- 
device to be selected. The presence of a 1 in 
bit 14 will cause the AC to be cleared at 
Event time 1. Bits 15-17 determine when 
pulses are to be sent to the selected device. 


The bit assignment of the iot instruction is shown in Figure 7. The instruc- 
tions of the iot class are described in Chapter 3. 


23 


Operation Sub-Device Device Sub-Device 
Code | Selection Selection Selection 






HEDBEBBUIEBIBEIDDEBIBEBIBBI 


| | Clear AC at event time t | 
Transfer an IOT pulse at event time 3 = 


Transfer an IOT pulse at event time 2= 
Tranefer an IOT pulse at event time 1 





if Bit Is a 1: 





Figure 7 — Bit assignment for input-output transfer instruction (iot) 


24 


CHAPTER 3 


INPUT-OUTPUT EQUIPMENT 
FUNCTIONS AND PROGRAMMING 


PDP-4 is capable of operating with the ten input-output devices described 
in Chapter 1 and with a variety of others. The computer can operate with 
most of the devices simultaneously. The Interface, consisting of the Real- 
Time Connection or the Real-Time Option, issues commands to the devices, 
monitors their state of availability, transfers information to them, and 
receives information from them. Since the Internal Processor can store 
or read out data much faster than the devices can operate, the Interface 
and the individual devices provide buffering to minimize the amount of 
program time consumed in transfers. 


The Real-Time Connection, furnished as standard equipment, provides 
communication between the Internal Processor and the Perforated-Tape 
Reader, the Perforated-Tape Punch, and the Keyboard-Printer. The Real- 
Time Option, Type 25, gives the system the additional capability to operate 
efficiently over a wide range of information handling rates, from seconds 
per event to 125,000 words per second, and with a large variety of input- 
output devices. The Real-Time Option consists of the Device Selector, the 
Information Collector, the Information Distributor, the Input-Output Skip 
Facility, the Program Interrupt Control, the Data Interrupt Control, and 
the Clock/Timer (see Figure 8). 


The coupling of input-output equipment to PDP-4 is similar for all devices. 
The electrical characteristics of the coupling are discussed in Chapter 4. 
The logical functions and programming instructions are given below. 


Input-Output Commands 


DEVICE SELECTOR (DS) 


The input-output transfer (lot) augmented instruction causes the Interface 
to produce pulses which select 10 devices and transfer information. Upon 
receipt of an instruction, the Device Selector in the Interface performs one 
of the following functions: 


(a) Starts a device (e.g.asks for a line of perforated tape to be read and 
assembled into a word, a card to be moved to a reading or punching 
station, etc.) 


25 


(b) Transfers data from the information buffer of an input device to 
the AC, through the Information Collector 


(c) Transfers information from the AC, through the Information Dis- 
tributor to the buffer of an output device 


(d) Senses the flag(s) associated with a device to determine its avail- 
ability 

(e) Resets the flags. These commands dismiss a device without asking 
for additional action. 


The flags referred to above are signals generated by an external device 
upon completion of its assigned task. This technique allows the Internal 
Processor to resume its arithmetic operations after issuing an instruction 
to a relatively slow input-output device (data rate of less than 20,000 
words per second). When a flag is set to 1 by the device, it signifies that: 


(a) an output action (punch out, etc.) has been completed; the Arith- 
metic and Control Element may transmit data to the device. 


(b) an input action (card or tape input, etc.) has occurred; information 
is available for the Arithmetic and Control Element. 


(c) an alarm condition exists. 


Flags may be sensed, and a program skip take place, using the Output 
Skip Facility (see below). Flags may be read into the AC using the iors (in-out 
read status) instruction. Most flags are connected to the Program Interrupt 
(see below). 


The Device Selector selects an input-output device or subdevice according 
to the address code of the device in bits 4-13 in the iot instruction. It then 
generates IO pulses at event times 0, 1, and 2 if the appropriate micro- 
instruction code bits are present in bits 17, 16, and 15. Pulse iot O occurs 
near the end of an iot instruction, followed by iot 1 in 2 microseconds. 
Pulse iot 2 occurs at the beginning of the next instruction, 1.2 microseconds 
after iot 1. This timing enables one iot instruction to perform multiple 
operations. 


INFORMATION COLLECTOR (IC) 
The Information Collector enables information to be collected from eight 
18-bit word input devices. The AC must contain 0 at the time the inputs are 
sampled. Å word can be broken into smaller words according to the word 


size requirements of the input device. The program steps for reading the 
contents of a group of static parallel data bits are: 


cla Clear the AC (AC must equal 0) 
iot Selected device (sample the selected device outputs) 


dac Y Deposit C(AC). The C(AC) are sent to a particular memory ceil, Y. 


(the first two steps may be microprogrammed together in one in- 
struction) 


26 














à or eee 1 “OT Pulses (3 X 20) 
D E SELECTOR ES ax) 


From D$ Lx OTE pulsas: ici “i -—À 00S 
| SERBE neorwarion [USA 
^. From input Data Linde EXT © COLLECTOR ki: "7 
: Devices — T d Ei B E ae à Å Fen : 
| From ID. mm PR Å po Ve O, 
th Device Flags: NT PE a | 
ve INFORMATION 
DISTRIBUTOR 


Jumped Coñneëtions E 
Tepe pates. IC, and IOS 























: LT oT. 
| From DS — 8 





‘Device Status 







. From io Device , 
/ UN pi qu E Mb occur me NE: 
2 pe | Program lore IE EA rr 

ica gn. rcf PROGRAM 
peine INTERRUPT 












er io Device å — 
fide 











TT "DATA. T 
el INTERRUPT. do zen 


DATA 
INTERRUPT |] ó 
ADDRESS [xs 


quest Acknowleged — 








DATA 
INTERRUPT 
INFORMATION 


(in) meo 










DATA 
INTERRUPT 
INFORMATION E 

(out) SE 










Figure 8 — Real Time Option, Type 25 


27 


INFORMATION DISTRIBUTOR (ID) 


The Information Distributor presents the static data contained in the AC 
to each output device requiring AC information. The devices sample the 
Information Distributor using the program-controlled pulses from the 
Device Selector. The program steps for transmitting information from a 
particular memory cell are: 


lac Y Load the AC with C(Y) 
iot Clear selected output register to prepare for information 


iot transmit The information is sampled and placed in the register of the 
input-output device. 
(the second two steps may be microprogrammed together 
in one instruction) 


INPUT-OUTPUT SKIP FACILITY (IOS) 


The Input-Output Skip facility enables the program to skip (or branch) 
according to various external device states. There are eight inputs to the 
Skip facility. The iot pulses from the Device Selector strobe an input line 
and if a logic condition is present, the instruction following the iot is skipped. 
The ¡ot skip pulse must occur at event time 1. 


PROGRAM INTERRUPT CONTROL (PIC) 


The program interrupt allows a logic line state to interrupt the program. 
It is used to speed the processing of input-output device information, or 
to allow certain alarm conditions to be sensed by the computer. The in- 
terrupt may be enabled or disabled by the program. 


When the interrupt occurs, the contents of the Program Counter and the 
Link are stored in memory location O (bits O, 5...17) and an interrupt 
program begins in memory location 1. This action disables the interrupt 
mode. The interrupt program is responsible for finding the signal causing 
the interruption, for removing the condition, and for returning to the 
original program. 


When the condition for interruption is removed, an iot signal to re-enable 
the Program Interrupt is given, followed by the instruction, jmp indirect O, 
or 620000. The interrupt program will then resume. If a Program Interrupt 
request is waiting, it will be serviced after the 620000 instruction. If a 
second interruption condition occurs and the interrupt program is running, 
the signal will have no effect; that is, there is only one level of interruption. 
The START key disables the Program Interrupt system. The iot instructions 
for the program interrupt are: 


iof — 700002 — Disable the Program Interrupt 
ion — 700042 — Enable the Program Interrupt 


28 


INPUT-OUTPUT STATUS INSTRUCTION 


The iors (in-out read status) instruction, 700314, enables the status of all 
IO devices to be read into the AC and sampled. Various IO device states 
are indicated by the presence of a 1 or O in the bit positions allocated for 
that device (see Figure 9). 





X X11X X XIX X 


X 
UNPEEEBBBEH 


Program interrupt On 11 | 
Tape Reader Flag 
Tape Punch Flag 
Keyboard Input Flag 
Type-Out Flag 
. Display Flag 
Clock Overflow Flag 
Clock Enabled 


Magnetic Tape Interrupt 





X X X X 
reos Tope Ta p TT. 


| [L. Printer Spacing Flag 
Line Printer Flag 
Card Punch Malfunction . 

' Card Punch Row Flag - 
Card Reader End of File Switch 


Card Reader Malfunction 
Card Reader Not Busy 
Card Reader Column Flag 





x « Program Interrupt Connected 


Figure 9 — Input-Output Status instruction, bit assignment 


CLOCK/TIMER 


The Clock produces a pulse every 1/60 second (16.6 milliseconds) which 
temporarily interrupts the program (in the same manner as the data 
interrupt) and a 1 is added to the contents of memory cell 7 using 2's 
complement addition. If the contents of memory cell 7 are O after the 
addition, the Clock flag is set to 1, which initiates a Program Interrupt if 
the Interrupt is on. Depressing the START key on the Operator Console 
clears the Clock flag and disables the Clock. The iot instructions associated 
with the Clock are: 


csf — 700001 — Skip the next instruction if the Clock flag is a 1 
cof — 700004 — Disable the Clock and clear the Clock flag 
con — 700044 — Enable the Clock and clear the Clock flag 


Register 7 is identical to other core memory registers, that is, its contents 
may be examined or modified. By presetting register 7 to a number, a 
Program Interrupt will occur when the register overflows after a timed 
interval. 


29 


Input-Output Devices 


All of the Input-Output Devices discussed below can be controlled by the 
Real-Time Option, Type 25. The Real-Time Connection, furnished as 
standard equipment, provides communication between the Internal Proc- 
essor and the Perforated-Tape Reader, the Perforated-Tape Punch and 
Control, and the Printer-Keyboard and Control. All devices except the 
Perforated-Tape Reader are optional. This section is arranged in the order 


of increasing complexity of connection. 


PRECISION CRT DISPLAY, TYPE 30A 


Data points are displayed on a 94 inch by 9% inch area. Information is 
plotted point by point to form either graphical or tabular data. Two digital- 
to-analog converters drive the deflection yokes in the X and Y directions. 
Data can be plotted at a 20 kc rate, or every 50 miscroseconds. 


The program loads the AC with a point to be plotted. Bits O through 8 specify 
the X co-ordinate of the point and Bits 9 through 17 the Y co-ordinate. The 
C(AC) are then transferred to the Display Buffer. The specifying of the 
point initiates the plotting of the point on the CRT. 


(18) Specifies 
X, Y Coordinates 





| Status Bits: 
. None 


PIC 


Program Interrupt: 
one a 


Figure 10 — Precision CRT Display, Type 30A programming logic 


30 


The CRT, Type 30A is selected when the numbers 0 and 5 (octal) are speci- 
fied in bits 8 and 9 respectively, of the iot instruction. The display com- 
mands are: 


dis — 700506 — Load the Display Buffer and select the display. The program 
loads the Display Buffer from the AC. A point is plotted as 
specified by the C(Display Buffer). The plotting requires 
50 microseconds, after which another dis can be given. The 
Light Pen flag or Display flag is cleared with dls. 


700502 — Clear the X and Y display buffers. O => C(Display Buffer). 


700504 — C(AC) V C(Display Buffer)-» C(Display Buffer). Plot the 
point specified by the C(Display Buffer). 


The points specified in the AC are plotted as unsigned quantities, beginning 
in the lower left hand corner of the cathode ray tube. The pointlocationsare: 


400377 . . 377377 
000000 iji 
000777! . "d 
777000 2? points 
777777 

400400 . . 377400 


914" 
| 2° points | | 


À program sequence is given in PDP-4 Assembly language below. The 
program begins in register 40, and plots a point, XY, as specified by Core 
Memory register 10. 


PROGRAM SEQUENCE 


/display a point 30a 
107 wad /xy bits 0-8, bits 9-17 y. 
40/ lac 10 /place xy co-ordinate in ac 
/display the point, next dls command 


/must wait 50 microsec. 


31 


LIGHT PEN, TYPE 32 


The Light Pen is a photosensitive device which detects the presence of 
information displayed on a CRT. If the Light Pen is held in front of the CRT 
at a point displayed, the Display flag will be set to a 1. The Pen is specified 
by O and 5 in bits 8 and 9 of the ¡ot instruction. The commands are: 

dsf — 700501 — Skip if Display flag is a 1. 

dcf — 700502 — Reset the Display flag to a O. 


The Display flag is connected to bit 5 of the iors instruction, and to the 
Program Interrupt. 





Status Bits: 
05-Light Pen Flag —1 


Program Interrupt: 
Light Pen Flag 


Figure 11 — Light Pen programming logic 


PRECISION CRT DISPLAY, TYPE 30D 
AND LIGHT PEN, TYPE 32 


The Type 30D display plots points at a 20kc rate. The X and Y co-ordinate 
buffers (XB and YB) are loaded from the 10 bits, AC... 


32 


The instructions are: 


dsf — 700501 — Skip if the Display flag is a 1. The Display Flag is set to 1 
when the Light Pen senses light. 


dcf — 700601 — Clear the Display flag. 

dxl — 700506 — Load the C(XB) with C(ACx.17). 

dyl — 700606 — Load the C(YB) with C(AC: 1). 

dxs — 700546 — Load the C(XB) with C(AC;.17). Plot the point: C(XB), C(YB). 
dys — 700646 — Load the C(YB) with C(ACy.17). Plot the point: C(XB), C(YB). 


dib — 700706 — Load the Brightness Register with AC bits 15-17. The bits of 
AC specify the brightness of the points displayed. Clear the 
Display flag. 


700502 — Clear XB. 
700504 — C(SB) V C(AC) => C(XB). Display a point. 
700602 — Clear YB. 
700604 — C(YB) V C(AC) => C(YB). Display a point. 










n (10) Specifies . 
X or Y Coordinate 

and intensity 
MB: (1) 






16" CRT 






Qc uH Lun 
IC ) AND 
LIGHT PEN 








700601 


700502 Output 
700504 PRECISION CRT | 

DISPLAY CONTROL, 
E TYPE 30D 
700604 


700702 | 


D |^ Status Bits: None SE 
Program Interrupt: None = > 









Display 
Fiag 






Figure 12 — Precision CRT Display, Type 30D, and Light Pen, Type 32 


33 


The Display flag is connected to the Program Interrupt and to bit 5 ofthe 
iors instruction. The co-ordinates of the corners are: 


0,1777 , e 1777, 1777 


914" 
21? points 


X0, Y 0. e777, 0 dl 
914" 
re mecs 


PROGRAM SEQUENCE 


/display a point 304 


107 '$ 3 /x bits 8-17 
/y 
40/ lac 10 
dxl /load x 
lac 11 
dys /load y and plot the point 





HIGH SPEED ANALOG-TO-DIGITAL CONVERTER 
(TYPICAL INPUT DEVICE) 


An analog-to-digital converter with a resolution of 8 bits and a conversion 
time of 2 microseconds may be connected to the Real-Time Option. The 
input-output transfer instructions, series 11, for the converter are: 


sci — 701115 — Sample the analog input. Convert the sampled quantity to 
digital form and load the AC with the converted number. 


701101 — This micro-instruction starts the converter. In a period of 2 
microseconds the converter will form an 8-bit number pro- 
portional to the analog input. 


701104 — C(A-D converter) V C(AC) => A(AC). 


34 










(8) Information 
AC Bits 10-17 — 


Data Read In 









11 Series 8 BIT Analog 


ANALOG 
TO- 

DIGITAL 

CONVERTER 


PIC 
Figure 13 — High-speed analog-to-digital converter programming logic 
A program sequence to sample a function at the input to the converter, 


and store the result in memory register 10 would be: 


PROGRAM SEQUENCE 


/analog-to-digital converter 


10/ /iocation of sampled result 
42/ sci /places sample in AC 
dac 10 /deposit result 


LOW SPEED ANALOG-TO-DIGITAL CONVERTER 
(TYPICAL INPUT DEVICE) 


An analog-to-digital converter with a resolution of 12 bits and a conversion 
time of 60 microseconds can be connected to PDP-4. The converter is given 
an iot command to sample the analog function, and in 60 microseconds the 
converter will contain a 12-bit number proportional to the input. At the 
completion of the sample, the converter flag is set to a 1, signifying that 
the input data is ready. 


The contents of the converter buffer are read into the AC with a program 
command. The action which transfers the information from the converter 
to the AC also resets the converter flag. An iot skip instruction is used which 


35 


skips if the conversion is complete; i.e., the converter flag is a 1. The 
program instructions, lot series 11, are: 


asf — 701101 — Skip if the converter flag is a 1. 
arb — 701112 — Read converter buffer and clear converter flag. 
ase — 701104 — Start the converter and clear the converter flag. 


701102 —A micro-instruction which clears the converter flag, and 
C(converter buffer) V C(AC) => C(AC). 


The converter flag might connect to the Program Interrupt. 











(12) Information 


Read Data 
AC Bits 6-17 
Sample Data 

















chow Pag 12 BIT Analog 
51104 ANALOG Input 
Start Conversion TO- 
DIGITAL 
CONVERTER 









Skip if Done 


Done Flag Status Bits: None 


Program énterrupt: 
Convert Done Flag 


PIC 


Figure 14 — Slow-speed analog-to-digital converter programming logic 


PERFORATED-TAPE READER 


The Tape Reader senses 5-, 7-, or 8-hole perforated-paper (or Mylar) tape 
photoelectrically at 300 characters (or lines) per second. The Reader con- 
trol requests Reader movement, assembles data from the Reader into a 
Reader Buffer (RB), and signals the computer when incoming data is 
present. Reader tape movement is started by the Reader control request 
to release the Reader brake and simultaneously engage the clutch. 


In addition to the Reader movement control logic, the control unit contains 
an 18-bit Reader Buffer (RB) which can collect one or three lines from the 
tape. The C(RB) can be read into the AC. The Reader flag becomes a 1 
when a character or word has been assembled in the RB. 


36 










MB"; (Alphanumeric) 


MB; (Binary) | 

















(18)RB (information) 
E a T Information Strobe 
|a * [Bit 1 (Check Feed Hole 
ps 
8 Holes o 
PERFORATED- RATED- 
= 700102 TAPE Information eee 
JET | 700104 READER Run Signal READER 
; CONTROL (Clutch Engaged, 
Brake 
700101 Disengaged) 
Reader Flag 
Status Bit: 
( 9 1-Reader Flag 
nterrup 
PIC Interrupt: 
Reader Fiag 


Figure 15 — Perforated — Tape Reader programming logic 


O 1 2 3 





= *The next select puise must be given 
Binary Mode during this interval to keep the 
reader running at maximum rate. 


Figure 16 — Perforated-Tape Reader timing 
37 


An alphanumeric character is one line (5, 7, or 8 holes) on tape. A binary 
word consists of three consecutive characters (18 bits) on tape which have 
the 8th hole present. Only 8-hole tape is used in the binary mode; the /th 
hole is ignored. The first, second, and third six-bit characters are the left, 
middle, and right thirds, respectively, of the 18-bit word. The reader 
commands, iot select series O1, are: 


rsf — 700101 — Skip if Reader flag is a 1, i.e., character or word present. 


rsa — 700104 — Select Reader and fetch one alphanumeric character from 
tape. Clear the Reader flag. Reset RB. The character is read 
into RB bits 10-17. Turn on the Reader flag when character 
is present. 


rsb — 700144 — Select Reader and fetch a binary word from tape. Clear the 
Reader flag. Reset the RB. Fetch the next three characters 
(with 8th holes present) from perforated tape and place in 
RB bits 0-5, 6-11, and 12-17. Turn on Reader flag when a 
word is assembled. 


rrb — 700112 — Read RB. Clear the Reader flag, and transfer the contents of 
RB to the AC. 


rcf — 700102 — Clear the Reader flag. C(RB) V C(AC) => C(AC) 


The Reader flag is connected to the Program Interrupt Control and to bit 0 
of the iors instruction. Several methods may be used to program the 
Reader. The following sequence reads a character from tape and places it 
in the AC. Up to 400 microseconds of computation time are available 
between the end of the sequence and the next command to read a character 
or word from tape. The sequence, starting in register 40 is: 


PROGRAM SEQUENCE 


/perforated-tape reader 


40/ rsa /select reader alphanumeric 


/begin loop to look for character arrival 
/end loop to look for arrival 


/fetch character from reader buffer 





By changing instruction 40 to rsb the sequence would fetch a binary word. 


PRINTER-KEYBOARD AND CONTROL, TYPE 65 


The Printer-Keyboard is a Teletype Model 28 KSR (keyboard send-receive) 
which can print or receive ten characters per second. A five-bit code, given 
in Appendix 2, represents the characters. The printing (output) and key- 
board (input) functions have separate commands and control logic. 


38 


The signals to and from the KSR to the control logic are standard serial, 
7.5-unit-code Teletype signals. The signals are: start (1.0 unit), information. 
bits 1-5 (1.0 unit each), and stop (1.5 units). Figure 17 illustrates the 
current pattern produced by the binary code 10110. 


O (Current) 100 MS | 
1 Unit = 33.33MS 1 1 1 1 1 1 15 





idle Line 
(Bias Current) 





Sian Ar ems st (return to 
= Bit5 Stop ine) 
Signal | Signal Idle Line) 


Figure 17 — Teletype timing of information code 10110 


KEYBOARD 


The Keyboard control contains a 5-bit buffer (KB) which holds the code for 
the last key struck. The Keyboard flag signifies that a character has been 
typed and its code is present in the Keyboard buffer. The Keyboard flag 
and Keyboard buffer are cleared each time a character starts to appear 
on the Teletype line. The Keyboard flag becomes a 1, signifying the buffer 
is full 0.5 + 0.125 units after the end of information bit 5, or 86.6 milli- 
seconds after key strike time. The instructions to manipulate the Keyboard 
are: 
ksf — 700301 — Skip if the Keyboard flag is a 1, i.e., character present. 


krb — 700312 — Read Keyboard buffer. Clear the Keyboard flag. C(KB)=> 
C(AC) 


700302 — Clear the Keyboard flag. C(KB) V C(AC)=> C(AC) 
0 10 20 30 40 50 60 70 80 90 100 © 





Computing Time=100MS 
0 Between Characters - 
At Maximum Rate — 


Figure 18 — Keyboard timing 


39 


(5)KB(Info.) 














ic info. Strobe 
|` Check | 

Status) Serial 
¡OT 03 info. 
KEYBOARD 1, Input 

os os i || CONTROL KEYBOARD 

700301 
Keyboard To 
Flag Printer 
$ Status Bit: 


03 Keyboard F! 
(Interrupt) Ne 





Interrupt: 
Keyboard Flag 


PIC 


Figure 19 — Keyboard programming logic 
The Keyboard flag is connected to the Program Interrupt Control and the 
iors instruction, bit 3. A simple sequence which "listens" for keyboard 
inputs is: 


PROGRAM SEQUENCE 


/listen loop for keyboard 


400/ ksf /skip when a character arrives from keyboard 


jmp 400 


krb /read in the character 





The sequence following the listen sequence beginning in 403 may operate 
for up to 100 + 13.3 milliseconds before returning to listen for the next 
character without missing the next character. The average computing time 
between any two characters must be less than 100 milliseconds (for an 
input rate of 10 characters per second). 


TELEPRINTER 


The Teleprinter is given 5 bits of information from AC bits 13 to 17, coding 
the character to be printed. The teleprinter Buffer (TB) receives this infor- 
mation, transmits it to the Teleprinter serially, and when finished turns on 


40 


the Teleprinter flag. The Flag is connected to the Program Interrupt and to 
bit 4 of the iors instruction. The printing rate is ten characters per second. 
The instructions for the printer are: 


tsf — 700401 — Skip if Teleprinter flag isal. 


tis — 700406 — Load the Teleprinter from AC bits 13-17, clear the Teleprinter 
flag. Select the Teleprinter for printing. 


tcf — 700402 — Clear the Teleprinter flag. 
700404 — C(AC) V C(TB). Print a character. 


O 10 20 30 40 50 60 70 80 90 100 
MS 


Ref. 


Flag O VP AA AA 
I T 
TLS 
Or TT E l EE ESS LE 
TCF** 
Load 
TB 





Print E 
Action 


Buffer Must Be Loaded By This Time 
To Allow 10 Char/Sec Operation 


**1f TCF, Flag Will Not Come On Until Next TLS Complete 
*Determined By Printer 


Figure 20 — Printer timing 


PROGRAM SEQUENCES 


/print and wait for Teleprinter 


tls /print the character from AC bits 13-17 

tsf /begin listen loop for printing completion 

jmp.-1 /return to previous instruction or listen loop 
/again 


41 


/wait for previously printed character completion, then print 


tsf /wait loop until previous character printed 
jmp.-1 /return to wait loop beginning 


tis /print the new character 





In the first sequence above, 20 milliseconds of program time is available 
between that tls and the next one that can be given. In the second se- 
quence, 100 milliseconds of program time is available between that tls 
and the next one that can be given. 


From 





Keyboard 
(5) Information 
(For Printer 
| . Buffer) 
= ^ Bit4 
(Check Status) 
A D Serial 
AL 700402. | PRINTER L_information | 
DS [TTT 7004043 | contro} | PR 
700401 Printer 
>a di _ Flag 
Status Bit: 
( | | 04-Print Flag 
nterrupt ; 
interrupt: 
Print Flag 


Figure 21 — Printer programming logic 


PERFORATED-TAPE PUNCH AND CONTROL, TYPE 75 


The Teletype BRPE paper-tape punch perforates 5-, 7-, or 8-hole tape at 
63.3 characters (lines) per second. Information to be punched on a line of 
tape is loaded on an 8-bit buffer (PB) from the AC bits 10 through 17. The 
Punch flag becomes a 1 at the completion of punching action, signaling 
that new information may be read into Punch Buffer (PB) (and punching 
initiated). The Punch flag is connected to the Program Interrupt and to 
the iors instruction bit 2. The Punch instructions, iot series 02, are: 


42 


psf — 700201 — Skip if the Punch flag is a 1. 
pcf — 700202 — Clear the Punch flag. 


pls — 700206 — Load a character into PB from AC bits 10-17. Clear the Punch 
flag. Punch the specified character. 


700204 — C(PB) V C(AC)=> C(PB). Punch the C(PB). 


0 2 4 6 8 10 43? 14 15.20 





| Buffer Must B 
Loaded By This 
Time to Allow 63.3 
Char/Sec Operation 


*Determined By Punch 
**PCF Flag Will Not Come On Until Next P Is Complete 


Figure 22 — Perforated-Tape Punch timing 
PROGRAM SEQUENCES 


/punch the contents of AC and wait 
pls /punches AC 10-17 
psf /wait till done loop beginning 
jmp.-1 /wait till done loop end 
/wait for previous punching, then punch next 
psf /wait loop for previous character punching 


jmp.-1 /wait loop end 


pls /punch the next character on tape 





In the first sequence above, 11.3 milliseconds of program time is available 
between the instruction following the wait loop and the next pls that can 
be given. In the second sequence, 15.8 milliseconds or more program 
time is available between the pls and the next time a pls can be given. 


43 


i: ut or m is 


Bit 2 2 (Check Status) 






8 Info. 









tor 02. SEU are | PERFORATED | 
EA] 700202 TAPE 
YY 


_ 700201 


| TELETYPE 
| BRPE 







Feed + ROR 


Punch — 
Timing Signal — 









DS 


PUNCH 
CONTROL 


TAPE 
PUNCH 










md ee d Status Bit: 
ea nd Aic nterrupt: 


Punch Flag 


Figure 23 — Perforated-Tape Punch programming logic 


CARD READER AND CONTROL, TYPE 41-4 


The control of the Card Reader is different than the control of other input 
devices, in that the timing of the read-in sequence is dictated by the device. 
Once the command to fetch a card is given, the Reader will read all 80 
columns of information in order. To read a column, the program must 
respond to a flag set as each new column is started. The instruction to read 
the column must come within 300 microseconds after the flag is set. The 
interval between flags is 2.3 milliseconds. The commands for the Card 
Reader, lot series 67, are: 


crsf — 706701 — Skip if Card Reader flag is a 1. If a card column is present 
for reading, the instruction will skip. 


crrb — 706712 — Read the card column buffer information into AC and clear 
the Card Reader flag. One crrb reads alphanumeric in- 
formation. Two crrb instructions read the upper and lower 
column binary information. 


crsa — 706704 — Select a card in alphanumeric mode. Select the card reader 
and start a card moving. Information will appear in alpha- 
numeric form. 


crsb — 706714 — Select a card in binary mode. Select the card reader and 
start a card moving. Information will appear in binary form. 


Upon instruction to read the Card Reader buffer, 6 information bits a e 
placed into AC bits 12-17. Alphanumeric (or Hollerith) information on the 
card is encoded or represented with these six bits. The binary mode enablés 
the 12 bits (or rows) of each column to be obtained. The first read buffér 
instruction transfers the upper six rows (Y, X, O, 1, 2, and 3), the second 


44 


instruction transfers the lower six rows (4, 5, 6, 7, 8, and 9). The mode is 
specified with the Card Read Select instruction. The mode can be changed 
while the card is being read. 


0 20 40 60 80 109 d 20 140 160 180 200 220 240 260 2 





MS 


CRSA 
Or 
CRSB 
Card 15 usec 
Reader 0 ma 
Done 
Card 
Reader 
Flag 









| Next ORSA Or CREB Can “Ba Glen — 


800 usec 80-Column Ready Signals 
| Every 23 MS .. 





80-CRRB Each Command » El 
“Clears Col Flag = 


Figure 24 — Card Reader timing 





MB (Alphanumeric) _ 
MB: Binary) ——  — 









(6) Info. Col. 








CARD 
READER 


oe CARD 
CONTROL beg 


« A READER | s | > | 












| Status Bits; o 
Card Reader Flag © 
Fen 11-Card Malfurction. - ee yes 
Gard Col. Flags 7 7 007 


E 
Skip 





(Interrupt) | 






| PIC 


Figure 25 — Card Reader programming logic 


45 


The Card Read Flag is connected to the Program Interrupt Control and to 
bit 9 of the iors instruction. The Card Read Done status level bit is con- 
nected to bit 10 of the lors instruction. A Card Read Malfunction status is 
connected to bit 11 of the iors instruction. Card Read Malfunction status 
indicates one or more of the following conditions: Reader not ready (power 
off, etc.), hopper empty, stacker full, card jam, validity check error (if 
validity is on), or real circuit failure. 


Bit 12 of the iors instruction is connected to the END OF FILE switch at the 
Card Reader. The switch is activated manually, and when depressed, 
holds until the RESET END OF FILE switch is depressed. 


PROGRAM SEQUENCE 


/ sequence to read an 80-column card and place alphanumerlc codes 


/in register 1000-1117 (octal). Program begins in register cardrd. 


cardrd, crsa /read card in alphanumeric mode 
lac cardlo /initialize card location table 
dac 10 /place in indexable register 
lac cardct /initialize card count 80 (decimal) 
dac temp 
cdloop, crsf /wait for column loop 
jmp cdloop 
errb /place column information in AC 
dac 1 10 finfo t0 1000, 1001 522531117 
isz temp 
jmp cdioop 
hlt /finish of card, and halt 
cardlo, 1000-1 /location of card table 
cardct, ~120+1 /80 column counter initial value 
temp, O /reserved for column counter 


CARD PUNCH CONTROL, TYPE 40-4 


The Card Punch dictates the timing of a read-out sequence, much as the 
Card Reader controls the read-in timing. Once a card has started, all 12 
rows are punched at intervals of 40 milliseconds. Punching time for each 
row is 24 milliseconds, leaving 16 milliseconds to load the buffer for the 


46 


next row. À flag indicates that the buffer is ready to load. The commands 
for the Card Punch Control, iot series 64, are: 


cpsf — 706401 — Skip if Card Punch flag is a 1. The Card Punch flag indicates 
the Punch buffer is available, and should be loaded. 


cpcf — 706402 — Clear Card Punch flag. 


cpse — 706442 — Select the Card Punch. Transmit a card to the 80-column 
punch die from the hopper. 


cplb — 706406 — Load the Card Punch buffer from the C(AC). Five load in- 
structions must be given to fill the buffer. 








O 100 200 300 | 400  J 500 ss. 
MS 108 ! ws | a E 
Punch 0 | i 
Flag 1 | | | 
CPUR | bw s | NM 
| | To Clear 
Load | + Flag 
Buffer | 19 Í 
- Time 
Punch 
Action 





*CPSE Must be Given to Maintain 
Max Rate. A Delay of 600 or 1200 
MS Will Exist on Starting. 


Figure 26 — Card Punch timing 


Since 18 bits are transmitted with each iot instruction, 5 lot instructions 
must be issued to load the 80-bit row buffer. The first four loading in- 
struction fill the first 72 bits (or columns); the fifth loads the remaining 
8 bits of the buffer from AC bits 10-17. 


After the last row punching is complete, 28 milliseconds are available to 
select the next card for continuous punching. If the next card is not re- 
quested in this interval, the Card Punch will stop. The maximum rate of 
the Punch is 100 cards per minute in continuous operation. Å delay of 
1308 milliseconds follows the command to select the first card; a delay of 
108 milliseconds separates the reading of cards in continuous operation. 


The Card Punch flag is connected to the Program Interrupt, and to bit 13 
of the iors instruction. Faults occurring in the punch are detected by status 
bit 14 of the iors and signify the punch is disabled, the stacker is full, or 
the hopper is empty. 


47 


MB; 





(18) Information 


(For Row Buffer) 





[e Bit 15 
p« 3r 
IOT64 
os HH 
os > 
706401 Row 
Punch 
os ST] Flag 


Interrupt 
PIC ( på 





(80) Info 
Card 
Card 
Not OK 


Status Bits: 
13-Row Flag 
14-Card Not OK 


interrupt: 
Row Flag 


CARD 
PUNCH 


(Type 


523 
Summary 
Punch) 





Figure 27 — Card Punch programming logic 
PROGRAM SEQUENCE 


/sequence to punch 12 rows of data on a card. 


/5 consecutive registers beginning in location 100. 


/in register cardph. 
cardph, cpse 
lac punloc 
dac 10 

lac rowct 
dac tempt 
lac 


/loopi, grpct 


dac tempe 
cpsf 
jmp.-1 

loop2, lac i 10 


cpir 


Each row is stored in 


The program begins 


/select the card 


/initialize the card image 
/initialize the row counts, 12. 
/initialize the 5 groups per row 


/sense punch load availability 


/5 groups of 18 bit per row 


/load buffer command 


48 


¡A A Even 


isz temp2 

Jmp loop2 

isz tempi test for 19 rows 

jmp loop1 

hlt /end punching 1 card 
punloc, 100-1 /location of card image 
rowct, -14+1 /L2 rows per card 


grpct, -5+1 /5 groups per row 


templ, O /row counter 


temp?, O /group counter 





AUTOMATIC LINE PRINTER AND CONTROL, TYPE 62 


The Line Printer can print 600 lines of 120 columns per minute. Each col- 
umn has 64 characters. Spacing rate is approximately 132 lines (or two 
66-line pages) per second. 


MB: 
nm (18) Information 


Check Status 
Bit 12 
















706502 (120) Info. 






| ]1 ] [706504 , | 
LINE 8) S 
E 706602, 1 PRINTER (8) Space LINE 


PRINTER 
Info 


Status Bits: 
16-Space Flag 
15-Print Flag 


Interrupt: 
Space Flag 
Print Flag 


Figure 28 — Line Printer programming logic 


49 


A complete line, or 120 columns of information, is placed in the printing 
buffer. Six bits specify each character (the codes are given in Appendix 2). 
The information is transferred to the printing buffer through the AC, three 
characters at a time from AC bits 0-5, 6-11, and 12-17. Forty load print 
buffer instructions fill the 120-column line. 


After the printing buffer is loaded, a print instruction is given which prints 
the contents of the buffer. The action of printing does not disturb the 
printing buffer. When a column of information has been printed, the print- 


ing flag becomes a 1. Approximately 80 milliseconds are required to print 
one line. 


An eight-channel format-control tape inside the Printer moves in synchro- 
nism with the paper and specifies how far the paper is to be spaced. Holes 
punched in each channel of the format tape signify the next paper position. 
The channel is selected by placing a three-bit code in AC bits 15-17, and 
giving an instruction to space paper. The spacing flag becomes a 1 when 
the spacing action is complete. À recommended control tape has the 
following characteristics, where the middle column indicates the number 
of lines between successive holes in the channel: 


Channel Spacing Time 
O 1 line 16 ms 
1 2 lines <2 X 16 ms 
2 3 lines «3 x 16 ms 
3 6 lines <6 X 16 ms 
4 11 fines (1/6 page) <11 X 16 ms 
5 22 lines (1/3 page) <22 X 16 ms 
6 33 lines (1/2 page) «33 x 16 ms 
7 restores page 520 ms for 66 lines 


The Line Printer printing and spacing instructions, iot series 65 and 66, are: 
losf — 706501 — Skip if the printing flag is a 1. 
locf — 706502 — Clear the printing flag. 
Ipld — 706542 — Load the Printing buffer. 


Ipse — 706506 — Select the Printer. Print the contents of the Printing buffer. 


Clear the printing flag. (The printing flag becomes a 1 at 
the completion of the printing.) 


Issf — 706506 — Skip when the spacing flag becomes a 1. 
Iscf — 706602 — Clear the spacing flag. 


Isis — 706606 — Load the spacing buffer from AC bits 15-17 and select 
spacing. Clear the spacing flag. (The spacing flag becomes 
a 1 when spacing is complete.) 


The printing and spacing flags are connected to the Program Interrupt 
and to the iors instruction bits 15 and 16. 


50 


PROGRAM SEQUENCE 


/sequence to print a line of 120 columns. Output stored 3 


/characters per word. 


/Data begins in register 2000. Sequence assumes printer is 


/in process of printing a line previously assigned. "print" is 


/begin of prog. 


print, 


ldloop, 


lpsf 
Jmp .-1 
lsls 4 10 


lac (2000-1 
dac 10 
lac(-5044 
dac temp 
lac i 10 
lpid 

isz temp 
jmp ldloop 


lssf 


Jmp space 


lpse 


/wait till previous printing done 


/space 1 line (0 in AC)iot 10 clears 
/AC 

/location of data 

/print table initialize 


/40x3 characters 


/load print buffer loop 


/load from AC 


/test for spacing done before 


/proceeding 


/print activate...end of printing 


/a line 





51 


CHAPTER 4 


THE INTERFACE 
ELECTRICAL CHARACTERISTICS 


As explained in previous sections, the standard Interface contains the 
Real-Time Connection, which can operate only with the Perforated-Tape 
Reader, the Perforated-Tape Punch, and the Printer-Keyboard. The Real- 
Time Option can operate with a variety of external devices over a wide 
range of information handling rates. In this section the location of the 
Real-Time Option, its electrical characteristics, and its connections to 
input-output devices are presented. 


Real-Time Option 


A coordinate system locates modules and connectors in PDP-4 with a 
four-place, alphanumeric code. Bays are numbered 1 and 2, panels are 
lettered alphabetically downward, connectors or modules are numbered 
left to right in the panels (blank spaces included), and terminals are let- 
tered alphabetically downward on the connectors or modules. The Real: 
Time Option is located in panels 2E, 2F, and 2H. Connections to external 
control units are made through a cable connector in positions 2J1-6. 


DEVICE SELECTOR (LOCATION 2F6-25) 


The standard Device Selector contains provisions for up to 20 selector 
modules, each of which is a Pulse Amplifier, Type 4605. The amplifiers 
are pulsed with standard DEC 4000 Series negative logic pulses which 
can drive 18 units of base load. 


Each module is wired to respond to one address code only (see example, 
Figure 29). The 6-bit address portion of the iot instruction will therefor 
pass only through the six-level AND gate of those modules wired to th 
same combination of ones and zeros. The output of the AND gate enable 
three AND gates to pass the common iot 1, 2, and 3 pulses. These pulse 
are available at terminals E, H, and K, respectively, of modules 2F6-25. 


52 


Common IOT 1 ea | = i e debita 


Common IOT 2 | ous. | - > PA | IOT 1 


Common IOT 3 m 1 
| OAM | | y Selected 
MBe , vo—bl- > IOT 2. 
Y Lal | | 
0 AP M Selected 
st s IOT 3 


= 
œ 
~J 
dv 
o 
y 
"U 
z 


Figure 29-Typical Pulse Amplifier, Type 4605, used in 
PDP-4 Device Selector. Example shown is wired to pass 
the iot address 001101. The six-level AND gate will pass 
only that address if it is present in the instruction word 
from the Memory Buffer, thus enabling three AND gates 
to pass three 10 pulses to the pulse amplifier. 


The Device Selector modules are delivered with jumpers across the address 
terminals. The user can remove appropriate jumpers to establish the 
module select mode according to the table below. 


Instruction ZERO Input ONE Input 
Word Bit Terminal Terminal 


6 
7 
8 
9 
10 
11 


<scoøovz 
NxX<HDZ 


INFORMATION COLLECTOR (LOCATION 2H8-25) 


The information collecting sequence begins with an iot pulse from the 
Device Selector applied to the strobe input of the Information Collector. 
The IC then ANDs with the input device information present level and the 
results are transmitted to the AC. The results of the AND functions are 
mixed, or ORed together, to enable eight 18-bit-word devices to read data 
into the AC. Two or more devices requiring less than 18 bits could share 
a word, provided their bit-position requirements did not conflict. In such 
cases, more than eight input devices could be handled by the IC. The 
incoming information signal polarities are: 


O volts O bit transmitted to AC 
— 3 volts | 1 bit transmitted to AC 


The IC consists of 18 modules, one for each bit of the word, starting with 
bit O in module 2H8. All eight input channels are wired to each module. 
The convention for designating bits is IC; x, where j specifies the bit number 
and k the channel number. The eight input-level terminals and associated 
iot-pulse terminals are: 


Channel Data-Bit Associated 
(k) input iot Input 
F 


NO O1 B Y N HO 
<scnzxxnm 
NX<4Z2r — 


INFORMATION DISTRIBUTOR (LOCATION 2H1-3) 


The Information Distributor presents the static data contained in the AC 
to an output device when the Device Selector commands the device to 
sample the ID. The signal polarities are: 


—3 volts AC bit contains a 0 
O volts AC bit contains a 1 


Eight groups of 18 outputs are available in the ID. The module driving the 
output bus is a Type 1690 or 1685 Bus Driver supplying up to 15 ma at 
O or —3 volts. All eight groups must share the bus. 


Connections to the ID are made at three taper-pin terminal blocks, 2H1, 
2H2, 2H3. Each block has 3 columns of 20 terminals each. Each column 
represents a group; the first 18 terminals (A-U) in the column represent 
AC bits 0-17 and the last two (V, W) the bipolar bit 12 in the Memory Buffer. 
V and W may be used to select a subdevice. The terminals are tied together 
horizontally to form 20 rows. 


54 


INPUT-OUTPUT SKIP FACILITY (LOCATION 2H06) 


There are 8 inputs to Input-Output Skip. The iot pulses from the Device 
Selector strobe an input line and if a logic condition is present, the instruc- 
tion following the iot will be skipped. The conditions for skipping are: 


—3 volts skip 
O volts do not skip 
The ¡ot skip pulse must occur at event time 1 of the ¡ot instruction. 


The IOS consists of a Capacitor-Diode Gate, Type 4129. The input con- 
nections are: 


10 Device Device Selector 
Input Connection Pulse Connection 
F E 
J H 
L K 
N M 
T S 
V U 
X W 
Z Y 


PROGRAM INTERRUPT CONTROL (LOCATION 2HO5) 


Eleven Program Interrupt lines are available. Any one of the 11 signals 
may cause an interruption of a program. All signals are identical; the 
polarities are: 
—3 volts interrupt the program 
O volts no effect 


The connections from 10 devices which request program interrupt are 
made to module 2HO5 at pins E, F, H, J, S, T, U, W, X, Y, and Z. 


DATA INTERRUPT CONTROL (LOCATION 2E13) 


The signal levels associated with the DI are shown in Figure 30. In trans- 
ferring data, the Memory Address is first transmitted to the Memory 
Address Register on 13 lines from the external source. Data is next trans- 
ferred to or from the MB on 18 + 18 lines. 


Incoming data is received from 18 lines and placed in the Memory Buffer 
and on into Memory. 


Outgoing data from the Core Memory addressed is transferred to the 
Memory Buffer and appears on 18 lines for sampling by the IO device. 


55 








18 Datalines à 
(3 Volts=0,0 Volts=1) — 





À DATA 
^ f INTERRUPT 
{ CONTROL 










DONE 


















^. .. Minimum Maximum 
 Acknowledgment — ^ . . TimeTo Avoid - 
(5. Time Another Interrupt 





B Address Accepted | . —— 
» e 2.0 Sac ` 





Figure 30 — Data Interrupt Control signals and timing 


56 


MNEMONIC 


CODE 
cal Y 


dac Y 


jms Y 


dzm Y 
lac Y 
xor Y 
add Y 


tad Y - 


xct Y 


isz Y 


and Y 
sad Y 


jmp Y 
law N 


APPENDIX 1 


Instruction Lists 


MEMORY REFERENCE INSTRUCTIONS 


OCTAL 


CODE 
00 


04 
10 


14 
20 
24 
30 
34 
40 
44 


50 
54 


60 
76 


TIME 
(usec) 


16 


16 
16 


16 
16 
16 
16 
16 
8+ 
16 


16 
16 


OPERATION 


Call Subroutine. Y is ignored 
jms 20 if bit 4 = 0, jms i 20 if bit 4 = 1. 


Deposit AC. C(AC) => C(Y) 


Jump to subroutine. C(PC) => C(Ys_17), 
C(L) 2» C(Y;), Y + 1 => CCPC) 


Deposit zero in memory. O => C(Y) 

Load AC. C(Y) => C(AC) 

Exclusive OR. C(AC) V C(Y) => C(AC) 

Add (1's complement). C(AC) + C(Y) => C(AC) 
2's complement add. C(AC) + C(Y) => C(AC) 
Execute. 


Index and skip if O. C(Y) + 1 => C(Y), if 
C(Y) + 1 = 0, then C(PC) + 1 => C(PC) 


AND. C(AC) À C(Y) => C(AC) 


Skip if AC and Y differ. If C(AC) = C(Y), then 
C(PC) + 1 => C(PC) 


Jump. Y => C(PC) 


Load AC with law N. 1 => C(AC,..), 
N => C(AC:.15) 


57 


MNEMONIC 


CODE 
opr 
nop 
cma 
cml 


oas 


las 


ral 


rcl 


rtl 


rar 


rcr 


rtr 


hit 
sza 


sna 


spa 
sma 
szi 
snl 
skp 
cil 
stl 
cla 
cle 
glk 


OCTAL 
CODE 


740000 
740000 
740001 
740002 
740004 


750004 


740010 


744010 
742010 


740020 


744020 
742020 


740040 
740200 
741200 


741100 
740100 
741400 
740400 
741000 
744000 
744002 
750000 
750001 
750020 


EVENT 
TIME 


219 


2, 3 
2:9 


25:3 
2; 3 


m 


N N NM NB N Ro Ra nm eK 
QJ 


Ww C9 


OPERATE INSTRUCTIONS 


| OPERATION 
Operate. 
No Operation. 
Complement, C(AC) => C(AC) 
Complement Link, C(L) => CL) 


Inclusive OR AC Switches. 
C(ACS) V C(AC) => C(AC) 


Load AC from Switches. 
C(ACS) => C(AC) 


Rotate AC + Link left one place. 
C(AC ;) => C(AC;_1), C(L) =>C(ACi7), 
C(AC,) => C(L) 


Clear Link, then ral. 0 => C(L), then ral 


Rotate AC left twice. Same as two ral 
instructions 


Rotate AC + Link right one place. 
C(AC ;) => C(AC j+1), C(L) => C(ACo), 
C(ACi7) => C(L) 


Clear Link, then rar. O => C(L), then rar 


Rotate AC right twice. Same as two rar 
instructions 


Halt. 0 => RUN 
Skip on zero AC. Skip if C(AC) — positive zero 


Skip on non-zero AC. Skip if C(AC) + 
positive zero 


Skip on positive AC. Skip if C(AC:) = 0 
Skip on negative AC. Skip if C(ACo) = 1 
Skip on zero Link. Skip if C(L) = O 

Skip on non-zero Link. Skip if C(L) = 1 
Skip, unconditional. Always skip 

Clear Link. O => C(L) 

Set the Link. 1 => L 

Clear AC. O => C(AC) 

Clear and Complement AC. —0 => C(AC) 
Get Link. O => C(AC), C(L) => C(AC::) 


58 


MNEMONIC 
CODE 


iof 
ion 


iors 


clsf 
clof 
clon 


rsf 
rsa 
rsb 
rrb 


psf 


pls 
pcf 


ksf 
krb 


tsf 
tls 
tcf 


dsf 
dis 
dcf 


dsf 
dcf 
dxl 
dxs 
dyl 
dys 
dib 


BASIC IOT INSTRUCTIONS 


OCTAL 
CODE 


700002 
700042 


700314 


700001 
700004 
700044 


700101 
700104 
700144 
700112 


700201 
700206 
700202 


OPERATION 


Interrupt 


turn off interrupt 
turn on interrupt 


10 Equipment 
read status of io equipment 


Clock 
skip if clock flag is 1 
turn off clock, clear clock flag 
turn on clock, clear clock flag 


Paper tape reader 
skip if reader flag is a 1 
select reader for alphanumeric, clear reader flag 
select reader for bry, clear reader flag 
read the reader buffer into AC, clear reader flag 


Paper tape punch 
skip if punch flag isa 1 
load punch buffer and select punch, clear punch flag 
clear punch flag 


Keyboard input from teleprinter 


700301 
700312 


700401 
700406 
700402 


700501 
700506 
700502 


700501 
700601 
700506 
700546 
700606 
700646 
700706 


skip if keyboard flag is a I 
read the beyboard buffer into the AC, 
clear keyboard flag 


Teleprinter 


skip if teleprinter flag is a 1 
load teleprinter buffer and select, clear teleprinter flag 
clear the teleprinter flag 


Display type 30A 
skip if display flag is a 1 
load display buffer and select, clear display flag 
clear display flag 


Display type 30D 
skip if display flag is a 1 (light pen) 
clear display flag 
load x co-ordinate 
load x co-ordinate and select 
load y co-ordinate 
load y co-ordinate and select 
load brightness register 


59 


MNEMONIC 
CODE 


mci 
mrs 
mli 
msc 
msi 
msf 
mri 


crsf 
crsa 
crsb 


crrb 


cpsf 
cpse 
cplr 

cpcf 


ipsf 
Ipcf 
Ipld 
Ipse 
Issf 

Iscf 
Isis 


BASIC IOT INSTRUCTIONS 


OCTAL 
CODE 


707001 
707012 
707005 
707101 
707201 
707301 
707112 


707202 
707302 


707104 
707204 
707304 


706701 
706704 
706744 
706712 


706401 
706444 
706406 
706442 


706501 
706502 
706542 
706506 
706601 
706602 
706606 


(continued) 


OPERATION 


Magnetic tape type 54 

clear tape instruction and character buffer 
read tape status into AC 

load instruction buffer 

skip if character is present for reading 
clear interrupt flag and select interrupt 
skip if the tape flag is a 1 (end of record) 
clear AC, read character buffer into AC left 
clear character buffer 

read character buffer into AC middle 

clear character buffer 

read character buffer into AC right 

clear character buffer 
write a character from AC left 
write a character from AC middle 
write a character from AC right 


Card reader 
skip if reader character flag is a 1 
select card reader for alphanumeric 
select card reader for binary 
read card column buffer into AC 


Card punch 
skip if the card punch flag is a 1 
select a card, set card punch flag 
load row buffer, clear punch flag 
clear punch flag 


Line printer 
skip if printing flag isa 1 
clear printing flag 
load the printing buffer 
select printing, clear printing flag 
skip if spacing flag is a 1 
clear spacing flag 
load spacing buffer and select spacing, 
clear spacing flag 


60 


WONAMAPWNHRONK KES CFTHNVNODCIOD ZT RR T0 + Q NT 
VV AD><ÜÙ $ D n N-XxXE«cCcALUomIoOuozzrmxe—-e-rtaommuoouo 


61 
62 
63 
64 
65 
66 
67 


71 
41 
42 
43 
44 
45 
46 
47 
90 
51 
22 
23 
24 
25 
26 
27 
30 
31 
20 
Ol 
02 
03 
04 
05 
06 
07 
10 
11 


[p + x O 


EN pot 


APPENDIX 2 


Low order 
bits 


0000 
0001 
0010 
0011 
0100 
0101 
0110 
0111 
1000 
1001 
1010 
1011 
1100 
1101 
1110 


1111 


21 
33 
73 
54 
55 
57 
40 
56 


Codes 


FIO-DEC CODE 


00 


o 
D 
~ & 
Me] 
(D 


~ 


WON AUP WYP 


61 


High order bits 


O1 


N<xXEZ<C TO 
N<xs<c-g+ov| 


black 
red 
tab 


stop code 
lower case 
upper case 
black 

red 

tab 

backspace 
carriage return 
space 


10 


SOTO OS 


"iss 
) ]  backspace 
| 


( 


L 


DOUVOZEM RO 


13 
72 
74 
34 
35 
36 
75 
77 
00 


11 


—=:300 +0 000 
T”TXØTIMOOUWUP> 


lower case 
X 
upper case 


car ret 


code delete punches seventh channel 


TELETYPE CODE 


High order bits 


00 O1 10 11 
Low order | 

bits 
000 line feed E 3 A — 
001 T 5 L ) ZT W 2 
010 car ret R 4 D $ J ! 
011 O 9 G & B ? figures 
100 space | 8 S bell U 7 
101 H # PO Y 6 Q 1 
110 N, C F ! K ( 
111 M. V ; X / letters 
letters 37 figures 33 
A 30 0 15 
B 23 1 35 
C 16 2 31 
D 22 3 20 
E 20 4 12 
F 26 5 01 
G 13 6 25 
H 05 7 34 
| 14 8 14 
J 32 9 03 
K 36 ( 36 
L 11 ) 11 
M 07 ! 07 
N 06 ; 06 
O 03 - 30 
P 15 ? 23 
Q 35 | 16 
R 12 $ 22 
S 24 bell 24 
T O1 & 13 
U 34 Å 05 
V 17 | 32 
W 31 17 
X 27 / 27 
Y 25 | 26 
Z 21 a 21 
space 04 carriage return 02 
line feed 10 


62 


CARD READER CODE 


High order bits 
61 00 01 10 11 
62 Low order 
63 bits 


65 0000 blank — 
67 0001 


ho 


71 0010 
42 0011 
44 0100 
46 0101 
50 0110 
22 0111 
24 1000 


N < xXx g < cc 1 o — 
D O U O z z 
"rl 


26 1001 


O © OO N M OC! P» € N 


30 1010 
12 1011 ; $ 


02 1100 ' t9] € [96] : ) LOJ 


| 
= 
LJ 


05 HOLLERITH CARD CODE 






no zone 12 11 






blank 


rA 
Ro 
L i 


40 no punch 


l| ^" |4- 90 «X400» 0oNv—ON-»xXz«cHOmoOUuOozzmrxce-—-rommoou» 
N 
WwW 


£9 ~ 
al 
C2 


HKN NS 

w 

A 
— Ir0mmocogm». 
M-«xz«cado-o jo 


st 

NI 

p 
| WOON A ORWNH (n2 


*4 ZO VOZZEF AC | 


a 


pa 
A 
Qo Q9 10 00 - OY O1 4 Q0 I 5 


RA 


[76] 


PT cS 


#] 
blank OO Q ] ) SETS 


63 


[O | PPA><US 7 °OHNHHBUNARONKXE<CANTOTOZETAT TOHAMGOWS 


LINE PRINTER CODE 


space 00 


= 


SS ee 


60 
32 
33 
34 
35 
36 
37 
72 
73 
74 
75 
77 
76 


Low order 
bits 


0000 
0001 
0010 
0011 
0100 
0101 
0110 
0111 
1000 
1001 
1010 
1011 
1100 
1101 
1110 
1111 


64 


00 


space 


UV 0 nN MM 0 Pp W N 


D 


S 


A > < U 


High order bits 


01 


O 
/ 
S 
T 
U 
V 
W 
X 
Y 
Z 


# 


10 


A Xx O TD OZ ET zx & 


il 


11 


m O o > 


I oO mn 


APPENDIX 3 


Read-In Mode Sequence 


The initial data input to PDP-4 is made using the keys and switches on the 
Operator Console. Å small program read in manually can be used to read 
in a somewhat larger program from perforated tape. An example of such 
a routine is given below. It can also be used to read in other programs from 
perforated tape. 


READ-IN LOADER 


The purpose of the read-in loader is to load programs punched in "read-in 
mode," such as the block format loader described below. The read-in 
loader must be loaded by means of the console toggle switches. It loads 
tapes of the following format: 


dacA 
c(A) 
dac B 
c(B) 


jmp Y 

dummy word 
Read-in mode tapes consist of word pairs giving a dac into an address, 
followed by the contents of that address. They are terminated by a jmp to 
the program followed by a dummy word (e.g., 0). 


To load a read-in mode tape, place the tape in the reader, set the ADDRESS 
switches to 7770, and press START. 


LOCATION OCTAL CODE MNEMONIC REMARKS 
7762/ 0 r, O /read one binary word 
7763/ 700101 rsf 
7764/ 607763 jnp.— 1  /wait for word to come in 
7765/ 700112 rrb /read buffer 
7766/ 700144 rsb /read another word 
7767] 627762 jmp i r /exit subroutine 
7770/ 700144 go, rsb /enter here, start reader going 
7771/ 107762 g, jmsr /get next binary word 
7772/ 47775 dac out 
7773/ 407775 xct out /execute control word 
7774/ 107762 jms r /get data word 
7775/ 0 out, /store data word 
7776/ 607771 jmp g /continue 


65 


BLOCK FORMAT LOADER 


The block format loader will read a block format binary tape of the following 
format: 


dac À A is the address of the first data word 

—N /complement of number of data words in block 
N data words /data words 

Check sum /sum of every word in block, except check sum 


The routine occupies register 7737 to 7761, and uses the read-in loader 
subroutine to read each binary word. Upon completing a block, the com- 
puted check sum is compared with the read check sum and the loader 
halts if these differ. The block may be re-read by pulling the tape back to 
the beginning of the block and pressing the CONTINUE switch on the 
console. 


LOCATION MNEMONIC REMARKS 
7737! rsb 

a, imsr /block format loader 
dac s 
xct s 
dac cks 
jms r 
dac out 

b, add cks /loop 
dac cks 
jmsr 
isz out /check count, last word read is check sum 
jmp s 
sad cks 
jmp a /sum checks, continue 
hit /stop on check sum error 
impa- 1 /out 

S, XX 
ISZ S 
jmp b 
cks = 7777 


66 


APPENDIX 4 
PDP-4 Assembly Program 


The more important characteristics of the PDP-4 Assembly Program are 
mentioned briefly here to provide the background necessary to understand 
the programming examples in this manual. The program and its complete 
description are furnished to purchasers of PDP-4. 


CHARACTER SET: The character set includes digits O through 9, letters 
a through z, and the following punctuation characters: 


Punctation Characters Meaning 

+ plus add values 

— minus subtract values 

Å space add values 

A and combine values by logical AND 
V or combine values by inclusive OR 
( left parenthesis enclose constant word 

) fright parenthesis enclose constant word 

. period has value of current address 

, comma assign address tag 

= equals sign assign symbol on left of = 

/ slash begin comments; set current address 
D carriage return termination character 

— tab termination character 

— overbar variable indicator 


The characters A , ), and — are nonprinting. 


NUMBERS: Any sequence of digits delimited on the left and right by a 
punctuation character. 


SYMBOLS: Any sequence of alphanumeric characters, the first of which 
must be a letter. Symbols are identified by the first six characters only. 


‘Value symbols’ are those symbols which have a numerical value assigned 
to them, either in the permanent symbol table, or during assembly. Value 
symbols may be assigned by the use of a comma, indicating the symbol 
to the left of the comma is an address tag; or by an equals sign, indicating 
the symbol to the left of the equals sign is to be assigned the value of the 
word to the right of the equals sign. | 


Example: a, dzm 100 
b= —] 
c=a+b 


67 


SYLLABLES: A syllable can take several forms. It can be a value symbol, 
a period (.), a flexowriter input pseudo-instruction (flex or char), or a 
constant (a word enclosed in parentheses). 


Examples: | 
al 
100 
1z2 
flex abc 
flex now 
(add a+ 1) 
lac 
abcdef 


WORDS: A word is a string of syllables connected by the arithmetic opera- 
tors plus, minus, space, AND or OR, delimited on the left by tab, carriage 
return, left parenthesis, or equals sign, and on the right by a tab or car- 
riage return. A word may be a single number or symbol so delimited, or a 
string of symbols connected by the operators. If the word is delimited on 
the left by an equals sign then the symbol to the left of the equals sign is 
assigned a value equal to that of the word. Otherwise, the word is a storage 
word and will become part of the binary version of the program being 
assembled. The arithmetic operators, plus and space both mean add, 
while the operator minus means subtract. 


Examples: 
sad K 32 


laca y) 

1000 — 20%) 

add b+2,) 

jmp .— 2y) 

a+b-c- 2» 

lac (add a 4- 1). 
THE CHARACTER SLASH ( / ): The slash has two meanings. lf immediately 
preceded by a tab or carriage return then slash initiates a comment, which 
is terminated by the next tab or carriage return. If slash is preceded by a 
word, then the address part of the word indicates the address into which 
the next instruction or data word wil! go. Normally, the first instruction or 
data word goes into register 22 and succeeding instructions or data words 
into succeeding registers. If the programmer wishes to break this sequence 
or wishes to start translating into some register other than 22, then a 
slash may be used to set the new address. 


INDIRECT ADDRESSING: Indirect addressing is indicated by the symbol, i 
which has the value 20000. 


Example: lac i abc 


THE CHARACTER PERIOD (..): The period (. ) hasas its value the current 
address. 
Example: dac.is equivalent to 
a, dac a 


68 


PSEUDO INSTRUCTIONS 


FLEXOWRITER INPUT PSEUDO INSTRUCTIONS: The pseudo-instruction, 
flex AaBy causes the (six-bit) FIO-DEC codes for the three characters follow- 
ing the space (A) to be read into one word which is taken as the value of 
the syllable. The code for the character a will go into bits 0-5 of the word, 
for 8 into bits 6-11, and for y into bits 12-17. The code is a six-bit character, 
the first five of which are the FIO-DEC code, the sixth a 1 for upper case 
or a O for lower case. 
Example: flex À boy 


The pseudo-instruction, char AZy causes the (six-bit) FIO-DEC character, 
y to be assembled into the left, middle, or right six bits of the word, de- 
pending on whether Z is r, m, or l. 


Example: char rO 
char m( 
char la 


CONSTANTS: The MACRO assembly system has available a facility by which 
the program constants may be automatically stored. A constant must follow 
the rules for a word and is delimited on the left by a left parenthesis. The 
right delimiter may be a right parenthesis, carriage return, or tab. The 
value of the syllable, (o) is the address of the register containing o. The 
constant a will be stored in a constants block at the end of the program, and 
the address of o will replace (o). 


Examples of the use of constants: 
add (1)45 
lac (add z 1)%) 
lac (— 760000)%) 
lac (flexo abc),) 


START: The pseudo-instruction, start indicates the end of the English tape. 
Instruction, start A must be followed by a carriage return. “A” is the ad- 
dress at which execution of the program is to begin, and causes a jmp A 
instruction punched at the end of the binary tape on pass two. 


DECIMAL: The pseudo-instruction, decimal indicates all numbers are to be 
considered decimal. 


OCTAL: The pseudo-instruction, octal indicates all numbers are to be 
considered octal. 


69 


APPENDIX 5 
Multiply and Divide Subroutines 


MULTIPLY SUBROUTINE 


/PDP-4 ones complement single precision multiplication subroutine 
/calling sequence: /lac multiplier 

/jms mult 

/lac multiplicand 

/return; low order product in AC, high order product in mp5 
/time = 2.6 msec. for non-zero cases, approximately 100 microsec. for zero. 


mult, 0 
dzm mp5 
sna 
jmp mpz 
spa + cll — opr 
cma + cml — opr 
dac mpl 
xct j mult 
sna 
jmp mpz 
spa 
cma 4- cml — opr 
dac mp2 
lac (360000 
ral 
dac mpsign 
lac (—21 
dac mp3 


mp4, lac mpl 
rar 
dac mpl 
lac mp5 
spl 4- cll — opr 
tad mp2 
rar 
dac mp5 
isz mp3 
imp mp4 


mpsign, O 
dac mp5 
lac mpl 
rar 
xct mpsign 


mpz, isz mult 
jmp i mult 


start 


70 


DIVIDE SUBROUTINE 


/PDP-4 ones complement divide subroutine 
/calling sequence: /lac high order dividend 


/jms divide 

/lac low order dividend 

/lac divisor 

/return; quot. in AC, rem. in dvd. if high dividend is 


/greater than divisor, no divide takes place and L=>1. Time = 3.1 ms 


divide, 


dv5, 


dv4, 


dv3, 


0 

spa + cll — opr 
cma + cml — opr 
dac dvd 

xct i divide 

spl 

cma 

dac quo 

jms dv5 


O /remainder has sign of dividend 
isz divide 

xct i divide 

sma +-cml — opr 

cma + cml — opr 

jms dv4 


0 

cll 

tad (1 
dac dvs 
tad dvd 
isz divide 
spl 

jmp i divide 
lac (—22 
dac dv1 
jmp dv2 


lac dvd 
ral 

dac dvd 
tad dvs 
spi 
dac dvd 


71 


dv2, 


start 


DIVIDE SUBROUTINE 


(continued) 


lac quo 
ral 

dac quo 
isz dvl 
jmp dv3 


lac dv5 

ral 

lac dvd 

spl 

cma 

dac dvd 

lac dv4 

ral 

lac quo 

spl 

cma + cll — opr 
jmp i divide 


72 


APPENDIX 6 
Programming Aids 


The following programming aids are supplied with the PDP-4. 


PDP-4 ASSEMBLY PROGRAM—A one-pass assembler which allows 
mnemonic symbols to be used for addresses and instructions. Constants 
are automatically assigned. Text statements may be written for printing 
at run time, and a decimal mode may be specified. Up to six character 
symbols may be used, and the symbol table may be punched on paper 
tape for use with the debugging tape below. 


DDT-4 DEBUGGING TAPE — Provides communication with a program 
via the on-line typewriter. Registers may be examined (using mnemonic 
codes) and modified. Communication is entirely in symbolic language. 
Programs may have break points inserted and then run under DDT-4 
control, similar to a tracing routine. A program may be searched for par- 
ticular words. 


DOUBLE-PRECISION FLOATING POINT PACKAGE — Provides floating- 
point arithmetic with a 36-bit mantissa and 18-bit exponent. The routines 
include plus, minus, divide, multiply, fix-to-float, and float-to-fix, with 
decimal input and output. 


MAINTENANCE ROUTINES — There are five maintenance routines. These 
tests are also used as DEC’s standard acceptance test routines. 


(a) CONTEST (CONtinuous TEST) — Verifies that all machine functions 
are performing properly. Each instruction is tested, a core checker- 
board pattern is run, a tape is punched and read, and a message 
is typed. The test then repeats itself. 


(b) INSTEP (INStruction TEst Programs) — Test all machine instruc- 
tions under various modes. 


(c) Checkerboard Program — Provides continuous memory testing 
with four different patterns. 


(d) Reader and Punch Test — Checks the start time of the reader and 
checks the reader using different patterns and variable times. The 
punch is tested by providing tapes for the reader test. 


(e) Teleprinter Test. 
TAPE REPRODUCER — Reproduces tape using the Interrupt Mode. 


PUNCH ROUTINES — Allow punching in either block format or read-in 
mode format. 


73 


OCTAL DEBUG — A simple debugging routine. 


MISCELLANEOUS INPUT-OUTPUT ROUTINES —Octal, decimal, double 
precision input and output and special Teletype conversion routines. 


DEMONSTRATION PROGRAMS — Included are: Three Point Display 
(Tri-Pos), Pen Follow, Type-in Character Display, and Character Punch. 


FLOATING POINT FUNCTIONS — Allows various functions to be computed, 
such as double precision sine, cosine, tangent, exponents, log base e, 
and square root. Inquire at DEC for the completion date of these sub- 
routines. 


ALGEBRAIC COMPILER — Inquire at DEC for the completion date of this 
FORTRAN compiler. 


74 


AN — 


co 


17 

35 

70 
140 
281 
562 
125 
251 
503 
007 
014 
028 
057 


230 
460 
921 


899 
799 
599 
199 
398 
797 
594 
188 
376 
752 
504 


606 


hn —- 


16 
32 


131 
262 
524 
048 
097 
194 
388 
777 
554 
108 
217 
435 
870 
741 
483 
967 
934 
869 
738 
476 
953 
906 
813 
627 
239 
511 
022 
044 
088 
177 
355 
710 
421 
842 
985 
370 


481 
963 
927 
855 
711 
423 
846 


144 
288 


3 


GONG qyYN-— © 


APPENDIX 7 


Powers Of Two 


ND 
i 
3 


OO DO O 
GD ON Ch 
— BS ON 


OoOoOoOooooooooooooooooooooooooooooooooooooooooooooooooooooooooorc- 


,000 


25 
125 


562 


25 

625 
312 
156 
578 
789 
394 
697 
348 
674 
837 
418 
209 
604 
802 
901 
450 
725 


931 
465 
232 
116 


25 

625 
312 
656 
808 
914 
957 
478 
739 
869 
934 
467 
733 


183 
091 
545 
772 
886 
443 
721 
860 


715 
357 
678 
839 
419 
209 
604 
302 
151 
575 
787 
893 


723 
361 


062 


5 


125 
062 
531 
765 
882 
941 
970 
485 
242 
621 
810 
905 
452 
726 


171 
590 
215 
647 


411 
205 


25 
625 
812 


703 
351 
675 
337 
668 
334 
667 


166 
513 
791 
395 
697 


924 
962 


125 
562 
781 
890 
945 
472 
236 
668 
834 
417 
708 
854 
927 
963 
481 
240 


625 
312 
656 
328 
164 
582 
041 
520 
260 
130 
565 
782 
891 


125 
062 
031 
015 
507 
253 
126 
063 
531 
265 


5 

25 

625 

812 5 
906 . 25 

953 125 

476 562 5 
738 281 25 
869 140 625 





DIGITAL EQUIPMENT CORPORATION + MAYNARD, MASSACHUSETTS 


F.45 Printed in U.S.A. 2M—10/63