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United States Patent [i9] 

Miller 



[11] 4,069,478 

[45] Jan. 17, 1978 



[54] BINARY TO BINARY CODED DECIMAL 
CONVERTER 

[75] Inventor: Anthony J. Miller, Bethesda, Md. 

[73] Assignee: The United States of America as 

represented by the Administrator of 
the National Aeronautics and Space 
Administration, Washington, D.C. 

[21] Appl. No.: 631,341 

[22] Filed: Nov. 12, 1975 

[51] Int. C1.2 H03K 13/24 

[52] U.S. a 340/347 DD 

[58] Field of Search 235/155; 340/347 DD 

[56] References Cited 

U.S. PATENT DOCUMENTS 

3,026,034 3/1962 Couleur 235/155 

3,257,547 6/1966 Bernstein 235/155 

3,564,225 2/1971 Watson 235/155 

3,943,350 3/1976 Lanning 235/155 

FOREIGN PATENT DOCUMENTS 

921,330 3/1963 United Kingdom 235/155 



Primary Examiner— Chaxles D. Miller 

Attorney, Agent, or Firm — John R. Tresansky; Ronald F. 

Sandler; John R. Manning 



[57] 



ABSTRACT 



A binary coded input signal is converted to a binary 
coded decimal signal having N decades by employing N 
four bit shift registers. The bits of the input signal are 
sequentially supplied, in order, to the least significant 
position of the register for the units decade, with the 
most significant bit of the input signal being applied to 
the units register first. Each of the registers includes a 
right shift-parallel load mode control input terminal. In 
response to the sum of the values stored in each register 
and the binary value 0011 being less than the binary 
value 1000, the mode control input terminal is activated 
to shift the register contents one bit to the right. In 
response to the sum being greater than 1000, the mode 
control input terminal is activated to load the sum into 
the register. A binary one is loaded into the least signifi- 
cant bit position of the register for the adjacent higher 
decade in responise to the sum being greater than 1000. 

7 Claims, 2 Drawing Figures 



14 



I 



CLOCK 



'^ 



\ 



32 BIT 
BINARY WORD 



32 BIT SHIFT 
REGISTER 

7 



1 



SHIFT H^ II 

CLOCK 



15 



X 



START 



18 



b 



0-13 



MSB 

L0^7\ s""^ 
CLOCK 
16 



4 BIT 
REG. 



7f 



^CLEAR 



KXXJMTER 
(4) 



\ 



IL 



LOAD 



f\ 



MODE 
CONTROL 



f^ 



LOCK 



V 



U.S. Patent 



Jan. 17, 1978 



4,069,478 



14 



L 



CLOCK 



. ^. 32 BIT SHIFT mor 
' ^ REGISTER ^^^ 

' ^ f /% «;hift 



32 BIT 
BINARY WORD 



\ 



SHIFT 



I 



CLOCK 



15 



16 



X 



START 



^^■ 



0-13 



4 BIT 
"71 REG. 



CLOCK 



18. ^CLE AR 

-i_r 



COUNTER 
(4) 



LOAD 



FIGl 



f^MODE TS 
CONTROL 



CLOCK 



M7 



FROM 
COUNTER 18 



2! 



\ 

Ao Bo Co Do 

imThh 

lb 8 3 I 16 4 7 li 



13 FULL ADDER 7483 
9 6 2 15 



-25 



22 



X 



Aj B| C| D| 

1111 





ri- 



fO 8 3 \ 16 4 7 11 
13 FULL ADDER 7483 
9 6 2 15 



26 

J. 



SERIAL BINARY (— *K 

WITH FOUR ,r-*-*ll 
LEADING^'ZEROS" 
MSB FIRST 23" 




TO NEXT 
DECADE 



L-S 3 5 6 , 
W 4-BIT SHIFT ' 
REG. 74L95 8 
13 12 10 9 



TTTT 

AqBoCoPo 



REG. 74L95 o 
13 12 10 9 ° 



24' 



mr 

A, B, C| D| 



FROM 
CLOCK 14 



FIG 2 



4,069,478 

1 2 

conversion from a binary coded signal to a binary coded 

BINARY TO BINARY CODED DECIMAL signal having a base other than the ten's base, the con- 

CONVERTER version can be effected only by replacing each of the 

Tvrv/cxrxTOM ^°^^ networks associated with each register. Such a 

ORIGIN OF THE INVENTION j replacement is necessary because it is necessary to test 

The invention described herein was made by an em- the contents of the register against a different number, 

ployee of the United States Govenmient and may be depending upon the order to which the binary signal is 

manufactured and used by or for the Government for to be converted. 

governmental purposes without the payment of any It is, accordingly, an object of the present invention 

royalties thereon or therefor. 10 to provide a new and improved apparatus for convert- 

ijTET TA oc Txn/cTvTTTr»xT '"8 ^^^^^ ^°'^^^ "^P"* ^'^Hals iuto binary coded output 

FIELD OF INVENTION signals having an order greater than two. 

The present invention relates generally to apparatus It is another object of the invention to provide a new 

for converting a binary coded input signal to an output and improved binary to binary coded decimal converter 

signal having a binary code of base K (where K is 15 whereinthe value of each decade is selectively added to 

greater than 2) and more particularly to such a con- the binary value 0011, depending upon whether the 

verier wherein a register for each of the K orders stores value of the decade is greater than 0100 or less than 

a value equal to the sum of the signal previously stored 0101. 

in the register and a predetermined value in response to A further object of the invention is to provide a new 

the most significant bit of the sum having a binary one 20 and improved binary to binary coded decimal converter 

value. wherein a relatively small amount of hardware is used 

„.^ ,„ XT»T„ ^^ ^,x^ ^»„ ,^»T,x,^^,.T to determine if the signal valve for each decade is equal 

BACKGROUND OF THE INVENTION ^o or greater than 0101, thereby to provide increased 

One known technique for converting a binary coded reliability and ease of troubleshooting, 

signal to an output signal having a binary code of base 25 An additonal object of the invention is to provide a 

K (e.g., for converting a binary coded signal to a binary new and improved apparatus for converting a binary 

coded decimal signal, in which case K = 10) is reported coded input signal to an output signal having a binary 

by John F. Couleur in the December 1958 issue of the code of base K, where K is greater than two, wherein 

IRE Transactions on Electronic Computers, Volume the apparatus is readily adapted to convert the input 

EC-7, No. 7. For conversion into binary coded decimal, 30 signal to output signals of different bases, 

the prior art technique basically involves sequentially DESCRIPTION OF THE INVENTION 
supplymg bits of the bmary coded mput signal to the 

least significant bit position of the lowest order register In accordance with the present invention, a binary 

of a plurality of cascaded four-bit shift registers. The coded input signal is converted to an output signal hav- 

bits are entered in order, with the most significant bit 35 ing a binary code of base K and order N, where K is 

being entered first. After each bit has been entered the greater than two, by adding the binary signal for each 

contents of each register are examined and, prior to the order to a predetermined value and responding to the 

next shift, the binary value 00 11 is added to the register most significant bit resulting from the addition to deter- 

contents. In response to the sum of the register contents mine if the binary signal for the order is to be modified 

and the binary value 001 1 being less than the binary 40 to be equal to the sum of the signal and the predeter- 

value 1000, no change is made in the contents of a par- mined value. In the particular application of converting 

ticular register. However, if the sum of the register a binary code decimal output signal having N decades, 

contents and the binary value 0011 is greater than the N four bit shift registers are provided. The bits of the 

binary value 1000, the binary value 001 1 is added to the binary coded input signal are sequentially supplied in 

register contents. 45 order to the least significant bit position of the units 

One prior art device for implementing the technique decade register, with the most significant bit of the 

disclosed by Couleur is found on page 240 of the Texas input signal being supplied first. Each of the registers is 

Instruments publication entitled "Designing With Inte- provided with a right shift-parallel load mode control 

grated Circuits". This prior art implementation utilizes input terminal or means. A full adder is provided for 

relatively straightforward apparatus for adding the 50 each register and is responsive to the sum of the values 

register contents with the values 0011 or 0000, depend- stored in each of the registers, as well as the binary 

ing upon whether the register contents are greater than value 0011. The full adder activates the mode control 

0100 or less than 0101. In particular, a logic network is input means of its associated register to shift the register 

provided to sense the contents of each register to deter- contents one bit to the right in response to the sum being 

mine if they are greater than 0100 or less than 0101. In 55 less than the binary value 1000. The full adder activates 

response to the register contents being greater than 0100 the mode control input means of its associated register 

the register contents are added to the binary value 001 1 to load the sum of the values stored in its associated 

in a binary adder; the same binary adder adds the regis- register and the binary value 001 1 into the register m 

ter contents to 0000 in response to the register contents response to the sum being greater than the binary value 

being less than 0101. The logic network required for 60 1000. In response to the sum being greater than 1000, a 

each register includes two NAND gates having two binary one is loaded into the least significant bit position 

inputs, one NAND gate having three inputs, and an of the register for the adjacent higher decade, 

inverter.. Hence, the prior art device uses a relatively The determination as to whether the sum of the val- 

large number of components to test the value of each ues stored in each of the registers and the binary value 

register. The large number of components has a ten- 65 001 1 is less than 1000 is made merely by examining the 

dency to reduce the reliability of the device, as well as most significant bit value of the full adder output, 

making the device somewhat difficult to construct and thereby obviating the need for a logic circuit including 

troubleshoot. Further, if it is desirable to perform a several AND gates and an inverter at the input of the 



4,069,478 



adder, as in one of the prior art configurations. Thereby, 
there is a considerable reduction in the hardware re- 
quired for the present invention; the hardware reduc- 
tion resuhs in lower cost, greater reliabUity, and ease in 
troubleshooting. Further, by testing the most significant 5 
bit position of the output of the adder, rather than test- 
ing the register contents to determine if they are greater 
than 0100, the present apparatus is capable of being 
easily modified so that it can convert a binary coded 
signal into a binary coded output signal having any 10 
desired order greater than two. 

In accordance with a further feature of the invention, 
a binary zero is initially loaded into each position of 
each shift register in a relatively short time interval, 
without requiring the power associated with simulta- 15 
neously loading a zero into all of the register stages 
simultaneously. In particular, a binary zero is loaded 
into the first position or stage of each register while four 
clock pulses are being supplied in parallel to the regis- 
ters and the mode control input means of each register 20 
is activated to the right shift state. To enable the regis- 
ters of all but the units order to be so initially activated, 
an AND gate is connected to be responsive to a mode 
control source to supply a binary zero to a mode control 
input of order M to a shift input terminal of the register 25 
for order M+1. The same AND gate is responsive to a 
binary one input from the mode control source while 
the conversion operation is being performed, to selec- 
tively supply binary ones and zeros to the mode control 
input terminal of the register for order M and the shift 30 
input terminal of the register for order M+1. To enable 
the units order register to be initially loaded with binary 
zeros, a register is provided between a serial source of 
the binary signal to be decoded; the register injects four 
binary zeros into the binary coded signal to be encoded 35 
prior to the most significant bit being supplied to the 
shift input of the units register. 

It is an additional object of the invention to provide a 
binary to binary coded decimal converter wherein the 
same gate is utilized to control shifting and addition 40 
within a register during a conversion operation and to 
control the initial loading of the registers prior to a 
conversion operation being performed. 

The above and still further objects, features and ad- 
vantages of the present invention will become apparent 45 
upon consideration of the following detailed description 
of one embodiment thereof, especially when taken in 
conjunction with the accompanying drawing. 



BRIEF DESCRIPTION OF THE DRAWING 

FIG. 1 is a block diagram of the converter and its 
input and control mechanism; and 

FIG. 2 is a block diagram of the units and ten stages 
of a binary to binary code decimal converter in accor- 
dance with the invention. 

DETAILED DESCRIPTION OF T^HE DRAWING 

Reference is now made to FIG. 1 of the drawing 
wherein there is illustrated apparatus for converting a 
32-bit binary coded word signal into an 40-bit binary 
coded decimal word signal, i.e., a binary coded decimal 
word having ten decades, each of which includes four 
bits. The 32-bit binary coded word is derived from a 
suitable source, such as a digital computer, and is ap- 
plied to a 32-bit shift register 11, with the most signifi- 
cant bit of the word being applied to the right-most or 
last stage or the shift regiseter and the least significant 
bit being applied to the leftmost stage or zero stage of 



50 



55 



60 



65 



the register. The last stage of register 11 is connected to 
supply an input to the lowest order stage of 4-bit shift 
register 12. Initially, the four stages of register 12 are 
loaded in parallel with binary zeros from a binary zero 
source 13. 

To selectively load the 32-bit binary coded word and 
the four binary zeros into the respective stages of regis- 
ters 11 and 12, both of the registers are provided with a 
load input terminal; the registers are initially loaded in 
response to a binary one being applied to the load input 
terminals thereof. In response to a binary zero being 
applied to the load input terminals of registers 11 and 
12, the registers are not responsive to the signals applied 
to their parallel inputs; instead, registers 11 and 12 are 
shifted in response to sequentially derived pulses de- 
rived from clock source 14, the output of which is ap- 
plied to clock or shift inputs of the registers. In response 
to each clock pulse from source 14, the signals in the 
different stages of registers 11 and 12 are shifted one 
position to the right. Thereby, there is derived from the 
most significant bit stage of register 12 a sequence of 
thirty-six binary bits, with the first four bits invariably 
having a binary zero value, and the remaining thirty- 
two bits being commensurate with the binary bits of the 
binary coded word loaded into register 11. 

To control loading into registers 11 and 12, a start 
signal source 15 is provided. When it is desired to begin 
a new conversion operation, start signal source 15 de- 
rives a binary one output level that subsists for a dura- 
tion equal to the period of one cycle of clock source 14. 
To assure synchronization between the output signal of 
start source 15 and clock source 14, the two sources 
feed AND gate 16, having an output which drives the 
load inputs of registers 11 and 12 in parallel. 

The serial output signal derived from the most signifi- 
cant bit stage of register 12 is supplied to the binary to 
binary coded decimal converter 17 of the present inven- 
tion. Converter 17 includes ten shift registers, each of 
which includes four stages; one of the registers is pro- 
vided for each of the ten decades of the binary coded 
decimal output signal. All of the stages of converter 17 
are cleared to zero while the four initial binary zero 
pulses are derived from registier 12 so that each of the 
stages of converter 17 of all of the registers is loaded 
with a binary zero value prior to the acutal conversion 
process beginning. To this end, counter 18, having a 
maximum count of four, is provided. Counter 18 in- 
cludes a clear input terminal responsive to the output of 
AND gate 16, whereby the counter is reset to zero 
while registers 11 and 12 are initially loaded. Thereaf- 
ter, counter 18 responds to four clock pulses from 
source 14 to derive a binary zero level for a duration 
equal to the period of four cycles of clock source 14. 
Counter 18 derives a binary one during the entire con- 
version interval, and does not return to the binary zero 
state until it is cleared again by the output of AND gate 
16. The output of counter 18 is applied as a mode con- 
trol input to converter 17, whereby the converter is 
loaded while the counter derives a binary zero output; 
the converter performs its desired binary coded decimal 
conversion function while counter 18 derives a binary 
one level. Converter 17 is also responsive to the output 
of clock source 14 so that the binary signal stored in 
each of the ten shift registers is shifted right one position 
within its respective shift register in response to the 
trailing edge of each pulse from clock pulse 14. Con- 
verter 17, upon completion of the conversion operation. 



4,069,478 



derives a 40-bit output word, consisting of ten decades, 
each having four bits. 

Reference is now made in FIG. 2 of the drawing 
wherein there are illustrated the first two decades 21 
and 22 of converter 17, i.e., the units and tens decades of 5 
the thirty two bit decade converter. Each of units and 
tens decade stages 21 and 22 includes a four-bit shift 
register and a four-bit, two word binary full adder; the 
registers for stages 21 and 22 are respectively denomi- 
nated 23 and 24, while the adders of stages 21 and 22 are 10 
respectively denominated with reference numerals 25 
and 26. 

Registers 23 and 24 include four parallel input pins 
14, 2, 3, and 5 for the least to most significant bits, as 
well as output pins 13, 12, 10, and 9 for the least to most 15 
significant output bits; i.e., pins 14 and 13 are provided 
for the least significant bits of the inputs and outputs, 
pins 2 and 12 are provided for the second least signifi- 
cant bits of the inputs and outputs, pins 3 and 10 are 
provided for the third least significant bits of the inputs 20 
and outputs, and pins 5 and 9 are provided for the most 
significant bits outputs of the inputs and outputs. A shift 
or serial input pin 1 is connected in parallel to parallel 
input pin 14; left shift and right shift pins 7 and 8 are 
connected in parallel to each other to be responsive to 25 
clock pulses from source 14. Mode control pin 6 con- 
trols shifting of bits from the least significant bit position 
to the adjacent higher position within the register, or to 
enable signals to be loaded- from the parallel input pins 
14, 2, 3, and 5 of the register to the register stages; the 30 
shifting operation occurs in response to a binary zero 
level on pin 6 during the negative going edge of each 
pulse from clock source 14; the parallel load operation 
is performed in response to a binary one level on pin 6 
during the negative going trailing edge of each pulse 35 
from clock source 14. In one preferred configuration, 
registers 23 and 24 are Texas Instrument 74L95 regis- 
ters. 

Each of adders 25 and 26 includes pins 10, 8, 3, and 1 
responsive to the least to most significant bits of a first 40 
binary word derived from pins 13, 12, 10, and 9 of the 
register for the corresponding decade. Adders 25 and 26 
also include pins 16, 4, 7, and 11 responsive to a second 
four-bit binary word having a constant value, equal to 
0011 for conversion to binary coded decimal. To this 45 
end, pins 16 and 14 are connected together to a binary 
zero source, while pins 7 and 11 are connected together 
to a binary one source. Each of the adders 25 and 26 
includes a grounded, carry input pin 13, as well as four 
output pins 9, 6, 2, and 15 on which are derived the least 50 
to most significant bits of the modulo sixteen sum of the 
two input words fed to the particular adder. In one 
preferred embodiment, adders 25 and 26 are Texas In- 
strument SN7483 four-bit binary full adders. 

Each of adders 25 and 26 responds to the two binary 55 
words applied to its inputs to derive a binary one level 
at its most significant bit output pin 15 in response to the 
word read out from its corresponding register 23 or 24 
having a value of more than 0100 (decimal 4); in the 
opposite manner, a binary zero level is derived on the 60 
most significant bit output pin 15 of adders 25 and 26 in 
response to the binary word read from its correspond- 
ing register having a value of less than 0101 (decimal 5). 
This result is apparent because of the addition of 00 11 in 
adders 25 and 26 to the contents of registers 23 and 24. 65 

The three least significant bit signals derived from full 
adders 25 and 26 are respectively applied to the three 
most significant bit parallel pins of registers 23 and 24; 



i.e., pins 9, 6, and 2 of registers 25 and 26 are respec- 
tively connected to pins 2, 3, and 5 of registers 23 and 
24. The most significant bit signals derived from regis- 
ters 25 and 26, on pins 15, are supplied to the mode 
control input terminals 6 of registers 23 and 24 via AND 
gates 27 and 28 while the converter is in a conversion 
mode, a result achieved by feeding the binary one out- 
put of counter 18 (FIG. 1) to enable inputs of gates 27 
and 28. Thereby, in response to adder 25 or 26 deriving 
a binary one output of most significant bit output pins 
15, registers 23 and 24 are activated to load the three 
least significant bit outputs of adders 25 and 26 into the 
three most significant bit stages of registers 23 and 24. 
The output signal of AND gates 27 and 28 are applied 
to the serial and parallel input pins 1 and 4 of the tens 
and hundreds decades of converter 17; the connection 
from AND gate 28 to the converter of the hundreds 
decade is not illustrated since only two decades of the 
converter are illustrated. 

The higher order converter stages have internal cir- 
cuits and connections identical to those for stage 22. 
Connections between adjacent higher order stages, e.g., 
between stages M and {M+ 1) are the same as illustrated 
for stages 21 and 22. These connections enable the least 
significant bit position of the register of each stage to be 
loaded with a binary one in response to the adjacent, 
preceding decade having a value greater than 0100. 
Hence, in response to register 23 storing a value greater 
than 0100, a binary one is loaded into the first stage of 
register 24. 

The lowest order stage of shift register 23 is sequen- 
tially responsive, in order, to the four initial binary 
zeros and to the bits of the 32-bit binary coded word, 
with the most significant bit being initially appUed to 
the first stage of register 23. To this end, pins 1 and 14 
of register 23 are connected to the most significant bit 
stage of register 12. 

To provide a better understanding of the functioning 
of the converter of the present invention, an example of 
the operation will be considered. Assume that the bi- 
nary coded word 11110 (decimal 30) is to be converted 
to a binary coded decimal word which has the value 
0011-0000 for the tens and units decades, respectively. 
Assume, for the purposes of simplicity, that the con- 
verter only includes two decades so that the 32-bit shift 
register 11 of FIG. 1 is replaced with a five-bit register 
and the 40 bit converter 17 is replaced with an eight-bit 
converter. Also assume that the input terminals of the 
most significant to least significant bit stages of the 
five-bit register have been supplied with the binary bits 
1 11 10, and that the four parallel input terminals of the 
intermediate register 12 have all been supplied with 
binary zeros. In response to a binary one output of 
AND gate 16, the stages of the 5-and 4-bit registers are 
respectively loaded with the words applied to their 
inputs. In response to the clock pulse from source 14 
that occurs immediately after the binary one level is 
derived from AND gate 16, counter 18 derives a binary 
zero level to disable AND gates 27 and 28. With AND 
gates 27 and 28 disabled, the first binary zero from the 
most significant stage of register 12 is supplied to pins 1 
and 14 of register 23, causing the least significant bit 
stage of register 23 to be loaded with a binary zero. 
Simultaneously, a binary zero is derived from AND 
gate 27 and supplied to pins 1 and 14 of register 24, 
whereby the least significant stage of register 24 is 
loaded with a binary zero. In response to the next three 
clock pulses from source 14, binary zeros are similarly 



4,069,478 

7 8 

supplied to pins 1 and 14 of registers 23 and 24. Because values 1010 on output pins 15, 2, 6, and 9. The binary 

the mode control signals applied by gates 27 and 28 to one level on most significant bit output pin 15 is coupled 

pins 6 of registers 23 and 24 are both zeros, the zeros through AND gate 27 to mode control input pin 6 of 

loaded into the least signiflcant bit stages of the registers register 23 so that pins 2, 3, and 5 of register 23 are 

are shifted to the right in response to each clock pulse 5 respectively responsive to the 010 outputs of pins 9, 6, 

from source 14. Thereby, upon the conclusion of the and 2 of adder 25. Thereby, in the interval between the 

first four clock pulses from source 14, each of registers trailing and leading edges of the seventh and eighth 

23 and 24 has a binary zero in each of its four positions; clock pulses the least to most significant bits stages of 

also the four stages of register 12 are loaded with the register 23 respectively store the binary values 1010. 

four most significant bits of the binary word to be en- 10 The binary one value in the least significant bit stage of 

coded because of the shifting operation from register 11 register 23 occurs because the clock input of register 12 

to register 12 in response to each clock pulse from is, during this interval, a binary one value and an output 

source 14. signal is derived from the most significant bit stage of 

After the fourth clock pulse has been derived, register 12 during this interval. Simultaneously with a 

counter 18 derives a binary one level and enable signals 15 binary one.signal being supplied to pin 6 of register 23, 

are applied to one of the inputs of each of AND gates 27 AND gate 27 supplies a binary one input to pins 1 and 

and 28. Thereby, AND gates 27 and 28 can selectively 4 of register 24. Thereby, the least significant bit posi- 

couple the output signals at pins 15 of adders 25 and 26 tion of register 24 is loaded with a binary one while the 

to the mode control input pins 6 of registers 23 and 24, next (eighth) clock pulse is being derived, 

respectively. 20 While the eighth clock pulse is being derived, a bi- 

In response to the next (fifth) clock pulse from source nary one level is supplied to pins 1 and 14 of register 23 

14, the most significant bit of the binary coded word to by the most significant bit position of registers 12. 
be encoded into a binary coded decimal word is cou- Thereby, the least to most significant bit stages of regis- 
pled from the most signficant bit stage of register 12 to ters 23 are now respectively loaded with the binary 
pins 1 and 14 of register 23. In the cited example, a 25 values 1010. Thereby, in response to the trailing edge of 
binary one is coupled to pins 1 and 14 of register 23 and the eighth clock pulse, pins 13, 12, 10, and 9 of register 
the least significant bit stage of register 23 is storing a 23 respectively supply the binary bits 1010 to pins 10, 8, 
binary one value. In response to the trailing edge of the 3, and 1 of adder 25. Adder 25 responds to its two input 
fifth clock pulse, the binary one level at pin 13 of regis- signals to derive the binary bits 0001 on its output pins 
ter 23 is coupled to pin 10 of adder 25. Adder 25 re- 30 9, 6, 2, and 15, respectively. The binary one value on 
sponds to the 0001 inputs respectively applied to its pins most significant bit pin 15 is coupled by AND gate to 
1, 3, 8, and 10, as well as the 0011 signal applied to its mode control input pin 6 of register 23 and to pins 1 and 
pins 16, 4, 7, and 11 to derive a binary zero output on pin 14 of register 24. In response to the binary one value 

15. Thereby, a binary zero is derived from AND gate 27 coupled to pin 6 of register 23, binary zero levels are 
and no input can be supplied to parallel input pins 2, 3, 35 loaded into the three most significant bit stages of regis- 
and 5 of register 23. Hence, register 23 remains in the ter 23 (by virtue of the connection of pins 9, 6, and 2 of 
same state it previously had, with zeros in its three most adder 25 to pins 2, 3, and 5, respectively, of register 23) 
significant bit stages and a one in its least significant bit and a binary zero is loaded into the least significant bit 
stage. stage of register 23. The binary one level is coupled by 

In response to the next (sixth) clock pulse, a binary 40 AND gate 27 to the least significant bit stage of register 
one signal is again applied to pins 1 and 14 of register 23 24 and is clocked into that stage in response to the lead- 
while a clock pulse is supplied to pins 7 and 8 of the ing edge of the next (ninth) clock pulse from source 14. 
register. The clock pulse causes the binary one loaded in The ninth clock pulse from source 14 also causes the 
the least significant bits stage of register 23 to be shifted binary one stored in the least significant bit stage of 
to the second least significant bits stage, while the least 45 register 24 to be transferred to the second least signifi- 
significant bit stage of the register is loaded with a bi- cant bit stage of register 24. Thereby, the two least 
nary one signal. The binary one signals in the least and significant bit stages of register 24 store binary ones 
second least significant stages of register 23 are respec- during the ninth clock pulse. When the ninth clock 
tively read from pins 13 and 12 to pins 10 and 18 of pulse is being derived, the most significant bit output of 
adder 25, in response to the trailing edge of the clock 50 register 12 has a binary zero level, whereby a binary 
pulse. Adder 25 responds to the binary one levels at its zero is shifted into the least significant bit position of 
input pins 10 and 8, as well as the binary one levels at its register 23 during the ninth clock pulse. In response to 
input pins 7 and 11, to derive an output signal respec- the ninth clock pulse the 000 values previously stored m 
tively having the values 0110 on pins 15, 2, 6, and 9. The the three least significant bit stages of register 23 are 
binary zero level on pin 15 is coupled by AND gate 27 55 shifted right one position and the zero value supplied to 
to mode control input pin 6 of register 23, whereby the pins 1 and 14 is loaded into the least significant bit posi- 
register is unresponsive to the signals at pins 9, 6, and 2 tion of register 23. Hence, when the trailing edge of the 
of register 25. ninth clock pulse occurs, the most to least significant bit 

In response to the next (seventh) clock pulse, a binary positions of register 24 are storing the binary values 

one is again fed in parallel to pins 1 and 14 of register 23 60 001 1, while register 23 is storing the values 0000. These 

whereby the three least significant bit stages of register binary values are read out from registers 23 and 24 to 

23 are all loaded with binary ones, while the most signif- the register output pins 9, 10, 12, and 13 to indicate the 

icant bit stage of the register is loaded with a binary binary coded decimal value 001 1-0000 (decimal 30). 

zero. In response to the trailing edge of the output of While the specific embodiment has been described in 

clock source 14, the binary values 1110 are coupled 65 connection with a binary coded to binary coded deci- 

from pins 13, 12, 10, and 9 of register 23 to pins 10, 8, 3, mal converter, it is to be understood that the principles 

and 1 of adder 25. Adder 25 responds to the signals at its " can be extended to convert a binary coded signal to a 

input pins to derive binary bits respectively having the signal having a coded form of any base. To convert to 



4,069,478 



10 



any even base, it is only necessary to add a di^erent 
number to the number stored in registers 23 and 24. In 
general, for any even base, the number to be added to 
the number in register 23 or 24 is (16 — base/2). Such a 
change is easily implemented, merely by changing the 
magnitude of the binary signal applied to pins 11, 7, 4, 
and 16 of adders 25 and 26. For the specific binary to 
binary coded decimal converter, wherein the base = 

10, the number is ((16 - 10)/2) = S^for a base of 8, the 
number is (16 — 8)/2) = 4. Adding 4 is easily imple- 
mented by supplying a binary one level to pin 4 of ad- 
ders 25 and 26, and by supplying a binary zero to pins 

11, 7, and 16 of the adders. If the order or base equals 
eight, the decision as to whether registers 23 and 24 are 
to be responsive to the signals applied to pins 2, 3, and 
5 and whether a binary one is to be supplied to the least 
significant bit stage of register 24, is made merely by 
inspecting the binary value of the most significant bit 
outputs of adders 25 and 26, at pins 15. 

While there has been described and illustrated one 
specific embodiment of the invention, it will be clear 
that variations in the details of the embodiments specifi- 
cally illustrated and described may be made without 
departing from the true spirit and scope of the invention 
as defined in the appended claims. 

What is claimed is: 

1. Apparatus for converting a binary coded input 
signal to a binary coded decimal output signal having N 
decades comprisng N shift registers each having four bit 
positions, means for sequentially supplying the bits of 
the input signal to the least significant bit position of the 
register for the units decade of the binary coded deci- 
mal signal, the bits of the input signal being supplied in 
order to the least significant bit position of the units 
decade register with the most significant bit of the input 
signal being applied first, each of said registers having a 
right shift-pardlel load most control input means, and 
means responsive to the sum of the value stored in each 
of said registers and the binary value 0011 for: (a) acti- 
vating the mode control input means to shift the register 
contents one bit to the right in response to the sum being 
less than the binary value 1000, (b) activating the mode 
control input means to load the sum into the register in 
response to the sum being greater than to 1000, and (c) 45 
loading a binary one into the least significant bit posi- 
tion of the register for the adjacent higher decade in 
response to the sum being greater than 1000. 

2. The apparatus of claim 1 wherein the means re- 
sponsive to the sum of the value stored in each register 
and the binary value 001 1 includes a binary full adder 
responsive to the binary bits stored in the register and a 
constant indicative of the binary value 0011, said adder 
including a most significant bit output and three less 
significant bit outputs , means for supplying the most 55 
significant bit output of the adder to the mode control 
input terminal and the least significant bit position of the 
register for the adjacent higher decade, and means for 
supplying the three less signficant bit outputs to the 
three most significant bit positions of the register. 

3. The apparatus of claim 1 further including means 
for initially loading a binary zero into each position of 
each shift register, said means for initially loading in- 
cluding means for supplying a binary zero to the least 
significant bit position of each register while four clock 
pulses are supplied in parallel to the registers and the 



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15 



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25 



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35 



40 



50 



60 



65 



mode control input terminal of each register is activated 
to the right shift state. 

4. The apparatus of claim 3 wherein the means for 
supplying a binary zero to the first position of the units 
register includes means for injecting four binary zeros 
before the most significant bit of the binary coded input 
signal. 

5. The apparatus of claim 3 further including an AND 
gate responsive to the most significant bit output of the 
adder for selectively activating the means responsive to 
the sum of the value stored in each of the registers and 
the binary value 0011, and means for disabling the AND 
gate while the means for initially loading a binary zero 
into each position of each shift register is activated. 

6. Apparatus for converting a binary coded input 
signal to a binary coded decimal output signal having N 
decades comprising N shift registers each having four 
bit positions, means for sequentially supplying the bits 
of the input signal to the least significant bit position of 
the register for the units decade of the binary coded 
decimal signal, the bits of the input signal being supplied 
in order to the least significant bit position of the units 
decade register with the most significant bit of the input 
signal being applied first, each of said registers having a 
right shift-parallel load mode control input means, and 
means for: (a) activating the mode control input means 
to shift the register contents one bit to the right in re- 
sponse to the most significant bit of the sum of the regis- 
ter contents and the binary value 001 1 being a zero, (b) 
activating the mode control input means to add the 
binary value 00 11 to the register contents in response to 
the most significant bit of the sum of the register con- 
tents and the binary value 0011 being a one, and (c) 
loading a binary one into the least significant bit posi- 
tion of the register for the adjacent higher decade in 
response to the most significant bit of the sum of the 
register contents and the binary value 001 1 being a one. 

7. Apparatus for converting a binary coded input 
signal to an output signal having a binary code of base 
K, wher K > 2, N orders of said output signal being 
provided, comprising N shift registers, one for each of 
said orders, each of said registers having M stages, 
where M is an integer enabling a binary signal to be 
represented in order K, means for sequentially supply- 
ing the bits of the input signal to the least significant bit 
position of the register for the lowest order of the out- 
put signal, the bits of the input signal being supplied in 
order to the least significant bit position of the lowest 
order register with the most significant bit being applied 
first, each of said registers having a right shift-parallel 
load mode control input means, and means for: (a) acti- 
vating the mode control input means to shift the register 
contents one bit to the right in response to the most 
significant bit of the sum of the register contents and a 
predetermined binary value of 2 M — K/2 being a zero, 
(b) activating the mode control input means to add the 
predetermined binary value to the register contents in 
response to the most significant bit of the sum of the 
register contents and the predetermined binary value 
being a one, and (c) loading a binary one into the least 
significant bit position of the register for the adjacent 
higher order in response to the most significant bit of 
the sum of the register contents and the predetermined 
binary value being a one, said predetermined binary 
value being dependent upon the order K.